ADP5134数据手册

Dual 3 MHz, 1200 mA Buck Regulators and Two 300 mA LDO
Regulators With Precision Enable and Power-Good Output
ADP5134
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
APPLICATIONS
10
VIN
2.5V TO
5.5V
VIN1
C1
4.7µF
ON
OFF
16
15
BUCK1
1.2A
EN1
11
14
12
VIN2
3
C3
4.7µF
ON
OFF
EN2
AVIN
VIN3
ON
OFF
BUCK2
1.2A
4
8
17
FB1
PGND1
L1 1µH
R1
C2
10µF
R2
VIN4
21
20
19
PSM/PWM
VOUT2
SW2
FB2
PGND2
L2 1µH
R3
C4
10µF
R4
VOUT3
FB3
R5
C7
1µF
R6
22
23
LDO2
300mA
EN4
MODE
HOUSEKEEPING
LDO1
300mA
EN3
C8
1µF
ON
Power for processors, application specific integrated circuits
(ASICs), field programmable gate arrays (FPGAs), and
radio frequency (RF) chipsets
Portable instrumentation and medical devices
Space constrained devices
9
7
C6
1µF
OFF
MODE
5
C5
0.1µF
VINLDO2
1.7V TO
5.5V
SW1
PWM
13
VINLDO1
1.7V TO
5.5V
VOUT1
24
1
VOUT4
FB4
2
R7
C9
1µF
R8
VDDIO
POWER GOOD
PG
R1
100kΩ
6
18
ADP5134
AGND
11710-001
Main input voltage range of 2.5 V to 5.5 V
Two 1200 mA buck regulators and two 300 mA LDO regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy of ±1.8%
Factory programmable or external adjustable VOUTx
Precision enable pins for easier power sequencing
Factory selectable power-good pin
3 MHz buck operation with forced PWM and automatic
PWM/PSM modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: input voltage range from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
Figure 1.
GENERAL DESCRIPTION
The ADP5134 combines two high performance buck regulators
and two low dropout (LDO) regulators. It is available in a 24-lead
4 mm × 4 mm LFCSP.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced pulse-width modulation (PWM) mode. When the MODE
pin is set to low, the buck regulators operate in PWM mode
when the load is above a predefined threshold. When the load
current falls below a predefined threshold, the regulator operates
in power save mode (PSM), improving the light load efficiency.
The two buck regulators operate out of phase to reduce the input
capacitor requirement. The low quiescent current, low dropout
voltage, and wide input voltage range of the ADP5134 LDO
regulators extend the battery life of portable devices. The
ADP5134 LDO regulators maintain power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage of 500 mV.
Rev. 0
Regulators in the ADP5134 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
Table 1. Family Models
Model
ADP5023
Channels
2 Bucks, 1 LDO
Maximum
Current
800 mA, 300 mA
Package
LFCSP (CP-24-10)
ADP5024
2 Bucks, 1 LDO
1.2 A, 300 mA
LFCSP (CP-24-10)
ADP5034
2 Bucks, 2 LDOs
1.2 A, 300 mA
ADP5037
2 Bucks, 2 LDOs
800 mA, 300 mA
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
ADP5033
2 Bucks, 2 LDOs
with 2 ENx pins
1 Bucks, 2 LDOs
800 mA, 300 mA
WLCSP (CB-16-8)
1.2 A, 300 mA
LFCSP (CP-20-10)
1.2 A, 300 mA
LFCSP (CP-20-10)
ADP5040
ADP5041
1 Bucks, 2 LDOs
with supervisory
circuit, watchdog
function, and
manual reset
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ADP5134
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Applications ....................................................................................... 1
Power Management Unit........................................................... 15
Typical Application Circuit ............................................................. 1
BUCK1 and BUCK2 .................................................................. 17
General Description ......................................................................... 1
LDO1 and LDO2 ........................................................................ 18
Revision History ............................................................................... 2
Applications Information .............................................................. 19
Specifications..................................................................................... 3
Buck Regulator External Component Selection .................... 19
General Specifications ................................................................. 3
LDO Regulator External Component Selection .................... 20
BUCK1 and BUCK2 Specifications ........................................... 4
Power Dissipation and Thermal Considerations ....................... 22
LDO1 and LDO2 Specifications ................................................. 4
Buck Regulator Power Dissipation .......................................... 22
Input and Output Capacitor, Recommended Specifications .. 5
Junction Temperature ................................................................ 23
Absolute Maximum Ratings............................................................ 6
PCB Layout Guidelines .................................................................. 24
Thermal Resistance ...................................................................... 6
Typical Application Schematics .................................................... 25
ESD Caution .................................................................................. 6
Bill of Materials ........................................................................... 26
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 27
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 27
REVISION HISTORY
10/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP5134
SPECIFICATIONS
GENERAL SPECIFICATIONS
VAVIN = VVIN1 = VVIN2 = 2.5 V to 5.5 V, VVIN3 = VVIN4 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and
TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
START-UP TIME 1
BUCK1
BUCK2
LDO1, LDO2 (Fast Soft Start)
LDO1, LDO2 (Slow Soft Start)
START-UP TIME, BUCK2 First
BUCK2
BUCK1
LDO1, LDO2 (Fast Soft Start)
LDO1, LDO2 (Slow Soft Start)
SHUTDOWN CONTROL
Level High
Level Low
PRECISION ENABLE PINS (ENx)
Analog Activation Threshold
Hysteresis (Regulator Deactivation)
Input Leakage Current
POWER-GOOD PIN (PG)
Power-Good Falling Threshold
Power-Good Rising Threshold
Power-Good Delay
Power-Good Leakage Current
Power-Good Output Voltage Low
MODE PIN
Level High
Level Low
INPUT CURRENT
All Channels Enabled
All Channels Disabled
VIN1 UNDERVOLTAGE LOCKOUT
Low UVLO Input Voltage Rising
Low UVLO Input Voltage Falling
1
Symbol
VAVIN, VVIN1,
VVIN2
Test Conditions/Comments
TSSD
TSSD-HYS
TJ rising
Min
2.5
Typ
Max
5.5
Unit
V
150
20
°C
°C
tSTART1
tSTART2
tSTART3
tSTART4
650
750
650
900
µs
µs
µs
µs
tSTART5
tSTART6
tSTART7
tSTART8
750
300
300
600
µs
µs
µs
µs
VIH_EN
VIL_EN
VENR
VENH
VI-LEAKAGE
VPGLOW
VPGHYS
tPGDLY
IPGIQ
VPGOL
All ENx pins below VIL_EN level to achive ISHUTDOWN
TJ = −40°C to +85°C
0.35
Regulator(s) activation/deactivation thresholds
Device out of shutdown (VENx > VIH_EN)
Monitors VOUT falling out of regulation
At VOUT
At VOUT
0.94
91
VPG = VIN
Load current (ILOADx) = 1 mA
VIH_MOD
VIL_MOD
ISTBY-NOSW
ISHUTDOWN
0.9
0.97
80
0.05
90
94
15
0.02
1
1
UVLOVIN1RISE
UVLOVIN1FALL
113
0.3
1.95
V
mV
µA
1
0.15
%
%
µs
µA
V
0.4
V
V
182
1
µA
µA
2.45
V
V
97
1.1
No load, no buck switching
TJ = −40°C to +85°C
V
V
Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 at 0 V to VAVIN to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up
times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 28
ADP5134
Data Sheet
BUCK1 AND BUCK2 SPECIFICATIONS
VAVIN = VVIN1 = VVIN2 = 2.5 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 3.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
Line Regulation
Load Regulation
VOLTAGE FEEDBACK
OPERATING SUPPLY CURRENT
BUCK1 Only
Symbol
Test Conditions/Comments
Min
ΔVVOUT1/VVOUT1,
ΔVVOUT2/VVOUT2
(ΔVVOUT1/VVOUT1)/ΔVVIN1,
(ΔVVOUT2/VVOUT2)/ΔVVIN2
(ΔVVOUT1/VVOUT1)/ΔIVOUT1,
(ΔVVOUT2/VVOUT2)/ΔIVOUT2
VFB1, VFB2
IIN
PWM mode, ILOAD1 = ILOAD2 = 0 mA
−1.8
BUCK2 Only
BUCK1 and BUCK2
PSM CURRENT THRESHOLD
SWx CHARACTERISTICS
SWx On Resistance
Current Limit
ACTIVE PULL-DOWN
OSCILLATOR FREQUENCY
IPSM
RNFET
RPFET
RNFET
RPFET
ILIMIT1, ILIMIT2
RPDWN-B
fSW
Typ
Max
Unit
+1.8
%
PWM mode
−0.05
%/V
ILOAD = 0 mA to 1200 mA, PWM mode
−0.1
%/A
Models with adjustable outputs
MODE = ground
ILOAD1 = 0 mA, device not switching, all
other channels disabled
ILOAD2 = 0 mA, device not switching, all
other channels disabled
ILOAD1 = ILOAD2 = 0 mA, device not
switching, LDO channels disabled
PSM to PWM operation
VVIN1 = VVIN2 = 3.6 V
VVIN1 = VVIN2 = 3.6 V
VVIN1 = VVIN2 = 5.5 V
VVIN1 = VVIN2 = 5.5 V
PFET switch peak current limit
VVIN1 = VVIN2 = 3.6 V, channels disabled
0.491
1600
2.5
0.5
0.509
V
44
μA
55
μA
67
μA
100
mA
155
205
137
162
1950
75
3.0
240
310
204
243
2300
mΩ
mΩ
mΩ
mΩ
mA
Ω
MHz
3.5
LDO1 AND LDO2 SPECIFICATIONS
VVIN3 = (VVOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, VVIN4 = (VVOUT4 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V, CIN =
COUT = 1 µF, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise
noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 4.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Bias Current per LDO 1
Total System Input Current
LDO1 or LDO2 Only
LDO1 and LDO2
Symbol
VVIN3, VVIN4
Test Conditions/Comments
IVIN3BIAS/IVIN4BIAS
IVOUT3 = IVOUT4 = 0 µA
IVOUT3 = IVOUT4 = 10 mA
IVOUT3 = IVOUT4 = 300 mA
Includes all current into AVIN, VIN1, VIN2,
VIN3, and VIN4
IVOUT3 = IVOUT4 = 0 µA, all other channels
disabled
IVOUT3 = IVOUT4 = 0 µA, buck channels disabled
IIN
Rev. 0 | Page 4 of 28
Min
1.7
Typ
Max
5.5
Unit
V
10
60
165
30
100
245
µA
µA
µA
63
µA
84
µA
Data Sheet
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Accuracy
Line Regulation
Load Regulation 2
VOLTAGE FEEDBACK
DROPOUT VOLTAGE 3
CURRENT-LIMIT THRESHOLD 4
ACTIVE PULL-DOWN
OUTPUT NOISE
Regulator LDO1
Regulator LDO2
POWER SUPPLY REJECTION
RATIO
Regulator LDO1
ADP5134
Symbol
Test Conditions/Comments
Min
ΔVVOUT3/VVOUT3,
ΔVVOUT4/VVOUT4
(ΔVVOUT3/VVOUT3)/ΔVVIN3,
(ΔVVOUT4/VVOUT4)/ΔVVIN4
(ΔVVOUT3/VVOUT3)/ΔIVOUT3,
(ΔVVOUT4/VVOUT4)/ΔIVOUT4
IVOUT3 = IVOUT4 = 1 mA
IVOUT3 = IVOUT4 = 1 mA
ILIMIT3, ILIMIT4
RPDWN-L
NOISELDO1
NOISELDO2
PSRR
Regulator LDO2
Unit
−1.8
+1.8
%
−0.0
3
+0.0
3
0.003
%/V
0.509
V
mV
mV
mV
mV
mA
Ω
0.001
0.491
%/mA
Channels disabled
0.5
50
75
100
180
600
600
10 Hz to 100 kHz, VVIN3 = 5 V, VVOUT3 = 2.8 V
10 Hz to 100 kHz, VVIN4 = 5 V, VVOUT4 = 1.2 V
100
60
µV rms
µV rms
10 kHz, VVIN3 = 3.3 V, VVOUT3 = 2.8 V, IVOUT3 = 1 mA
100 kHz, VVIN3 = 3.3 V, VVOUT3 = 2.8 V, IVOUT3 = 1 mA
1 MHz, VVIN3 = 3.3 V, VVOUT3 = 2.8 V, IVOUT3 = 1 mA
10 kHz, VVIN4 = 1.8 V, VVOUT4 = 1.2 V, IVOUT4 = 1 mA
100 kHz, VVIN4 = 1.8 V, VVOUT4 = 1.2 V, IVOUT4 = 1 mA
1 MHz, VVIN4 = 1.8 V, VVOUT4 = 1.2 V, IVOUT4 = 1 mA
60
62
63
54
57
64
dB
dB
dB
dB
dB
dB
VFB3, VFB4
VDROPOUT
Max
IVOUT3 = IVOUT4 = 1 mA to 300 mA
Typ
VVOUT3 = VVOUT4 = 5.2 V, IVOUT3 = IVOUT4 = 300 mA
VVOUT3 = VVOUT4 = 3.3 V, IVOUT3 = IVOUT4 = 300 mA
VVOUT3 = VVOUT4 = 2.5 V, IVOUT3 = IVOUT4 = 300 mA
VVOUT3 = VVOUT4 = 1.8 V, IVOUT3 = IVOUT4 = 300 mA
335
140
This is the input current into VIN3 or VIN4 that is not delivered to the output load. If LDO1 is only activated, it is the current into VIN3. If LDO2 is only activated, it is the
current into VIN4.
2
Based on an endpoint calculation using 1 mA and 300 mA loads.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
greater than 1.7 V.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
1
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
TA = −40°C to +125°C, unless otherwise specified.
Table 5.
Parameter
NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS
BUCK1, BUCK2 Input Capacitor Ratings
BUCK1, BUCK2 Output Capacitor Ratings
LDO1, LDO2 1 Input and Output Capacitor Ratings
CAPACITOR ESR
1
Symbol
Min
CMIN1, CMIN2
CMIN1, CMIN2
CMIN3, CMIN4
RESR
4.7
10
1.0
0.001
Typ
Max
Unit
40
40
µF
µF
µF
Ω
1
The minimum input and output capacitance must be greater than 1.0 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R type and X5R type capacitors are
recommended, and Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics.
Rev. 0 | Page 5 of 28
ADP5134
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
AVIN to AGND
VIN1, VIN2 to AVIN
PGND1, PGND2 to AGND
VIN3, VIN4, VOUT1, VOUT2, FB1, FB2,
FB3, FB4, EN1, EN2, EN3, EN4,
MODE, PG to AGND
VOUT3 to AGND
VOUT4 to AGND
SW1 to PGND1
SW2 to PGND2
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (AVIN + 0.3 V)
−0.3 V to (VIN3 + 0.3 V)
−0.3 V to (VIN4 + 0.3 V)
−0.3 V to (VIN1 + 0.3 V)
−0.3 V to (VIN2 + 0.3 V)
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
24-Lead, 0.5 mm Pitch LFCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
Rev. 0 | Page 6 of 28
θJA
35
θJC
3
Unit
°C/W
Data Sheet
ADP5134
24
23
22
21
20
19
VOUT4
VIN4
EN3
VIN3
VOUT3
FB3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
PIN 1
INDICATOR
ADP5134
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
AGND
AVIN
VIN1
SW1
PGND1
MODE
NOTES
1. SOLDER THE EXPOSED PAD TO THE GROUND PLANE.
11710-002
EN2
FB2
VOUT2
VOUT1
FB1
EN1
7
8
9
10
11
12
FB4
EN4
VIN2
SW2
PGND2
PG
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
Mnemonic
FB4
2
3
4
5
6
7
8
EN4
VIN2
SW2
PGND2
PG
EN2
FB2
9
10
11
VOUT2
VOUT1
FB1
12
13
EN1
MODE
14
15
16
17
18
19
PGND1
SW1
VIN1
AVIN
AGND
FB3
20
21
22
23
24
VOUT3
VIN3
EN3
VIN4
VOUT4
EP
Description
LDO2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
LDO2 resistor divider. For device models with a factory programmed output voltage, connect FB4 to the top of the
capacitor on VOUT4.
LDO2 Enable Pin. When EN4 is set to high, it turns the regulator on. When EN4 is set to low, it turns the regulator off.
BUCK2 Input Supply (2.5 V to 5.5 V). Connect VIN2 to VIN1 and AVIN.
BUCK2 Switching Node.
Dedicated Power Ground for BUCK2.
Power-Good Pin Output. Factory selectable to monitor the output voltage of up to four regulators.
BUCK2 Enable Pin. When EN2 is set to high, it turns the regulator on. When EN2 is set to low, it turns the regulator off.
BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the BUCK2 output capacitor.
BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the BUCK1 output capacitor.
BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected.
BUCK1 Enable Pin. When EN1 is set to high, it turns the regulator on. When EN1 is set to low, it turns the regulator off.
BUCK1/BUCK2 Operating Mode. When MODE is set to high, the device is set to forced PWM operation. When MODE
is set to low, the device is automatically set to PWM/PSM operation.
Dedicated Power Ground for BUCK1.
BUCK1 Switching Node.
BUCK1 Input Supply (2.5 V to 5.5 V). Connect VIN1 to VIN2 and AVIN.
Analog Input Supply (2.5 V to 5.5 V). Connect AVIN to VIN1 and VIN2.
Analog Ground.
LDO1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the
LDO1 resistor divider. For device models with a factory programmed output voltage, connect FB3 to the top of the
capacitor on VOUT3.
LDO1 Output Voltage.
LDO1 Input Supply (1.7 V to 5.5 V).
LDO1 Enable Pin. When EN3 is set to high, it turns on the regulator, and when EN3 is set to low, it turns off the regulator.
LDO2 Input Supply (1.7 V to 5.5 V).
LDO2 Output Voltage.
Exposed Pad. Solder the exposed pad to the ground plane.
Rev. 0 | Page 7 of 28
ADP5134
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VVIN1 = VVIN2 = VVIN3 = VVIN4 = 3.6 V, TA = 25°C, unless otherwise noted.
3.320
160
3.315
140
TA = –40°C
3.305
100
VVOUT1 (V)
80
3.300
TA = +25°C
3.295
3.290
60
3.285
40
TA = +85°C
3.280
20
3.275
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
3.270
11710-003
0
2.5
Figure 3. System Quiescent Current vs. Input Voltage, VVOUT1 = 3.3 V,
VVOUT2 = 1.8 V, VVOUT3 = 1.2 V, VVOUT4 = 3.3 V, All Channels Unloaded
0
0.2
0.4
0.6
0.8
1.0
1.2
IVOUT1 (A)
11710-006
QUIESCENT CURRENT (µA)
3.310
120
Figure 6. BUCK1 Load Regulation Across Temperature, VVIN1 = 4.2 V, VVOUT1 =
3.3 V, PWM Mode
1.812
1.810
SW1
1.808
4
VVOUT2 (V)
IVOUT1
2
1
TA = –40°C
VVOUT1
TA = +25°C
1.806
1.804
1.802
TA = +85°C
1.798
BW
BW
CH2 50.0mA BW
CH4 5.00V BW
M 0.0µs
A CH3
2.40V
0
11710-004
CH1 2.00V
CH3 5.00V
0.2
0.4
0.6
0.8
1.0
1.2
IVOUT2 (A)
Figure 4. BUCK1 Startup, VVIN1 = 4.2 V, VVOUT1 = 1.8 V, IVOUT1 = 5 mA
11710-007
1.800
EN1
3
Figure 7. BUCK2 Load Regulation Across Temperature,
VVIN2 = 3.6 V, VVOUT2 = 1.8 V, PWM Mode
0.808
T
0.807
SW2
4
0.806
VVOUT1 (V)
IVOUT2
2
1
VVOUT2
TA = +25°C
0.805
TA = –40°C
TA = +85°C
0.804
0.803
BW
BW
CH2 50.0mA BW
CH4 5.00V BW
M 0.0µs
T 10.10%
A CH3
2.40V
11710-005
0.802
CH1 2.00V
CH3 5.00V
0
0.2
0.4
0.6
0.8
1.0
IVOUT1 (A)
Figure 8. BUCK1 Load Regulation Across Input Voltage,
VVIN1 = 3.6 V, VVOUT1 = 0.8 V, PWM Mode
Figure 5. BUCK2 Startup, VVIN2 = 4.2 V, VVOUT2 = 3.3 V, IVOUT2 = 10 mA
Rev. 0 | Page 8 of 28
1.2
11710-008
EN2
3
Data Sheet
100
VVIN1 = 3.9V
90
90
80
VVIN1 = 4.2V
70
70
EFFICIENCY (%)
60
50
40
40
20
20
10
10
0.1
0
0.001
11710-009
0.01
1
Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VVOUT1 = 3.3 V, Auto Mode
100
90
90
80
70
EFFICIENCY (%)
VVIN1 = 3.9V
50
40
30
60
50
40
20
VVIN1 = 4.2V
= 2.5V
= 3.6V
= 4.2V
= 5.5V
10
0.1
1
0
0.001
11710-010
0.01
IVOUT1 (A)
0.01
0.1
1
IVOUT1 (A)
Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VVOUT1 = 3.3 V, PWM Mode
Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VVOUT1 = 0.8 V, Auto Mode
100
90
90
80
80
70
EFFICIENCY (%)
70
60
50
VVIN2
VVIN2
VVIN2
VVIN2
40
30
= 2.5V
= 3.6V
= 4.2V
= 5.5V
60
50
40
30
20
20
10
10
0.1
0.01
IVOUT2 (A)
1
0
0.001
11710-011
0
0.001
VVIN1
VVIN1
VVIN1
VVIN1
30
20
0
0.001
1
VVIN1 = 5.5V
60
10
0.1
Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VVOUT2 = 1.8 V, PWM Mode
100
70
0.01
IVOUT2 (A)
80
EFFICIENCY (%)
50
30
IVOUT1 (A)
EFFICIENCY (%)
60
30
0
0.001
= 2.5V
= 3.6V
= 4.2V
= 5.5V
11710-013
EFFICIENCY (%)
VVIN1 = 5.5V
VVIN2
VVIN2
VVIN2
VVIN2
11710-012
80
VVIN1
VVIN1
VVIN1
VVIN1
0.01
0.1
IVOUT1 (A)
Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage,
VVOUT2 = 1.8 V, Auto Mode
= 2.5V
= 3.6V
= 4.2V
= 5.5V
1
11710-014
100
ADP5134
Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage,
VVOUT1 = 0.8 V, PWM Mode
Rev. 0 | Page 9 of 28
ADP5134
Data Sheet
100
3.3
+25°C
–40°C
90
3.2
+25°C
+85°C
SCOPE FREQUENCY (MHz)
80
–40°C
EFFICIENCY (%)
70
60
50
40
30
3.1
3.0
+85°C
2.9
2.8
2.7
20
2.6
10
1
IVOUT1 (A)
0
0.4
0.2
0.8
1.0
1.2
IVOUT2 (A)
Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature,
VVIN1 = 3.9 V, VVOUT1 = 3.3 V, Auto Mode
Figure 18. BUCK2 Switching Frequency vs. Output Current, Across
Temperature, VVOUT2 = 1.8 V, PWM Mode
100
90
0.6
11710-018
0.1
0.01
11710-015
2.5
0
0.001
T
+25°C
+85°C
VVOUT1
80
1
EFFICIENCY (%)
70
–40°C
ISW1
60
50
2
40
VSW1
30
20
10
0.1
1
IVOUT2 (A)
Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature,
VVOUT2 = 1.8 V, Auto Mode
CH2 500mA Ω
CH4 2.00V
CH1 50.0mV
A CH2
240mA
T 28.40%
Figure 19. Typical Waveforms, VVOUT1 = 3.3 V, IVOUT1 = 30 mA, Auto Mode
100
T
+25°C
90
M 4.00µs
11710-019
0.01
11710-016
4
0
0.001
VVOUT2
80
1
EFFICIENCY (%)
70
+85°C
–40°C
60
ISW2
2
50
40
VSW2
30
20
10
0.1
1
IVOUT1 (A)
Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature,
VVOUT1 = 0.8 V, Auto Mode
CH1 50.0mV
BW
M 4.00µs A CH2
CH2 500mA Ω
BW
CH4 2.00V
T 28.40%
220mA
11710-020
0.01
11710-017
4
0
0.001
Figure 20. Typical Waveforms, VVOUT2 = 1.8 V, IVOUT2 = 30 mA, Auto Mode
Rev. 0 | Page 10 of 28
Data Sheet
ADP5134
T
T
VVOUT1
1
VVIN2
ISW1
VVOUT2
2
1
VSW2
VSW1
4
3
CH2 500mA Ω
M 400ns A CH2
BW
CH4 2.00V
T 28.40%
BW
220mA
CH1 50.0mV
CH3 1.00V
M 1.00ms
BW
BW
CH4 2.00V
A CH3
4.80V
BW
T 30.40%
Figure 21. Typical Waveforms, VVOUT1 = 3.3 V, IVOUT1 = 30 mA, PWM Mode
11710-024
CH1 50mV
11710-021
4
Figure 24. BUCK2 Response to Line Transient, VVIN2 = 4.5 V to 5.0 V,
VVOUT2 = 1.8 V, PWM Mode
T
T
VSW1
VVOUT2
1
4
ISW2
VVOUT1
2
1
VSW2
IVOUT1
CH2 500mA Ω
M 400ns A CH2
BW
CH4 2.00V
T 28.40%
BW
220mA
11710-022
CH1 50mV
CH1 50.0mV
Figure 22. Typical Waveforms, VVOUT2 = 1.8 V, IVOUT2 = 30 mA, PWM Mode
BW
CH2 50.0mA Ω BW M 20.0µs A CH2
BW T 60.000µs
CH4 5.00V
356mA
11710-025
2
4
Figure 25. BUCK1 Response to Load Transient, IVOUT1 from 1 mA to 50 mA,
VVOUT1 = 3.3 V, Auto Mode
T
T
VSW2
4
VVIN1
VVOUT2
VVOUT1
1
1
VSW1
IVOUT2
3
BW
BW
M 1.00ms
CH4 2.00V
BW
T 30.40%
A CH3
4.80V
CH1 50.0mV
11710-023
CH1 50.0mV
CH3 1.00V
Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to
5.0 V, VVOUT1 = 3.3 V, PWM Mode
BW
CH2 50.0mA Ω BW M 20.0µs A CH2
BW
CH4 5.00V
T 22.20%
379mA
11710-026
2
Figure 26. BUCK2 Response to Load Transient, IVOUT2 from 1 mA to 50 mA,
VVOUT2 = 1.8 V, Auto Mode
Rev. 0 | Page 11 of 28
ADP5134
Data Sheet
T
T
VSW1
1
EN4
4
2
VVOUT1
VVOUT4
1
IVOUT1
BW
CH2 200mA Ω
CH4 5.00V
BW
M 20.0µs A CH2
408mA
BW
T 20.40%
CH1 5.00V
CH3 1.00V
11710-027
CH1 50.0mV
Figure 27. BUCK1 Response to Load Transient, IVOUT1 from 20 mA to 180 mA,
VVOUT1 = 3.3 V, Auto Mode
BW
BW
M 200µs
CH4 20.0mA
BW
A CH1
1.80V
T 798.600µs
11710-030
INRUSH CURRENT
4
2
Figure 30. LDO Regulator Startup, VVOUT4 = 1.8 V
3.3160
T
3.3155
VSW2
3.3150
VVIN3 = 5.5V
4
VVOUT3 (V)
3.3145
VVOUT2
1
3.3140
3.3135
VVIN3 = 4.2V
3.3130
3.3125
IVOUT2
VVIN3 = 3.8V
3.3120
2
BW
CH2 200mA Ω
CH4 5.00V
BW
M 20.0µs A CH2
88.0mA
BW
T 19.20%
3.3110
11710-028
CH1 100mV
0
50
100
150
250
200
300
IVOUT3 (mA)
Figure 28. BUCK2 Response to Load Transient, IVOUT2 from 20 mA to 180 mA,
VVOUT2 = 1.8 V, Auto Mode
Figure 31. LDO Load Regulation Across Input Voltage, VVOUT3 = 3.3 V
400
T
350
VOUT2
2
300
SW1
RDSON (mΩ)
+125°C
3
VOUT1
250
+25°C
200
150
–40°C
1
SW2
100
50
BW
BW
CH2 5.00V
CH4 5.00V
BW
M 400ns
BW
T 50.00%
A CH4
1.90V
0
2.3
11710-029
CH1 5.00V
CH3 5.00V
2.8
3.3
3.8
4.3
INPUT VOLTAGE (V)
Figure 29. VOUTx and SWx Waveforms for BUCK1 and BUCK2 in PWM Mode
Showing Out-of-Phase Operation
4.8
5.3
11710-032
4
Figure 32. LFCSP NMOS RDSON vs. Input Voltage Across Temperature
Rev. 0 | Page 12 of 28
11710-031
3.3115
Data Sheet
ADP5134
50
250
45
40
200
+125°C
GROUND CURRENT (µA)
RDSON (mΩ)
+25°C
150
–40°C
100
35
30
25
20
15
10
50
3.3
3.8
4.3
4.8
0
11710-033
2.8
5.3
INPUT VOLTAGE (V)
0
0.05
0.10
0.15
0.20
11710-036
5
0
2.3
0.25
LOAD CURRENT (A)
Figure 33. LFCSP PMOS RDSON vs. Input Voltage Across Temperature
Figure 36. LDO Ground Current vs. Load Current, VVIN3 = 3.3 V, VVOUT3 = 2.8 V
1.802
T
1.801
TA = –40°C
1.800
IVOUT3
1.799
VVOUT3 (V)
2
1.798
TA = +25°C
1.797
1.796
1
VVOUT3
1.795
1.794
TA = +85°C
0
50
100
150
200
250
11710-034
1.792
300
IVOUT3 (mA)
Figure 34. LDO Load Regulation Across Temperature,
VVIN3 = 3.6 V, VVOUT3 = 1.8 V
3.0
2.5
VVOUT3 (V)
2.0
IVOUT3 = 10mA
CH1 100mV
BW
CH2 100mA Ω
BW
M 40.0µs A CH2
52.0mA
T 19.20%
11710-037
1.793
Figure 37. LDO Response to Load Transient, IVOUT3 from 1 mA to 80 mA,
VVOUT3 = 2.8 V
IVOUT3 = 100µA
T
IVOUT3 = 1mA
IVOUT3 = 100mA
IVOUT3 = 150mA
IVOUT3 = 300mA
VVIN3
1.5
VVOUT3
1
2
1.0
0.5
VIN (V)
Figure 35. LDO Line Regulation Across Output Load, VVOUT3 = 2.8 V
CH1 20.0mV
CH3 1.00V
M 100µs
T 28.40%
A CH3
4.80V
11710-038
0
2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
11710-035
3
Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V,
VVOUT3 = 2.8 V
Rev. 0 | Page 13 of 28
ADP5134
Data Sheet
60
0
VVIN3 = 5V
55
–20
VVIN3 = 3.3V
–40
PSRR (dB)
45
40
–60
–80
35
–100
30
0.01
0.1
1
10
–120
10
11710-039
25
0.001
100
ILOAD (mA)
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 42. LDO PSRR Across Output Load, VVIN3 = 3.3 V, VVOUT3 = 3.0 V
Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage,
VVOUT3 = 2.8 V
65
0
VVIN3 = 5V
60
–20
VVIN3 = 3.3V
55
100µA
1mA
10mA
50mA
100mA
150mA
–40
50
PSRR (dB)
RMS NOISE (µV)
100µA
1mA
10mA
50mA
100mA
150mA
11710-042
RMS NOISE (µV)
50
45
40
–60
–80
35
0.01
0.1
1
ILOAD (mA)
10
–120
10
11710-040
100
0
–20
–10
–20
–30
PSRR (dB)
–40
–50
–60
1M
10M
–50
–60
–70
–80
–80
–90
–90
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 41. LDO PSRR Across Output Load, VVIN3 = 3.3 V, VVOUT3 = 2.8 V
100µA
1mA
10mA
50mA
100mA
150mA
–40
–70
–100
10
10k
100k
FREQUENCY (Hz)
0
100µA
1mA
10mA
50mA
100mA
150mA
11710-041
PSRR (dB)
–30
1k
Figure 43. LDO PSRR Across Output Load, VVIN3 = 5.0 V, VVOUT3 = 2.8 V
Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage,
VVOUT3 = 3.0 V
–10
100
–100
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
11710-044
25
0.001
11710-043
–100
30
Figure 44. LDO PSRR Across Output Load, VVIN3 = 5.0 V, VVOUT3 = 3.0 V
Rev. 0 | Page 14 of 28
Data Sheet
ADP5134
THEORY OF OPERATION
VOUT1 FB1 FB2 VOUT2
GM ERROR
AMP
AVIN
ENBK1
75Ω
75Ω
ENBK2
GM ERROR
AMP
PWM
COMP
PWM
COMP
VIN1
SOFT START
SOFT START
PSM
COMP
PSM
COMP
VIN2
ILIMIT
ILIMIT
LOW
CURRENT
PWM/
PSM
CONTROL
BUCK1
PWM/
PSM
CONTROL
BUCK2
LOW
CURRENT
SW2
SW1
OSCILLATOR
DRIVER
AND
ANTISHOOT
THROUGH
DRIVER
AND
OP
ANTISHOOT
MODE THROUGH
SYSTEM
UNDERVOLTAGE
LOCKOUT
SEL
THERMAL
SHUTDOWN
PGND1
B
PGND2
MODE2
600Ω
ENLDO2
Y
A
MODE
ENBK1
EN2
EN3
ENABLE
AND
MODE
CONTROL
ENBK2
LDO
UNDERVOLTAGE
LOCKOUT
ENLDO1
ENLDO2
EN4
LDO
UNDERVOLTAGE
LOCKOUT
R3
R1
FB1
PG
POWERGOOD
CONTROL
FB2
AVIN
LDO
CONTROL
AVIN
LDO
CONTROL
FB3
FB4
R2
600Ω
ENLDO1
R4
ADP5134
AGND FB3 VOUT3 VIN4
VIN3
FB4
VOUT4
11710-045
EN1
Figure 45. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5134 is a micropower management unit (micro PMU)
combining two step-down (buck) dc-to-dc converters and two
low dropout (LDO) linear regulators. The high switching
frequency and tiny 24-lead LFCSP package provide a small
power management solution.
To combine these high performance regulators into the micro
PMU, there is a system controller allowing them to operate
together.
The buck regulators can operate in forced PWM mode if the
MODE pin is set to logic high. In forced PWM mode, the buck
regulator switching frequency is always constant and does not
change with the load current. If the MODE pin is set to logic
low, the switching regulators operate in automatic PWM/PSM
mode. In this mode, the regulators operate at a fixed PWM
frequency when the load current is above the PSM current
threshold. When the load current falls below the PSM current
threshold, the regulator in question enters PSM mode, where
the switching occurs in bursts. The burst repetition rate is a
function of the current load and the output capacitor value. This
operating mode reduces the switching and quiescent current
losses. The automatic PWM/PSM mode transition is controlled
independently for each buck regulator. The two buck regulators
operate in synchronization with each other.
The ADP5134 has individual enable pins (EN1 to EN4) that
control the activation of each regulator. The regulators are activated by a high logic level applied to the respective ENx pin.
EN1 controls BUCK1, EN2 controls BUCK2, EN3 controls
LDO1, and EN4 controls LDO2.
Regulator output voltages are set through external resistor
dividers or can be optionally factory programmed to default
values (see the Ordering Guide section).
When a regulator is turned on, the output voltage ramp rate is
controlled through a soft start circuit to avoid a large inrush
current due to the charging of the output capacitors.
Rev. 0 | Page 15 of 28
ADP5134
Data Sheet
Power-Good Output
the synchronous rectifier turn off. When the voltage on AVIN
rises above the UVLO threshold, the device is enabled once more.
A power-good output is available at Pin 6 (PG) to monitor the
output voltage of any combination of the four regulators. The PG
output can also be factory programmed to monitor a specific
regulator channel, such as BUCK1, as shown in Figure 46. The PG
pin can connect to a pull-up current to drive external regulators or
other circuits. In this configuration, the PG pin goes high when
the channels monitored are in regulation and goes low when the
output voltage falls below 90% of the nominal VVOUTx level. The
PG pin can also drive an LED for fault monitoring. For example, in
this configuration, a red LED is biased, and current sinks into the
PG pin when the output voltage falls below 90% of the nominal
VVOUTx level. This turns the LED on, and, when the output
voltage is in regulation, turns it off.
Alternatively, the user can request a new device model with a
UVLO set at a higher level, suitable for 5 V supply applications.
For these models, the device reaches the turn-off threshold when
the input supply drops to 3.65 V typical. To order a device with
options other than the default options listed in the Ordering
Guide section, contact your local Analog Devices sales or
distribution representative.
In case of a thermal or UVLO event, the active pull-downs
(unless factory disabled) are enabled to discharge the output
capacitors quickly. The pull-down resistors remain engaged
until the thermal fault event is no longer present or the input
supply voltage falls below the power-on reset voltage (VPOR)
level. The typical value of VPOR is approximately 1 V.
Thermal Protection
In the event that the junction temperature rises above 150°C,
the thermal shutdown circuit turns off all the regulators. Extreme
junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature.
A 20°C hysteresis is included so that when thermal shutdown
occurs, the regulators do not return to operation until the on-chip
temperature drops below 130°C. When coming out of thermal
shutdown, all regulators restart with soft start control.
Precision Enable and Shutdown Control
The ADP5134 has an individual enable control pin for each
regulator. A voltage input to the ENx pin above the VIH_EN level
takes the device out of shutdown and turns on the housekeeping
block of the ADP5134. As the VENx level continues to rise above
the precision enable threshold (VENR), the regulators activate.
When VENx goes 80 mV typical below the VENR level, the regulators
deactivate, and as the VENx level continues to go down below the
VIL_EN level, the device enters shutdown mode. In this mode, the
current consumption of the device falls to below 1 µA.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout (UVLO)
circuitry is integrated into the system. If the input voltage on AVIN
drops below a typical 2.15 V UVLO threshold, all channels shut
down. In the buck regulator channels, both the power switch and
Figure 46 shows the activation timings for the ADP5134 when
regulators are in sequence, VOUT1 controlling EN2, VOUT2
controlling EN3, and VOUT3 controlling EN4. Also shown is
the power-good signal monitoring BUCK1 only.
EN1
PE_GOOD_BUCK1
VOUT_BUCK1
EN2
PE_GOOD_BUCK2
VOUT_BUCK2
EN3
PE_GOOD_LDO1
VOUT_LDO1
EN4
PE_GOOD_LDO2
VOUT_LDO2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
TIME (ms)
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
11710-046
POWER GOOD
Figure 46. Regulator Sequencing on the ADP5134, Shutdown Control and Precision Enable Thresholds with PG Monitoring BUCK1 Only
Rev. 0 | Page 16 of 28
Data Sheet
ADP5134
BUCK1 AND BUCK2
Power Save Mode (PSM)
The buck regulator uses a fixed frequency and high speed current
mode architecture. The buck regulator operates with an input
voltage of 2.5 V to 5.5 V.
The buck regulators smoothly transition to PSM operation when
the load current decreases below the PSM current threshold.
When either of the buck regulators enters PSM, an offset is induced
in the PWM regulation level, which makes the output voltage
rise. When the output voltage reaches a level approximately 1.5%
above the PWM regulation level, PWM operation is turned off.
At this point, both power switches are off, and the buck regulator
enters an idle mode. The output capacitor discharges until the
output voltage falls to the PWM regulation voltage level, at which
point the device drives the inductor to make the output voltage
rise again to the upper threshold. This process is repeated while
the load current is below the PSM current threshold.
The buck regulator output voltage is resistor programmable from
0.8 V to 3.8 V, shown in Figure 47 for BUCK1. The ratio of R1
and R2 multiplied by the feedback voltage determines the voltage
level at output. For example, if R1 and R2 are chosen to have
equal resistance values, the output voltage is set to 1.0 V. The
output voltage can optionally be factory programmed to default
values as indicated in the Ordering Guide section. In this event,
R1 and R2 are not needed, and FB1 can be left unconnected. In
all cases, VOUT1 must be connected to the output capacitor.
FB1 is 0.5 V.
VOUT1
VIN1
SW1
L1
1µH
VOUT1
PSM Current Threshold
BUCK
PGND
VOUT1 = VFB1
R1
C2
10µF
R2
R1
+1
R2
11710-047
FB1
The ADP5134 has a dedicated MODE pin that controls the PSM
and PWM operation. A logic high level applied to the MODE
pin forces both bucks to operate in PWM mode. A low logic level
sets the buck regulators to operate in automatic PSM/PWM mode.
Figure 47. BUCK1 External Output Voltage Setting
Control Scheme
The buck regulators operate with a fixed frequency, current mode
PWM control architecture at medium to high loads for high
efficiency; however, they shift to a power save mode (PSM) control
scheme at light loads to lower the regulation power losses. When
operating in fixed frequency PWM mode, the duty cycle of the
integrated switches is adjusted and regulates the output voltage.
When operating in PSM at light loads, the output voltage is
controlled in a hysteretic manner, with higher output voltage ripple.
During this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the buck regulators operate at a fixed frequency
of 3 MHz, set by an internal oscillator. At the start of each oscillator
cycle, the positive channel field effect transistor (PFET) turns
on, sending a positive voltage across the inductor. Current in the
inductor increases until the current sense signal crosses the
peak inductor current threshold that turns off the PFET switch
and turns on the negative channel field effect transistor (NFET)
synchronous rectifier. When the NFET switches on, it sends a
negative voltage across the inductor, causing the inductor current
to decrease. The synchronous rectifier stays on for the rest of
the cycle. The buck regulator regulates the output voltage by
adjusting the peak inductor current threshold.
The PSM current threshold is set to 100 mA. The buck regulators
employ a scheme that enables this current to remain accurately
controlled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.
Oscillator and Phasing of Inductor Switching
The ADP5134 ensures that both buck regulators operate at the
same switching frequency when both buck regulators are in
PWM mode.
Additionally, the ADP5134 ensures that when both buck regulators
are in PWM mode, they operate out of phase, whereby the BUCK2
PFET starts conducting exactly half a clock period after the BUCK1
PFET starts conducting.
Short-Circuit Protection
The buck regulators include frequency foldback to prevent
output current runaway on a hard short. When the voltage at
the feedback pin falls below half the target output voltage,
indicating the possibility of a hard short at the output, the
switching frequency is reduced to half the internal oscillator
frequency. The reduction in the switching frequency allows
more time for the inductor to discharge, preventing a runaway
of output current.
Buck Regulator Soft Start
The buck regulators have an internal soft start function that ramps
up the output voltage in a controlled manner upon startup, thereby
limiting the inrush current. Limiting the inrush current prevents
possible input voltage drops when a battery or a high impedance
power source is connected to the input of the converter.
Rev. 0 | Page 17 of 28
ADP5134
Data Sheet
Each buck regulator has protection circuitry to limit the amount
of positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
the amount of current that can flow from the input to the output.
The negative current limit prevents the inductor current from
reversing direction and flowing out of the load.
100% Duty Operation
With a drop in input voltage, or with an increase in load current,
the buck regulator may reach a limit where, even with the PFET
switch on 100% of the time, the output voltage drops below the
desired output voltage. At this limit, the buck regulator transitions
to a mode where the PFET switch stays on 100% of the time. When
the input conditions change again and the required duty cycle
falls, the buck immediately restarts PWM regulation without
allowing overshoot on the output voltage.
Each LDO regulator operates with an input voltage of 1.7 V to
5.5 V. The wide operating range makes these LDO regulators
suitable for cascading configurations where the LDO regulator
supply voltage is provided from one of the buck regulators.
Each LDO regulator output voltage is set through the external
resistor dividers shown in Figure 48 for LDO1. The output
voltage can optionally be factory programmed to default values
as indicated in the Ordering Guide section. In this event, R5
and R6 are not needed, and FB3 must be connected to the top of
the capacitor on VOUT3.
VOUT3
VIN3
LDO1
VOUT3 = VFB3
LDO1 AND LDO2
The ADP5134 contains two LDO regulators with low quiescent
current and low dropout linear regulators, and it provides up to
300 mA of output current. Drawing a low 10 μA quiescent current
(typical) at no load makes the LDO regulator ideal for batteryoperated portable equipment.
R5
R6
Active Pull-Down Resistors
All regulators have optional, factory programmable, active pulldown resistors that discharge the respective output capacitors
when the regulators are disabled. The pull-down resistors are
connected between VOUTx and AGND. Active pull-down
resistors are disconnected when the regulators are turned on.
The typical value of the pull-down resistors is 600 Ω for the
LDO regulators and 75 Ω for the buck regulators.
FB3
VOUT3
C7
1µF
R5
+1
R6
11710-048
Current Limit
Figure 48. LDO1 External Output Voltage Setting
The LDO regulators also provide high power supply rejection
ratio (PSRR), low output noise, and excellent line and load
transient response with only a small 1 µF ceramic input and
output capacitor.
LDO1 is optimized to supply the analog circuits because it offers
better noise performance compared to LDO2. Use LDO1 in
applications where noise performance is critical.
LDO Regulator Soft Start
On the ADP5134, the LDO regulators also have an internal soft
start function that ramps up the output voltage in a controlled
manner upon startup, thereby limiting the inrush current. There
are two soft start options, fast and slow, to control how long
the output voltage is ramped up. These options are factory
programmed.
Rev. 0 | Page 18 of 28
Data Sheet
ADP5134
APPLICATIONS INFORMATION
BUCK REGULATOR EXTERNAL COMPONENT
SELECTION
Trade-offs between performance parameters such as efficiency and
transient response can be made by varying the choice of external
components in the applications circuit, as shown in Figure 1.
Feedback Resistors
For the adjustable model, referring to Figure 47, the total
combined resistance for R1 and R2 is not to exceed 400 kΩ.
Inductor
The high switching frequency of the ADP5134 buck regulators
allows the selection of small chip inductors. For best performance,
use inductor values between 0.7 μH and 3 μH. Suggested inductors
are shown in Table 9.
The peak-to-peak inductor current ripple is calculated using the
following equation:
VOUT × (VIN − VOUT )
VIN × f SW × L
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT is 9.2 μF at 1.8 V, as shown in Figure 49.
where:
fSW is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
I PEAK = I LOAD( MAX ) +
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calculated using the following equation:
Substituting these values in the equation yields
CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF
12
I RIPPLE
2
10
CAPACITANCE (µF)
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc resistance
(DCR). Larger sized inductors have smaller DCR, which can
decrease inductor conduction losses. Inductor core losses are
related to the magnetic permeability of the core material. Because
the buck regulators are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its
low core losses and low electromagnetic interference (EMI).
8
6
4
2
0
Output Capacitor
0
1
2
3
4
5
DC BIAS VOLTAGE (V)
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
6
11710-049
I RIPPLE =
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended for best performance.
However, Y5V and Z5U dielectrics are not recommended for
use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
Figure 49. Capacitance vs. Voltage Characteristic
Table 9. Suggested 1.0 μH Inductors
Vendor
Murata
Murata
Murata
Taiyo Yuden
Coilcraft®
Coilcraft
Toko
Model
LQM2MPN1R0NG0B
LQM2HPN1R0MJ0L
LQH32PN1R0NN0
CBC3225T1R0MR
XFL4020-102ME
XPL2010-102ML
MDT2520-CN
Dimensions (mm)
2.0 × 1.6 × 0.9
2.5 × 2.0 × 1.1
3.2 × 2.5 × 1.6
3.2 × 2.5 × 2.5
4.0 × 4.0 × 2.1
1.9 × 2.0 × 1.0
2.5 × 2.0 × 1.2
Rev. 0 | Page 19 of 28
ISAT (mA)
1400
1500
2300
2000
5400
1800
1350
DCR (mΩ)
85
90
45
71
11
89
85
ADP5134
Data Sheet
To guarantee the performance of the buck regulators, it is imperative that the effects of dc bias, temperature, and tolerances on
the behavior of the capacitors be evaluated for each application.
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
VRIPPLE =
I RIPPLE
VIN
≈
8 × f SW × COUT (2π × f SW )2 × L × COUT
VRIPPLE
I RIPPLE
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 7 µF and a
maximum of 40 µF.
The buck regulators require 10 µF output capacitors to guarantee stability and response to rapid load variations and to transition
into and out of the PWM/PSM modes. A list of suggested capacitors is shown in Table 10. In certain applications where one or
both buck regulators power a processor, the operating state is
known because it is controlled by software. In this condition,
the processor can drive the MODE pin according to the operating
state; consequently, it is possible to reduce the output capacitor
from 10 µF to 4.7 µF because the regulator does not expect a
large load variation when working in PSM mode (see Figure 50).
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response. Maximum input
capacitor current is calculated using the following equation:
I CIN ≥ I LOAD ( MAX )
VOUT (VIN − VOUT )
VIN
To minimize supply noise, place the input capacitor as close as
possible to the VINx pin of the buck regulator. As with the
output capacitor, a low ESR capacitor is recommended.
The effective capacitance needed for stability, which includes
temperature and dc bias effects, is a minimum of 3 µF and a
maximum of 10 µF. The recommended range is from 4.7 µF to
10 µF to compensate for any capacitance losses for the buck
regulator input and output capacitors. A list of suggested
capacitors is shown in Table 10 and Table 11.
Table 10. Suggested 10 μF Capacitors
Vendor
Murata
TDK
Taiyo Yuden
Panasonic
Type
X5R
X5R
X5R
X5R
Model
GRM188R60J106
C1608JB0J106K
JMK107BJ106MA-T
ECJ-1VB0J106M
Case
Size
0603
0603
0603
0603
Vendor
Murata
Taiyo Yuden
Panasonic
Type
X5R
X5R
X5R
Model
GRM188R60J475ME19D
JMK107BJ475
ECJ-0EB0J475M
Case
Size
0603
0603
0402
Voltage
Rating (V)
6.3
6.3
6.3
LDO REGULATOR EXTERNAL COMPONENT
SELECTION
Feedback Resistors
Capacitors with lower effective series resistance (ESR) are
preferred to guarantee low output voltage ripple, as shown in
the following equation:
ESRCOUT ≤
Table 11. Suggested 4.7 μF Capacitors
Voltage
Rating (V)
6.3
6.3
6.3
6.3
For the adjustable model, the maximum value of R6 is not to
exceed 200 kΩ (see Figure 48).
Output Capacitor
The ADP5134 LDO regulators are designed for operation with
small, space-saving ceramic capacitors; however, they function
with most commonly used capacitors as long as care is taken
with the ESR value. The ESR of the output capacitor affects
stability of the LDO control loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure the
stability of the ADP5134. Transient response to changes in load
current is also affected by output capacitance. Using a larger value
of output capacitance improves the transient response of the
ADP5134 to large changes in load current.
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN3 and VIN4 to ground
reduces the circuit sensitivity to printed circuit board (PCB)
layout, especially when long input traces or high source impedance is encountered. A list of 1.0 µF output capacitors is shown
in Table 12. If greater than 1.0 µF of output capacitance is
required, increase the input capacitor to match it.
Table 12. Suggested 1.0 μF Capacitors
Vendor
Murata
Murata
TDK
Panasonic
Taiyo Yuden
Type
X5R
X5R
X5R
X5R
X5R
Model
GRM155B30J105K
GRM155R61A105KE15D
C1005JB0J105K
ECJ0EB0J105K
LMK105BJ105MV-F
Case
Size
0402
0402
0402
0402
0402
Voltage
Rating (V)
6.3
10.0
6.3
6.3
10.0
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5134 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with a different behavior over temperature
and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a
voltage rating of 6.3 V or 10 V are recommended for best performance. However, Y5V and Z5U dielectrics are not recommended
for use with any LDO because of their poor temperature and dc
bias characteristics.
Rev. 0 | Page 20 of 28
Data Sheet
ADP5134
VDDIO
10
VIN
2.5V TO
5.5V
VIN1
C1
4.7µF
16
15
BUCK1
1.2A
ON
OFF
EN1
11
14
12
13
VIN2
3
C3
4.7µF
ON
OFF
EN2
C5
0.1µF
VIN3
ON
OFF
8
17
EN3
VIN4
ON
21
20
19
FB1
PGND1
VIO
R1
C2
10µF
R2
MODE
GPOx
VOUT2
SW2
FB2
PGND2
L2 1µH
VCORE
R3
C4
10µF
R4
VOUT3
FB3
VMEM
R5
C7
1µF
R6
22
23
LDO2
300mA
EN4
SW1
L1 1µH
HOUSEKEEPING
LDO1
300mA
C8
1µF
OFF
4
7
C6
1µF
VINLDO2
1.7V TO
5.5V
BUCK2
1.2A
5
AVIN
VINLDO1
1.7V TO
5.5V
MODE
9
PROCESSOR/FPGA
VOUT1
24
1
VOUT4
FB4
VAUX
R7
C9
1µF
R8
2
VDDIO
POWER GOOD
R1
100kΩ
PG
GPIx
6
ADP5134
11710-050
18
AGND
Figure 50. Processor System Power Management with PSM/PWM Control and PG
Figure 51 depicts the capacitance vs. dc bias voltage characteristic
of a 0402 size, 1 µF, 10 V, X5R capacitor. The voltage stability of
a capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or with higher
voltage rating exhibits better stability. The temperature variation of
the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.
1.2
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
CBIAS is 0.85 μF at 1.8 V, as shown in Figure 51.
1.0
0.8
Substituting these values into the following equation,
0.6
CEFF = 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF
0.4
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO regulator
over temperature and tolerance at the chosen output voltage.
0.2
0
0
1
2
3
4
DC BIAS VOLTAGE (V)
5
Figure 51. Capacitance vs. DC Bias Voltage Characteristic
6
11710-051
CAPACITANCE (µF)
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature,
component tolerance, and voltage:
To guarantee the performance of the ADP5134, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
Rev. 0 | Page 21 of 28
ADP5134
Data Sheet
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The ADP5134 is a highly efficient micro PMU, and, in most
cases, the power dissipated in the device is not a concern.
However, if the device operates at high ambient temperatures
and maximum loading condition, the junction temperature can
reach the maximum allowable operating limit (125°C).
When the temperature exceeds 150°C, the ADP5134 turns off
all the regulators, allowing the device to cool down. When the
die temperature falls below 130°C, the ADP5134 resumes
normal operation.
This section provides guidelines to calculate the power dissipated in the device and ensure that the ADP5134 operates
below the maximum allowable junction temperature.
The power loss of the buck regulator is approximated by
PLOSS = PDBUCK + PL
(3)
where:
PDBUCK is the power dissipation on one of the ADP5134 buck
regulators.
PL is the inductor power losses.
The inductor power losses are external to the device, and they
do not have any effect on the die temperature.
The inductor power losses are estimated (without core losses) by
PL ≈ IVOUT1(RMS)2 × DCRL
The efficiency for each regulator on the ADP5134 is given by
P
η = OUT × 100%
PIN
BUCK REGULATOR POWER DISSIPATION
(1)
where:
η is the efficiency.
POUT is the output power.
PIN is the input power.
(4)
where:
IVOUT1(RMS) is the rms load current of the buck regulator.
DCRL is the inductor series resistance.
I VOUT 1( RMS ) = I VOUT1 × 1 +
r
12
(5)
where r is the normalized inductor ripple current.
r = VVOUT1 × (1 − D)/(IVOUT1 × L × fSW)
Power loss is given by
PLOSS = PIN − POUT
(2a)
PLOSS = POUT (1− η)/η
(2b)
or
Power dissipation can be calculated in several ways. The most
intuitive and practical method is to measure the power dissipated
at the input and all the outputs. Perform the measurements at
the worst-case conditions (voltages, currents, and temperature).
The difference between input and output power is dissipated in
the device and the inductor. Use Equation 4 to derive the power
lost in the inductor and, from this, use Equation 3 to calculate
the power dissipation in the ADP5134 buck converter.
A second method to estimate the power dissipation uses the
efficiency curves provided for the buck regulator, and the power
lost on each LDO regulator can be calculated using Equation 12.
When the buck regulator efficiency is known, use Equation 2b
to derive the total power lost in the buck regulator and inductor,
use Equation 4 to derive the power lost in the inductor, and then
calculate the power dissipation in the buck converter using
Equation 3. Add the power dissipated in the buck regulator and
in the two LDO regulators to find the total dissipated power.
Note that the efficiency curves of the buck regulator are typical
values and may not be provided for all possible combinations of
VVINx, VVOUTx, and IVOUTx. To account for these variations, it is
necessary to include a safety margin when calculating the power
dissipated in the buck regulator.
A third way to estimate the power dissipation is analytical and
involves modeling the losses in the buck regulator circuit provided
by Equation 8 to Equation 11 and the losses in the LDO regulator
provided by Equation 12.
(6)
where:
L is the inductance.
fSW is the switching frequency.
D is the duty cycle.
D = VVOUT1/VVIN1
(7)
The buck regulator power dissipation, PDBUCK, of the ADP5134
includes power switch conductive losses, switch losses, and
transition losses of each channel. There are other sources of loss;
however, these are generally less significant at high output load
currents where the thermal limit of the application is. Equation 8
captures the calculation that can estimate the power dissipation
in the buck regulator.
PDBUCK = PCOND + PSW + PTRAN
(8)
The power switch conductive losses are due to the output current,
IVOUT1, flowing through the P-channel MOSFET and the N-channel
MOSFET power switches that have internal resistance, RDSON-P
and RDSON-N, respectively. The amount of conductive power loss
is found by
PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IVOUT1(RMS)2
(9)
where:
RDSON-P is approximately 0.2 Ω.
RDSON-N is approximately 0.16 Ω.
The RDSON-P and RDSON-N values are correct given that VIN1 =
VIN2 = 3.6 V, at a junction temperature of 25°C.
At VIN1 = VIN2 = 2.5 V, these values change to 0.31 Ω and 0.21 Ω,
respectively, and at VIN1 = VIN2 = 5.5 V, the values are 0.16 Ω
and 0.14 Ω, respectively.
Rev. 0 | Page 22 of 28
Data Sheet
ADP5134
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
PSW = (CGATE-P + CGATE-N) × VVIN12 × fSW
(10)
where:
CGATE-P is the P-channel MOSFET gate capacitance.
CGATE-N is the N-channel MOSFET gate capacitance.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SWx node takes some time to slew from near ground to near
VVOUTx (and from VVOUTx to ground). The amount of transition
loss is calculated by
(11)
where tRISE and tFALL are the rise time and the fall time of the
switching node, SWx. For the ADP5134, the rise and fall times
of SWx are approximately 5 ns.
If Equation 1 through Equation 11 and their associated parameters
are used for estimating the converter efficiency, note that the
equations do not describe all of the converter losses, and the
parameter values given are typical numbers. The converter performance also depends on the choice of passive components and
board layout; therefore, include a sufficient safety margin in the
estimate.
LDO Regulator Power Dissipation
The power loss of an LDO regulator is given by
PDLDO = [(VVINx − VVOUTx) × ILOAD] + (VVINx × IGND)
In cases where the board temperature, TA, is known, the thermal
resistance parameter, θJA, can be used to estimate the junction
temperature rise. TJ is calculated from TA and PD using the formula
TJ = TA + (PD × θJA)
For the ADP5134, the total of (CGATE-P + CGATE-N) is
approximately 150 pF.
PTRAN = VVINx × IVOUTx × (tRISE + tFALL) × fSW
JUNCTION TEMPERATURE
(12)
where:
VVINx and VVOUTx are the input and output voltages of the LDO
regulator, respectively.
ILOAD is the load current of the LDO regulator.
IGND is the ground current of the LDO regulator.
Refer to Table 7 for the thermal resistance values. A very important
factor to consider is that θJA is based on a 4-layer, 4 in × 3 in,
2.5 oz copper board, as per JEDEC standard, and real applications
can use different sizes and layers. It is important to maximize
the copper used to remove the heat from the device. Copper
exposed to air dissipates heat better than copper used in the
inner layers. Connect the exposed pad to the ground plane with
several vias.
If the case temperature is measured, the junction temperature is
calculated by
TJ = TC + (PD × θJC)
(15)
where:
TC is the case temperature.
θJC is the junction-to-case thermal resistance provided in Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5134 power
dissipation (PD) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
junction temperature, TJ, can be estimated using Equation 14.
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5134 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBFs) are highly affected by
increasing the junction temperature. Additional information
about product reliability can be found in the ADI Reliability
Handbook at www.analog.com/UG-311.
Power dissipation due to the ground current is small, and it
can be ignored.
The total power dissipation in the ADP5134 simplifies to
PD = PDBUCK1 + PDBUCK2 + PDLDO1 + PDLDO2
(14)
(13)
Rev. 0 | Page 23 of 28
ADP5134
Data Sheet
PCB LAYOUT GUIDELINES
Poor layout can affect the performance of the ADP5134, causing
EMI and electromagnetic compatibility (EMC) problems,
ground bounce, and voltage losses. Poor layout can also affect
regulation and stability. A good layout is implemented using the
following guidelines. Also, refer to the User Guide UG-591,
Evaluating the ADP5134 Micropower Management Unit (PMU).
•
Place the inductor, input capacitor, and output capacitor
near the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
•
•
•
•
Rev. 0 | Page 24 of 28
Route the output voltage path away from the inductor and
SWx node to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise interference
on sensitive circuit nodes.
Connect VIN1, VIN2, and AVIN together near the IC
using short tracks.
Data Sheet
ADP5134
TYPICAL APPLICATION SCHEMATICS
10
VIN1
C1
4.7µF
ON
OFF
16
15
BUCK1
1.2A
EN1
11
14
12
VIN2
3
C3
4.7µF
ON
OFF
EN2
AVIN
BUCK2
1.2A
4
8
7
VIN3
17
L1 1µH
FB1
C2
10µF
PGND1
ON
OFF
EN3
VIN4
C8
1µF
ON
EN4
MODE
AUTO
VOUT2
SW2
L2 1µH
FB2
C4
10µF
PGND2
HOUSEKEEPING
21
C6
1µF
OFF
MODE
9
5
C5
0.1µF
VINLDO2
1.7V TO
5.5V
SW1
MWM
13
VINLDO1
1.7V TO
5.5V
VOUT1
LDO1
300mA
20
LDO2
300mA
24
19
VOUT3
FB3
C7
1µF
22
23
1
VOUT4
FB4
C9
1µF
2
VDDIO
POWER GOOD
PG
R1
100kΩ
6
18
ADP5134
AGND
Figure 52. ADP5134 Fixed Output Voltages with Enable Pins
Rev. 0 | Page 25 of 28
11710-052
VIN
2.5V TO
5.5V
ADP5134
Data Sheet
10
VIN
2.5V TO
5.5V
VIN1
C1
4.7µF
ON
OFF
16
15
BUCK1
1.2A
EN1
11
14
12
VIN2
3
C3
4.7µF
ON
OFF
EN2
AVIN
BUCK2
1.2A
4
8
7
VIN3
17
FB1
PGND1
L1 1µH
R1
C2
10µF
R2
ON
OFF
VIN4
C8
1µF
ON
20
LDO1
300mA
EN3
19
PSM/PWM
VOUT2
SW2
FB2
PGND2
L2 1µH
R3
C4
10µF
R4
VOUT3
FB3
R5
C7
1µF
R6
22
23
LDO2
300mA
EN4
MODE
HOUSEKEEPING
21
C6
1µF
OFF
MODE
9
5
C5
0.1µF
VINLDO2
1.7V TO
5.5V
SW1
MWM
13
VINLDO1
1.7V TO
5.5V
VOUT1
24
1
VOUT4
FB4
2
R7
C9
1µF
R8
VDDIO
POWER GOOD
PG
R1
100kΩ
6
ADP5134
11710-053
18
AGND
Figure 53. ADP5134 Adjustable Output Voltages with Enable Pins
BILL OF MATERIALS
Table 13.
Reference
C5
C6, C7, C8, C9
C1, C3
C2, C4
L1, L2
IC1
Value
0.1 µF, X5R, 6.3 V
1 µF, X5R, 6.3 V
4.7 µF, X5R, 6.3 V
10 µF, X5R, 6.3 V
1 µH, 0.18 Ω, 850 mA
1 µH, 0.085 Ω, 1400 mA
1 µH, 0.09 Ω, 1500 mA
1 µH, 0.089 Ω, 1800 mA
1 µH, 0.086 Ω, 1350 mA
Four-regulator micro PMU
Part Number
GRM155R71C104KA88D
GRM155R60J105KE19D
GRM155R60J475ME87D
GRM188R60J106ME47D
GRM155R60J105KE19D
LQM2MPN1R0NG0B
LQM2HPN1R0MJ0L
XPL2010-102ML
MDT2520-CN
ADP5134
Rev. 0 | Page 26 of 28
Vendor
Murata
Murata
Murata
Murata
Murata
Murata
Murata
Coilcraft
Toko
Analog Devices, Inc.
Package or Dimension (mm)
0402
0402
0402
0603
0603
2.0 × 1.6 × 0.9
2.5 × 2.0 × 1.1
1.9 × 2.0 × 1.0
2.5 × 2.0 × 1.2
24-lead LFCSP
Data Sheet
ADP5134
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.50
0.40
0.30
0.80
0.75
0.70
13
12
2.65
2.50 SQ
2.45
6
7
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
04-12-2012-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5134ACPZ-R7
Temperature
Range
−40°C to +125°C
Output
Voltage (V)2
Adjustable
UVLO 3
Low
Active
Pull-Down 4
Enabled on All
Channels
ADP5134CP-EVALZ
Power
Good 5
BUCK1
Package Description
24-Lead LFCSP_WQ
Evaluation Board
Z = RoHS Compliant Part.
For additional options, contact a local sales or distribution representative. Additional options available are:
BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, or adjustable.
LDO1 and LDO2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2.0 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V, or adjustable.
3
UVLO: low or high. To order a device with other than the default options listed, contact your local Analog Devices sales or distribution representative.
4
BUCK1, BUCK2, LDO1, and LDO2: Active pull-down resistor is programmable to be either enabled or disabled.
5
Regulator channels selected for power good monitoring.
1
2
Rev. 0 | Page 27 of 28
Package
Option
CP-24-7
ADP5134
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11710-0-10/13(0)
Rev. 0 | Page 28 of 28
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