5 4 3 2 1 D D C C B B A A Actel Corporation Title Size C Date: 5 4 3 2 Actel Confidential MPU Platform Demo Board Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 1 of 6 4 3 FPGA_USER_SW1 FPGA_USER_SW2 FPGA_USER_SW3 FPGA_USER_SW4 FPGA_USER_SW5 FPGA_USER_SW6 FPGA_USER_SW7 FPGA_USER_SW8 IO BANK 5 IO BANK 7 IO BANK 7 IO BANK 5 IO BANK 5 IO BANK 7 IO BANK 7 IO BANK 5 IO BANK 6 IO BANK 8 IO BANK 3 IO_Y10 IO_Y12 IO_AA7 IO_AA8 IO_AA9 IO_AA10 IO_AA11 IO_AA12 IO_AA13 IO_AB8 IO_AB9 IO_AB10 IO_AB11 IO_AB12 IO_AB13 IO_AC6 IO_AC7 IO_AC8 IO_AC10 IO_AC11 IO_AC12 IO_AC13 IO_AD4 IO_AD5 IO_AD6 IO_AD7 IO_AD8 IO_AD9 IO_AD10 IO_AD11 IO_AD12 IO_AD13 IO_AE4 IO_AE5 IO_AE6 IO_AE7 IO_AE8 IO_AE9 IO_AE10 IO_AE11 IO_AE12 IO_AE13 IO_AF5 IO_AF6 IO_AF7 IO_AF8 IO_AF9 IO_AF10 IO_AF11 IO_AF12 IO_AF13 FPGA_MEM_A0 FPGA_MEM_A1 FPGA_MEM_A2 FPGA_MEM_A3 FPGA_MEM_A4 FPGA_MEM_A5 FPGA_MEM_A6 FPGA_MEM_A7 FPGA_MEM_A8 FPGA_MEM_A9 FPGA_MEM_A10 FPGA_MEM_A11 FPGA_MEM_A12 FPGA_MEM_A13 FPGA_MEM_A14 FPGA_MEM_A15 FPGA_MEM_A16 FPGA_MEM_A17 FPGA_MEM_A18 FPGA_MEM_A19 FPGA_MEM_A20 FPGA_MEM_A21 FPGA_MEM_DQ0 FPGA_MEM_DQ1 FPGA_MEM_DQ2 FPGA_MEM_DQ3 FPGA_MEM_DQ4 FPGA_MEM_DQ5 FPGA_MEM_DQ6 FPGA_MEM_DQ7 FPGA_MEM_DQ8 FPGA_MEM_DQ9 FPGA_MEM_DQ10 FPGA_MEM_DQ11 FPGA_MEM_DQ12 FPGA_MEM_DQ13 FPGA_MEM_DQ14 FPGA_MEM_DQ15 FPGA_MEM_DQ16 FPGA_MEM_DQ17 FPGA_MEM_DQ18 FPGA_MEM_DQ19 FPGA_MEM_DQ20 FPGA_MEM_DQ21 FPGA_MEM_DQ22 FPGA_MEM_DQ23 FPGA_MEM_DQ24 FPGA_MEM_DQ25 FPGA_MEM_DQ26 FPGA_MEM_DQ27 FPGA_MEM_DQ28 FPGA_MEM_DQ29 FPGA_MEM_DQ30 FPGA_MEM_DQ31 IO_D1 IO_D2 IO_E1 IO_E2 IO_E3 IO_E4 IO_F1 IO_F2 IO_F3 IO_F4 IO_G1 IO_G2 IO_G3 IO_G4 IO_G5 IO_H1 IO_H2 IO_H3 IO_H4 IO_H5 IO_H6 IO_J1 IO_J2 IO_J3 IO_J4 IO_J5 IO_J6 IO_K1 IO_K2 IO_K3 IO_K4 IO_K5 IO_K6 IO_K7 IO_L1 IO_L2 IO_L3 IO_L4 IO_L5 IO_L6 IO_M1 IO_M2 IO_M3 IO_M4 IO_M5 IO_M6 IO_M7 IO_N4 IO_N6 D1 D2 E1 E2 E3 E4 F1 F2 F3 F4 G1 G2 G3 G4 G5 H1 H2 H3 H4 H5 H6 J1 J2 J3 J4 J5 J6 K1 K2 K3 K4 K5 K6 K7 L1 L2 L3 L4 L5 L6 M1 M2 M3 M4 M5 M6 M7 N4 N6 FPGA_1553B_RXDAp FPGA_1553B_RXDAn FPGA_1553B_RXDBp FPGA_1553B_RXDBn FPGA_1553B_TXDAp FPGA_1553B_TXDAn FPGA_1553B_TXDBp FPGA_1553B_TXDBn FPGA_1553B_TXINHIBITA FPGA_1553B_TXINHIBITB FPGA_1553B_RXSTROBEA FPGA_1553B_RXSTROBEB FPGA_OPPINS1 FPGA_OPPINS2 FPGA_OPPINS3 FPGA_OPPINS4 FPGA_HDR_TCK FPGA_HDR_TDI FPGA_HDR_TDO FPGA_HDR_TMS FPGA_HDR_TRST FPGA_FLASH_STS FPGA_FLASH_CE FPGA_FLASH_OE FPGA_FLASH_WE FPGA_FLASH_RP FPGA_FLASH_BYTE FPGA_MEM_DP0 FPGA_MEM_DP1 FPGA_MEM_DP2 FPGA_MEM_DP3 A1 A2 A25 A26 B1 B2 B3 B4 B25 B26 C1 C2 C3 C4 D3 F5 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11 L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 AA6 AA22 AA23 AB6 AB7 AC5 AC9 AE1 AE2 AE3 AE25 AE26 AF1 AF2 AF3 AF4 AF25 AF26 GND__A1 GND__A2 GND_A25 GND_A26 GND__B1 GND__B2 GND__B3 GND__B4 GND_B25 GND_B26 GND__C1 GND__C2 GND__C3 GND__C4 GND__D3 GND__F5 GND_K10 GND_K11 GND_K12 GND_K13 GND_K14 GND_K15 GND_K16 GND_K17 GND_L10 GND_L11 GND_L12 GND_L13 GND_L14 GND_L15 GND_L16 GND_L17 GND_M10 GND_M11 GND_M12 GND_M13 GND_M14 GND_M15 GND_M16 GND_M17 GND_N10 GND_N11 GND_N12 GND_N13 GND_N14 GND_N15 GND_N16 GND_N17 GND_P10 GND_P11 GND_P12 GND_P13 GND_P14 GND_P15 GND_P16 GND_P17 GND_R10 GND_R11 GND_R12 GND_R13 GND_R14 GND_R15 GND_R16 GND_R17 GND_T10 GND_T11 GND_T12 GND_T13 GND_T14 GND_T15 GND_T16 GND_T17 GND_U10 GND_U11 GND_U12 GND_U13 GND_U14 GND_U15 GND_U16 GND_U17 GND_AA6 GND_AA22 GND_AA23 GND_AB6 GND_AB7 GND_AC5 GND_AC9 GND_AE1 GND_AE2 GND_AE3 GND_AE25 GND_AE26 GND_AF1 GND_AF2 GND_AF3 GND_AF4 GND_AF25 GND_AF26 D23 E5 F8 G21 Y6 AA20 AB23 AC4 GNDQ_D23 GNDQ_E5 GNDQ_F8 GNDQ_G21 GNDQ_Y6 GNDQ_AA20 GNDQ_AB23 GNDQ_AC4 F21 G6 N2 P26 Y21 AA5 APA600_FG676 APA600_FG676 COMP_PLL_F21 COMP_PLL_G6 COMP_PLL_N2 COMP_PLL_P26 COMP_PLL_Y21 COMP_PLL_AA5 G8 H8 H19 H20 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 K9 K18 L9 L18 M9 M18 N9 N18 P9 P18 R9 R18 T9 T18 U9 U18 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 W7 W8 W19 Y19 VDDP_H9 VDDP_H10 VDDP_H11 VDDP_H12 VDDP_H13 H9 H10 H11 H12 H13 VMV_D4 H14 H15 H16 H17 H18 G19 VMV_F20 F20 VDDP_J19 VDDP_K19 VDDP_L19 VDDP_M19 VDDP_N19 J19 K19 L19 M19 N19 VMV_C24 C24 VDDP_P19 VDDP_R19 VDDP_T19 VDDP_U19 VDDP_V19 VDDP_W20 P19 R19 T19 U19 V19 W20 VMV_AC24 AC24 VDDP_W14 VDDP_W15 VDDP_W16 VDDP_W17 VDDP_W18 W14 W15 W16 W17 W18 VMV_AB20 AB20 VDDP_W13 VDDP_W12 VDDP_W11 VDDP_W10 VDDP_W9 VDDP_Y8 W13 W12 W11 W10 W9 Y8 VMV_Y7 1 2 2.5V to CORE HEADER2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C43 C44 C45 C46 C47 C48 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D V3_3 V3_3 C D4 VDDP_H14 VDDP_H15 VDDP_H16 VDDP_H17 VDDP_H18 VDDP_G19 HEADER8 1 2 3 4 5 6 7 8 P8 R8 T8 U8 V8 VMV_AD3 AD3 VDDP_H7 VDDP_J8 VDDP_K8 VDDP_L8 VDDP_M8 VDDP_N8 H7 J8 K8 L8 M8 N8 VMV_G7 G7 VPP VPN GND TCK TDI TDO TMS RCK J2 J3 U1C Y7 VDDP_P8 VDDP_R8 VDDP_T8 VDDP_U8 VDDP_V8 BUIN_GL_N1 ADIP_GL_N22 BUIN_GL_N25 ADIP_GL_P1 N1 N22 N25 P1 AUIN_NPECL_N5 AUIN_NPECL_N24 N5 N24 AUIP_PPECL_P5 AUIP_PPECL_P24 P5 P24 BUIP_IO_GLMX_N3 BUIP_IO_GLMX_P22 2 VDDP_2 NC_1 1 4 VDDP_4 NC_3 3 6 VPP NC_5 5 8 VPN GND_7 7 10 GND_10 GND_9 9 12 TCK GND_11 11 14 TDI NC_13 13 16 TDO NC_15 15 18 TMS GND_17 17 20 RCK GND_19 19 22 TRST NC_21 21 24 VDD_24 NC_23 23 26 VDD_26 NC_25 25 CLK_25MHZ CLK_16MHZ FPGA_DBC_GCLK FPGA_RESET J4 NPECL_N5 NPECL_N24 PPECL_P5 PPECL_P24 GLMX_N3 GLMX_P22 N3 P22 1 2 3 4 5 6 VJTAG_RCK AC23 HEADER6 TCK TRST TMS TDI TDO AB21 AB22 AC22 AD23 AA21 B FlashPRO Connector APA600_FG676 0 R1 0 R2 FPGA_VDD_CORE FPGA_VDD_PAD FPGA_VPN FPGA_VPP VCC_PLL_E22 VCC_PLL_F6 VCC_PLL_P2 VCC_PLL_P25 VCC_PLL_Y22 VCC_PLL_AB5 E22 F6 P2 P25 Y22 AB5 VPP_Y20 Y20 VPN_AD24_IO A J1 VDD_G8 VDD_H8 VDD_H19 VDD_H20 VDD_J9 VDD_J10 VDD_J11 VDD_J12 VDD_J13 VDD_J14 VDD_J15 VDD_J16 VDD_J17 VDD_J18 VDD_K9 VDD_K18 VDD_L9 VDD_L18 VDD_M9 VDD_M18 VDD_N9 VDD_N18 VDD_P9 VDD_P18 VDD_R9 VDD_R18 VDD_T9 VDD_T18 VDD_U9 VDD_U18 VDD_V9 VDD_V10 VDD_V11 VDD_V12 VDD_V13 VDD_V14 VDD_V15 VDD_V16 VDD_V17 VDD_V18 VDD_W7 VDD_W8 VDD_W19 VDD_Y19 IO BANK 8 FPGA_MEM_FT FPGA_MEM_E FPGA_MEM_G FPGA_MEM_BA FPGA_MEM_BB FPGA_MEM_BC FPGA_MEM_BD FPGA_MEM_BW FPGA_MEM_GW FPGA_MEM_ADSC FPGA_MEM_ADSP FPGA_MEM_ADV FPGA_MEM_ZZ FPGA_MEM_LBO FPGA_MEM_CLK Y10 Y12 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AB8 AB9 AB10 AB11 AB12 AB13 AC6 AC7 AC8 AC10 AC11 AC12 AC13 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 IO BANK 6 FPGA_EE_SPI_S FPGA_EE_SPI_Q FPGA_EE_SPI_W FPGA_EE_SPI_HOLD FPGA_EE_SPI_C FPGA_EE_SPI_D FPGA_EE_I2C_EN FPGA_EE_I2C_WC FPGA_EE_I2C_SCL FPGA_EE_I2C_SDA IO BANK 8 FPGA_LED0 FPGA_LED1 FPGA_LED2 FPGA_LED3 FPGA_LED4 FPGA_LED5 FPGA_KEYPAD1 FPGA_KEYPAD2 FPGA_KEYPAD3 FPGA_KEYPAD4 FPGA_KEYPAD5 IO BANK 8 FPGA_DBC_IO68 FPGA_DBC_IO67 FPGA_DBC_IO66 FPGA_DBC_IO65 FPGA_DBC_IO64 FPGA_DBC_IO63 FPGA_DBC_IO62 FPGA_DBC_IO61 FPGA_DBC_IO60 FPGA_DBC_IO59 FPGA_DBC_IO58 FPGA_DBC_IO57 FPGA_DBC_IO56 FPGA_DBC_IO55 FPGA_DBC_IO54 FPGA_DBC_IO53 FPGA_DBC_IO52 FPGA_DBC_IO51 FPGA_DBC_IO50 IO BANK 6 IO BANK 1 IO BANK 3 IO BANK 3 IO BANK 1 IO BANK 1 IO BANK 3 IO BANK 4 IO BANK 2 IO BANK 2 IO BANK 4 IO BANK 4 IO BANK 2 FPGA_ADC_DIN FPGA_ADC_SCLK FPGA_ADC_CS FPGA_ADC_DOUT FPGA_ADC_SSTRB P3 P4 P6 P7 R1 R2 R3 R4 R5 R6 T1 T2 T3 T4 T5 T6 T7 U1 U2 U3 U4 U5 U6 V1 V2 V3 V4 V5 V6 V7 W1 W2 W3 W4 W5 W6 Y1 Y2 Y3 Y4 Y5 AA1 AA2 AA3 AA4 AB1 AB2 AB3 AB4 AC1 AC2 AC3 AD1 AD2 1 V2_5 U1D IO_P3 IO_P4 IO_P6 IO_P7 IO_R1 IO_R2 IO_R3 IO_R4 IO_R5 IO_R6 IO_T1 IO_T2 IO_T3 IO_T4 IO_T5 IO_T6 IO_T7 IO_U1 IO_U2 IO_U3 IO_U4 IO_U5 IO_U6 IO_V1 IO_V2 IO_V3 IO_V4 IO_V5 IO_V6 IO_V7 IO_W1 IO_W2 IO_W3 IO_W4 IO_W5 IO_W6 IO_Y1 IO_Y2 IO_Y3 IO_Y4 IO_Y5 IO_AA1 IO_AA2 IO_AA3 IO_AA4 IO_AB1 IO_AB2 IO_AB3 IO_AB4 IO_AC1 IO_AC2 IO_AC3 IO_AD1 IO_AD2 IO BANK 7 FPGA_DBC_IO49 FPGA_DBC_IO48 FPGA_DBC_IO47 FPGA_DBC_IO46 FPGA_DBC_IO45 FPGA_DBC_IO44 FPGA_DBC_IO43 FPGA_DBC_IO42 FPGA_DBC_IO41 FPGA_DBC_IO40 FPGA_DBC_IO39 FPGA_DBC_IO38 FPGA_DBC_IO37 FPGA_DBC_IO36 FPGA_DBC_IO35 FPGA_DBC_IO34 FPGA_DBC_IO33 FPGA_DBC_IO32 FPGA_DBC_IO31 FPGA_DBC_IO30 FPGA_DBC_IO29 FPGA_DBC_IO28 FPGA_DBC_IO27 FPGA_DBC_IO26 FPGA_DBC_IO25 FPGA_DBC_IO24 FPGA_DBC_IO23 FPGA_DBC_IO22 FPGA_DBC_IO21 FPGA_DBC_IO20 FPGA_DBC_IO19 FPGA_DBC_IO18 FPGA_DBC_IO17 FPGA_DBC_IO16 FPGA_DBC_IO15 FPGA_DBC_IO14 FPGA_DBC_IO13 FPGA_DBC_IO12 FPGA_DBC_IO11 FPGA_DBC_IO10 FPGA_DBC_IO9 FPGA_DBC_IO8 FPGA_DBC_IO7 FPGA_DBC_IO6 FPGA_DBC_IO5 FPGA_DBC_IO4 FPGA_DBC_IO3 FPGA_DBC_IO2 FPGA_DBC_IO1 FPGA_IRDA_16XCLK FPGA_IRDA_TXD FPGA_IRDA_RCV FPGA_IRDA_NRST FPGA_IRDA_SD IO_Y14 IO_Y16 IO_Y18 IO_AA14 IO_AA15 IO_AA16 IO_AA17 IO_AA18 IO_AA19 IO_AB14 IO_AB15 IO_AB16 IO_AB17 IO_AB18 IO_AB19 IO_AC14 IO_AC15 IO_AC16 IO_AC17 IO_AC18 IO_AC19 IO_AC20 IO_AC21 IO_AD14 IO_AD15 IO_AD16 IO_AD17 IO_AD18 IO_AD19 IO_AD20 IO_AD21 IO_AD22 IO_AE14 IO_AE15 IO_AE16 IO_AE17 IO_AE18 IO_AE19 IO_AE20 IO_AE21 IO_AE22 IO_AE23 IO_AE24 IO_AF14 IO_AF15 IO_AF16 IO_AF17 IO_AF18 IO_AF19 IO_AF20 IO_AF21 IO_AF22 IO_AF23 IO_AF24 IO BANK 6 P20 P21 P23 R21 R22 R23 R24 R25 R26 T20 T21 T22 T23 T24 T25 T26 U21 U22 U23 U24 U25 U26 V20 V21 V22 V23 V24 V25 V26 W21 W22 W23 W24 W25 W26 Y23 Y24 Y25 Y26 AA24 AA25 AA26 AB24 AB25 AB26 AC25 AC26 AD25 AD26 FPGA_LCD_DB7 FPGA_LCD_DB6 FPGA_LCD_DB5 FPGA_LCD_DB4 FPGA_LCD_DB3 FPGA_LCD_DB2 FPGA_LCD_DB1 FPGA_LCD_DB0 Y14 Y16 Y18 AA14 AA15 AA16 AA17 AA18 AA19 AB14 AB15 AB16 AB17 AB18 AB19 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 IO BANK 5 IO_P20 IO_P21 IO_P23 IO_R21 IO_R22 IO_R23 IO_R24 IO_R25 IO_R26 IO_T20 IO_T21 IO_T22 IO_T23 IO_T24 IO_T25 IO_T26 IO_U21 IO_U22 IO_U23 IO_U24 IO_U25 IO_U26 IO_V20 IO_V21 IO_V22 IO_V23 IO_V24 IO_V25 IO_V26 IO_W21 IO_W22 IO_W23 IO_W24 IO_W25 IO_W26 IO_Y23 IO_Y24 IO_Y25 IO_Y26 IO_AA24 IO_AA25 IO_AA26 IO_AB24 IO_AB25 IO_AB26 IO_AC25 IO_AC26 IO_AD25 IO_AD26 FPGA_USB_SUSPEND FPGA_USB_VM FPGA_USB_VP FPGA_USB_RCV FPGA_USB_VPO FPGA_USB_VMO FPGA_USB_SPEED FPGA_USB_OE FPGA_LCD_TR FPGA_LCD_RS FPGA_LCD_RW FPGA_LCD_E IO BANK 4 IO_A14 IO_A15 IO_A16 IO_A17 IO_A18 IO_A19 IO_A20 IO_A21 IO_A22 IO_A23 IO_A24 IO_B14 IO_B15 IO_B16 IO_B17 IO_B18 IO_B19 IO_B20 IO_B21 IO_B22 IO_B23 IO_B24 IO_C14 IO_C15 IO_C16 IO_C17 IO_C18 IO_C19 IO_C20 IO_C21 IO_C22 IO_C23 IO_D14 IO_D15 IO_D16 IO_D17 IO_D18 IO_D19 IO_D20 IO_D21 IO_D22 IO_E14 IO_E15 IO_E16 IO_E17 IO_E18 IO_E19 IO_E20 IO_E21 IO_F14 IO_F15 IO_F16 IO_F17 IO_F18 IO_F19 IO_G14 IO_G16 IO_G18 FPGA_SER_RD FPGA_SER_CTS FPGA_SER_TD FPGA_SER_RTS IO BANK 3 B A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D14 D15 D16 D17 D18 D19 D20 D21 D22 E14 E15 E16 E17 E18 E19 E20 E21 F14 F15 F16 F17 F18 F19 G14 G16 G18 C25 C26 D24 D25 D26 E23 E24 E25 E26 F22 F23 F24 F25 F26 G22 G23 G24 G25 G26 H21 H22 H23 H24 H25 H26 J21 J22 J23 J24 J25 J26 K20 K21 K22 K23 K24 K25 K26 L21 L22 L23 L24 L25 L26 M20 M21 M22 M23 M24 M25 M26 N21 N23 N26 IO BANK 2 FPGA_ENB_MDC FPGA_ENB_MDIO FPGA_ENB_CRS FPGA_ENB_COL FPGA_ENB_TXCLK FPGA_ENB_TXD3 FPGA_ENB_TXD2 FPGA_ENB_TXD1 FPGA_ENB_TXD0 FPGA_ENB_TXEN FPGA_ENB_TXER FPGA_ENB_RXCLK FPGA_ENB_RXD3 FPGA_ENB_RXD2 FPGA_ENB_RXD1 FPGA_ENB_RXD0 FPGA_ENB_RXER FPGA_ENB_RXDV FPGA_ENB_RESET U1B IO_C25 IO_C26 IO_D24 IO_D25 IO_D26 IO_E23 IO_E24 IO_E25 IO_E26 IO_F22 IO_F23 IO_F24 IO_F25 IO_F26 IO_G22 IO_G23 IO_G24 IO_G25 IO_G26 IO_H21 IO_H22 IO_H23 IO_H24 IO_H25 IO_H26 IO_J21 IO_J22 IO_J23 IO_J24 IO_J25 IO_J26 IO_K20 IO_K21 IO_K22 IO_K23 IO_K24 IO_K25 IO_K26 IO_L21 IO_L22 IO_L23 IO_L24 IO_L25 IO_L26 IO_M20 IO_M21 IO_M22 IO_M23 IO_M24 IO_M25 IO_M26 IO_N21 IO_N23 IO_N26 IO BANK 1 C IO_A3 IO_A4 IO_A5 IO_A6 IO_A7 IO_A8 IO_A9 IO_A10 IO_A11 IO_A12 IO_A13 IO_B5 IO_B6 IO_B7 IO_B8 IO_B9 IO_B10 IO_B11 IO_B12 IO_B13 IO_C5 IO_C6 IO_C7 IO_C8 IO_C9 IO_C10 IO_C11 IO_C12 IO_C13 IO_D5 IO_D6 IO_D7 IO_D8 IO_D9 IO_D10 IO_D11 IO_D12 IO_D13 IO_E6 IO_E7 IO_E8 IO_E9 IO_E10 IO_E11 IO_E12 IO_E13 IO_F9 IO_F10 IO_F11 IO_F12 IO_F13 IO_G10 IO_G12 IO BANK 2 D A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B5 B6 B7 B8 B9 B10 B11 B12 B13 C5 C6 C7 C8 C9 C10 C11 C12 C13 D5 D6 D7 D8 D9 D10 D11 D12 D13 E6 E7 E8 E9 E10 E11 E12 E13 F9 F10 F11 F12 F13 G10 G12 IO BANK 1 U1A FPGA_ENA_MDC FPGA_ENA_MDIO FPGA_ENA_CRS FPGA_ENA_COL FPGA_ENA_TXCLK FPGA_ENA_TXD3 FPGA_ENA_TXD2 FPGA_ENA_TXD1 FPGA_ENA_TXD0 FPGA_ENA_TXEN FPGA_ENA_TXER FPGA_ENA_RXCLK FPGA_ENA_RXD3 FPGA_ENA_RXD2 FPGA_ENA_RXD1 FPGA_ENA_RXD0 FPGA_ENA_RXER FPGA_ENA_RXDV FPGA_ENA_RESET 2 + C49 4.7UF C51 0.1UF + 5 C50 C52 4.7UF 0.1UF AD24 A APA600_FG676 Actel Corporation Title Size C Date: 5 4 3 2 Actel Confidential MPU Platform Demo Board Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 2 of 6 5 4 3 2 1 V3_3 C53 C54 0.1UF 0.1UF D VCC VCC HSDL3000 C61 C62 C63 C64 0.1UF 0.1UF 0.1UF 0.1UF V3_3 33 24 5V_VCC_B TXDATAIN_A TXDATAOUT_A 1 TXDATAOUT_A 2 1 54.9 3 RXDATAOUT_A RXDATAIN_A 29 8 RXDATAOUT_A RXDATAIN_A 30 26 TXDATAIN_B TXDATAOUT_B 10 27 TXDATAIN_B TXDATAOUT_B 11 1 3 5 RXDATAOUT_B RXDATAIN_B 20 17 RXDATAOUT_B RXDATAIN_B 21 34 25 TX_INHIBIT_A TX_INHIBIT_B 6 15 RX_STROBE_A RX_STROBE_B 2 4 6 J6 2 4 6 2 1 54.9 3 Triax R4 J7 R5 1 3 5 4 5 6 7 8 2 1 3 5 HEADER6A 54.9 BTTC_HLP6000 3 14 J5 R3 4 5 6 7 8 2 10 1 3 5 2 4 6 J8 2 4 6 2 1 HEADER6A 54.9 BTTC_HLP6000 3 Triax R6 BU63147 GND_CASE NC 4,13,18, 19,23,28,32 GND_B12 GND_B16 GND_B22 18 17 16 15 14 13 12 11 B0 B1 B2 B3 B4 B5 B6 B7 OE T/R V3_3 A0 A1 A2 A3 A4 A5 A6 A7 19 1 V3_3 D 1553B Interface C 9 C 0.1UF 12 16 22 SHIELD 2 3 4 5 6 7 8 9 FPGA_1553B_TXDAp FPGA_1553B_TXDAn FPGA_1553B_TXDBp FPGA_1553B_TXDBn FPGA_1553B_TXINHIBITA FPGA_1553B_TXINHIBITB FPGA_1553B_RXSTROBEA FPGA_1553B_RXSTROBEB 0.1UF 5 GND_A3 GND_A7 GND_A31 7 U8 IrDA 0.1UF U4 3 7 31 LEDA TXD RXD SD VCC GND GND HSDL7000 FPGA_IRDA_NRST FPGA_IRDA_SD 1 2 3 4 5 6 VCC VCC 74ABT245 10 8 7 6 5 VCC IR_TXD IR_RCV NRST 16XCLK TXD RCV GND 0.1UF VCC 1 2 3 4 U6 2.7 U7 C58 0.1UF C60 0.1UF VCC C57 1 20 C59 TXDATAIN_A 36 VCC R7 FPGA_IRDA_16XCLK FPGA_IRDA_TXD FPGA_IRDA_RCV 35 VCC C56 U5 19 1 74LVT245 V3_3 18 17 16 15 14 13 12 11 B0 B1 B2 B3 B4 B5 B6 B7 OE T/R A0 A1 A2 A3 A4 A5 A6 A7 GND 2 3 4 5 6 7 8 9 FPGA_1553B_RXDAp FPGA_1553B_RXDAn FPGA_1553B_RXDBp FPGA_1553B_RXDBn U3 U2 5V_VCC_A 20 V3_3 VCC C55 FPGA_EE_SPI_HOLD FPGA_EE_SPI_C FPGA_EE_SPI_D M95040-WDW6 B V3_3 C65 C66 0.1UF 0.1UF V3_3 U12 1 2 3 4 FPGA_EE_I2C_EN EN0 EN1 NC3 VSS VCC WC SCL SDA 8 7 6 5 FPGA_EE_I2C_WC FPGA_EE_I2C_SCL FPGA_EE_I2C_SDA M24256-AW R8 R9 10K 10K FT E2 G BA BB BC BD BW GW ADSC ADSP ADV ZZ LBO FPGA_MEM_CLK 89 CK 98 92 E1 E3 V3_3 GS84036A 4 11 20 27 54 61 70 77 FPGA_MEM_DQ0 FPGA_MEM_DQ1 FPGA_MEM_DQ2 FPGA_MEM_DQ3 FPGA_MEM_DQ4 FPGA_MEM_DQ5 FPGA_MEM_DQ6 FPGA_MEM_DQ7 FPGA_MEM_DP0 DQB_68 DQB_69 DQB_72 DQB_73 DQB_74 DQB_75 DQB_78 DQB_79 DQPB 68 69 72 73 74 75 78 79 80 FPGA_MEM_DQ8 FPGA_MEM_DQ9 FPGA_MEM_DQ10 FPGA_MEM_DQ11 FPGA_MEM_DQ12 FPGA_MEM_DQ13 FPGA_MEM_DQ14 FPGA_MEM_DQ15 FPGA_MEM_DP1 DQC_2 DQC_3 DQC_6 DQC_7 DQC_8 DQC_9 DQC_12 DQC_13 DQPC 2 3 6 7 8 9 12 13 1 FPGA_MEM_DQ16 FPGA_MEM_DQ17 FPGA_MEM_DQ18 FPGA_MEM_DQ19 FPGA_MEM_DQ20 FPGA_MEM_DQ21 FPGA_MEM_DQ22 FPGA_MEM_DQ23 FPGA_MEM_DP2 DQD_18 DQD_19 DQD_22 DQD_23 DQD_24 DQD_25 DQD_28 DQD_29 DQPD 18 19 22 23 24 25 28 29 30 FPGA_MEM_DQ24 FPGA_MEM_DQ25 FPGA_MEM_DQ26 FPGA_MEM_DQ27 FPGA_MEM_DQ28 FPGA_MEM_DQ29 FPGA_MEM_DQ30 FPGA_MEM_DQ31 FPGA_MEM_DP3 U10 FPGA_MEM_A0 FPGA_MEM_A1 FPGA_MEM_A2 FPGA_MEM_A3 FPGA_MEM_A4 FPGA_MEM_A5 FPGA_MEM_A6 FPGA_MEM_A7 FPGA_MEM_A8 FPGA_MEM_A9 FPGA_MEM_A10 FPGA_MEM_A11 FPGA_MEM_A12 FPGA_MEM_A13 FPGA_MEM_A14 FPGA_MEM_A15 FPGA_MEM_A16 FPGA_MEM_A17 FPGA_MEM_A18 FPGA_MEM_A19 FPGA_MEM_A20 FPGA_MEM_A21 FPGA_FLASH_CE FPGA_FLASH_OE FPGA_FLASH_WE FPGA_FLASH_RP FPGA_FLASH_STS FPGA_FLASH_BYTE C74 0.1UF 0.1UF A 32 28 27 26 25 24 23 22 20 19 18 17 13 12 11 10 8 7 6 5 4 3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 14 2 29 54 55 16 53 CE0 CE1 CE2 OE WE RP STS 31 BYTE 15 VPEN R10 10K DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 33 35 38 40 44 46 49 51 34 36 39 41 45 47 50 52 FPGA_MEM_DQ0 FPGA_MEM_DQ1 FPGA_MEM_DQ2 FPGA_MEM_DQ3 FPGA_MEM_DQ4 FPGA_MEM_DQ5 FPGA_MEM_DQ6 FPGA_MEM_DQ7 FPGA_MEM_DQ8 FPGA_MEM_DQ9 FPGA_MEM_DQ10 FPGA_MEM_DQ11 FPGA_MEM_DQ12 FPGA_MEM_DQ13 FPGA_MEM_DQ14 FPGA_MEM_DQ15 MT28F320J3RG-11 C67 C68 C69 C70 C71 C72 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF A V3_3 C75 C76 C77 C78 C79 C80 C81 C82 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Actel Corporation Title Size C Date: 5 4 3 B V3_3 V3_3 C73 9 37 43 14 97 86 93 94 95 96 87 88 85 84 83 64 31 52 53 56 57 58 59 62 63 51 VCC9 VCC37 VCCQ FPGA_MEM_FT FPGA_MEM_E FPGA_MEM_G FPGA_MEM_BA FPGA_MEM_BB FPGA_MEM_BC FPGA_MEM_BD FPGA_MEM_BW FPGA_MEM_GW FPGA_MEM_ADSC FPGA_MEM_ADSP FPGA_MEM_ADV FPGA_MEM_ZZ FPGA_MEM_LBO VDDQ_4 VDDQ_11 VDDQ_20 VDDQ_27 VDDQ_54 VDDQ_61 VDDQ_70 VDDQ_77 A_32 A_33 A_34 A_35 A_44 A_45 A_46 A_47 A_48 A_49 A_50 A_81 A_82 A_99 A_100 VDD_15 VDD_41 VDD_65 VDD_91 32 33 34 35 44 45 46 47 48 49 50 81 82 99 100 V3_3 DQA_52 DQA_53 DQA_56 DQA_57 DQA_58 DQA_59 DQA_62 DQA_63 DQPA VSS21 VSS42 VSS48 VCC HOLD C D S Q W VSS FPGA_MEM_A2 FPGA_MEM_A3 FPGA_MEM_A4 FPGA_MEM_A5 FPGA_MEM_A6 FPGA_MEM_A7 FPGA_MEM_A8 FPGA_MEM_A9 FPGA_MEM_A10 FPGA_MEM_A11 FPGA_MEM_A12 FPGA_MEM_A13 FPGA_MEM_A14 FPGA_MEM_A15 FPGA_MEM_A16 A0 A1 21 42 48 FPGA_EE_SPI_S FPGA_EE_SPI_Q FPGA_EE_SPI_W 8 7 6 5 37 36 VSS_5 VSS_10 VSS_17 VSS_21 VSS_26 VSS_40 VSS_55 VSS_60 VSS_67 VSS_71 VSS_76 VSS_90 V3_3 U11 1 2 3 4 FPGA_MEM_A0 FPGA_MEM_A1 5 10 17 21 26 40 55 60 67 71 76 90 U9 15 41 65 91 V3_3 2 Actel Confidential MPU Platform Demo Board Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 3 of 6 5 4 3 2 1 L1 BLM31AF700SN1K V3_3 RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] RX_ER/PAUSE_EN RX_DV 27 26 25 AN_EN AN_1 AN_0 FPGA_ENA_RESET 62 RESET CLK_25MHZ 67 66 X1 X2 RBIAS 9.31K 0 0 0 0 AN_EN 1 1 1 0 0 1 1 AN1 0 0 1 0 1 0 1 AN0 0 1 0 1 1 1% Forced Mode DP83846A 4 7 12 14 24 49 72 49.9 R16 11 TD+ TD- 16 17 10BASE-T, Half-Duplex 10BASE-T, Full-Duplex 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex Advertised Mode 10BASE-T, Half/Full-Duplex 100BASE-T, Half/Full-Duplex 10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex 12 RD+ RD- 11 10 R17 R18 54.9 54.9 1 2 3 4 5 6 7 8 C84 0.1UF 0.1UF 10 13 CHS RESERVED 1,5,8,20, 21,22,47, 63,68,69, 70,71,74, 75,77,78,80 33 32 31 30 29 28 CHS 9 14 1K RJ45_WM C85 LED_DPLX/PHYAD0 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_TX/PHYAD3 LED_RX/PHYAD4 LED_SPEED D R19 C83 R20 10K 0.1UF R21 R26 1K 10K D1 V3_3 R27 R22 R23 1K 1K 10K D2 LED D3 LED R24 R28 LED COLOR SIGNAL Description D1 GREEN LED_FDPLX FULL DUPLEX LED STATUS: Indicates Full-Duplex status. D2 GREEN LED_COL COLLISION LED STATUS: Indicates Collision activity in Half Duplex mode. D3 GREEN LED_SPEED SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low for 10 Mb/s. D4 GREEN LED_RX RECEIVE LED STATUS: Indicates receive activity. LED is on for activity, off for no activity. J9 Left GREEN LED_TX TRANSMIT LED STATUS: Indicates transmit activity. LED is on for activity, off for no activity. J9 Right GREEN LED_GCLNK GOOD LINK LED STATUS: Indicates Good Link Status for 10BASET and 100BASE-TX. 1K 10K D4 LED LED C R29 R30 R31 V3_3 4.99K V3_3 3 2 1 1 AN0 R15 49.9 4.99K J10 J11 4.99K C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 3 2 1 C AN1 3 2 1 AN_EN 34 42 53 56 64 3 R25 R14 SUB_GND SUB_GND SUB_GND 45 38 39 40 41 46 44 R11 10K J9 19 76 79 FPGA_ENA_RXCLK FPGA_ENA_RXD3 FPGA_ENA_RXD2 FPGA_ENA_RXD1 FPGA_ENA_RXD0 FPGA_ENA_RXER FPGA_ENA_RXDV ANA_VDD ANA_VDD ANA_VDD ANA_VDD TX_CLK TXD[3] TXD[2] TXD[1] TXD[0] TX_EN TX_ER ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND 51 59 58 55 54 52 50 V3_3 1K 2 6 9 13 15 18 FPGA_ENA_TXCLK FPGA_ENA_TXD3 FPGA_ENA_TXD2 FPGA_ENA_TXD1 FPGA_ENA_TXD0 FPGA_ENA_TXEN FPGA_ENA_TXER CORE_VDD CORE_VDD CORE_VDD MDC MDIO CRS/LED_CFG COL IO_GND IO_GND IO_GND IO_GND IO_GND 37 36 61 60 FPGA_ENA_MDC FPGA_ENA_MDIO FPGA_ENA_CRS FPGA_ENA_COL D CORE_GND CORE_GND CORE_GND U13 23 48 73 R13 1.5K IO_VDD IO_VDD IO_VDD IO_VDD R12 1.5K 35 43 57 65 L2 BLM31AF700SN1K 10/100 V3_3 J12 HEADER3 HEADER3 HEADER3 L3 BLM31AF700SN1K V3_3 V3_3 V3_3 R32 10K AN_EN AN_1 AN_0 FPGA_ENB_RESET 62 RESET CLK_25MHZ 67 66 X1 X2 RBIAS 9.31K 1% DP83846A 34 42 53 56 64 3 R46 4 7 12 14 24 49 72 49.9 J13 R37 11 TD+ TD- 16 17 RD+ RD- 11 10 R38 R39 54.9 54.9 1 2 3 4 5 6 7 8 C98 0.1UF 0.1UF 0 0 0 0 AN_EN 1 1 1 0 0 1 1 AN1 0 0 1 0 1 0 1 AN0 0 1 0 1 1 10BASE-T, Half-Duplex 10BASE-T, Full-Duplex 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex Advertised Mode 10BASE-T, Half/Full-Duplex 100BASE-T, Half/Full-Duplex 10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex 1 R50 R51 CHS RESERVED 1,5,8,20, 21,22,47, 63,68,69, 70,71,74, 75,77,78,80 33 32 31 30 29 28 CHS 9 14 1K RJ45_WM R41 10K 0.1UF R42 R47 1K 10K R48 R43 R44 1K 1K 10K D5 LED COLOR SIGNAL D5 GREEN LED_FDPLX FULL DUPLEX LED STATUS: Indicates Full-Duplex status. D6 GREEN LED_COL D7 GREEN LED_SPEED COLLISION LED STATUS: Indicates Collision activity in Half Duplex mode. SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low for 10 Mb/s. D8 GREEN LED_RX RECEIVE LED STATUS: Indicates receive activity. LED is on for activity, off for no activity. J13 Left GREEN LED_TX TRANSMIT LED STATUS: Indicates transmit activity. LED is on for activity, off for no activity. J13 Right GREEN LED_GCLNK GOOD LINK LED STATUS: Indicates Good Link Status for 10BASET and 100BASE-TX. 1K 10K D6 LED R45 R49 Description LED D7 D8 LED LED A R52 V3_3 4.99K 4.99K 4.99K V3_3 J14 J15 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF Actel Corporation 3 2 1 Forced Mode 3 2 1 AN0 3 2 1 A AN1 10 13 C99 LED_DPLX/PHYAD0 LED_COL/PHYAD1 LED_GDLNK/PHYAD2 LED_TX/PHYAD3 LED_RX/PHYAD4 LED_SPEED B R40 C97 V3_3 AN_EN 12 10/100 27 26 25 49.9 SUB_GND SUB_GND SUB_GND RX_CLK RXD[3] RXD[2] RXD[1] RXD[0] RX_ER/PAUSE_EN RX_DV R36 19 76 79 45 38 39 40 41 46 44 ANA_VDD ANA_VDD ANA_VDD ANA_VDD FPGA_ENB_RXCLK FPGA_ENB_RXD3 FPGA_ENB_RXD2 FPGA_ENB_RXD1 FPGA_ENB_RXD0 FPGA_ENB_RXER FPGA_ENB_RXDV ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND ANA_GND TX_CLK TXD[3] TXD[2] TXD[1] TXD[0] TX_EN TX_ER R35 1K 2 6 9 13 15 18 51 59 58 55 54 52 50 CORE_VDD CORE_VDD CORE_VDD FPGA_ENB_TXCLK FPGA_ENB_TXD3 FPGA_ENB_TXD2 FPGA_ENB_TXD1 FPGA_ENB_TXD0 FPGA_ENB_TXEN FPGA_ENB_TXER CORE_GND CORE_GND CORE_GND MDC MDIO CRS/LED_CFG COL IO_GND IO_GND IO_GND IO_GND IO_GND 37 36 61 60 FPGA_ENB_MDC FPGA_ENB_MDIO FPGA_ENB_CRS FPGA_ENB_COL 23 48 73 IO_VDD IO_VDD IO_VDD IO_VDD U14 B L4 BLM31AF700SN1K R34 1.5K 35 43 57 65 R33 1.5K Title J16 Actel Confidential MPU Platform Demo Board HEADER3 HEADER3 HEADER3 Size C Date: 5 4 3 2 Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 4 of 6 5 4 3 2 1 J17 5 8 VPN GND_7 7 GND_10 GND_9 9 GND_11 11 12 S1 FPGA_USER_SW1 FPGA_USER_SW2 FPGA_USER_SW3 FPGA_USER_SW4 FPGA_USER_SW5 FPGA_USER_SW6 FPGA_USER_SW7 FPGA_USER_SW8 TDI NC_13 13 16 TDO NC_15 15 18 TMS GND_17 17 20 RCK GND_19 19 22 TRST NC_21 21 24 VDD_24 NC_23 23 26 VDD_26 NC_25 25 SW DIP-8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 10 13 U15 C111 C112 0.1UF 0.1UF 16 15 CHS CHS 9 14 U16 18 17 16 15 14 13 12 11 FPGA_LCD_DB7 FPGA_LCD_DB6 FPGA_LCD_DB5 FPGA_LCD_DB4 FPGA_LCD_DB3 FPGA_LCD_DB2 FPGA_LCD_DB1 FPGA_LCD_DB0 RJ45_WM V3_3 B0 B1 B2 B3 B4 B5 B6 B7 J20 FPGA_HDR_TCK R55 4.7K 11 FPGA_HDR_TDI FPGA_LCD_TR 12 2 3 4 5 6 7 8 9 R58 4.7K J22 1 2 3 4 OPPINS FPGA_HDR_TRST 10 13 LCD CONTRAST C CHS CHS 9 14 RJ45_WM CON14 V3_3 V3_3 CLK_25MHZ_2 FPGA_EE_I2C_SDA CLK_USER ADC_CH6_DBC_P78 DBC_IO5VIN3 DBC_IO5VIN1 DBC_IO5VOUT3 DBC_IO5VOUT1 FPGA_DBC_IO60 FPGA_DBC_IO58 FPGA_DBC_IO56 FPGA_DBC_IO54 FPGA_DBC_IO52 FPGA_DBC_IO50 FPGA_DBC_IO48 FPGA_DBC_IO46 FPGA_DBC_IO44 FPGA_DBC_IO42 FPGA_DBC_IO40 FPGA_DBC_IO38 FPGA_DBC_IO36 FPGA_DBC_IO34 FPGA_DBC_IO32 FPGA_DBC_IO30 FPGA_DBC_IO28 FPGA_DBC_IO26 FPGA_DBC_IO24 FPGA_DBC_IO22 FPGA_DBC_IO20 FPGA_DBC_IO18 FPGA_DBC_IO16 FPGA_DBC_IO14 FPGA_DBC_IO12 FPGA_DBC_IO10 FPGA_DBC_IO8 FPGA_DBC_IO6 FPGA_DBC_IO4 FPGA_DBC_IO2 74LVT245 C116 0.1UF 0.1UF 20 DBC_IO5VIN0 DBC_IO5VIN1 DBC_IO5VIN2 DBC_IO5VIN3 T/R OE GND 18 17 16 15 14 13 12 11 1K R59 LED-R D9 1K R60 LED-G D10 1K R61 LED-R D11 1K R62 LED-G D12 1K R63 LED-R D13 1K R64 LED-G D14 74LVT245 V3_3 C113 C114 0.1UF 0.1UF VCC VCC B 10 C115 19 1 OE T/R V3_3 B0 B1 B2 B3 B4 B5 B6 B7 2 3 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 1 19 A0 A1 A2 A3 A4 A5 A6 A7 U18 10 2 3 4 5 6 7 8 9 FPGA_DBC_IO65 FPGA_DBC_IO66 FPGA_DBC_IO67 FPGA_DBC_IO68 V3_3 FPGA_DBC_GCLK B0 B1 B2 B3 B4 B5 B6 B7 GND 20 V3_3 C117 C118 0.1UF 0.1UF VCC VCC C124 0.1UF 0.1UF U20 1 3 4 5 11 10 FPGA_SER_CTS_5V 12 FPGA_SER_RD_5V 9 FPGA_SER_RTS FPGA_SER_TD VCC 74ABT245 C1+ C1C2+ C2T1IN T2IN R1OUT R2OUT MAX232 V+ 2 V- 6 T1OUT T2OUT R1IN R2IN C121 1UF C122 1UF SERIAL PORT 1UF 16 1UF VCC DBC_IO5VOUT0 DBC_IO5VOUT1 DBC_IO5VOUT2 DBC_IO5VOUT3 + C120 GND 18 17 16 15 14 13 12 11 + C119 J24 5 9 4 8 3 7 2 6 1 14 7 13 8 CONNECTOR DB9 15 C123 B0 B1 B2 B3 B4 B5 B6 B7 GND A0 A1 A2 A3 A4 A5 A6 A7 10 VCC VCC U19 2 3 4 5 6 7 8 9 FPGA_DBC_IO61 FPGA_DBC_IO62 FPGA_DBC_IO63 FPGA_DBC_IO64 20 VCC OE T/R 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 19 1 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 18 17 16 15 14 13 12 11 FPGA_SER_RD FPGA_SER_CTS + B FPGA_EE_I2C_SCL CLK_16MHZ_2 ADC_CH5_DBC_P77 DBC_IO5VIN2 DBC_IO5VIN0 DBC_IO5VOUT2 DBC_IO5VOUT0 FPGA_DBC_IO59 FPGA_DBC_IO57 FPGA_DBC_IO55 FPGA_DBC_IO53 FPGA_DBC_IO51 FPGA_DBC_IO49 FPGA_DBC_IO47 FPGA_DBC_IO45 FPGA_DBC_IO43 FPGA_DBC_IO41 FPGA_DBC_IO39 FPGA_DBC_IO37 FPGA_DBC_IO35 FPGA_DBC_IO33 FPGA_DBC_IO31 FPGA_DBC_IO29 FPGA_DBC_IO27 FPGA_DBC_IO25 FPGA_DBC_IO23 FPGA_DBC_IO21 FPGA_DBC_IO19 FPGA_DBC_IO17 FPGA_DBC_IO15 FPGA_DBC_IO13 FPGA_DBC_IO11 FPGA_DBC_IO9 FPGA_DBC_IO7 FPGA_DBC_IO5 FPGA_DBC_IO3 FPGA_DBC_IO1 Daughter Board Connector J23 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 FPGA_LED0 FPGA_LED1 FPGA_LED2 FPGA_LED3 FPGA_LED4 FPGA_LED5 U17 V3_3 FPGA_LED0 FPGA_LED1 FPGA_LED2 FPGA_LED3 FPGA_LED4 FPGA_LED5 V3_3 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VK2116 HEADER4 VCC E RW RS 14 13 12 11 10 9 8 7 RJ45 R57 4.7K FPGA_HDR_TMS FPGA_OPPINS1 FPGA_OPPINS2 FPGA_OPPINS3 FPGA_OPPINS4 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FPGA_HDR_TDO VO 6 5 4 D R53 R-VAR 74LVT245 J21 R56 4.7K VSS VDD 3 FPGA_LCD_E FPGA_LCD_RW FPGA_LCD_RS A0 A1 A2 A3 A4 A5 A6 A7 + - 1 2 V3_3 R54 4.7K C V3_3 CON14 FlashPRO Connector JTAG FS2CLAM VCC 12 J19 GND 16 15 14 13 12 11 10 9 TCK 14 J18 11 LCD DISPLAY NC_5 20 VPP V3_3 3 6 T/R OE NC_3 10 4.7K 1 2 3 4 5 6 7 8 VDDP_4 1 19 USER SWITCH V3_3 1 4 + D NC_1 10 10 9 8 7 6 5 4 3 2 1 VDDP_2 RJ45 RA1 2 V2_5 HEADER90 A A Actel Corporation Title Size C Date: 5 4 3 2 Actel Confidential MPU Platform Demo Board Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 5 of 6 5 4 3 2 1 V3_3 1 OUT 8 18 17 16 15 14 13 12 11 VCC 6 5 4 XTALOSC-25MHZ B0 B1 B2 B3 B4 B5 B6 B7 VCC 14 VCC NC 1 7 GND OUT 8 U24 C130 22UF + C126 0.1UF C127 0.1UF 0.1UF VCC 0.1UF NC 1 7 GND OUT 8 XTALOSC 4 SENSE/ADJ 5 C131 C132 0.1UF 0.1UF V3_3 C138 22UF + LT1764-3.3 C133 C134 C135 C136 0.1UF 0.1UF 0.1UF 0.1UF V3_3 U27 VCC L5 C147 100UF SENSE/ADJ 5 BLM31AF700SN1K V2_5 1/1W/1% GND SHDN 4 R66 LT1764-2.5 + C148 22UF C143 C144 C145 C146 0.1UF 0.1UF 0.1UF 0.1UF C140 C141 0.1UF 0.1UF U28 FPGA_USB_OE FPGA_USB_SPEED D15 0.1UF ZENER 4.7V C142 0.1UF J26 V3_3 1K C149 C139 68UF + ADC_CH0 FPGA_USB_VMO FPGA_USB_VPO FPGA_USB_RCV FPGA_USB_VP FPGA_USB_VM FPGA_USB_SUSPEND V3_3 FPGA_USB_OE FPGA_USB_SPEED 2 OE 9 SPEED FPGA_USB_VMO FPGA_USB_VPO 13 VMO 12 VPO FPGA_USB_RCV 3 RCV FPGA_USB_VP 4 VP 1 2 3 4 14 + 1 R65 OUT 3 C IN D 74LVT245 V3_3 VCC V2_5 2 CLK_16MHZ_2 CLK_USER FPGA_USB_VM 5 VM FPGA_USB_SUSPEND 6 SUSPEND 1 MODE USB PORT SHDN OUT GND 1 C137 100UF CLK_16MHZ U25 14 V3_3 3 + IN CLK_25MHZ_2 C128 U26 2 CLK_25MHZ XTALOSC-16MHZ C125 UA7805KTE C129 100UF 2 3 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 D- 10 27 R67 27 R68 C CON USB L6 D+ 11 C151 47PF C152 47PF R69 R70 15K 15K BLM31AF700SN1K OUT 2 + IN 3 GND 1 10 D GND U23 PWRIN V3_3 NC GND T/R OE 2 U22 VCC 7 1 19 3 2 1 U21 14 SW1 DPDT_Switch 20 VCC J25 POWER IN 1 C150 470PF GND 7 PDUSBP11A_3 V3_3 1 2 3 4 SWPUSHBUTTON 3 RESET 2 MR GND 1 SW3 FPGA_RESET 1 2 MAX6315 C153 3 4 4 3 RESET 2 MR GND 1 FPGA_KEYPAD3 B R75 MAX6315 C154 SWPUSHBUTTON 0.1UF 10K PWR PWRIN VCC 3K 0.1UF V3_3 V3_3 R76 C155 1K 0.1UF VCC R77 D16 V3_3 V2_5 10K U31 1 2 3 4 5 6 7 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ZENER 4.7V SW4 1 2 U32 R81 10K 3 4 4 3 RESET 2 MR GND 1 10K SW5 FPGA_KEYPAD1 1 2 U33 R82 KEYPAD4 10K PWR 3 4 4 3 MAX6315 SWPUSHBUTTON R79 R83 10K PWR RESET 2 MR GND 1 ADC_CH0 VCC FPGA_KEYPAD4 R84 MAX6315 SWPUSHBUTTON C157 C156 1K C158 0.1UF ADC_CH5_DBC_P77 ADC_CH6_DBC_P78 1K FPGA_ADC_CS FPGA_ADC_SCLK FPGA_ADC_DIN 0.1UF VCC 0.1UF V3_3 V3_3 U34 VCC KEYPAD2 SW6 10K PWR 3 4 RESET 2 3 MR GND 1 SWPUSHBUTTON MAX6315 C167 10K SW7 FPGA_KEYPAD2 1 2 3 4 10K 4 PWR RESET 2 3 MR GND 1 FPGA_KEYPAD5 MAX6315 SWPUSHBUTTON C165 C166 0.1UF 0.1UF 1 VCC 2 A 3 GND OUT 5 12 11 REFADJ REF 14 VL C162 0.1UF B CS SCLK DIN SHDN 4 C163 0.01UF + C161 4.7UF R80 10K DOUT 15 FPGA_ADC_DOUT SSTRB 16 FPGA_ADC_SSTRB VCC MAX1204 VSS 9 VCC C159 C160 0.1UF 0.1UF C164 0.1UF MAX6605 A Temperature Sensor C168 0.1UF VCC R86 U36 R88 KEYPAD5 10K 4 A 1 2 R85 U35 R87 V3_3 18 19 17 10 V3_3 GND KEYPAD1 R78 20 B 10K R72 U30 R74 KEYPAD3 10K PWR VCC SW2 4 13 10K R71 U29 R73 RESET V3_3 0.1UF Actel Corporation Title Size C Date: 5 4 3 2 Actel Confidential MPU Platform Demo Board Document Number <Doc> Rev 1.1 Sheet Friday, February 20, 2004 1 6 of 6