PLUS EB-ProASIC Evaluation Board User Manual Version 1.0 April 3, 2002 First Silicon Solutions, Inc. 5440 SW Westgate Dr. Suite 240 Portland, OR 97221 voice: +1-503-292-6730 fax: +1-503-292-5840 [email protected] [email protected] Copyright © 2002 First Silicon Solutions, Inc. EB-ProASICPLUS Evaluation Board User Manual 1. Introduction This document presents the design and usage information for the Actel EB-ProASICPLUS Evaluation Board. The board is intended to demonstrate the ability to program a ProASICPLUS device from a microprocessor. 2. Overview The evaluation board is based on a microcontroller with a simple on-board user interface consisting of a single-line LCD and a few buttons. On-board flash memory stores one or more programming files. A device is programmed by selecting the desired file and executing the program function. The ProASICPLUS devices are programmed via JTAG. The microcontroller drives the JTAG signals according to the programming file through a simple API. The JTAG signals are connected to generalpurpose I/O pins on the microcontroller and controlled by software. The evaluation board provides a site to accommodate either a socket or a ProASICPLUS device. RS232 JTAG Supervisor Microcontroller RCK SRAM Dual-port SRAM Program Flash Data Flash Buttons LCD ProASICPLUS site Power supply Figure 1. ProASICPLUS Evaluation Board 3. Design Details 3.1. Mechanical Design The evaluation board is rectangular with rubber pads affixed to the bottom. It is not enclosed in a case. The board size is 5 by 8 inches. First Silicon Solutions, Inc. Page 2 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual 3.2. Microcontroller The CPU is a Zilog eZ80190. This is a single-chip integrated controller with a 16 megabyte address space, 8K on-chip SRAM, glueless interface to memory and I/O, serial ports, timers, and general-purpose I/O as well as a debug interface which will be used for development and also to download the software monitor during manufacturing. JTAG signals are directly connected to CPU general-purpose I/O pins and toggled by software. RCK is a free-running 4 MHz clock that is generated by a dedicated oscillator that also connects to one of the FPGA's global clock inputs. 3.3. Flash Separate flash devices on the evaluation board are used for program and data storage. Separate devices allow the CPU to execute from one device while programming the other and also provide additional security for the program memory so it is less likely to get accidentally erased. The eZ80 executes the software monitor from the program flash starting at reset. Program flash is protected and requires a jumper to be installed in order to erase or program the device. Programming files downloaded from a PC are stored in the data flash using a simple sectorbased file system. The data flash is allocated to programming files in 64KB sectors. Each file may occupy any number of sectors and the sectors that make up a file need not be contiguous. One sector is reserved for the directory. A 2 megabyte JEDEC-compatible device is installed but the site can accommodate devices from 1 to 8 megabytes. A 1 megabyte flash contains 15 data sectors while an 8 megabyte device contains 127 data sectors. Both the program flash and the data flash are in 48-pin TSOP packages. 3.4. RS232 The eZ80 CPU includes an integrated UART. An interface chip in the Maxim MAX232 family is used to translate the TTL signals to RS232 levels. A DB-9 connector is provided so the board may be hooked up to a PC with a 9-pin serial cable. A crossover cable is required and is provided with the board. 3.5. SRAM Four SRAM devices are populated for a total memory storage of 2 megabytes. The SRAMs are in 44-pin TSOP packages. 3.6. Dual-Port SRAM A small (8K byte) dual-ported SRAM is installed on the board and may be addressed from either the eZ80 CPU or the FPGA. After programming the FPGA, this SRAM is used to pass messages to and from the FPGA using the buttons and LCD display. The dual-port SRAM is in a 64-pin TQFP package. 3.7. LCD An integrated high-contrast liquid-crystal character display will be used to display messages to the user allowing selection of a programming file and initiation of the programming sequence. The LCD is 16 characters by 2 lines. The content is determined by firmware and is shown in the document section describing the software monitor. First Silicon Solutions, Inc. Page 3 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual 3.8. Buttons A set of four buttons is provided as the user interface to the software monitor. The software monitor is menu-based. The buttons are labeled ">", "<", "Enter", and "Cancel". The user interface is described in the document section describing the software monitor. The buttons are directly read through general-purpose I/O signals. Each button is an SPST switch connecting the I/O signal to ground. A pullup resistor causes the signal to be read high when the switch is not depressed. Debouncing is done in software. 3.9. ProASICPLUS Device One site is provided for a ProASICPLUS device. The site is a BGA that can be populated by either a BGA socket or a ProASICPLUS chip. A number of unassigned I/O pins of the device are made available at 0.1" double-row header sites. PLUS A 38-pin Mictor connector is directly connected to the ProASIC to be used by a logic analyzer or the FS2 Configurable Logic Analysis Monitor (CLAM) instantiated in the device. Finally, a ProASICPLUS external programming header is provided to support programming the device from an external programmer. 3.10. Power Supplies Power enters the board from a +24V DC universal desktop power supply. The supply voltages are created with a combination of DC/DC converters and linear regulators. +24V Powertrends Integrated DC/DC +5V +5V 3.3V LDO Regulator +3.3V VDDP 2.5V LDO Regulator VDD Adjustable Linear Regulator VPP Adjustable DC/DC VPN Figure 2. Power Supply Tree There are four power supplies required for the ProASICPLUS and two for other board circuitry. All of these are fixed supply voltages as follows: First Silicon Solutions, Inc. Page 4 of 9 Confidential Material EB-ProASICPLUS Evaluation Board Supply VDDP VDD VPP VPN +5V +3.3V User Manual Purpose ProASICPLUS I/O supply ProASICPLUS logic supply ProASICPLUS programming voltage ProASICPLUS programming voltage Board logic supply Board logic supply Voltage +3.3V +2.5V +16.2V ± 0.3V -13.6V ± 0.2V +5V +3.3V 3.11. Digital Signals Digital signals between the CPU and ProASICPLUS are all +3.3V level. 4. Software Overview There are 4 major software levels--a Windows-based downloader GUI, the on-board user-interface, the on-board STAPL player, and the low-level board control or ABI. LCD Windows GUI RS232 Monitor STAPL Player ABI Hardware Figure 3. Software Structure 5. Low-Level Control Software ABI Low-level control software is a collection of C functions described in ebactel.h. 5.1. Initialization AbiInit initializes the ABI layer. It is called when programming begins. AbiCleanup is called when programming completes. 5.2. JTAG Communication There are several primitive functions available to allow the application to fully control the JTAG port. These functions execute by toggling TCK, TDI, and TMS in a sequence that executes the desired operation. TDO is sampled and is available for reading if desired. First Silicon Solutions, Inc. Page 5 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual 6. Software Monitor On reset, firmware in the program flash is executed. After initialization to set up chip selects, waitstates, etc, the monitor displays the menu on the LCD and sends a message to the RS232 port. The monitor may be controlled from either the on-board buttons or via the RS232 port from a remote PC. The on-board buttons and LCD display together form a simple user interface with a hierarchical menu. reset proASICPLUS version X.Y < any key > Select File Filename Enter Cancel > > Filename 1 > Filename n < Enter Enter < Program Device Filename Enter Programming... Filename <result string> Filename any key > < Monitor Device Filename Enter > <Messages from FPGA> > < Enter Cancel < Remote > Enter <Messages from PC> > < Enter Cancel Figure 4. Menu Structure To program a device, first one or more files are downloaded from a PC (see next section). The Select File menu is used to cycle through the filenames until the desired one is found. Press Enter to return to the main menu. Use the arrow keys to cycle to Program Device, then Enter to begin the programming process. When programming is complete, a message is displayed until any key is pressed. To allow interaction with the FPGA after programming, select Monitor Device. In this state, the CPU continually updates the display by reading 32 bytes from the dual-ported memory and writing those bytes to the 32 characters in the display. Line 1 of the display is offset 0x00..0x0F and line 2 is offset 0x10..0x1F in the dual-port RAM. During programming, these memory regions are filled with blanks which will be displayed if the programmed FPGA image does not initialize the memory region. First Silicon Solutions, Inc. Page 6 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual In FPGA Monitor mode, dual-port memory location 0x20 bits 0, 1, and 2 reflect the states of the Enter, >, and < keys, respectively. 1 indicates the key is depressed. The key states are debounced in the CPU. This feature provides basic user interaction with the programmed FPGA image. The remaining space in the dual-port RAM may be used by the FPGA. Host software can read and write locations in this memory so two-way communication to/from the PC can be accomplished if desired. 7. RS232 Communication Protocol The on-board monitor can operate on files once they are in the data flash. The files are downloaded from the PC to the data flash via RS232. The RS232 port is fixed at 38400 baud and uses a linebased command/response protocol. Each command and response line ends with a newline. Command F Response index name length > index name length > > Action Select next file. Response is new selected file. C <length> index name length > N <filename> index name length > > Create new file of length <length> bytes and name "newNNN" where NNN is a 3-digit decimal number. Response is new selected file. Rename file. Response is selected file. Del Din S… K Delete file. Response is new selected file. Initialize data flash (erase all files). Load S record into download buffer. The S record is checked for parity. Write download buffer to selected file. Xe index name length > > Xp > Write download buffer to program flash. I > Initialize download buffer to zero. P index name length > > Program FPGA from current file. data > > Read addr in eZ80 memory space. product name version number > > Retrieve firmware version information. W <addr> <data> R <addr> Z V JA First Silicon Solutions, Inc. Erase program flash. Write data to addr in eZ80 memory space. Display 32 bytes at 0x7FFFE0 on LCD. AbiInit Page 7 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual JZ > AbiCleanup JR > AbiJtagReset JI > AbiJtagIrEnter JD > AbiJtagDrEnter JT > AbiJtagIdle JW <clocks> > AbiWait (clocks) JS <data> tdodata > AbiJtagShift (data, 8) AbiJtagRead (tdodata, 8) 8. Windows Host Software On the Windows PC, a simple program allows a user to download files and otherwise control the evaluation board via RS232. The program is a command window based on Tcl/tk and is fully extensible using Tcl/tk scripts. The following table lists the available commands apart from the built-in Tcl commands. Command Syntax help help openport openport <port> firmware firmware version version download download <filename> [<remote filename>] nextfile nextfile deletefile deletefile renamefile programfpga renamefile <filename> programfpga monitorfpga monitorfpga initdataflash initdataflash updateprogramflash updateprogramflash [<filename>] LCD <string> LCD Action List commands and syntax. Open communication port. <port> must becom1: to com9:. Display firmware version information Display software version information Copy file from PC to data flash, then select it. If not specified, the remote filename is the same as the PC filename. The remote filename is limited to 12 characters and must contain only letters, numbers, underscore, and period. Select next file. Display new file's index, name, and length (if any). Delete selected file. Display new file's index, name, and length (if any). Rename selected file to <filename>. Display file's index, name, and length. Program FPGA from selected file. Shows a popup window continuously updated with the message from the FPGA, read from dual-port RAM locations 0x00-0x1F. Initialize data flash (erase all files). Download and reprogram firmware image in the board. Filename defaults to ebfw.bin. Display <string> on LCD. The installer sets up an icon with the following command line: First Silicon Solutions, Inc. Page 8 of 9 Confidential Material EB-ProASICPLUS Evaluation Board User Manual c:\Program Files\fs2\ebactel\bin\cliebactel.exe ebstartup.tcl ebstartup.tcl is a 2-line script that sets the default communication port, then calls the main initialization script initebactel.tcl. set defaultport "com1:" source initebactel.tcl If you attach to the unit via a port other than com1:, you can change the port in ebstartup.tcl to avoid having to issue an openport command every time you start the software. If a user.tcl exists in the startup directory, it is executed after the general initialization script has completed. This file could be used to install a different command set, create alternate display windows, etc. First Silicon Solutions, Inc. Page 9 of 9 Confidential Material