Axcelerator Evaluation Platform

Product Brief
Axcelerator Evaluation Platform
The Axcelerator evaluation platform has been designed to
demonstrate the unique capabilities of Actel’s new
Axcelerator family of FPGAs. It provides the designers an
easy to use hardware platform to evaluate and test various
Axcelerator features such as the PLL, LVDS I/Os, Block
RAMs, etc. The modularity of the platform allows the designer
to build systems to their own special requirements, providing
them with a vehicle to test their FPGA design.
PowerQUICC II DAUGHTER BOARD
RS-232
(2 x DB-9)
10/100
ETHERNET
TRANSCEIVER
(RJ-45)
2 MEGABYTE
DDR HSTL MEMORY
SILICON
EXPLORER II
Power
QUICC
II
25 LVDS PAIRS
25 LVDS PAIRS
PowerQUICC II LOCAL BUS
32 MBYTES
FLASH
155Mb/s
ATM
(RJ-45)
EXTERNAL
USER
INTERFACE
SIGNALS
PowerQUICC II SUBSYSTEM
8 LVTTL SIGNALS
128 MBYTES
SDRAM
DIMM
LOOP BACK SIGNALS
AX
FG896
FPGA
Processor Interface
HEX 10/100
ETHERNET
TRANSCEIVER
(2x3 RJ-45)
GIGABIT
ETHERNET
TRANSCEIVER
(RJ-45)
POWER
SEQUENCING
C
O
N
N
E
C
T
O
R
MII
GMII
OSC CLOCK
SOURCE
(19.44 MHz)
LVPECL, GTL+,
LVCMOS,LVTTL &
LVDS LOOP BACK VIA
EXT COMPONENTS
MULTIPLEXED
CLOCK
DRIVER
EXT CLOCK
SOURCE
(SMB)
ALT OSC
CLOCK
SOURCE
POWER
ON RESET
V
H
D
M
VOLTAGE
REGULATORS
3.3V 2.5V
1.5V 1.25V
1.0V 0.8V
0.75V
1.5V (CORE)
DIFFERENTIAL
CLOCK
DRIVER
FLEXIBLE I/O BANK
I/O AND
REFERENCE
VOLTAGE SELECT
Figure 1 • Demo Board Block Diagram
A u gu s t 2 00 3
© 2003 Actel Corporation
1
A x c e le r a t o r Ev a lu a t io n P la t f o r m
Fe a t ur es
C om m un i ca t i o n Sy st e m D ev e l op m en t
Mot her Boar d
The Axcelerator demo board provides a complete hardware
environment for developing and testing communication
system FPGA design. The Hex Ethernet and the Gigabit
Ethernet transceivers allow the FPGA to communicate with
other Ethernet devices, giving a designer the ability to
monitor traffic between the FPGA and other devices in the
system.
• LXT9763 Hex Ethernet Transceiver
• LXT1000 Gigabit Ethernet Transceiver
• VHDM High Speed Connector
• HSTL DDR Memory
• FG896 FPGA Socket
Lo op-B ack Bo ar d
Dau ght er B oar d
A loop-back board is provided with each Axcelerator demo
board. This loop-back board connects to the VHDM connector
of the Axcelerator demo board. It allows outputs from the
Axcelerator device to be brought back to inputs of the
Axcelerator device (Figure 2).
• PowerQUICC II Microprocessor
• 32 MB Flash Memory
• 128 MB SDRAM
• LXT971 Ethernet Transceiver
Mi ni Ba ckpl ane
• PM5350 155 MB/S ATM
• RS232
B as i c B u i l di n g Bl o c ks
The evaluation platform is separated into two pieces: a
mother board and a daughter board. The mother board
contains the Axcelerator FPGA (socketed), clocks, voltage
selector for I/O bank VREFs, daughter board connectors, and a
Silicon Explorer II connector.
The daughter board contains a PowerQUICC II
Microprocessor, 32MB of Flash Memory, 128MB of SDRAM,
and is connected to the mother board through the mezzanine
connectors.
An optional mini backplane, which allows two Axcelerator
demo board to be connected together, is also available from
Actel. This mini backplane allows the two Axcelerator devices
to communicate with each other, giving the designer the
ability to simulate/test two communication systems and their
communication with each other (Figure 3).
S il ic on E xp lor er II Head er
A Silicon Explorer II header is used to further enhance the
development process by allowing the designer to use the
Silicon Explorer II to perform real time probing without
having to recompile and reprogram.
Axcelerator Demo/Eval Board
AX
FG896
FPGA
4 LVTTL Signals
25 LVDS Pairs
4 LVTTL Signals
Figure 2 • System Block Diagram (1 Card)
2
Product Brief
C
O
N
N
E
C
T
O
R
Loop-Back Card
25 LVDS Pairs
V
H
D
M
A x c e le r a t o r E va l u a t io n Pla t fo r m
Axcelerator Demo/Eval Board #1
25 LVDS Pairs
AX
FG896
FPGA
4 LVTTL Signals
25 LVDS Pairs
4 LVTTL Signals
V
H
D
M
C
O
N
N
E
C
T
O
R
Axcelerator Demo/Eval Board #2
25 LVDS Pairs
AX
FG896
FPGA
4 LVTTL Signals
25 LVDS Pairs
4 LVTTL Signals
V
H
D
M
C
O
N
N
E
C
T
O
R
Figure 3 • System Block Diagram (2 Card)
D em o n s t r a t i o n A p p l i c a t i o n
One of the key features of this board is to demonstrate the
wide range of I/O standards that the Axcelerator FPGA
supports. The Axcelerator FPGA is configured to transmit
and/or receive using the following I/O standards: LVTTL-3.3V,
LVCMOS-2.5V/1.8V/1.5V, GTL+, HSTL Class I, LVDS, LVPECL,
SSTL2 Class I, SSTL2 Class II.
App li cat ion S of t war e
All of these functions are selected and controlled through
the Graphical User Interface and all results are displayed
for easy debugging. Communication from the PC to the
Axcelerator demo board is done via the 10/100 Ethernet
Interface.
Kit C ont ai ns
• Mother Board
• PowerQuicc II Daughter Board
The application software consists of two parts: a PC
Window-based client application and an embedded server
running on the PowerQUICC II processor. The application
software allows the user to control the PowerQUICC II
10/100 Ethernet and ATM interface, the Hex 10/100
Ethernet interface on the main board, and other Gigabit
Ethernet devices via MDIO. The application also allows the
user to run diagnostic tests, Double Data Rate (DDR)
memory test, LVDS loop-back, Ethernet Interfacing, as well
as read and modify memory mapped FPGA status and user
registers.
• Loop-back Board
• Power Supply
• RS232 Cable
• CD – User Guide, Demo Design Files, Board Schematic,
Application Software
• CAT-5 Cable(s)
Product Brief
3
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
955 East Arques Avenue
Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
Dunlop House, Riverside Way
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United Kingdom
Tel: +44 (0)1276 401450
Fax: +44 (0)1276 401490
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
39th Floor
One Pacific Place
88 Queensway
Admiralty, Hong Kong
Tel: 852-22735712
5172167-1/8.03
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