5 4 3 2 1 Revision History Date D ECO# Description Sheet Initiater 28/06/05 0.1 Capture the full schematic 1 to 13 Actel 29/06/05 0.2 Capture the full schematic 1 to 13 Actel 01/07/05 0.3 Capture the full schematic 1 to 13 Actel 04/07/05 0.4 Updated all correction by checking the netlist 1 to 12 Actel 07/07/05 0.5 Corrected the switch and oscillator 2,4 Actel 07/08/05 0.6 1 to 12 Actel Up dated the manufacturer and Manufacturer part number Approval D C C 07/12/05 0.7 07/21/05 0.8 07/25/05 Up dated the manufacturer and Manufacturer part number 1 to 12 Actel Changed the schematic on pages 2,8,9,11 Actel 0.9 Changed the schematic on pages 2,11,12 Actel 11/15/05 1.1 Changed schematics on pages 1 to 12 Actel 11/17/05 1.2 Changed Asynchronous SRAM by Synchrnous SRAM 3 Actel 11/17/05 1.3 Changed the values of R84 and R85 10 Actel 11/21/05 1.4 Changed schematics on pages 1 to 12 Actel 11/23/05 1.5 Changed schematics on pages 1 to 12 Actel 11/28/05 1.6 Added R101 back in schematics 6 Actel 12/01/05 1.7 Updated the Part numbers 1 to 12 Actel B B CoreARM7 DEV KIT BOARD A A Actel Corp 2061 Stierlin Ct Mountain View, CA 94043 Approvals: SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. BOARD INFORMATION PCB FAB:,REV.0X PCB ASSEMBLY:,REV.0X 4 3 2 FRONT PAGE Eng Mgr: Engr: Doc Ctrl: Assembly Size: Document No: Rev B Thursday, December 01, 2005 Date: 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 1 of 12 5 4 VIN 9V input power DC jack 2 1 3.3V Switching regulator / 5A U1 TO MEASURE CURRENT 1 6 3 3.3V C6 0.01UF/50V + C5 0.22UF/50V 2 5 1 1 3.3V@ 5A (Max) 2 D LM2678S-3.3 1 + C7 100UF/10V C10 10UF/16V 2 1 3.3V 2.5V VIN + C8 100UF/10V 2 2 C9 0.01UF/50V D1 CMSH5-40 SW1 2 1 22UH 2 CONN_KLD_SMT NC VSW 1 GND 2 4 L1 1 + C4 10UF/35V 2 + C3 10UF/35V VIN FB ON/OFF CB 1 1 1 + C2 10UF/35V 2 2 + C1 10UF/35V 2 D17 1 1 1 2 2 3 2 2 1 1 JP1 TRANZORB J1 2 7 1 9 VOLT D 3 1 1 1 3 6 2 2 D3 D2 D4 RED LED 1 GREEN LED 1 GREEN LED 1.5V Linear regulator with reset R3 1K 2 2 2 R2 78.7 1 4 GPI-152-3013 2 R1 200 5 5V_ON_OFF 3.3V U2 GND GND1 GND2 GND3 GND4 21 1 1 10 11 17 20 21 2 2 4.99K C13 C VIN 5V Switching regulator / 5A 1.5V @ 5V@ 500mA (Max) 2A (Max) U3 1 2 TPS75215_QPWP C12 0.01UF/50V + 3 L2 47UF/16V 2 2 CB VSW NC1 VIN NC2 GND 8 3.3V Pwr LED 4 1 FB ON/OFF LM2674M-5.0 VIN Pwr LED 6 3.3V C14 0.22UF/50V 5 C15 100UF/16V 5V R6 274 5V_ON_OFF 2 R5 475E 2 D6 CMSH5-40 2 1 1 100uH 2.5V Pwr LED 7 1 1.5V 5V TP1 1 R4 0.22UF/25V 19 18 16 15 14 13 12 9 8 6 2 C11 NC7 NC6 NC5 NC4 NC3 NC2 NC1 O/P9 O/P8 RESET 2 1 1 C NC IN3 IN4 EN SENSE 1 2 3 4 5 7 RESET15N C17 100UF/10V R9 4.99K GND GND1 GND2 GND3 GND4 21 1 10 11 17 20 21 2 1 3 GREEN LED R8 Q1 1 1 1 MMBT2222 2.5V @ B 2 2K R10 2K 2A (Max) 2 2.5V 2 0.22UF/25V 19 18 16 15 14 13 12 9 8 6 2 1 1 C18 NC IN3 IN4 EN SENSE D5 NC7 NC6 NC5 NC4 NC3 NC2 NC1 O/P9 O/P8 RESET 1 2 3 4 5 7 RESET25N 1 U4 B 1.5V 2 2 3.3V D7 GREEN LED 2 1 C16 0.01UF/16V 2.5V Linear regulator with reset TPS75225_QPWP 5V Pwr LED + C19 47UF/16V 2 1.5V Pwr LED DECOUPLING CAPACITORS 2.5V 1.5V C22 1 1 C21 0.1uF Actel Corp C23 0.1uF 2061 Stierlin Ct Mountain View, CA 94043 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 2 0.1uF 2 0.1uF 2 2 C20 1 A 1 A Approvals: PCB FAB:,REV.0X PCB ASSEMBLY:,REV.0X Engr: Assembly 4 3 2 Size: Document No: Rev B Thursday, December 01, 2005 Date: 5 POWER SUPPLY Eng Mgr: Doc Ctrl: BOARD INFORMATION CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 2 of 12 5 4 3 2 1 3.3V 3.3V 37 26 47 FLASH_CSN FLASH_BYTEN 12 15 FLASH_RPN 3.3V R122 10K SSRAM_CLK FLASH_RB 46 27 VSS VSS1 VCC FLASH_READN FLASH_WRITEN 89 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQPA DQPB SSRAM_GWRITEN 88 SSRAM_BWRITEN SSRAM_B0N SSRAM_B1N SSRAM_PWRDWN 87 93 94 64 E2 E1 E3 CK GW G ADSP ADSC ADV BW BA BB ZZ LBO FT B 9 10 13 14 3.3V 37 VCC RP RB VSS VSS1 28 11 FLASH_READN FLASH_WRITEN 26 47 FLASH_CSN FLASH_BYTEN 12 15 FLASH_RPN FLASH_RB MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 46 27 SSRAM_CLK M29W800DT 3.3V 37 36 35 34 33 32 100 99 82 81 80 44 45 46 47 48 49 50 43 89 SSRAM_GWRITEN 88 SSRAM_BWRITEN SSRAM_B2N SSRAM_B3N SSRAM_PWRDWN 87 93 94 64 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQPA DQPB E2 E1 E3 CK GW G ADSP ADSC ADV BW BA BB ZZ LBO FT SSRAM_READN SSRAM_ADSP SSRAM_ADSC SSRAM_ADV 0.1uF JP47 10K SSRAM_LBO SSRAM_FT 31 14 C SSRAM_LBO MEM_DATA[31:0] MEM_DATA16 MEM_DATA17 MEM_DATA18 MEM_DATA19 MEM_DATA20 MEM_DATA21 MEM_DATA22 MEM_DATA23 MEM_DATA24 MEM_DATA25 MEM_DATA26 MEM_DATA27 MEM_DATA28 MEM_DATA29 MEM_DATA30 MEM_DATA31 58 59 62 63 68 69 72 73 8 9 12 13 18 19 22 23 74 24 3.3V B R118 97 98 92 SSRAM_CSN 86 84 85 83 SSRAM_READN SSRAM_ADSP SSRAM_ADSC SSRAM_ADV SSRAM_LBO SSRAM_FT 1 C161 C162 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V BOARD INFORMATION PCB FAB:,REV.0X 2 1 10K Approvals: PCB ASSEMBLY:,REV.0X 2 CoreARM7 DEV KIT BOARD Title: MEMORY Eng Mgr: Engr: Assembly Size: Document No: Rev B Thursday, December 01, 2005 Date: 3 JP48 SSRAM_FT A 0.1uF 0.1uF 10K R121 Doc Ctrl: 2 0.1uF 1 C160 2 0.1uF 1 C159 2 0.1uF 1 1 C158 2 0.1uF 2 1 2 1 2 1 2 0.1uF C157 2 0.1uF C156 R120 10K NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 31 14 2061 Stierlin Ct Mountain View, CA 94043 C155 R119 10K Actel Corp 3.3V 4 10K GS88018 0.1uF + C154 10UF/10V 5 R116 10K R117 1 2 3 6 7 16 25 28 29 30 38 39 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 C153 5 10 17 21 26 40 55 60 67 71 76 90 0.1uF 1 C152 2 0.1uF 1 1 0.1uF C151 2 0.1uF C150 2 1 1 0.1uF C149 2 0.1uF C148 2 1 C147 2 1 0.1uF 2 2 C29 C146 2 1 1 1 0.1uF + C145 10UF/10V 1 0.1uF C28 2 0.1uF C27 2 1 C26 2 0.1uF 1 1 C25 2 0.1uF 2 1 2 C24 1 3.3V A SSRAM_CSN 86 84 85 83 R115 10K 42 51 52 53 56 57 66 75 78 79 95 96 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DECOUPLING CAPACITORS DECOUPLING CAPACITORS 97 98 92 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 E BYTE MEM_ADDR[18:0] 15 41 65 91 NC1 NC2 NC3 NC4 G W U8 MEM_DATA16 MEM_DATA17 MEM_DATA18 MEM_DATA19 MEM_DATA20 MEM_DATA21 MEM_DATA22 MEM_DATA23 MEM_DATA24 MEM_DATA25 MEM_DATA26 MEM_DATA27 MEM_DATA28 MEM_DATA29 MEM_DATA30 MEM_DATA31 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 VDD1 VDD2 VDD3 VDD4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15A-1 4 11 20 27 54 61 70 77 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 R114 10K SSRAM 512K * 16 MEM_DATA[31:0] U7 MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 R113 3.3V FLASH 512K * 16 MEM_ADDR[18:0] 3.3V 1 2 3 6 7 16 25 28 29 30 38 39 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 5 10 17 21 26 40 55 60 67 71 76 90 GS88018 D NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 M29W800DT C MEM_DATA[31:0] MEM_DATA0 MEM_DATA1 MEM_DATA2 MEM_DATA3 MEM_DATA4 MEM_DATA5 MEM_DATA6 MEM_DATA7 MEM_DATA8 MEM_DATA9 MEM_DATA10 MEM_DATA11 MEM_DATA12 MEM_DATA13 MEM_DATA14 MEM_DATA15 58 59 62 63 68 69 72 73 8 9 12 13 18 19 22 23 74 24 1 RP RB 28 11 37 36 35 34 33 32 100 99 82 81 80 44 45 46 47 48 49 50 43 3 E BYTE G W MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC1 NC2 NC3 NC4 MEM_DATA0 MEM_DATA1 MEM_DATA2 MEM_DATA3 MEM_DATA4 MEM_DATA5 MEM_DATA6 MEM_DATA7 MEM_DATA8 MEM_DATA9 MEM_DATA10 MEM_DATA11 MEM_DATA12 MEM_DATA13 MEM_DATA14 MEM_DATA15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15A-1 2 9 10 13 14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 2 D 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 MEM_ADDR[18:0] VDD1 VDD2 VDD3 VDD4 MEM_DATA[31:0] U5 MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 42 51 52 53 56 57 66 75 78 79 95 96 U6 15 41 65 91 FLASH 512K * 16 MEM_ADDR[18:0] 4 11 20 27 54 61 70 77 SSRAM 512K * 16 DRAWN BY: 1.7 Sanmina-SCI 1 Pg 3 of 12 5 4 3 2 1 MEMORY INTERFACE MISC INTERFACE FPGA BANK B0 FPGA BANK B1 U9A MEM_DATA0 MEM_DATA1 MEM_DATA2 MEM_DATA3 MEM_DATA4 MEM_DATA5 MEM_DATA6 MEM_DATA7 MEM_DATA8 MEM_DATA9 MEM_DATA10 MEM_DATA11 MEM_DATA12 MEM_DATA13 MEM_DATA14 MEM_DATA15 MEM_DATA16 MEM_DATA17 MEM_DATA18 MEM_DATA19 MEM_DATA20 MEM_DATA21 MEM_DATA22 MEM_DATA23 MEM_DATA24 MEM_DATA25 MEM_DATA26 MEM_DATA27 MEM_DATA28 MEM_DATA29 MEM_DATA30 MEM_DATA31 MEM_DATA[31:0] D C B0 I/O[0..5] TX0 TX1 B0 I/O0 B0 I/O1 B0 I/O2 B0 I/O3 B0 I/O4 B0 I/O5 VCC_IB0 1.5V B5 B4 C7 C6 D8 E8 A5 A4 B7 B6 A7 A6 G10 G9 D9 E9 A8 B8 D10 E10 G11 H11 B10 C10 F11 F10 E11 D11 A9 B9 A11 A10 B11 C11 D5 D7 F8 E7 F9 D6 A3 H9 H10 C8 A1 FPGA BANK B2 U9B IO03PDB0V0 IO03NDB0V0 IO04PDB0V0 IO04NDB0V0 IO05PDB0V0 IO05NDB0V0 IO06PDB0V1 IO06NDB0V1 IO07PDB0V1 IO07NDB0V1 IO08PDB0V1 IO08NDB0V1 IO09PDB0V1 IO09NDB0V1 IO10PDB0V1 IO10NDB0V1 IO11PDB0V1 IO11NDB0V1 IO12PDB0V2 IO12NDB0V2 IO13PDB0V2 IO13NDB0V2 IO14PDB0V2 IO14NDB0V2 IO15PDB0V2 IO15NDB0V2 IO16PDB0V2 IO16NDB0V2 IO17PDB0V2 IO17NDB0V2 IO18PDB0V2 IO18NDB0V2 IO19PDB0V2 IO19NDB0V2 GAA0/IO00NDB0V0 GAB0/IO01NDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAC1/IO02PDB0V0 GAA1/IO00PDB0V0 VCCIB0 VCCIB0_1 VCCIB0_2 VCC0 GND0 MEM_ADDR[18:0] B1 I/O[0..5] B1 I/O0 B1 I/O1 B1 I/O2 B1 I/O3 B1 I/O4 B1 I/O5 VCC_IB1 MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 FLASH_RPN FLASH_BYTEN FLASH_CSN FLASH_WRITEN FLASH_READN FLASH_RB SSRAM_PWRDWN 1.5V F12 E12 G12 H12 A12 B12 D13 D12 E14 E13 G13 F13 A13 B13 F14 G14 D15 D14 A15 A14 B17 B16 A17 A16 B18 A18 D17 D18 D16 E16 F15 E15 A20 H13 H14 C9 A21 U9C IO20PDB1V0 IO20NDB1V0 IO21PDB1V0 IO21NDB1V0 IO22PDB1V0 IO22NDB1V0 IO23PDB1V0 IO23NDB1V0 IO24PDB1V0 IO24NDB1V0 IO25PDB1V0 IO25NDB1V0 IO26PDB1V0 IO26NDB1V0 IO27PDB1V0 IO27NDB1V0 IO28PDB1V1 IO28NDB1V1 IO29PDB1V1 IO29NDB1V1 IO30PDB1V1 IO30NDB1V1 IO31PDB1V1 IO31NDB1V1 IO32PDB1V1 IO32NDB1V1 GBA0/IO35NDB1V1 GBA1/IO35PDB1V1 GBB0/IO34PDB1V1 GBB0/IO34NDB1V1 GBC0/IO33NDB1V1 GBC1/IO33PDB1V1 VCCIB1 VCCIB1_1 VCCIB1_2 VCC1 GND1 SSRAM_CLK SSRAM_CSN SSRAM_GWRITEN SSRAM_READN SSRAM_BWRITEN SSRAM_B0N SSRAM_B1N SSRAM_B2N SSRAM_B3N SSRAM_ADSP SSRAM_ADSC SSRAM_ADV RX0 RX1 RTS CTS CAN_TXD CAN_RXD USB_MODE USB_OEN USB_RCV USB_VP USB_VM USB_SUSPND USB_VMO/SEO B2 I/O0 B2 I/O1 B2 I/O2 B2 I/O3 B2 I/O4 B2 I/O5 B2 I/O6 B2 I/O[0..6] VCC_IB2 1.5V A3PE600 F18 H17 J16 G18 G19 J18 J17 H19 H18 F19 E19 G20 G21 K18 K17 J19 K20 J22 K22 L22 L21 J21 K21 L20 K19 E18 G17 H16 L19 L16 L15 K16 B21 C22 J15 K15 H20 B22 VCC_IB0 IO36NDB2V0 IO37NDB2V0 IO38NDB2V0 IO39PDB2V0 IO39NDB2V0 IO40PDB2V0 IO40NDB2V0 IO41PDB2V0 IO41NDB2V0 IO42PDB2V0 IO42NDB2V0 IO43PDB2V0 IO43NDB2V0 IO44PDB2V1 IO44NDB2V1 IO45PDB2V1 IO45NDB2V1 IO46PDB2V1 IO46NDB2V1 IO47PDB2V1 IO47NDB2V1 IO48PDB2V1 IO48NDB2V1 IO49PPB2V1 IO49NPB2V1 GBA2/IO36PDB2V0 GBB2/IO37PDB2V0 GBC2/IO38PDB2V0 GCB0/IO51NPB2V1 GCB1/IO51PPB2V1 GCC0/IO50NPB2V1 GCC1/IO50PPB2V1 VCCIB2 VCCIB2_1 VCCIB2_2 VCCIB2_3 VCC2 GND2 3.3V D VCC_IB1 3.3V VCC_IB2 3.3V C A3PE600 A3PE600 VCC_IB0 C31 1 C30 1 C32 3.3V 0.1uF 1 B 1 0.1uF 2 2 0.1uF 2 3.3V B R12 1K U11 JP49 2 1 CLOCKA_G 1 CLOCKA_GPIO C34 0.1UF/50V 1 NC R14 1K OUT 3 CLOCKF 32KHz OSCILLATOR R15 1K 2 1 2 2 2 50MHZ OSCILLATOR 3 VCC 3 2 0.1uF OUT GND NC 2 1 GND C33 0.1UF/50V C38 2 0.1uF 1 C37 2 0.1uF 1 C36 2 2 1 1 VCC 2 4 U10 4 R11 1K 1.5V 1 1 FPGA DECOUPLING CAPACITORS 0.1uF 1 C41 2 0.1uF 1 C40 2 0.1uF 1 C39 2 2 1 VCC_IB2 C42 0.1uF A A Actel Corp 0.1uF 1 C44 2 0.1uF 1 C43 2 2 1 VCC_IB1 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V C45 0.1uF 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X FPGA_012 Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 4 of 12 5 4 3 2 1 TP4 TP5 TP6 TP7 TP8 TP9 T POINT B0 ETHERNET T POINT B0 T POINT B0 T POINT B0 T POINT B0 FPGA BANK B3 T POINT B0 D FPGA BANK B4 B4 I/O[0..23] U9D M20 N16 N18 M21 N21 N19 N17 N22 P22 P21 R21 P18 P17 P19 R19 R22 T22 U22 V22 T21 U21 R18 T18 R17 P16 T19 U19 M16 L17 M19 M15 M17 N15 P15 Y22 AA21 N14 N13 USB_VPO USB_SPEED SW_EN SW_FLG RVI-ME_VTref RVI-ME_nTRST RVI-ME_TDI RVI-ME_TMS RVI-ME_TCK RVI-ME_RTCK RVI-ME_TDO RVI-ME_nSRST RVI-ME_DBGRQ RVI-ME_DBGACK B3 I/O[0..11] B3 I/O0 B3 I/O1 B3 I/O2 B3 I/O3 B3 I/O4 B3 I/O5 B3 I/O6 B3 I/O7 B3 I/O8 B3 I/O9 B3 I/O10 B3 I/O11 C VCC_IB3 1.5V FPGA BANK B5 U9E B4 I/O0 B4 I/O1 B4 I/O2 B4 I/O3 B4 I/O4 B4 I/O5 B4 I/O6 B4 I/O7 B4 I/O8 B4 I/O9 B4 I/O10 B4 I/O11 B4 I/O12 B4 I/O13 B4 I/O14 B4 I/O15 B4 I/O16 B4 I/O17 B4 I/O18 B4 I/O19 B4 I/O20 B4 I/O21 B4 I/O22 B4 I/O23 IO53NDB3V0 IO54NPB3V0 IO55NPB3V0 IO56PDB3V0 IO56NDB3V0 IO57PPB3V0 IO57NPB3V0 IO58PDB3V0 IO58NDB3V0 IO59PDB3V0 IO59NDB3V0 IO60PDB3V1 IO60NDB3V1 IO61PDB3V1 IO61NDB3V1 IO62PDB3V1 IO62NDB3V1 IO63PDB3V1 IO63NDB3V1 IO64PDB3V1 IO64NDB3V1 GDC1/IO65PDB3V1 GDC0/IO65NDB3V1 GDB1/IO66PPB3V1 GDB0/IO66NPB3V1 GDA1/IO67PDB3V1 GDA0/IO67NDB3V1 GCA1/IO52PPB3V0 GCA0/IO52NPB3V0 GCA2/IO53PDB3V0 GCB2/IO54PPB3V0 GCC2/IO55PPB3V0 VCCIB3 VCCIB3_1 VCCIB3_2 VCCIB3_3 VCC3 GND W16 V15 W14 AA17 AA16 AB15 AB14 AB17 AB16 T14 T13 AB13 AB12 U14 U13 V14 V13 AA11 Y12 AA13 AA12 Y11 W11 W13 W12 W17 V16 W15 R13 R14 AB20 R20 AB21 CLOCKA_GPIO CLOCKA_G CLOCKF RESET# VCC_IB4 1.5V VCC_IB3 U9F IO68NDB4V0 IO69NDB4V0 IO70NDB4V0 IO71PDB4V0 IO71NDB4V0 IO72PDB4V0 IO72NDB4V0 IO73PDB4V0 IO73NDB4V0 IO74PDB4V1 IO74NDB4V1 IO75PDB4V1 IO75NDB4V1 IO76PDB4V1 IO76NDB4V1 IO77PDB4V1 IO77NDB4V1 IO78PPB4V1 IO78NDB4V1 IO79PDB4V1 IO79NDB4V1 IO80PDB4V1 IO80NDB4V1 IO81PDB4V1 IO81NDB4V1 GDA2/IO68PDB4V0 GDB2/IO69PDB4V0 GDC2/IO70PDB4V0 VCCIB4 VCCIB4_1 VCCIB4_2 VCC4 GND4 FPGA_MDIO FPGA_MDC FPGA_1TXD0 FPGA_1TXD1 FPGA_1TXD2 FPGA_1TXD3 FPGA_1TX_EN FPGA_1TX_ER FPGA_EXT_IN_CLK_2 FPGA_1RXD0 FPGA_1RXD1 FPGA_1RXD2 FPGA_1RXD3 FPGA_1RX_DV FPGA_1RX_ER FPGA_EXT_IN_CLK_3 FPGA_1COL FPGA_1CRS FPGA_0TXD0 FPGA_0TXD1 FPGA_0TXD2 FPGA_0TXD3 FPGA_0TX_EN FPGA_0TX_ER FPGA_EXT_IN_CLK_0 FPGA_0RXD0 FPGA_0RXD1 FPGA_0RXD2 FPGA_0RXD3 FPGA_0RX_DV FPGA_0RX_ER FPGA_EXT_IN_CLK_1 FPGA_0COL FPGA_0CRS B5 I/O0 B5 I/O1 B5 I/O2 B5 I/O3 B5 I/O4 B5 I/O5 B5 I/O[0..5] A3PE600 VCC_IB4 A3PE600 1.5V R93 0E R94 0E R95 0E VCC_IB5 1 1 1 2 2 2 U12 T12 V12 V11 R12 R11 AA9 AA10 AA8 AA7 AB9 AB8 W9 W8 Y10 W10 U11 T11 V10 V9 U10 T10 AB7 AB6 Y7 Y6 U9 V8 AA6 AA5 AB5 AB4 AA4 Y4 W7 W5 U8 T9 W6 V7 R9 R10 AB3 Y8 Y5 IO82PDB5V0 IO82NDB5V0 IO83PDB5V0 IO83NDB5V0 IO84PDB5V0 IO84NDB5V0 IO85PDB5V0 IO85NDB5V0 IO86PDB5V0 IO86NDB5V0 IO87PDB5V0 IO87NDB5V0 IO88PDB5V0 IO88NDB5V0 IO89PDB5V0 IO89NDB5V0 IO90PDB5V1 IO90NDB5V1 IO91PDB5V1 IO91NDB5V1 IO92PDB5V1 IO92NDB5V1 IO93PDB5V1 IO93NDB5V1 IO94PDB5V1 IO94NDB5V1 IO95PPB5V1 IO95NPB5V1 IO96PDB5V2 IO96NDB5V2 IO97PDB5V2 IO97NDB5V2 IO98PDB5V2 IO98NDB5V2 IO99NDB5V2 IO100NDB5V2 IO101NPB5V2 GEA2/IO101PPB5V2 GEB2/IO100PDB5V2 GEC2/IO99PDB5V2 VCCIB5 VCCIB5_1 VCCIB5_2 VCC5 GND5 3.3V VCC_IB4 1.5V 2.5V D 3.3V J6 5 4 3 2 1 5 4 3 2 1 CON5 C VCC_IB5 1.5V 2.5V 3.3V J7 5 4 3 2 1 5 4 3 2 1 CON5 A3PE600 B B DECOUPLING CAPACITORS VCC_IB3 VCC_IB4 0.1uF C58 0.1uF 1 C57 2 0.1uF 1 C56 2 0.1uF 1 C55 2 0.1uF 1 C54 2 0.1uF 1 1 C53 2 0.1uF 1 C52 2 0.1uF 1 C51 2 0.1uF 1 C50 2 0.1uF 1 C49 2 0.1uF 1 C48 2 0.1uF 1 C47 2 0.1uF 2 C46 1 3.3V 2 2 A 1 1.5V A C59 Actel Corp 0.1uF SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X FPGA_345 Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 5 of 12 5 4 JP44 2 3 1 RESET# 100E C60 1uF SW 3.3V TCK 1 TDO 3 TMS 5 7 TDI 9 TCK GND1 TDO NC TMS VJTAG VPUMP TRST TDI GND2 2 3.3V 4 6 8 TRST 10 B CON10 DECOUPLING CAPACITORS C61 0.1uF C62 0.1uF C63 0.1uF C64 0.1uF C65 0.1uF C66 0.1uF C67 0.1uF C68 0.1uF C69 0.1uF C70 0.1uF C71 0.1uF C72 0.1uF C73 0.1uF C74 0.1uF C75 0.1uF C76 0.1uF C77 0.1uF C78 0.1uF C79 0.1uF C80 0.1uF C81 0.1uF 1 1.5V 2 1 RESET# 1 2 3 J10 3 4 2 JP43 1 2 JTAG 10K SW2 2 1 1 TRST 1 2 3 3.3V C 1 JP42 2 2.5V CON5 2 1 1.5V 5 4 3 2 1 5 4 3 2 1 1 3 B GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 VCC_IB7 J9 2 A2 A22 B1 C5 C18 D4 D19 E3 E20 J9 J14 K11 K12 K13 L10 L11 L12 L13 M11 M12 M13 N10 N11 N12 P9 P14 V3 2 3.3V CON5 1 JP41 5 4 3 2 1 2 1 2.5V R17 SW2 R18 1 JP40 1.5V 5 4 3 2 1 3.3V 2 3 VCCPLA VCCPLE VCCPLF VCCPLB VCCPLC VCCPLD D VCC_IB6 J8 A3PE600 1 F7 U7 M6 F16 M18 R16 2 VCC_IB7 2 1 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCC_IB6 IO121PDB7V0 IO121NDB7V0 IO122PDB7V0 IO122NDB7V0 IO123PDB7V0 IO123NDB7V0 IO124PDB7V0 IO124NDB7V0 IO125PDB7V0 IO125NDB7V0 IO126PDB7V0 IO126NDB7V0 IO127PDB7V1 IO127NDB7V1 IO128PDB7V1 IO128NDB7V1 IO129PDB7V1 IO129NDB7V1 IO130PDB7V1 IO130NDB7V1 IO131PDB7V1 IO131NDB7V1 IO132NDB7V1 IO133NDB7V1 IO134NDB7V1 GFB0/IO119NPB7V0 GFB1/IO119PPB7V0 GFC0/IO120NPB7V0 GFC1/IO120PPB7V0 GAB2/IO133PDB7V1 GAA2/IO134PDB7V1 GAC2/IO132PDB7V1 VCCIB7 VCCIB7_1 VCCIB7_2 VCCIB7_3 VCC7 GND7 A3PE600 1 G7 G16 L18 T16 T7 L7 2 2 2 2 2 2 1 1 1 1 1 1 2 1.5V 0E 0E 0E 0E 0E 0E 2 2 2 2 1 R105 R106 R107 R108 R109 R110 1.5V 1 1 1 1 2 2 0E 0E 0E 0E 1 0E R96 R97 R98 R99 1.5V 2 R104 1 VCC_IB6 1 2 GNDQ_1 GNDQ_2 GNDQ_3 GNDQ_4 GNDQ_5 GNDQ_6 GNDQ_7 GNDQ_8 2 1 E6 G8 E17 G15 V18 V6 T8 T15 K2 K1 L2 L3 J2 J1 J4 K4 J5 K5 J6 K6 G2 G1 G4 H4 G5 H5 H7 J7 F3 F2 H6 F4 F5 L4 L6 L8 K7 E4 E5 G6 B2 C1 J8 K8 K9 K10 1 C 2 1.5V B7 I/O0 B7 I/O1 B7 I/O2 B7 I/O3 B7 I/O4 B7 I/O5 B7 I/O6 B7 I/O7 B7 I/O8 B7 I/O9 B7 I/O10 B7 I/O11 B7 I/O12 B7 I/O13 B7 I/O14 B7 I/O15 B7 I/O16 B7 I/O17 B7 I/O18 B7 I/O19 B7 I/O20 B7 I/O21 B7 I/O22 B7 I/O23 B7 I/O24 B7 I/O25 B7 I/O26 B7 I/O27 B7 I/O28 B7 I/O29 B7 I/O30 B7 I/O31 1 0E 2 R103 1 2 2 VCC_IB5 1 1 VCC_IB7 B6 I/O0 B6 I/O1 B6 I/O2 B6 I/O3 B6 I/O4 B6 I/O5 B6 I/O6 B6 I/O7 B6 I/O8 B6 I/O9 B6 I/O10 B6 I/O11 B6 I/O12 B6 I/O13 B6 I/O14 B6 I/O15 B6 I/O16 B6 I/O17 2 0E 1 2 R102 B6 I/O[0..17] 2 1 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 1 VCC_IB3 B7 I/O[0..31] IO105PDB6V0 IO105NDB6V0 IO106PDB6V0 IO106NDB6V0 IO107PDB6V0 IO107NDB6V0 IO108PDB6V0 IO108NDB6V0 IO109NPB6V0 IO109PPB6V0 IO110PDB6V0 IO110NDB6V0 IO111PDB6V1 IO111NDB6V1 IO112PDB6V1 IO112NDB6V1 IO113PPB6V1 IO113NDB6V1 IO114PDB6V1 IO114NDB6V1 IO115NDB6V1 IO116NDB6V1 IO117NDB6V1 GFA0/IO118NDB6V1 GFA1/IO118PDB6V1 GFA2/IO117PDB6V1 GFB2/IO116PDB6V1 GFC2/IO115PDB6V1 GEA0/IO102NDB6V0 GEA1/IO102PDB6V0 GEB1/IO103PDB6V0 GEB0/IO103NDB6V0 GEC0/IO104NPB6V0 GEC1/IO104PPB6V0 VCCIB6_1 VCCIB6_2 VCCIB6_3 VCCIB6 VCC6 GND6 2 VCC_IB6 L14 L9 C14 C15 H3 J10 J11 J12 J13 K14 M14 N9 P10 P11 P12 P13 R3 Y9 Y14 Y15 0E 1 2 R101 2 1 FPGA BANK B7 U9H T4 T5 R6 R5 U2 U3 P6 P7 R4 P5 R2 T2 P2 N2 N6 N7 N5 P4 N1 M2 P3 M7 M3 L5 M5 M4 M8 N4 V5 V4 U4 U5 R7 T6 P8 Y1 AA2 N8 M9 M10 SW_0 SW_1 SW_2 SW_3 SW_4 SW_5 SW_6 SW_7 LED_0 LED_1 LED_2 LED_3 LED_4 LED_5 LED_6 LED_7 1 VCC_IB1 VMV0 VMV2 VMV1 VMV4 VMV3 VMV6 VMV5 VMV7 FPGA BANK B6 U9G 2 VCC_IB4 1 SWITCH AND LED INTERFACE 1 H8 F17 H15 U15 R15 U6 R8 F6 A19 B3 B14 B15 B19 B20 C2 C3 C4 C12 C13 C16 C17 C19 C20 C21 D1 D2 D3 D20 D21 D22 E1 E2 E21 E22 F1 F20 F21 F22 G3 G22 H1 H2 H21 H22 J3 J20 K3 L1 M1 M22 N3 N20 P1 P20 R1 T1 T3 T20 U1 U20 V1 V2 V21 W1 W2 W3 W20 W21 W22 Y2 Y3 Y13 Y16 Y17 Y19 Y20 Y21 AA3 AA14 AA15 AA18 AA19 AA20 AB10 AB11 AB18 AB19 AB22 AB2 AB1 AA22 AA1 Y18 W19 W4 V20 2 VCC_IB0 D NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68 NC69 NC70 NC71 NC72 NC73 NC74 NC75 NC76 NC77 NC78 NC79 GND43 GND42 GND41 GND40 GND39 GND38 GND37 GND36 GND35 1 VCC_IB2 TRST TRST JP39 TCK TDI TMS TDO VJTAG TRST VPUMP 2 2 U16 V17 W18 V19 T17 U18 U17 1 1 2 U9I TCK TDI TMS TDO TCK TDI TMS TDO 2 3.3V 3 C82 0.1uF VCC_IB6 VCC_IB7 3.3V JP45 0.1uF C93 1 1 C164 C94 0.1uF 2 A C163 0.01uF 2 0.1uF 1 C84 2 0.1uF 1 C83 2 0.1uF 1 C88 2 0.1uF 1 C87 2 0.1uF 1 C86 2 0.1uF 1 C85 2 2 3 2 1 A3PE600 1 2 0.33uF/50V A Actel Corp SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X FPGA_67_PLL Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 6 of 12 5 4 3 VCC_IB6 2 VCC_IB6 SW3 1 JP2 2 2 4 1 1 3 2 4 JP3 R20 2 SW_0 1 332 2 1 TL1105SP_F100Q R21 1K SW6 3 JP4 2 2 4 1 1 3 2 4 JP5 R24 2 SW_1 1 332 2 1 2 JP6 2 2 4 1 1 3 2 4 JP7 R28 2 SW_2 1 2 1 332 C 1 1 R29 1K 2 2 2 SW9 1 SW10 3 JP8 R31 2 2 4 1 2 SW_3 3 2 4 JP9 2 1 2 SW_7 R34 1K 2 2 2 2 C102 0.01UF/50V 2 R42 274 1 1 1 1 TL1105SP_F100Q R33 1K C101 0.01UF/50V 1 1 1 2 R41 274 2 1 1 2 2 1 1 2 2 1 2 R40 274 1 332 TL1105SP_F100Q R39 274 1 R32 332 R38 274 R30 1K C100 0.01UF/50V 2 C99 0.01UF/50V 1 TL1105SP_F100Q 1 TL1105SP_F100Q R37 274 SW_6 SW8 3 332 R36 274 2 2 2 2 SW7 1 R26 1K C98 0.01UF/50V R27 R35 274 SW_5 1 1 1 1 TL1105SP_F100Q R25 1K C97 0.01UF/50V 1 2 332 TL1105SP_F100Q C D 2 2 2 SW5 1 R22 1K C96 0.01UF/50V R23 1 SW_4 2 C95 0.01UF/50V D 1 1 1 TL1105SP_F100Q 1 2 332 1 1 SW4 3 R19 1 1 D15 D16 2 1 1 D14 2 D13 2 1 1 D12 2 D11 2 1 D10 2 2 2 D9 1 B 1 B JP10 1 2 LED_0 2 LED_1 2 LED_2 2 LED_3 2 LED_4 JP11 1 JP12 1 JP13 1 JP14 1 A A Actel Corp JP15 1 2 LED_5 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V JP16 1 2 LED_6 2 BOARD INFORMATION LED_7 PCB FAB:,REV.0X SWITCHES & LEDS Engr: Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: Eng Mgr: Doc Ctrl: JP17 1 2061 Stierlin Ct Mountain View, CA 94043 Approvals: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 7 of 12 5 4 3 2 BANK 0,1,2,3,4 I/O INTERFACE HEADER 1 BANK 4,5,6 I/O INTERFACE HEADER B3 I/O[0..11] D B0 I/O[0..5] J11 B0 I/O0 B0 I/O1 B0 I/O2 B0 I/O3 B0 I/O4 B0 I/O5 B1 I/O[0..5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B1 I/O0 B1 I/O1 B1 I/O2 B1 I/O3 B1 I/O4 B1 I/O5 B2 I/O[0..6] B2 I/O0 B2 I/O1 B2 I/O2 B2 I/O3 B2 I/O4 B2 I/O5 B2 I/O6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D B4 I/O[0..23] B3 I/O0 B3 I/O1 B3 I/O2 B3 I/O3 B3 I/O4 B3 I/O5 B3 I/O6 B3 I/O7 B3 I/O8 B3 I/O9 B3 I/O10 B3 I/O11 J12 B4 I/O9 B4 I/O10 B4 I/O11 B4 I/O12 B4 I/O13 B4 I/O14 B4 I/O15 B4 I/O16 B4 I/O17 B4 I/O18 B4 I/O19 B4 I/O20 B4 I/O21 B4 I/O22 B4 I/O23 B5 I/O0 B5 I/O1 B5 I/O2 B5 I/O3 B5 I/O4 B4 I/O[0..23] B4 I/O0 B4 I/O1 B4 I/O2 B4 I/O3 B4 I/O4 B4 I/O5 B4 I/O6 B4 I/O7 B4 I/O8 B5 I/O[0..5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B6 I/O[0..17] 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 B6 I/O0 B6 I/O1 B6 I/O2 B6 I/O3 B6 I/O4 B6 I/O5 B6 I/O6 B6 I/O7 B6 I/O8 B6 I/O9 B6 I/O10 B6 I/O11 B6 I/O12 B6 I/O13 B6 I/O14 B6 I/O15 B6 I/O16 B6 I/O17 B5 I/O5 HEADER 20X2 HEADER 20X2 C C 3.3V 5V RVI ME HEADER BANK 7 I/O INTERFACE HEADER 3.3V 1 3 5 7 9 11 13 15 17 19 B7 I/O[0..31] J13 J14 1 3 5 7 9 11 13 15 17 19 RVI-ME_VTref RVI-ME_nTRST RVI-ME_TDI RVI-ME_TMS RVI-ME_TCK RVI-ME_RTCK RVI-ME_TDO RVI-ME_nSRST RVI-ME_DBGRQ RVI-ME_DBGACK 2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 B7 I/O[0..31] B7 I/O0 B7 I/O1 B7 I/O2 B7 I/O3 B7 I/O4 B7 I/O5 B7 I/O6 B7 I/O7 B7 I/O8 B7 I/O9 B7 I/O10 B7 I/O11 B7 I/O12 B7 I/O13 B7 I/O14 B7 I/O15 HEADER 10X2 B DE CAPS 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 B7 I/O16 B7 I/O17 B7 I/O18 B7 I/O19 B7 I/O20 B7 I/O21 B7 I/O22 B7 I/O23 B7 I/O24 B7 I/O25 B7 I/O26 B7 I/O27 B7 I/O28 B7 I/O29 B7 I/O30 B7 I/O31 B 2 1 HEADER 20X2 C103 5V 3.3V 0.1uF A A Actel Corp SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X HEADERS Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 8 of 12 5 4 3 2 1 D D STEERING DIODE U13 1 USB TRANSCEIVER JP18 USB_MODE 2 L1 VCC L2 2 D+ 3 D- USB POWER SWITCH 3.3V U14 1 PSR05-PD10611 5V 2 1 3 4 JP23 USB_VP 2 1 5 JP24 USB_VM 2 1 6 7 JP26 USB_SUSPND 2 1 VMO/SEO RCV VPO VP D+ VM D- SUSPND SPEED GND NC P1 JP201 13 2 USB_VMO/SEO JP221 12 U15 2 USB_VPO D+ 11 SW_EN_USB 1 SW_FLG_USB 2 D- 10 3 JP251 9 2 4 USB_SPEED 8 EN OUT1 FLG IN GND O U T 2 NC1 NC2 8 1 7 0.1uF C105 6 5 220uF/10V + C104 VBUS D- 2 D- 3 D+ 1 JP21 USB_RCV OE 2 2 1 1 14 2 2 VCC 1 JP19 USB_OEN MODE 2 1 C106 0.001uF/50V MIC2025 4 GND D+ C FB1 1 C 4 GND USB1T11AM 1 2 5 6 R43 BLM18PG121SN1 4.7K SHIELD1 SHIELD2 2 USB Receptacle A-type USB CONNECTOR TP14 3.3V 3.3V U16A 14 14 U16B U16C 14 JP27 1 2 3 4 7 5 6 SW_EN_USB 7 74LCX04 2 74LCX04 R44 2 R45 2 DD+ 7 1 15K 1 15K 74LCX04 1 1 SW_EN T POINT 3.3V R46 2 4.99K B B TP15 3.3V 3.3V U16E 14 11 10 U16D 13 12 1 7 74LCX04 9 2 SW_FLG 8 7 74LCX04 1 7 5V 1 10K 1 10K U16F JP28 SW_FLG_USB R47 2 R48 2 SW_EN_USB SW_FLG_USB 3.3V 14 14 3.3V T POINT 74LCX04 R49 2 4.99K 3.3V 5V DE CAPS 0.1uF Actel Corp C108 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 0.1uF 2 2 C107 1 A 1 A 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X USB Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 9 of 12 4 3 RS-232 + TX0 JP29 2 1 JP30 2 1 2 JP31 2 1 JP32 2 1 JP33 2 1 JP34 2 1 12 20 RX0 19 CTS 18 17 RX1 C110 0.1uF C111 C1V- D 0.1uF 3 1 C2+ P2 2 1 13 TX1 27 2 + 14 RTS V+ 2 1 C112 0.1uF C1+ + 24 D 1 + 28 16 15 23 3.3V 22 26 5 9 4 8 3 7 2 6 1 C2T1IN T1OUT T2IN T2OUT T3IN T3OUT TX0_RS232 9 10 RTS_RS232 11 TX1_RS232 4 RX0_RS232 5 CTS_RS232 6 RX1_RS232 RTS_RS232 RX0_RS232 CTS_RS232 TX0_RS232 R2OUTB R1OUT R1IN R2OUT R2IN R3OUT R3IN R4OUT R4IN R5OUT R5IN FORCEON INVALID 10 11 CONNECTOR DB9F P3 5 9 4 8 3 7 2 6 1 7 RX1_RS232 8 TX1_RS232 21 FORCEOFF 10 11 CONNECTOR DB9F VCC GND 25 C 1 C 1 TRANSCEIVER U17 1 C109 0.1uF 2 2 5 C113 0.1uF + 2 MAX3243 1 3.3V 2 R84 432E 2 CAN TRANSCEIVER D18 RED LED JP38 2 3.3V 1 1 U18 1 1 2 1 CANH RXD CANL GND SHDN 7 2 JP37 6 2 D19 8 GREEN LED RS MAX3051 5 C114 0.1uF 5 9 4 8 3 7 2 6 1 1 R50 120E 2 JP36 CAN_RXD TXD 1 4 P4 VCC 1 2 2 JP35 CAN_TXD B 1 3 B 10 11 2 2 CONNECTOR DB9M 1 R85 182E 3.3V DECOUPLING CAPACITORS 3.3V 0.1uF 2 2 C115 1 A 1 A Actel Corp C116 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 0.1uF 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X CAN_RS-232_TRANSCEIVER Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg10 of 12 5 4 3 2 1 3.3V ALL THE DCAP SHOULD BE PLACED WITHIN 3MM OF THE CHIP 1 R53 1.5K ETHERNET PHY PHY POWER SUPPLY U19A 2 1 R52 1.5K 3.3V 3.3V 2 64 63 PHY_RX0+ PHY_RX0- C 79 80 1 1 1 1 1 4.7K 4.7K 4.7K 4.7K 4.7K 2 2 2 2 2 2 75 2 2 1 4 76 XTL+ INTR XTL- GPIO[1]/TP125 GPIO[0]/10TXD--/7Wire PWRDN 3.3V C121 0.1uF C122 0.1uF 28 35 3.3V 1 CRVVCC REFVCC 73 1 C123 0.1uF 51 CRVGND 3.3V REFGND 60 59 55 54 53 48 47 46 45 44 DGND1 DGND2 52 2 2 1 2 TGND1 TGND2 3.3V 72 68 62 61 58 57 56 3.3V 27 36 1 C120 0.1uF 0.1uF C124 0.1uF 71 EQVCC ADPVCC LEDLNK0# C125 0.1uF C NetPHY-1LP 65 EQGND AM79C874VI PQT12x12_80H47 LEDSPD0# 43 ETHERNET-1 JUMPER Y1 74 C127 22pF 1 TECH_SEL[0]/LINK_BT TECH_SEL[1]/SPDSEL TECH_SEL[2]/DPX LEDLNK#/LED_10LNK/LED_PCSBP_SD LEDTX#/LEDBTB LEDRX#/LEDSEL LEDCOL#/SCRAM_EN# LEDSPD[0]#/LEDBTA/FX_SEL# PCSBP ISODEF ISO REFCLK CLK25 BURN_IN C126 22pF 1 66 67 69 70 RST# 1 2 3 5 6 7 R62 1K IBREF TEST2 TEST3/SDI+ RPTR LEDDPX#/LEDTXB LEDSPD[1]#/LEDTXA/CLK25EN# ANEGA PHYAD[4]/10RXDPHYAD[3]/10RXD+ PHYAD[2]/10TXD++ PHYAD[1]/10TXD+ PHYAD[0]/10TXD- 8 1 25Mhz 2 J26 20 19 9 AM79C874VI PQT12x12_80H47 3.3V 1 0PHYAD_0 2 3 P5 B 1 PHY_TX0+ 4 2 TX+ RX+ CT1 CT2 TX- RX- 3 LEDL1 LEDL2 PHY_RX0+ 6 PHY_RX0- LEDR1 LEDR2 3 1 2 3 CON3 LED01 11 LEDSPD0# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA_MDIO FPGA_MDC FPGA_0TXD0 FPGA_0TXD1 FPGA_0TXD2 FPGA_0TXD3 FPGA_0TX_EN FPGA_0TX_ER FPGA_EXT_IN_CLK_0 FPGA_0RXD0 FPGA_0RXD1 FPGA_0RXD2 FPGA_0RXD3 FPGA_0RX_DV FPGA_0RX_ER FPGA_EXT_IN_CLK_1 FPGA_0COL FPGA_0CRS RESET# B HEADER20X2 3.3V J18 8 12 MDIO MDC 0TXD0 0TXD1 0TXD2 0TXD3 0TX_EN 0TX_ER EXT_IN_CLK_0 0RXD0 0RXD1 0RXD2 0RXD3 0RX_DV 0RX_ER EXT_IN_CLK_1 0COL 0CRS RST# 3.3V 1 GND J17 1 0PHYAD_1 2 5 2 9 10 RJ-45 13 14 LED00 LEDLNK0# NC 13 14 7 1 2 3 CON3 1 PHY_TX0C128 0.1uF 3.3V J16 CON-RJ45 2 VDD1 VDD2 R56 10K NetPHY-1LP COL/10COL CRS/10CRS 14 15 16 17 18 RST# 3.3V TVCC1 TVCC2 0.1uF C119 12 50 2 R57 R58 R59 R60 R61 TEST0/FXRTEST1/FXR+ FXT+ FXT- 2 RXD[0]/10RXD RXD[1] RXD[2] RXD[3] RX_DV RX_ER/RXD[4] RX_CLK/10RXCLK 41 42 0COL 0CRS 0PHYAD_0 0PHYAD_1 0PHYAD_2 0PHYAD_3 0PHYAD_4 PHY AD = 02h OGND1 OGND2 C118 1 2 22.1E PLLGND 3.3V 2 R55 1 26 25 24 23 29 31 30 0RXD0 0RXD1 0RXD2 0RXD3 0RX_DV 0RX_ER D 1 11 RX+ RX- 22.1E EXT_IN_CLK_1 C117 0.1uF 1 PHY_TX0+ PHY_TX0- 13 49 2 77 78 1 TX+ TX- TXD[0]/10TXD TXD[1] TXD[2] TXD[3] TX_EN/10TXEN TX_ER/TXD[4] TX_CLK/10TXCLK/PCSBP_CLK OVDD1 OVDD2 1 2 37 38 39 40 34 32 33 PLLVCC 1 1 0TXD0 0TXD1 0TXD2 0TXD3 0TX_EN 0TX_ER 10 MDIO MDC 2 R54 EXT_IN_CLK_0 21 22 2 2 D 3.3V U19B MDIO MDC C129 0.1uF 1 0PHYAD_2 2 3 1 2 3 CON3 J19 1 0PHYAD_4 2 3 1 2 3 CON3 J00-0065 3.3V J20 1 3.3V 0PHYAD_3 2 3 LED01 LED00 R63 1 R64 1 2 330E 2 330E A 1 2 3 CON3 A 3.3V Actel Corp PHY_TX0PHY_TX0+ PHY_RX0PHY_RX0+ R65 R66 R67 R68 1 1 1 1 2 2 2 2 SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 49.9E 49.9E 49.9E 49.9E C130 0.1uF 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X ETHERNET-1 Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg 11 of 12 5 4 3 2 1 ALL THE DCAP SHOULD BE PLACED WITHIN 3MM OF THE CHIP ETHERNET PHY U20A 41 42 1COL 1CRS 1PHYAD_0 1PHYAD_1 1PHYAD_2 1PHYAD_3 1PHYAD_4 PHY AD = 04h R72 R73 R74 R75 R76 1 1 1 1 1 2 2 2 2 2 4.7K 4.7K 4.7K 4.7K 4.7K 14 15 16 17 18 66 67 69 70 OGND1 OGND2 VDD1 VDD2 TECH_SEL[0]/LINK_BT TECH_SEL[1]/SPDSEL TECH_SEL[2]/DPX 72 68 62 61 58 57 56 R71 1 2 10K 12 50 3.3V 3.3V 27 36 1 C134 0.1uF 4 76 IBREF TEST2 TEST3/SDI+ RPTR LEDDPX#/LEDTXB LEDSPD[1]#/LEDTXA/CLK25EN# ANEGA TVCC1 TVCC2 3.3V 52 TGND1 TGND2 DGND1 DGND2 1 PLLGND C133 0.1uF C135 0.1uF 2 79 80 1 11 D C132 0.1uF 2 C131 0.1uF 2 PHY_RX1+ PHY_RX1- 1 64 63 3.3V 13 49 2 1 OVDD1 OVDD2 3.3V NetPHY-1LP PHYAD[4]/10RXDPHYAD[3]/10RXD+ PHYAD[2]/10TXD++ PHYAD[1]/10TXD+ PHYAD[0]/10TXD- 8 C136 0.1uF 28 35 3.3V CRVVCC 51 3.3V 55 54 53 REFVCC C137 0.1uF 73 CRVGND 60 59 RST# REFGND C138 0.1uF 71 EQVCC ADPVCC 1 RST# RX+ RX- TEST0/FXRTEST1/FXR+ FXT+ FXT- COL/10COL CRS/10CRS PLLVCC 2 RXD[0]/10RXD RXD[1] RXD[2] RXD[3] RX_DV RX_ER/RXD[4] RX_CLK/10RXCLK 3.3V U20B 10 1 2 22.1E 26 25 24 23 29 31 30 1RXD0 1RXD1 1RXD2 1RXD3 1RX_DV 1RX_ER 3.3V PHY_TX1+ PHY_TX1- 2 R70 1 TXD[0]/10TXD TXD[1] TXD[2] TXD[3] TX_EN/10TXEN TX_ER/TXD[4] TX_CLK/10TXCLK/PCSBP_CLK 77 78 1 2 22.1E 37 38 39 40 34 32 33 TX+ TX- 2 EXT_IN_CLK_3 R69 1 1TXD0 1TXD1 1TXD2 1TXD3 1TX_EN 1TX_ER PHY POWER SUPPLY MDIO MDC 1 EXT_IN_CLK_2 21 22 2 D MDIO MDC 1 2 3 5 6 7 R77 1K 1 2 C140 22pF 2 75 2 1 1 1 XTL+ INTR XTL- GPIO[1]/TP125 GPIO[0]/10TXD--/7Wire PWRDN LEDLNK1# LEDSPD1# 25Mhz 2 AM79C874VI PQT12x12_80H47 20 19 9 ETHERNET-2 JUMPER J27 3.3V CON-RJ45 3.3V J21 1 1 2 3 1PHYAD_0 2 1 PHY_TX1+ TX+ RX+ CT1 CT2 TX- RX- 3 3 PHY_RX1+ J22 1 1PHYAD_1 2 3 CON3 5 1 2 3 CON3 7 NC RJ-45 6 PHY_RX1- 8 GND 2 2 PHY_TX1- C143 0.1uF 3.3V LEDL1 LEDR1 LEDL2 LEDR2 13 14 9 10 13 14 LED10 12 LED11 11 LEDSPD1# 1 1 2 3 1PHYAD_2 2 3 CON3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 FPGA_MDIO FPGA_MDC FPGA_1TXD0 FPGA_1TXD1 FPGA_1TXD2 FPGA_1TXD3 FPGA_1TX_EN FPGA_1TX_ER FPGA_EXT_IN_CLK_2 FPGA_1RXD0 FPGA_1RXD1 FPGA_1RXD2 FPGA_1RXD3 FPGA_1RX_DV FPGA_1RX_ER FPGA_EXT_IN_CLK_3 FPGA_1COL FPGA_1CRS RESET# B HEADER20X2 3.3V J23 LEDLNK1# MDIO MDC 1TXD0 1TXD1 1TXD2 1TXD3 1TX_EN 1TX_ER EXT_IN_CLK_2 1RXD0 1RXD1 1RXD2 1RXD3 1RX_DV 1RX_ER EXT_IN_CLK_3 1COL 1CRS RST# 1 1 4 2 EQGND 43 P6 3.3V C142 0.1uF C NetPHY-1LP 65 AM79C874VI PQT12x12_80H47 B C139 0.1uF Y2 74 C141 22pF LEDLNK#/LED_10LNK/LED_PCSBP_SD LEDTX#/LEDBTB LEDRX#/LEDSEL LEDCOL#/SCRAM_EN# LEDSPD[0]#/LEDBTA/FX_SEL# PCSBP ISODEF ISO REFCLK CLK25 BURN_IN 2 C 48 47 46 45 44 J24 1 1PHYAD_3 2 3 1 2 3 CON3 J00-0065 3.3V 3.3V R78 1 R79 1 LED11 LED10 2 330E 2 330E J25 1 1 2 3 1PHYAD_4 2 3 3.3V A R80 R81 R82 R83 1 1 1 1 2 2 2 2 CON3 A Actel Corp 49.9E 49.9E 49.9E 49.9E SCHEMATIC DIAGRAM NOTES 1.UNLESS STATED OTHERWISE: A.ALL RESISTOR ARE IN OHMS, 5% TOLERANCE. B.ALL CAPACITORS ARE IN MICROFARADS,10% TOLERANCE. C.ALL DECOUPLING CAOACITORS ARE 0.1uF/10V 2 1 PHY_TX1PHY_TX1+ PHY_RX1+ PHY_RX1- C144 0.1uF 2061 Stierlin Ct Mountain View, CA 94043 Approvals: PCB FAB:,REV.0X ETHERNET-2 Eng Mgr: Engr: Doc Ctrl: BOARD INFORMATION Assembly PCB ASSEMBLY:,REV.0X Size: Date: 4 3 2 Document No: Rev B Thursday, December 01, 2005 5 CoreARM7 DEV KIT BOARD Title: DRAWN BY: 1.7 Sanmina-SCI 1 Pg12 of 12