SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Demo Guide

SmartFusion2 SoC FPGA In-System
Programming Using USB OTG Controller
Interface
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Demo Guide
May 2014
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface
Revision History
Date
Revision
Change
3 May 2014
3.0
Fourth release
16 December 2013
2.0
Third release
27 November 2013
1.0
Second release
09 October 2013
0.0
First release
Confidentiality Status
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This is a non-confidential document.
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Microsemi Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
In-System Programming Using USB OTG Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Requirements and Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Demo Design Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setting Up the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Alternate Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Board Setup Snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Running the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Authenticate Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
17
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21
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Checking if the Fabric is Programmed Successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Checking if the eNVM is Programmed Successfully . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Programming Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Appendix 1: Connecting the SmartFusion2 Device to the Host PC Through the USB to UART (FTDI) Interface .
Appendix 2: Board Setup when using the USB-RS232 Serial Adapter or RS232 Cable . . . . . . . . . . . . . . . . . . . .
Appendix 3: Board Setup Through the USB to UART (FTDI) Interface using the USB A to Mini - B Cable . . . . .
Appendix 4: Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 5: Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 6: Generating .spi Programming File using Libero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
26
27
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A List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-31
B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-32
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
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Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision 3
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Preface
About this document
This demo is for SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices. It
provides instructions on how to use the corresponding reference design.
Intended Audience
•
FPGA designers
•
Embedded designers
•
System-level designers
References
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SmartFusion2 devices are used by:
Microsemi Publications
SmartFusion2 Programming User Guide
•
SmartFusion2 System Controller User Guide
•
SmartFusion2 Microcontroller Subsystem User Guide
•
SmartFusion2 SoC FPGA Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories
Application Notes
•
Configuring Serial Terminal Emulation Programs Tutorial
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•
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See the following web page for a complete and up-to-date listing of SmartFusion2 device documentation:
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documents.
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In-System Programming Using USB OTG
Controller Interface
Introduction
You can use in-system programming (ISP) to reprogram for design iterations and field upgrades.
SmartFusion2 devices support ISP using universal serial bus (USB) on-the-go (OTG) controller interface.
This document describes how to program the following using ISP through the USB OTG controller
interface:
Embedded nonvolatile memory (eNVM)
•
FPGA fabric
•
Both the eNVM and the FPGA fabric
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For information on different programming modes supported by SmartFusion2 SoC FPGAs, refer to the
SmartFusion2 Programming User Guide. For information on USB OTG controller, refer to the
SmartFusion2 Microcontroller Subsystem User Guide.
Requirements and Details
Table 1 • Reference Design Requirements and Details
Hardware Requirements
SmartFusion2 Development Kit
•
12 V adapter
•
FlashPro4 programmer
USB A to Mini-B cable
•
USB cable with Micro-A end
Rev C or later
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Description
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Reference Design Requirements and Details
USB-RS232 Serial adapter or RS232 cable
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Host PC or Laptop
Windows 64-bit Operating System
Software Requirements
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Libero® System-on-Chip (SoC) for viewing the design
files
•
11.3
FlashPro Programming Software v11.3
Host PC Drivers
USB to UART drivers
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In-System Programming Using USB OTG Controller Interface
Demo Design
Introduction
The demo design files are available for download from the following path in the Microsemi® website:
http://soc.microsemi.com/download/rsc/?f=sf2_isp_using_usb_interface_demo_df
The demo design files include:
•
Sample programming files
•
Libero SoC project
•
STAPL programming file
•
readme.txt
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Figure 1 shows the top level structure of the design files. For further details, refer to the readme.txt file.
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Demo Design Files Top Level Structure
Figure 2 describes the demo. The SmartFusion2 device application configures the following:
The MMUART_1 peripheral for serial communication with host PC.
•
The USB OTG as mass storage class host, which can read or write files from the mass storage
device connected to the SmartFusion2 device through USB cable with Micro A end.
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The SmartFusion2 device also initializes the system controller to run the ISP service. The SmartFusion2
device detects the connected USB mass storage device and accesses the programming files. The
Cortex-M3 processor reads 512 byte blocks of the programming file data from the USB mass storage
device and sends the received blocks of data to the system controller ISP service. The system controller
ISP service executes the ISP operation in the requested mode and reports the status to the Cortex-M3
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SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
processor. Refer to the "Demo Design Description" section on page 8 for information on the various
modes of operation.
Cortex-M3
System
Controller
MSS
COMM_
BLK
COMM_
BLK
Cache
Controller
USB Mass
Storage Device
USB OTG
APB_1
SII
Master
UJTAG
AHB Bus Matrix
eNVM_0
FPGA Fabric
eNVM_1
APB_1
Top Level Demo Diagram
Host PC
Data Transfer from
USB Mass Storage Device
Programming eNVM and/or
Fabric using System
Controller ISP Service
SmartFusion2
Figure 2 •
MMUART_1
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AHB SII
Master
There are two ways to connect the host PC to the SmartFusion2 device:
•
Using the USB-RS232 Serial adapter or the RS232 cable.
•
Using the USB to UART (FTDI) interface.
Refer to the "Appendix 1: Connecting the SmartFusion2 Device to the Host PC Through the
USB to UART (FTDI) Interface" on page 24.
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Refer to the "Running the Demo Design" section on page 12.
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In-System Programming Using USB OTG Controller Interface
Demo Design Features
This demo design performs three types of programming based on the input provided by the programming
file.
•
eNVM programming: The ISP programming service programs only eNVM. In this case the input
programming file has only eNVM content.
•
FPGA fabric programming: The ISP programming service programs only the FPGA fabric. In
this case the input programming file has only the FPGA fabric content.
•
eNVM and FPGA fabric programming: The ISP programming service programs both the FPGA
fabric and eNVM. In this case the input programming file has both the FPGA fabric and eNVM
content.
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Demo Design Description
The ISP in SmartFusion2 devices is performed by the Cortex-M3 processor and the system controller.
The system controller manages the SmartFusion2 device programming and handles the system service
requests. The SmartFusion2 device allows the Cortex-M3 processor to directly provide a bitstream to the
system controller for programming. The Cortex-M3 processor initializes the system controller and
receives the programming bitstream from the USB mass storage device through the USB OTG controller
interface. The received bitstream is sent to the system controller to execute the ISP service in one of the
following modes of operation:
Authenticate: System controller ISP service validates the integrity of the input data bitstream and
reports the status information to the Cortex-M3 processor.
–
Program: System controller ISP service programs the following depending on the input data
bitstream:
–
eNVM
–
FPGA fabric
–
Both the eNVM and the FPGA fabric
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•
For security and reliability reasons, Microsemi recommends that the bitstream is
authenticated before the program is executed using Authenticate Operation mode. The
SmartFusion2 device application must commit only the bitstream for programming after
successful authentication and the integrity of the bitstream is validated.
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•
•
Verify: System controller ISP service verifies the contents of the SmartFusion2 device against the
input data bitstream and reports the status information to the Cortex-M3 processor.
The system controller ISP service utilizes the COMM_BLK interface to receive the entire programming
data bitstream as a continuous stream of bytes. Refer to the SmartFusion2 Microcontroller Subsystem
User Guide for more information on communication block (COMM_BLK).
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The Cortex-M3 processor in the SmartFusion2 device can execute an application image from embedded
SRAM (eSRAM), eNVM or DDR/SDR memories. Refer to the SmartFusion2 SoC FPGA Remapping
eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Notes for more information on remapping
techniques. In this demo design, the Cortex-M3 processor executes the ISP application image from
eSRAM while the eNVM programming taking place, that is during Program operation mode. In order to
execute the application image from eSRAM, the Cortex-M3 processor copies the ISP application image
(resides in eNVM data client) to the eSRAM and remaps the eSRAM to the Cortex-M3 processor code
region. For Verify and Authenticate operation modes, the application image can be executed from either
eNVM or eSRAM since the eNVM programming is not taking place.
Programming Files
Sample programming files with the file extension .spi are provided to program:
•
eNVM
•
FPGA Fabric
•
Both the eNVM and the FPGA fabric
The folder <download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files
contains the following sample programming files along with Libero design files.
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R e vi s i o n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
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envmonly.spi: Programs only eNVM. The eNVM client has a simple message display program.
•
fabriconly.spi: Programs only the FPGA fabric. The FPGA fabric has a light-emitting diode
(LED) blinking logic.
•
fabenvm.spi: Programs both the FPGA fabric and eNVM. The eNVM client has a message
display program and the FPGA fabric has an LED blinking logic.
•
isp_demo.spi: This is the .spi file format version of isp_demo.stp file provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\stapl_programming_file.
Note: For more information on generating .spi programming files refer to the "Appendix 6: Generating
.spi Programming File using Libero" on page 29.
ISP Execution Flow
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Figure 3 on page 10 describes the ISP flow. The SmartFusion2 Device application initially configures the
USB OTG controller in Host mode and MMUART_1 for serial communication. It also initializes the
system controller to start the ISP service in the selected operation mode.
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On receiving the ISP operation mode and the programming file index, the application starts reading the
input source programming file in a 512 byte blocks. The application stores the received data in a
temporary buffer and sends the same data to the ISP service. The application requests the next block of
512 byte data until the entire file gets transferred from the USB mass storage device. The SmartFusion2
Device application is notified with a status code when the ISP service completes the authentication or the
verification process. When the operation mode is Program, an internal device reset is generated for the
new design to take effect.
Revision 3
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In-System Programming Using USB OTG Controller Interface
Figure 3 shows the ISP execution flow.
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SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Setting Up the Demo Design
1. Connect the FlashPro4 programmer to the J59 connector of the SmartFusion2 Development Kit
board.
2. Connect the host PC to the DB9-RS232 connector provided on the SmartFusion2 Development
Kit board using the USB-RS232 serial adapter cable or the RS232 cable.
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When using USB-RS232 serial adapter cable, make sure that the USB-RS232 serial adapter
drivers are automatically detected. Figure 4 shows an example Device Manager window that has
the USB-to-Serial Comm Port listed under Ports (Comm & LPT). COM port number is required
to run the demo design, so make a note of it.
Figure 4 •
USB-to-Serial Communication Port
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In-System Programming Using USB OTG Controller Interface
3. Connect the jumpers on the SmartFusion2 Development Kit board, as described in Table 2. For
information on jumper locations, refer to the "Appendix 4: Jumper Locations" on page 27.
–
Caution: Before making the jumper connections, switch off the power supply switch, SW7.
Table 2 • SmartFusion2 Development Kit Jumper Settings
Jumper Number
Settings
Notes
J70, J93, J94, J117, J123, J142,
J157, J160, J167, J225, J226, J227
1-2 closed
These are the default jumper settings of the Development Kit
board. Make sure these jumpers are set accordingly.
J2
1-3 closed
2-3 closed
J139
1-2 closed
Jumper to select USB reset.
J163
1-2 closed
Jumper to select USB OTG mode of operation.
J164
1-2 closed
Jumper to provide the VBUS supply to USB when using in
Host mode.
J188, 197
1-2 closed
•
Jumper settings when using MMUART_1. These are not
set by default and must be set manually.
•
Leave these jumpers open if the USB to UART (FTDI)
interface is used. Refer to "Appendix 3: Board Setup
Through the USB to UART (FTDI) Interface using the USB
A to Mini - B Cable".
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J23
4. Connect the power supply to the J18 DC jack.
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Alternate Setup
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This demo can also be run using the USB to UART (FTDI) interface without using the USB-RS232 serial
adapter or the RS232 cable. Refer to "Appendix 1: Connecting the SmartFusion2 Device to the Host PC
Through the USB to UART (FTDI) Interface" on page 24 for information on how to connect the host PC to
the SmartFusion2 Development Kit board for serial communication through the FTDI USB interface using
the USB A to Mini - B cable.
Board Setup Snapshot
Snapshots of the SmartFusion2 Development Kit board with all the setup made in both types of
connections are given in the following appendices:
"Appendix 2: Board Setup when using the USB-RS232 Serial Adapter or RS232 Cable" on
page 25
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•
•
"Appendix 3: Board Setup Through the USB to UART (FTDI) Interface using the USB A to Mini - B
Cable" on page 26
Running the Demo Design
1. Download the demo design from:
http://soc.microsemi.com/download/rsc/?f=sf2_isp_using_usb_interface_demo_df.
2. Switch ON the SW7 power supply switch.
3. Start any serial terminal emulation program such as:
12
–
HyperTerminal
–
PuTTY
–
Tera Term
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
The configuration for the program is:
–
Baud Rate: 57600
–
8 Data bits
–
1 Stop bit
–
No Parity
–
No Flow Control
For information on configuring the serial terminal emulation programs, refer to the Configuring
Serial Terminal Emulation Programs Tutorial.
4. Connect the USB cable Micro A end to the P1 connector of SmartFusion2 Development Kit board
and other end to the USB mass storage device.
The USB OTG controller in Host mode is tested to work with mass storage devices listed below:
Sandisc CruzeerBlade - 16Gb/8Gb/4Gb/1GB
–
Kingston Datatraveller - 4Gb/2Gb
–
Kingston DT109B - 8GB
–
Transcend JetFlash - 4Gb
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Make sure to connect preformatted USB Flash drive to the SmartFusion2 device with the sample
programming files provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files.
5. Launch the FlashPro software.
6. Click New Project.
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7. In the New Project window, type the project name.
Figure 5 •
FlashPro New Project
8. Click Browse and navigate to the location where you want to save the project.
9. Select Single device as the Programming mode.
10. Click OK to save the project.
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In-System Programming Using USB OTG Controller Interface
11. Click Configure Device on the FlashPro GUI.
FlashPro Project Configured
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Figure 6 •
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12. Click Browse and navigate to the location where the isp_demo.stp file is located and select the
file. The default location is:
<download_folder>\sf2_isp_using_usb_interface_demo_df\stapl_programming_file. The required
programming file is selected and is ready to be programmed in the device.
14
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Figure 7 •
pe
rs
ed
ed
13. Click PROGRAM to start programming the device. Wait until you get a message indicating that
the program passed. ISP requires the SmartFusion2 device to be preprogrammed with the
application code to activate the ISP service. So, the SmartFusion2 device is preprogrammed with
the isp_demo.stp using FlashPro software.
FlashPro Program Passed
–
LEDs 5 to 8 blinking in the board indicates that the SmartFusion2 device fabric is
preprogrammed successfully.
Su
On programming the SmartFusion2 device successfully using FlashPro, the serial terminal
emulation program shows the initialization messages and ISP operation modes as shown in
Figure 8 on page 16.
Revision 3
15
pe
ISP Operation Modes Selection
Su
Figure 8 •
rs
ed
ed
In-System Programming Using USB OTG Controller Interface
16
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
14. On selecting the operation mode, the files in the USB storage device are displayed as shown in
Figure 9.
Figure 9 •
pe
rs
ed
ed
Note: Maximum of 10 files can be shown from the USB storage device.
Available Files in USB Mass Storage Device
Su
15. Select the programming file from the listed files by its index to perform the selected ISP operation
mode.
Authenticate Operation Mode
To authenticate the data from fabenvm.spi, enter:
1. 0 to select Authenticate operation mode under Select ISP operation mode.
2. The corresponding index number to select fabenvm.spi programming file.
Revision 3
17
In-System Programming Using USB OTG Controller Interface
Su
pe
rs
ed
ed
On selecting the programming file, the application starts reading the programming file from USB
mass storage device to execute the ISP operation mode. On completion of the ISP
authentication, the serial terminal emulation program displays an operation success message.
Figure 10 shows the operation success message.
Figure 10 • ISP Authentication Results
3. Enter any value to try other ISP operation modes. If the USB storage device files are not
displayed on serial terminal emulation program, press SW9 to reset the board.
18
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Verify Operation Mode
To verify the device FPGA fabric and eNVM contents, enter:
1. 2 to select Verify operation mode under Select ISP operation mode.
2. The corresponding index number to select isp_demo.spi programming file.
Su
pe
rs
ed
ed
On selecting the programming file, the application starts reading the programming file from USB
mass storage device to execute the ISP operation mode. On completion of the ISP verification,
the serial terminal emulation program displays an operation success message. Figure 10 shows
the operation success message.
Figure 11 • ISP Verification Results
The verification operation demonstrated is for the isp_demo.stp file that is already running in the
SmartFusion2 device. If any other .spi file is verified while the isp_demo.stp file is still running,
that verification operation fails.
Revision 3
19
In-System Programming Using USB OTG Controller Interface
If the verification fails, the serial terminal emulation program displays an error message with an
error code. Figure 12 shows an example error message. For more information on error codes,
refer to the "Appendix 5: Error Codes" on page 28.
The programming files are at:
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files.
Su
pe
rs
ed
ed
All of them do not pass the verification. Only the isp_demo.spi file passes the verification
operation as it matches with the SmartFusion2 device contents (isp_demo.stp). The other
programming files fail verification.
Figure 12 • ISP Verification Failure Error Message
3. Enter any value to try other ISP operation modes. If the USB storage device files are not
displayed on the serial terminal emulation program, press SW9 to reset the board.
20
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Program Operation Mode
To program the FPGA fabric and the eNVM of the SmartFusion2 device using the fabenvm.spi file,
enter:
1. 1 to select Program operation mode under Select ISP operation mode.
2. The corresponding index number to select fabenvm.spi programming file.
On selecting the programming file, the application starts reading the programming file from the
USB mass storage device to execute the ISP operation mode. The application checks the data
integrity of the selected programming file prior to perform the ISP program operation. Once the
programming operation is completed, an internal reset is generated for the new design to take
effect.
Su
pe
rs
ed
ed
Figure 13 shows selection of program operation mode for the fabenvm.spi programming file.
Figure 13 • ISP Program Operation Mode
Revision 3
21
In-System Programming Using USB OTG Controller Interface
Press SW9 to reset the SmartFusion2 Development Kit or Power Cycle the SmartFusion2 Development
Kit.
Checking if the Fabric is Programmed Successfully
LEDs 1 to 4 blinking in the board indicates that the fabric is programmed successfully.
Checking if the eNVM is Programmed Successfully
Su
pe
rs
ed
ed
The serial terminal emulation program displays the success message as shown in Figure 14 if the eNVM
is programmed successfully.
Figure 14 • ISP Program Results
22
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Programming Results
The result shown in Figure 14 on page 22 is for the fabenvm.spi file. Table 3 shows the possible
results for ISP Program operation mode for sample programming files provided in folder
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_files. Not all .spi
files listed in the table are demonstrated.
Table 3 • ISP Programming Results
*.spi Programming
File Name
eNVM Programming Result
FPGA Fabric Programming Result
envmonly.spi
The serial terminal emulation program shows successful NA
eNVM program message
fabonly.spi
NA
fabenvm.spi
The serial terminal emulation program shows successful SmartFusion2 LEDs 1 to 4 blinks
eNVM program message
ed
ed
SmartFusion2 LEDs 1 to 4 blinks
Su
pe
rs
After successful ISP Program operation, the SmartFusion2 Development Kit board must be
reprogrammed with the original isp_demo.stp file to try the ISP operation modes again.
Revision 3
23
In-System Programming Using USB OTG Controller Interface
Appendix 1: Connecting the SmartFusion2 Device to the Host
PC Through the USB to UART (FTDI) Interface
The following procedure describes how to connect the SmartFusion2 device to the host PC through the
USB to UART (FTDI) interface using a USB A to Mini-B Cable for serial communication:
1. Connect the host PC to the J24 connector using the USB A to Mini-B cable.
Su
pe
rs
ed
ed
2. Make sure that the USB to UART bridge drivers are automatically detected. Of the four COM
ports, select the one with Location as on USD Serial Converter D. Figure 15 shows an example
Device Manager window that has the USB Serial Port and its properties showing the port
number and location. COM port number is required to run the demo design, so make a note of it.
Figure 15 • Device Manager window Showing the USB Serial Port
3. Connect the jumpers as follows:
24
–
Pin 2 of J197 to pin 3 of J129
–
Pin 2 of J188 to pin 3 of J133
–
Figure 17 on page 26 shows these pin connections.
–
Refer to Figure 18 on page 27 for the location of the jumpers. These connections are required
for connecting the MMUART_1 TXD and RXD signals to the FTDI USB to UART bridge
available in the SmartFusion2 Development Kit board.
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Appendix 2: Board Setup when using the USB-RS232 Serial
Adapter or RS232 Cable
Power supply
switch SW7
ed
ed
DC Jack
to connect
12 V adapter
USB Mass
Storage device
USB-RS232
serial adapter
pe
DB9-RS232
connector
rs
USB cable with
Micro A end
FlashPro4
Connector
LED 1 to LED 8
SW9 to reset
Su
Figure 16 • Board Setup when using the USB-RS232 Serial Adapter or RS232 Cable
Revision 3
25
In-System Programming Using USB OTG Controller Interface
Appendix 3: Board Setup Through the USB to UART (FTDI)
Interface using the USB A to Mini - B Cable
ed
ed
Power supply
switch SW7
DC Jack
to connect
12 V adapter
USB Mini - B Connector
Pin 2 of J197 to Pin 3 of J129
Pin 2 of J188 to Pin 3 of J133
USB Mass Storage device
rs
USB cable with
Micro A end
pe
FlashPro4
Connector
LED 1 to LED 8
SW9 to reset
Su
Figure 17 • Board Setup when Through the USB to UART (FTDI) Interface using the USB A to Mini - B Cable
26
R e visio n 3
SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
B11
B14
R26
C7
R27
R25
R24
R23
R36
R56
DS11 PGOOD
R52
R35
C42
6
AT FLAG
DS10
R55
C44
C58
R130
SC2
D11
C71
R131
U20
J44
SC1
U15 R104
C61
C68
SC3
SC4
R123
J31
L5
4
ON
OFF
D5
D6
3
1
R22
R21
C6
CONN1
R80
R113
R81
R114
DS16 P1LED3
DS17 P1LED2 R82
DS18 P1LED1
DS19 P1LED0 R83 DS12 P0LED3
DS13 P0LED2
DS14 P0LED1
DS15 P0LED0
POE PWR ENB
HPOUTCLK5
C32
C33
R50
R100
R111
R112
R150
R151
R152
R157R153
R154
C78
C79
R158R155
R137
C74
1
DS22
J103
U33
C84
GND
T2
J112
1
R170
Q18
DS25
J116
1
J132
R189
C105
U37
GND
C111
L10
A
B
C
D
E
F
G
H
J
TXN0
RXP0
RXN0
TXP2
TXN2
TXP1
TXN1
RXN1
RXP1
TXP3
TXN3
C119
C120
C121
TXP0
C134
J150
J148
J149
J171
R244
1P0V_PHY
J186 J182
J192
J191
RXN2
RXP2
RXN3
RXP3
D14
J189
TS_MDIO
TP25
J190
R238
R239
R240
R241
J185
TS_MDC
J169
J168
R243
R242
1 R247
J170
R219
J156
J166
1
C152
C153
R278
R279
J147
J151
C128
C129
C130
C131
L13
U45 R220
R221
1
R670
R230
J177
1
R377
R378
R379
R380
R381
R382
R383
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
1
J229
1
DDR3_1P5V
TP21 R354
R355
D18
R365 C204
R366
D20
TP20
R346
D17
D16
R339
R338
U61
TP12
U59
C200 C202
DVDD12
R375
D15
GND
R325
C186
R350
TP24
C198
J220
J219
J228
J207
J206
2P5V_LDO
U60
R353
LED8
LED7
R374 R364
LED6
R373 R363
LED5
R372 R362
LED4
R371 R361
LED3
R370 R360
LED2
R369 R359
R326
C191
R356 C189
SERDES1
REFCLK0_N
J208
GND
SF2 DEV KIT
LED1
R368 R358
R132
R143
J205
R312
3P3V_LDO
C70
Q15
GND
TP14
J211
DDR3_VTT
R367 R357
1
T1
J80
R182
R183
789
123
1
J160
RS6 1
J167
C150
C151
R276
R277
R102
R103
J16
R30
J15
R32
R46
J67
R178
R179
R184
R185
C94
C95
1
J142
R203
R204
R206
R207
R212
R217
C148
C149
R274
R275
C164 TP22
U56
J152
R256
R376
R385
1
1P0V_PHY
C67
1
J82
U36
R662
Y2
C85
C86
C87
C88
C89
C90
R205
C146
R2 C147
66
R226
R229
R231
R232
R234
R235
R236
R237
R267
R269
R280
C63
D10
Q14
ON
1
R218
R281
TP29
GND_0
C54
J153
R213
R215
R268
POE CONN
J10
J11
TP10
C28
C29
R45
C76 C75 C73 C72 C69 C62 C60 C59
SW8
2
4
R149
R159
R160
J81
3
1
R172
R173
C91
C92
R2
86
R282
R283
C159
R270
R97
TP13
DVP-102-000400-001 REFCLK0_P
RevC
U55
J227
C173
1
1
L12
U51
C167
789
A
B
C
D
E
F
G
H
J
K
L
M
N
PLLXVDDA
U54
C184
J230
R47
R48
R49
1
1
C66
1
3
J54
R146
U23
4
2
SW9
RS2
C98
J117
C100
C96
C103
C104
3
J224
C203
U40
U42
123
789
A
B
DC
E
F
G
H
J
K
L
M
N
J128
ON
SW10
A1
R86
C51
C77
R671 R181
R186
R188
J126 J127
J125
RS4
VPP
2
C197
2
1
B1
R148 LED9
RST LED
J70
U27
rs
R663
JTAG SEL
U31
U30
3
J233
1
123
789
J226
R329
C188
R340
C192
J223 R341
R342
1
R99
C49R87
R88
J33 C50R89
R90
R106
R107
R108
R109
R110
R95
C52 R91
C53 R92
R93
R94
J29
J19
J26
GND
J37
1
J55
1
J59
U25
3
R384
C199
R351 R344
R345
C195
1
R180
J124
RS3
RS5
C37
R74
C48
GND
R166
R167
R168
Y3
C162
123
R311
R319
R320
R317
R318
C177
C178
C182
C183
C185
R327
1
R335
R336
C190
R337
U58
J222
R343
C196
R348 R349
R352 C201
J203
J234
J215 R290
R291
C187
J217 R295 J130 R187
R332
R296
R333R334
1 R299
R302
R303
R304 TP7
R305
R306
R307
R308
R309 GND
R177
L8
J123
C114
A30
PLLMDDRVDDA
U53
J212
C181
R321
1
R322R314
R323
U57
R328
R331
R330
C193C194
J216
R289
C169C166 U50
R293
R300R294
U52
J204
C180 C176
C175
R315
J218
1
1
J172
K23
J175
L26
J179
H26
J184
J29
J188
H30
J195
H28
J197
G29
J200
F30
J202
K25 BA
J210 DC
L23 E
F
J214 G
N23 HJ
K
L
M
N
J225
C160
R288
R287
3
J193
L15 C171
1 C174
AK1
3
C172
C158
U48
1
1
L7
PCIEXVDD
AK30
R310
J173
J180
1
3
J14
J12
SW1
R39
R53
R54
R60
R61
U8
U12
J38
Q19
R271
C155
R272 R249
R273 C142
R227
R258 R233
C165
R313
R316
C179
R324
GND
DB9-RS232 1
ANALOG INPUT
PLLFDDRVDDA
R674
R673
R672
R676
J139
P24
J141
N26
J144
M27
J146
L29
J155
L28
J159
K30
J162
J27
Su
C143
R248
R255
C144
R264 C161
C163
1
HDR-RS485
R347
20
8
C97
C101 C102
C38
C40
C43
R78
C46
7
7
U62
C93
C99
GND_C
1
2
J43
1
R163
U29
1
3
3
R175
R176
pe
1
1
C125
R202
R192
D12
1
C112
J157
TP28
R261 C139
R262 R245
C154
R263
L14
R246 C140
HVDD R252 R253
R254
R257
1
1
V2J21 M2 J20 M2J20 H2 J19G3 J196 H2J19 J2 J18 J3 J18 J2 J17 K2 J174
9 4 8 7 0 3 6 8 4
63 4 9 5 1 7 9 0
C123
C124
C127
TP27
U47
C137
1
J176
C145
R259
R260R250
3
1
J138
P23
J140
N25
J143
N24
J145
M26
J154
L30
J158
K29
C133 J161
K28
1
J165
J137
D13
J181 C156 C157
1
TP26
VDDIO
R292
C168
R298 R297
C170 R301
19
J221
TP3
1
3
2
1
50 MHZ
R680
R681
R678
R679
R677
R675
DS26
C110
C108
R193
DS27
HVDD
C117
C118
R200 R197
U41
C141
R251
5
R284
J115
AA29
J119
Y30
J122
M23
J131
T27
J134
T26
J135
V23
J232
U24
W28
R29
R24
J105
J104
Y1
REFCLK0_P
REFCLK0_N
SERDES0
4
3
J111
V24
85
R2
1
U28
R161 R162
65
R2
U49
U46
4
3
J198
R190
HVSS
U39
U38
R199
C113
R208
R209
R210
R211
C126
R222
J164
J121
5
J113
USB MICRO AB
OTG Support
1
5
J106
1
C80
D7
U10
R69
R70
R73
J49
A14
P14
R28
4
2
C138
C81
C82
20
10
1
R196
R198
RESET
U19
P1
C39
Q13
P3LED2
TC2 P3LED3
TC1
TC4 P3LED1
J32 P3LED0 TC3
TC6 P2LED3
P2LED2 TC5
TC7 P2LED0
R121
A1
3
1
J163
C136
R214
R216
HVSS
R223
R225
C132
R224 U44
R228
1
C107
C106
R194
1
CR4
P1
R195
U22
GND
J30
1
1
R117
R118
R119
R122
R125
R126
R127
R129
R133
R135
R136
R138
R139
R141
R144
R145
R85
R59
TP30
2
U43
C135
C115
R201
TP5
CR3
J94
1
R76
SW6
R58
L4
R64
1
C109
TP4
R191
-
-
3
SFP CONN
A12
M12
ZL RST
12
J4
6
U34
L9
1 J93
J107
J108
C83
R174
J120
FP4 HEADER
R147
1
V22
J110
AA28
J114
W27
J118
TP8
DS24
U26
J63
J91
J99
J102
J101
J100
J98
R664
J92
R165
GND
1
J88
J60
J66
R171
J231
9
U69 1
J79
J136
J42
R169 1
REMOTE
PWR ENB
DS23
R134
10
1
U32
J83
6
1
R164
1
Q17
J75
J78
GND
R51
U9
R66
R68
TP11
17
5
J74
J84
J89 J90
TP2
A1 R62
R65
GND
J34
J72
J77
J40
J53
J69 J64
J87
1
19 R128
GND
2
10
J58
R142
J62
J68
R156
J73
U35
C122
J48 J41 J39
L6
J57
J86
J97
J85
J109
J45
9
J96
J71
C116
J28
J27
C55
C64
C65
1
1
5
R140
J65
J76
DB9-CAN2
3
1
U21
X1
U24
1
20
J51
2
19
J47
J50
J56
L11
20 R115
2
J13
SW3
SW4
C35
R105
U17
C56
D9
U18
J46
J61
J95
R63
R44
R98 U11
D8
ETM HEADER
RS1
J35
1
GND
1
R41
C30
R42
C31
R43
J18
DB9-CAN1
R120
Q10
R67
R71
R72
R75
R77
R79
R84
REFP6
1
R116
DS21
2
1
5
DS20
VDD_REG
1
R124
REFP5
C47
1.2V
J36
J52
U14
U13
1
RVI HEADER
TP15
R101
TP19
C57
3P3V_LDO
U16
M1
7
20
J5
J17
J20
3
J21
3
J22
3
J25
3
12
1
J7
R38
U7
C34
Q12
J23
C45
1
6
17
C20
U4
R33
C25
C26
C27
5
1
CR2
FTDI INTERFACE
R96
J24
1
7
C694
SW2
R14
R29
C13
U5
C23
C24
1.0V
CR1
J1
ed
ed
SW5
R13
D1
Q11
3
C41
1
1
SW7
TP1
C21
R57
ON
USB MINI B
J6
FMC HEADER
C19
C18
R37
4
R34
1
C10
C17
10
1
R40
J9
1
1
R31
D3
C16
L3
C22
6
Q8
J8
GND
U6
3
HPDIFFN4 HPDIFFP4
DS7
DS8
DS9
3P3V
5P0V
C1
R10
C14
C15
2P5V
J3
C3
C4
3P3V
R17
R18
C11
R19
R20
1P8V
Q7
1
C693
R9
D2
D4
C682
R16
C12
L2
TP23
OFF
FMC HEADER
L1
TP17
TP18
DC JACK12V/6A
A1
A40
7
1
7
R15
C9
1
K1
12P0V
DS4
DS5
DS6
VDD_REG
U1
R11 C2
R669
R12
5P0V
U3
C8
R6
Q5
GND
R7
R8
C683
R660
Q6
R4 2P5V_LDO
R5 2P5V
Q4
DS3
R3 3P3V_LDO
Q2
12V_POE
Q3
R1 1P8V
R2 DDR3-1P5V
DS2
Q1
12V
12V_PCIE
R668
C36
Q9
TP9
U2
12_DCJACK
TP16
K40
1
J2
1
DS1
Appendix 4: Jumper Locations
D19
C205
B49
Figure 18 • SmartFusion2 Development Kit Silkscreen Top View
Figure 18 shows the jumper locations in the Development Kit board:
•
Jumpers highlighted in red are set by default.
•
Jumpers highlighted in green must be set manually.
•
The location of the jumpers in Figure 18 on page 27 are searchable.
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In-System Programming Using USB OTG Controller Interface
Appendix 5: Error Codes
Table 4 • Error Codes
Error Code
#define
Description
#define MSS_SYS_CHAINING_MISMATCH
Device contents mismatch
0x02(2)
#define MSS_SYS_UNEXPECTED_DATA_RECEIVED
Data is not supported
0x03(3)
#define MSS_SYS_INVALID_ENCRYPTION_KEY
Invalid encryption key
0x0B(11)
#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER Bitstream is not supported
0x0C(12)
#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR
Verification is not allowed for
input bitstream
0x7F(127)
#define MSS_SYS_ABORT
Operation aborted
0x81(129)
#define MSS_SYS_NVM_VERIFY_FAILED
eNVM verification failed
0x82(130)
#define MSS_SYS_DEVICE_SECURITY_PROTECTED
Device is secured
0x83(131)
#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED
Programming mode is not
enabled
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0x01(1)
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SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
Appendix 6: Generating .spi Programming File using Libero
1. Launch the Libero SoC software to open a Libero project for fabenvm.spi programming file. The
Libero design file is provided in
<download_folder>\sf2_isp_using_usb_interface_demo_df\sample_programming_file\fabric_and
_envm.
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2. Right-click Export Programming File under Handoff Design for Production in the Design
Flow tab, and click Configure Options from the context menu.
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Figure 19 • Configuring Export Programming File
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In-System Programming Using USB OTG Controller Interface
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3. On the Export Programming File Options window, select the SPI file check box.
4. Click OK.
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Figure 20 • Export Programming File Options window
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5. Double-click Export Programming File under Handoff Design for Production in the Design
Flow tab to generate the .spi file (Figure 19 on page 29). Figure 21 shows the .spi file location
in Reports tab.
Figure 21 • .SPI File Location
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A – List of Changes
The following table lists critical changes that were made in each revision of the chapter in the demo
guide.
Date
Changes
Page
Updated the document for Libero v11.3 software release (SAR 56662).
Revision 2
(December 2013)
Updated "Demo Design Description" section (SAR 53451).
Revision 1
(November 2013)
Updated the document for Libero v11.2 software release (SAR 52963).
NA
Revision 0
(October 2013)
Initial release.
NA
NA
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Revision 3
(May 2014)
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B – Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
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Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
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Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
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Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more
information and support. Many answers available on the searchable web resource include diagrams,
illustrations, and links to other resources on the website.
Website
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You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected]
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SmartFusion2 SoC FPGA In-System Programming Using USB OTG Controller Interface Demo Guide
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
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For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected] Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
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Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
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