INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 04 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 FEATURES DESCRIPTION • 8-bit serial input The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • 8-bit serial or parallel output • Storage register with 3-state outputs • Shift register with direct clear The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. • 100 MHz (typ) shift out frequency • Output capability: – parallel outputs; bus driver Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. – serial output; standard • ICC category: MSI. APPLICATIONS • Serial-to-parallel data conversion The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. • Remote control holding register. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL PARAMETER tPHL/tPLH CONDITIONS propagation delay UNIT HC HCT 16 21 CL = 15 pF; VCC = 5 V SHCP to Q7’ ns STCP to Qn 17 20 ns MR to Q7’ 14 19 ns fmax maximum clock frequency SHCP, STCP 100 57 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 115 130 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑(CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V. 1998 Jun 04 2 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC595DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC595PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HCT595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PINNING SYMBOL PIN Q0 to Q7 DESCRIPTION 15, 1 to 7 GND 8 parallel data output ground (0 V) Q7’ 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable (active LOW) DS 14 serial data input VCC 16 positive supply voltage handbook, halfpage 11 handbook, halfpage Q1 1 16 VCC Q2 2 15 Q0 Q3 3 14 DS Q4 4 SHCP STCP Q7' Q0 Q1 13 OE Q2 595 Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 MR GND 8 9 12 14 Q3 DS Q4 Q5 Q6 Q7' Q7 MLA001 MR 10 9 15 1 2 3 4 5 6 7 OE 13 MLA002 Fig.1 Pin configuration. 1998 Jun 04 Fig.2 Logic symbol. 3 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state handbook, halfpage 13 EN3 OE STCP MR SHCP DS 74HC/HCT595 12 10 C2 R SRG8 11 14 C1/ 1D 2D 3 15 1 2 3 4 5 6 7 9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7' MSA698 Fig.3 IEC logic symbol. handbook, full pagewidth 14 DS 11 SHCP 10 MR 12 STCP 13 OE 8-STAGE SHIFT REGISTER Q7 ' 9 Q0 15 Q1 1 8-BIT STORAGE REGISTER 3-STATE OUTPUTS Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 MLA003 Fig.4 Functional diagram. 1998 Jun 04 4 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state handbook, full pagewidth DS STAGE 0 D 74HC/HCT595 STAGES 1 TO 6 Q D STAGE 7 Q D FF0 Q7' Q FF7 CP CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Fig.5 Logic diagram. 1998 Jun 04 5 Q7 MLA010 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 FUNCTION TABLE INPUTS OUTPUTS FUNCTON SHCP STCP OE MR DS Q7’ QN X X L L X L NC X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear. Parallel outputs in high-impedance OFF-state ↑ X L H H Q6’ NC logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6’) appears on the serial output (Q7’) X ↑ L H X NC Qn’ contents of shift register stages (internal Qn’) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6’ Qn’ contents of shift register shifted through. Previous contents of the shift register is transferred to the storage register and the parallel output stages. a LOW level on MR only affects the shift registers Notes 1. H = HIGH voltage level; L = LOW voltage level ↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition Z = high-impedance OFF-state; NC = no change X = don’t care. 1998 Jun 04 6 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 handbook, SHfull CPpagewidth DS STCP MR OE Q0 high-impedance OFF-state Q1 Q6 Q7 Q 7' MLA005 - 1 Fig.6 Timing diagram. 1998 Jun 04 7 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) +25 SYMBOL PARAMETER min tPHL/tPLH tPHL/tPLH tPHL tPZH/tPZL tPHZ/tPLZ tW tW tW tsu tsu 1998 Jun 04 typ max TEST CONDITION −40 to +85 −40 to +125 min min max max propagation delay SHCP to Q7’ − 52 160 − 200 − 240 − 19 32 − 40 − 48 − 15 27 − 34 − 41 propagation delay STCP to Qn − 55 175 − 220 − 265 − 20 35 − 44 − 53 UNIT V CC WAVEFORMS (V) ns 2.0 4.5 6.0 ns 2.0 − 16 30 − 37 − 45 − 47 175 − 220 − 265 − 17 35 − 44 − 53 − 14 30 − 37 − 45 3-state output enable time OE to Qn − 47 150 − 190 − 225 − 17 30 − 38 − 45 4.5 − 14 26 − 33 − 38 6.0 3-state output disable time OE to Qn − 41 150 − 190 − 225 − 15 30 − 38 − 45 4.5 − 12 26 − 33 − 38 6.0 storage clock pulse width HIGH or LOW master reset pulse width LOW set-up time DS to SHCP set-up time SHCP to STCP 6.0 ns 2.0 Fig.10 4.5 6.0 ns ns 2.0 2.0 75 17 − 95 − 110 − 15 6 − 19 − 22 − 4.5 13 5 − 16 − 19 − 6.0 ns 2.0 75 11 − 95 − 110 − 15 4 − 19 − 22 − 4.5 13 3 − 16 − 19 − 6.0 ns 2.0 75 17 − 95 − 110 − 15 6.0 − 19 − 22 − 4.5 13 5.0 − 16 − 19 − 6.0 ns 2.0 50 11 − 65 − 75 − 10 4.0 − 13 − 15 − 4.5 9.0 3.0 − 11 − 13 − 6.0 75 22 − 95 − 110 − ns ns 2.0 2.0 15 8 − 19 − 22 − 4.5 13 7 − 16 − 19 − 6.0 8 Fig.8 4.5 propagation delay MR to Q7’ shift clock pulse width HIGH or LOW Fig.7 Fig.11 Fig.11 Fig.7 Fig.8 Fig.10 Fig.9 Fig.8 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 Tamb (°C) +25 SYMBOL PARAMETER min th trem fmax 1998 Jun 04 hold time DS to SHCP removal time MR to SHCP maximum clock pulse frequency SHCP or STCP 3 typ −6 max − TEST CONDITION −40 to +85 −40 to +125 min min 3 max − 3 max − UNIT V CC WAVEFORMS (V) ns 2.0 3 −2 − 3 − 3 − 4.5 3 −2 − 3 − 3 − 6.0 50 −19 − 65 − 75 − ns 2.0 10 −7 − 13 − 15 − 4.5 9 −6 − 11 − 13 − 6.0 9 30 − 4.8 − 4 − 30 91 − 24 − 20 − 4.5 35 108 − 28 − 24 − 6.0 9 MHz 2.0 Fig.9 Fig.10 Figs 7 and 8 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI. Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. GND = 0 V; tr = tf = 6 ns; CL = 50 pF. INPUT UNIT LOAD COEFFICIENT 0.25 DS 1998 Jun 04 MR 1.50 SHCP 1.50 STCP 1.50 OE 1.50 10 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) +25 SYMBOL PARAMETER min typ −40 to +85 max min max TEST CONDITION −40 to +125 UNIT V CC WAVEFORMS (V) min max tPHL/ tPLH propagation delay SHCP to Q7’ − 25 42 − 53 − 63 ns 4.5 Fig.7 tPHL/ tPLH propagation delay STCP to Qn − 24 40 − 50 − 60 ns 4.5 Fig.8 tPHL propagation delay MR to Q7’ − 23 40 − 50 − 60 ns 4.5 Fig.10 tPZH/ tPZL 3-state output enable time OE to Qn − 21 35 − 44 − 53 ns 4.5 Fig.11 tPHZ/ tPLZ 3-state output disable time OE to Qn − 18 30 − 38 − 45 ns 4.5 Fig.11 tW shift clock pulse width HIGH or LOW 16 6 − 20 − 24 − ns 4.5 Fig.7 tW storage clock pulse width HIGH or LOW 16 5 − 20 − 24 − ns 4.5 Fig.8 tW master reset pulse width LOW 20 8 − 25 − 30 − ns 4.5 Fig.10 tsu set-up time DS to SHSP 16 5 − 20 − 24 − ns 4.5 Fig.9 tsu set-up time SHCP to STCP 16 8 − 20 − 24 − ns 4.5 Fig.8 th hold time DS to SHCP 3 −2 − 3 − 3 − ns 4.5 Fig.9 trem removal time MR to SHCP 10 −7 − 13 − 15 − ns 4.5 Fig.10 fmax maximum clock pulse frequency SHCP or STCP 30 52 − 24 − 20 − MHz 4.5 Figs 7 and 8 1998 Jun 04 11 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 AC WAVEFORMS 1/fmax handbook, full pagewidth SHCP INPUT VM(1) tW tPLH tPHL 90% VM(1) Q7' OUTPUT 10% tTLH tTHL MSA699 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and maximum shift clock frequency. handbook, full pagewidth SHCP INPUT VM(1) 1/fmax tsu STCP INPUT VM(1) tW tPLH Qn OUTPUT tPHL VM(1) MSA700 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 1998 Jun 04 12 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 handbook, full pagewidth SHCP INPUT VM(1) tsu tsu th th VM(1) DS INPUT VM(1) Q7' OUTPUT MLB196 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the data set-up and hold times for the DS input. handbook, full pagewidth MR INPUT VM(1) tW trem VM(1) SHCP INPUT tPHL VM(1) Q7' OUTPUT MLB197 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay and the master reset to shift clock (SHCP) removal time. 1998 Jun 04 13 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 tr handbook, full pagewidth tf 90% VM(1) OE INPUT 10% tPLZ Qn OUTPUT LOW-to-OFF OFF-to-LOW tPZL VM(1) 10% tPHZ tPZH 90% Qn OUTPUT HIGH-to-OFF OFF-to-HIGH VM(1) outputs enabled outputs disabled outputs enabled MSA697 (1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the 3-state enable and disable times for input OE. 1998 Jun 04 14 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE 1998 Jun 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 15 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.244 0.050 0.041 0.228 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1998 Jun 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 16 o 8 0o Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 1998 Jun 04 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-01-14 95-02-04 MO-150AC 17 o Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 1998 Jun 04 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 18 o Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state 74HC/HCT595 SOLDERING SO, SSOP and TSSOP Introduction REFLOW SOLDERING There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 1998 Jun 04 • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. 19 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state Even with these conditions: 74HC/HCT595 REPAIRING SOLDERED JOINTS • Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. • Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jun 04 20