INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT174 Hex D-type flip-flop with reset; positive-edge trigger Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jul 08 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 The 74HC/HCT174 have six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output capability: standard The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. • ICC category: MSI GENERAL DESCRIPTION A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER CONDITIONS UNIT HC HCT CP to Qn 17 18 ns MR to Qn propagation delay CL = 15 pF; VCC = 5 V 13 17 ns fmax maximum clock frequency 99 69 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop 17 17 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 1998 Jul 08 2 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC174N; 74HCT174N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HC174D; 74HCT174D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HC174DB; 74HCT174DB SSOP16 74HC174PW; 74HCT174PW TSSOP16 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR asynchronous master reset (active LOW) 2, 5, 7, 10, 12, 15 Q0 to Q5 flip-flop outputs 3, 4, 6, 11, 13, 14 D0 to D5 data inputs 8 GND ground (0 V) 9 CP clock input (LOW-to-HIGH, edge-triggered) 16 VCC positive supply voltage Fig.1 Pin configuration. 1998 Jul 08 Fig.2 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR CP Dn Qn reset (clear) L X X L load “1” H ↑ h H load “0” H ↑ I L Note 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition X = don’t care ↑= LOW-to-HIGH CP transition Fig.5 Logic diagram. 1998 Jul 08 4 74HC/HCT174 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER −40 to +85 +25 min. tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem tsu th fmax 1998 Jul 08 propagation delay CP to Qn propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency −40 to +125 min. UNIT VCC (V) WAVEFORMS 2.0 Fig.6 typ. max. min. max. max. 55 165 205 250 20 33 41 50 4.5 16 28 35 43 6.0 44 150 190 225 16 30 38 45 4.5 13 26 33 38 6.0 19 75 95 110 7 15 19 22 4.5 6 13 16 19 6.0 ns ns ns 2.0 80 17 100 120 16 6 20 24 4.5 14 5 17 20 6.0 80 12 100 120 16 4 20 24 4.5 14 3 17 20 6.0 5 −11 5 5 5 −4 5 5 4.5 5 −3 5 5 6.0 60 6 75 90 12 2 15 18 4.5 10 2 13 15 6.0 3 −6 3 3 3 −2 3 3 4.5 3 −2 3 3 6.0 6 30 5 4 30 90 24 20 4.5 35 107 28 24 6.0 5 ns 2.0 ns ns ns ns MHz 2.0 2.0 2.0 2.0 2.0 2.0 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 Fig.8 Fig.8 Fig.6 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT Dn 0.25 CP 1.30 MR 1.25 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to +85 +25 −40 to +125 UNIT VCC (V) WAVEFORMS min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay CP to Qn 21 35 44 53 ns 4.5 Fig.6 tPHL propagation delay MR to Qn 20 35 44 53 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.6 tW master reset pulse width; LOW 20 7 25 30 ns 4.5 Fig.7 trem removal time MR to CP 12 −3 15 18 ns 4.5 Fig.7 tsu set-up time Dn to CP 16 4 20 24 ns 4.5 Fig.8 th hold time Dn to CP 5 −3 5 5 ns 4.5 Fig.8 fmax maximum clock pulse frequency 30 63 24 20 MHz 4.5 Fig.6 1998 Jul 08 6 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 AC WAVEFORMS (1) Fig.6 (1) (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulses frequency. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn). 1998 Jul 08 7 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE 1998 Jul 08 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 8 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.041 0.228 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1998 Jul 08 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 9 o 8 0o Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 1998 Jul 08 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-01-14 95-02-04 MO-150AC 10 o Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 1998 Jul 08 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 11 o Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. DIP If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Even with these conditions: • Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). • Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. SO, SSOP and TSSOP Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Jul 08 74HC/HCT174 12 Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT174 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jul 08 13