NL17SHT00 D

NL17SHT00
Single 2-Input NAND Gate/
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The NL17SHT00 is a single gate 2−input NAND fabricated with
silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to
3 V CMOS Logic while operating at the high voltage power supply.
The NL17SHT00 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
NL17SHT00 to be used to interface 5 V circuits to 3 V circuits. The
output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
•
•
•
•
•
•
•
•
High Speed: tPD = 3.1 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
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MARKING
DIAGRAM
SOT−953
CASE 527AE
K
M
KM
1
= Specific Device Code
= Month Code
PIN ASSIGNMENT
1
IN A
2
GND
3
IN B
4
OUT Y
5
VCC
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
FUNCTION TABLE
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Inputs
Power Down Protection Provided on Inputs and Outputs
Output
Balanced Propagation Delays
A
B
Y
Pin and Function Compatible with Other Standard Logic Families
L
L
H
H
L
H
L
H
H
H
H
L
These are Pb−Free Devices
IN A
1
GND
2
IN B
5 VCC
ORDERING INFORMATION
3
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
4 OUT Y
Figure 1. Pinout
IN A
IN B
&
OUT Y
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 0
1
Publication Order Number:
NL17SHT00/D
NL17SHT00
MAXIMUM RATINGS
Symbol
Characteristics
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
IIK
Input Diode Current
VCC = 0
High or Low State
IOK
Output Diode Current
IOUT
DC Output Current
ICC
DC Supply Current, VCC and GND
TSTG
Value
Unit
−0.5 to +7.0
V
−0.5 to +7.0
V
−0.5 to 7.0
−0.5 to VCC + 0.5
V
−20
mA
±20
mA
±25
mA
VOUT < GND; VOUT > VCC
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
ILATCHUP
Latchup Performance
50
mA
*65 to )150
_C
260
_C
)150
_C
50
mW
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
mA
±100
Above VCC and Below GND at 125_C (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
3.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
0.0
0.0
5.5
VCC
V
−55
+125
°C
0
0
100
20
ns/V
VOUT
DC Output Voltage
TA
VCC = 0
High or Low State
Operating Temperature Range
tr , tf
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
419,300
TJ = 90 ° C
1,032,200
90
TJ =100° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ =110 ° C
Time, Years
TJ =120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
1
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time Junction Temperature
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2
NL17SHT00
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
1.4
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA = 25°C
VCC
(V)
Typ
TA ≤ 85°C
Max
Min
1.4
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = −50 mA
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
3.0
4.5
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Max
3.0
4.5
0.0
0.0
−55 ≤ TA ≤ 125°C
Min
Max
1.4
2.0
2.0
0.53
0.8
0.8
V
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
Unit
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
ICCT
Quiescent Supply
Current
Input: VIN = 3.4 V
5.5
1.35
1.50
1.65
mA
IOFF
Power Off Output
Leakage Current
VOUT = 5.5 V
0.0
0.5
5.0
10
mA
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA = 25°C
Symbol
tPLH,
tPHL
CIN
Parameter
Maximum Propagation
Delay, Input A or B to Y
Min
TA ≤ 85°C
Typ
Max
Max
Unit
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
4.1
5.5
10.0
13.5
11.0
15.0
13.0
17.5
ns
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.1
3.6
6.9
7.9
8.0
9.0
9.5
10.5
5.5
10
10
10
Test Conditions
Maximum Input
Capacitance
Min
Max
−55 ≤ TA ≤ 125°C
Min
pF
Typical @ 25°C, VCC = 5.0 V
CPD
11
Power Dissipation Capacitance (Note 2)
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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3
NL17SHT00
A or B
3.0 V
50%
GND
tPHL
tPLH
VOH
Y
50% VCC
VOL
Figure 4. Switching Waveforms
VCC
OUTPUT
INPUT
CL*
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended for propagation delay tests.
Figure 5. Test Circuit
ORDERING INFORMATION
Device
NL17SHT00P5T5G
Package
Shipping†
SOT−953
(Pb−Free)
8000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NL17SHT00
PACKAGE DIMENSIONS
SOT−953
CASE 527AE
ISSUE E
X
Y
D
PIN ONE
INDICATOR
5
A
4
HE
E
1
2 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
HE
L
L2
L3
C
TOP VIEW
SIDE VIEW
e
L
5X
5X
L3
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.175 REF
0.05
0.10
0.15
−−−
−−−
0.15
SOLDERING FOOTPRINT*
5X
0.35
5X
0.20
5X
L2
5X
BOTTOM VIEW
b
PACKAGE
OUTLINE
0.08 X Y
1.20
1
0.35
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NL17SHT00/D