5962-0620801QXC SMD

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
REV
SHEET
75
76
77
78
79
80
81
82
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REV
SHEET
REV
SHEET
REV
SHEET
REV STATUS
REV
OF SHEETS
SHEET
PMIC N/A
PREPARED BY
Charles F. Saffle
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Charles F. Saffle
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Thomas M. Hess
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, CMOS, DIGITAL
SIGNAL PROCESSOR, MONOLITHIC SILICON
06-09-25
AMSC N/A
REVISION LEVEL
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-06208
82
5962-E265-06
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
06208
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
Q
X
X
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
SMJ320F2812
Digital signal processor
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
CQCC2-F172
Terminals
Package style
172
Quad leaded chip carrier with
non-conductive tie bar
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
2
1.3 Absolute maximum ratings.
1/
Supply voltage ranges, (VDDIO, VDDA1, VDDA2, VDDAIO, AVDDREFBG) .............................................. -0.3 V to +4.6 V
Supply voltage ranges, (VDD, VDD1) ........................................................................................... -0.5 V to +2.5 V
VDD3VFL range ............................................................................................................................ -0.3 V to +4.6 V
Input voltage range, (VIN) .......................................................................................................... -0.3 V to +4.6 V
Output voltage range, (VO) ....................................................................................................... -0.3 V to +4.6 V
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) ......................................................................... ±20 mA 2/
Output clamp current, IOK (VO < 0 or VO > VDDIO) ...................................................................... ±20 mA
Operating ambient temperature range, (TA) .............................................................................. -55°C to +125°C
Storage temperature range, (TSTG) ............................................................................................ -65°C to +150°C
3/
3/
On-Chip Analog-to-Digital Converter.
Supply voltage ranges, (VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG) ............................................... -0.3 V to +4.6 V
Supply voltage ranges, (VSS1 to VDD1) ....................................................................................... -0.3 V to 2.5 V
Analog input (ADCIN) clamp current, total (max) ...................................................................... ±20 mA 4/
1.4 Recommended operating conditions.
Device supply voltage, I/O, (VDDIO) ........................................................................................... +3.14 V to +3.47 V
Device supply voltage, CPU, (VDD, VDD1):
1.8 V (135 MHz) ................................................................................................................ +1.71 V to 1.89 V
1.9 V (150 MHz) ................................................................................................................ +1.81 to +2 V
Supply ground, (VSS) ................................................................................................................. 0 V
ADC supply voltage (VDDA!, VDDA2, AVDDREFBG, VDDAIO) .............................................................. +3.14 V to +3.47 V
Flash programming supply voltage, (VDD3VFL) ........................................................................... +3.14 V to +3.47 V
Device clock frequency (system clock), (fSYSCLKOUT):
VDD = 1.9 V ± 5% .............................................................................................................. 2 MHz to 150 MHz
VDD = 1.8 V ± 5% .............................................................................................................. 2 MHz to 135 MHz
High level input voltage, (VIH):
All inputs except XCLKIN .................................................................................................. +2 V to VDDIO
XCLKIN (@ 50 µA max) .................................................................................................... +0.7VDD to VDD
Maximum low level input voltage, (VIL):
All inputs except XCLKIN .................................................................................................. +0.8 V
XCLKIN (@ 50 µA max) .................................................................................................... +0.3VDD
Maximum high level output source current, VOH = 2.4 V (IOH):
All I/Os except group 2 ...................................................................................................... -4 mA
Group 2 5/ ...................................................................................................................... -8 mA
Maximum low level output sink current, VOL = VOL max (IOL):
All I/Os except group 2 ...................................................................................................... 4 mA
Group 2 5/ ...................................................................................................................... 8 mA
Operating ambient temperature range, (TA) ............................................................................. -55°C to +125°C
Flash Timing.
Minimum flash endurance for the array (Nf) (Write/erase cycles) (0°C to 85°C) ....................... 100 cycles
Maximum One-Time Programmable (OTP) endurance for the array (NOTP)
(Write cycles) (0°C to 85°C) ............................................................................................. 1 write
6/
__________
1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2/ Continuous clamp current per pin is ±2 mA.
3/ Long term high temperature storage and/or extended use at maximum temperature conditions may result in a reduction of
overall device life.
4/ The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The
continuous clamp current per pin is ±2 mA.
5/ Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
6/ Flash Timing Endurance is the minimum number of write/erase or write cycles specified over a programming temperature
range of 0°C to 85°C. Flash may be read over the operating temperature range of the device (-55°C to +125°C).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535
-
Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
MIL-STD-1835
-
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103
MIL-HDBK-780
-
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 2.
3.2.4 Timing waveforms and test circuits. The Timing waveforms and test circuits shall be as specified on figures 3 – 39.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
4
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
5
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Electrical Characteristics Over Recommended Operating Conditions
High-level output voltage
VOH
1, 2, 3
IOH = IOH maximum
All
IOH = 50 µA
2.4
V
VDDIO –
0.2
Low-level output voltage
VOL
IOL = IOL maximum
0.4
V
Low-level input current
IIL
With pullup.
VDDIO = 3.3 V, VIN = 0 V,
All I/Os (including XRS) except
EVB 1/
-80
-190
µA
With pullup.
VDDIO = 3.3 V, VIN = 0 V,
GPIOB/EVB
-13
-35
High-level input current
IIH
With pulldown.
VDDIO = 3.3 V, VIN = 0 V
±2
With pullup.
VDDIO = 3.3 V, VIN = VDD
±2
28
With pulldown. 2/
VDDIO = 3.3 V, VIN = VDD
High-impedance (offstate)
state output current
IOZ
Input capacitance
Ci
Output capacitance
Co
Quiescent supply current
IDD
±2
4
Operational mode
HALT mode
3/
6/ 7/
HALT mode
7 TYP
pF
pF
230
8/
mA
150
8/
mA
10
8/
mA
µA
70 TYP
3/
4/
STANDBY mode
µA
7 TYP
5/ 6/
Operational mode
IDLE mode
1, 2, 3
4/
STANDBY mode
IDDIO
80
VO = VDDIO or 0 V
IDLE mode
µA
5/ 6/
6/ 7/
30
8/
mA
10
8/
mA
20
8/
µA
20
8/
µA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
6
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
1, 2, 3
All
Limits
Min
Quiescent supply current
IDD3VFL
Operational mode
IDLE mode
4/
STANDBY mode
HALT mode
IDDA
9/
3/
5/ 6/
6/ 7/
Operational mode
IDLE mode
4/
STANDBY mode
HALT mode
3/
5/ 6/
6/ 7/
Device Clocks
On-chip oscillator clock
XCLKIN
tc(OSC)
tc(CI)
SYSCLKOUT
XCLKOUT
tc(SCO)
tc(XCO)
HSPCLK
tc(HCO)
tc(LCO)
Cycle time
tc(ADCCLK)
11/
SPI clock
tc(SPC)
9, 10, 11
All
tc(CKG)
tc(XTIM)
4
8/
µA
4
8/
µA
4
8/
µA
50
8/
mA
20
8/
µA
20
8/
µA
20
8/
µA
50
ns
20
35
MHz
Cycle time
6.67
250
ns
Frequency
4
150
MHz
Cycle time
6.67
500
ns
Frequency
2
150
MHz
Cycle time
6.67
2000
ns
Frequency
0.5
150
MHz
Cycle time
6.67
150
MHz
75
MHz
25
MHz
20
MHz
20
MHz
150
MHz
Cycle time
ns
13.3
Cycle time
ns
40
Frequency
Cycle time
ns
50
Cycle time
ns
50
Frequency
XTIMCLK
mA
28.6
Frequency
McBSP
45
8/
Frequency
Frequency
ADC clock
Max
10/
Frequency
LSPCLK
Unit
Cycle time
ns
6.67
Frequency
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
7
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
20
35
Clock Requirements and Characteristics
Input Clock Frequency Requirements
Input clock frequency
fx
Resonator
9, 10, 11
All
Crystal
XCLKIN
12/
Limp mode clock
frequency
fl
Cycle time, XCLKIN
tc(CI)
See figure 4, reference C8.
Fall time, XCLKIN
tf(CI)
20
35
4
150
MHz
2 TYP
MHz
XCLKIN Timing Requirements – PLL Bypassed or Enabled
Rise time, XCLKIN
tr(CI)
9, 10, 11
All
250
ns
See figure 4, reference C9.
Up to 30 MHz.
6
ns
See figure 4, reference C9.
30 MHz to 150 MHz.
2
See figure 4, reference C10.
Up to 30 MHz.
6
See figure 4, reference C10.
30 MHz to 150 MHz.
2
Pulse duration,
X1/XCLKIN low as a
percentage of tc(CI)
tw(CIL)
Pulse duration,
X1/XCLKIN high as a
percentage of tc(CI)
tw(CIH)
Cycle time, XCLKIN
tc(CI)
See figure 4, reference C8.
Fall time, XCLKIN
tf(CI)
See figure 4.
6.67
ns
40
60
%
40
60
%
6.67
250
ns
See figure 4, reference C9.
Up to 30 MHz.
6
ns
See figure 4, reference C9.
30 MHz to 150 MHz.
2
See figure 4, reference C10.
Up to 30 MHz.
6
See figure 4, reference C10.
30 MHz to 150 MHz.
2
XCLKIN Timing Requirements – PLL Disabled
Rise time, XCLKIN
tr(CI)
Pulse duration,
X1/XCLKIN low as a
percentage of tc(CI)
tw(CIL)
Pulse duration,
X1/XCLKIN low as a
percentage of tc(CI)
tw(CIH)
9, 10, 11
All
See figure 4.
40
60
45
55
40
60
45
55
ns
%
XCLKIN ≤ 120 MHz
See figure 4.
120 MHz < XCLKIN ≤ 150 MHz
See figure 4.
%
XCLKIN ≤ 120 MHz
See figure 4.
120 MHz < XCLKIN ≤ 150 MHz
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
8
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
Cycle time, XCLKOUT
9, 10, 11
Unit
Max
13/ 14/
All
ns
tc(XCO)
See figure 4, reference C1.
Fall time, XCLKOUT
tf(XCO)
See figure 4, reference C3.
2 TYP
ns
Rise time, XCLKOUT
tr(XCO)
See figure 4, reference C4.
2 TYP
ns
Pulse duration, XCLKOUT
low
tw(XCOL)
See figure 4, reference C5.
H-2
H+2
ns
Pulse duration, XCLKOUT
high
tw(XCOH)
See figure 4, reference C6.
H-2
H+2
ns
PLL lock time
tp
See figure 4.
131072
tc(CI)
ns
Reset Timing
Reset (XRS) Timing Requirements
Pulse duration, stable
XCLKIN to XRS high
tw(RSL1)
See figures 5, 6, and 7.
Pulse duration, XRS low
tw(RSL2)
See figures 5, 6, and 7.
Warm reset
Pulse duration, reset
pulse generated by
watchdog
tw(WDRS)
Delay time, address/data
valid after XRS high
td(EX)
Oscillator start-up time
tOSCST
17/
Setup time for XPLLDIS
pin
Hold time for XPLLDIS pin
6.67
15/
16/
9, 10, 11
All
8tc(CI)
cycles
8tc(CI)
cycles
See figures 5, 6, and 7.
WD-initiated reset
512tc(CI)
NOM
See figures 5, 6, and 7.
512tc(CI)
NOM
cycles
32tc(CI)
NOM
cycles
1
ms
tsu(XPLLDIS)
16tc(CI)
cycles
th(XPLLDIS)
16tc(CI)
cycles
Hold time for XMP/MC pin
th(XMP/MC)
16tc(CI)
cycles
Hold time for boot-mode
pins
th(boot-
2520tc(CI)
18/
cycles
mode)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
9
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Low-Power Mode Wake-up Timing
IDLE Mode Switching Characteristics
Pulse duration, external
wake-up signal
tw(WAKEINT)
See figure 8.
Without input qualifier.
9, 10, 11
See figure 8.
With input qualifier.
Delay time, external wake
signal to program
execution resume 20/
cycles
2*tc(SCO)
All
1*tc(SCO)
+ IQT 19/
td(WAKEIDLE)
- Wake-up from Flash.
- Flash module in active
state.
See figure 8.
Without input qualifier.
- Wake-up from Flash.
- Flash module in sleep
state.
See figure 8.
Without input qualifier.
- Wake-up from SARAM.
See figure 8.
Without input qualifier.
See figure 8.
With input qualifier.
See figure 8.
With input qualifier.
See figure 8.
With input qualifier.
8*tc(SCO)
cycles
8*tc(SCO)
+ IQT 19/
cycles
1050 *
tc(SCO)
cycles
1050 *
tc(SCO)
+ IQT 19/
cycles
8*tc(SCO)
cycles
8*tc(SCO)
+ IQT 19/
cycles
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
10
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
STANDBY Mode Switching characteristics
Delay time, IDLE
instruction executed to
XCLKOUT high
td(IDLE-
Pulse duration, external
wake-up signal
tw(WAKE-
See figure 9.
9, 10, 11
All
INT)
See figure 9.
Without input qualifier.
See figure 9.
With input qualifier.
Delay time, external wake
signal to program
execution resume 20/
32*tc(SCO)
cycles
12*tc(CI)
cycles
XCOH)
21/
td(WAKESTBY)
- Wake-up from Flash.
- Flash module in active
state.
See figure 9.
Without input qualifier.
- Wake-up from Flash.
- Flash module in sleep
state.
See figure 9.
Without input qualifier.
1125 *
tc(SCO)
cycles
See figure 9.
With input qualifier.
1125 *
tc(SCO) +
cycles
See figure 9.
With input qualifier.
12*tc(CI)
cycles
12*tc(CI)
+ tw(WAKE-
cycles
INT)
tw(WAKE-INT)
- Wake-up from SARAM.
See figure 9.
Without input qualifier.
See figure 9.
With input qualifier.
12*tc(CI)
cycles
12*tc(CI)
+ tw(WAKE-
cycles
INT)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
11
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
HALT Mode Switching Characteristics
See figure 10.
Delay time, IDLE
instruction executed to
XCLKOUT high
td(IDLE-
Pulse duration, XNMI
wake-up signal
tw(WAKE-
Pulse duration, XRS
wake-up signal
tw(WAKE-
PLL lock-up time
tp
Delay time, PLL lock to
program execution
resume
td(WAKE)
9, 10, 11
All
32*tc(SCO)
cycles
2*tc(CI)
cycles
8*tc(CI)
cycles
XCOH)
XNMI)
XRS)
131072 cycles
* tc(CI)
- Wake-up from Flash.
- Flash module in sleep
state.
- Wake-up from SARAM.
1125 *
tc(SCO)
cycles
35*tc(SCO)
cycles
25
ns
Event Manager Interface – PWM Timing 22/
PWM Switching Characteristics 23/ 24/
Pulse duration, PWMx
output high/low
tw(PWM)
25/
See figure 11.
Delay time, XCLKOUT
high to PWMx output
switching
td(PWM)XCO
See figure 11.
XCLKOUT = SYSCLKOUT/4
Pulse duration, TDIRx
low/high
tw(TDIR)
9, 10, 11
10
Timer and Capture Unit Timing Requirements
tw(CAP)
Pulse duration, TCLKINx
low as a percentage of
TCLKINx cycle time
tw(TCLKINL)
Pulse duration, TCLKINx
high as a percentage of
TCLKINx cycle time
tw(TCLKINH)
All
2*tc(SCO)
cycles
1*tc(SCO)
+ IQT 19/
cycles
2*tc(SCO)
cycles
1*tc(SCO)
+ IQT 19/
cycles
See figure 12.
Without input qualifier
See figure 12.
With input qualifier
See figure 12.
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
40
60
%
40
60
%
4*tc(HCO)
Cycle time, TCLKINx
tc(TCLKIN)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
ns
26/ 27/
9, 10, 11
See figure 12.
Without input qualifier
See figure 12.
With input qualifier
Pulse duration, CAPx
input low/high
All
ns
SIZE
5962-06208
A
REVISION LEVEL
SHEET
12
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
External ADC Start-of-Conversion – EVA – Switching Characteristics
Delay time, XCLKOUT
high to EVASOC low
td(XCOH-
Pulse duration, EVASOC
low
tw(EVASOCL)
See figure 13.
9, 10, 11
Unit
Max
28/
All
1*tc(SCO) cycles
EVASOCL)
32*tc(HCO)
External ADC Start-of-Conversion – EVB – Switching Characteristics
Delay time, XCLKOUT
high to EVBSOC low
td(XCOH-
Pulse duration, EVBSOC
low
tw(EVBSOCL)
See figure 14.
9, 10, 11
ns
28/
All
1*tc(SCO) cycles
EVBSOCL)
32*tc(HCO)
ns
Interrupt Timing
Interrupt Switching Characteristics
Delay time, PDPINTx low
to PWM high-impedance
state
td(PDP-
Delay time,
CxTRIP/TxCTRIP
signals low to PWM
high impedance state
td(TRIP-
Delay time, INT low/high
to interrupt-vector fetch
td(INT)
PWM)HZ
See figure 15.
Without input qualifier
9, 10, 11
All
12
See figure 15.
With input qualifier
PWM)HZ
ns
1*tc(SCO) +
IQT + 12
19/
See figure 15.
Without input qualifier
3*tc(SCO)
See figure 15.
With input qualifier
[2*tc(SCO)]
+ IQT
19/
See figure 15.
tqual +
12tc(XCO)
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
13
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
Interrupt Timing Requirements
Pulse duration, INT input
low/high
tw(INT)
See figure 15.
With no qualifier
9, 10, 11
1*tc(SCO) +
IQT 19/
See figure 15.
With qualifier
Pulse duration, PDPINTx
input low
tw(PDP)
See figure 15.
With no qualifier
tw(CxTRIP)
1*tc(SCO) +
IQT 19/
See figure 15.
With no qualifier
tw(TxCTRIP)
cycles
2*tc(SCO)
1*tc(SCO) +
IQT 19/
See figure 15.
With qualifier
Pulse duration, TxCTRIP
input low
cycles
2*tc(SCO)
See figure 15.
With qualifier
Pulse duration, CxTRIP
input low
cycles
2*tc(SCO)
All
See figure 15.
With no qualifier
cycles
2*tc(SCO)
1*tc(SCO) +
IQT 19/
See figure 15.
With qualifier
General-Purpose Input/Output (GPIO) – Output Timing
General-Purpose Output Switching Characteristics
Delay time, XCLKOUT
high to GPIO low/high
td(XCOH-
Rise time, GPIO switching
low to high
tr(GPO)
10
ns
Fall time, GPIO switching
high to low
tf(GPO)
10
ns
Toggling frequency, GPO
pins
fGPO
20
MHz
GPO)
9, 10, 11
See figure 16.
All GPIOs
1*tc(SCO) cycles
See figure 16.
General-Purpose Input/Output (GPIO) – Input Timing
General-Purpose Input Timing Requirements
Pulse duration, GPIO
low/high
All
tw(GPI)
See figure 18.
With no qualifier.
9, 10, 11
29/
cycles
2*tc(SCO)
All
1*tc(SCO) +
IQT 19/
See figure 18.
With qualifier.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
14
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
tc(SPC)M
Unit
Min
Max
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
See figure 19, reference 2. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
0.5tc(SPC)M
See figure 19, reference 2. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M
- 0.5tc(LCO)
- 10
0.5tc(SPC)M
- 0.5tc(LCO)
See figure 19, reference 2. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
0.5tc(SPC)M
See figure 19, reference 2. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M
- 0.5tc(LCO)
- 10
0.5tc(SPC)M
- 0.5tc(LCO)
See figure 19, reference 3. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
0.5tc(SPC)M
See figure 19, reference 3. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 0.5tc(SPC)M
+ 0.5tc(LCO) + 0.5tc(LCO)
- 10
SPI Master Mode Timing
SPI Master Mode External Timing (Clock Phase = 0)
Cycle time, SPICLK
Limits
See figure 19, reference 1.
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
9, 10, 11
See figure 19, reference 1.
(SPI when (SPIBRR + 1) is
30/ 31/
All
ns
odd and SPIBRR > 3.)
Pulse duration, SPICLK
high (clock polarity = 0)
tw(SPCH)M
odd and SPIBRR > 3.)
Pulse duration, SPICLK
low (clock polarity = 1)
tw(SPCL)M
odd and SPIBRR > 3.)
Pulse duration, SPICLK
low (clock polarity = 0)
tw(SPCL)M
odd and SPIBRR > 3.)
Pulse duration, SPICLK
high (clock polarity = 1)
tw(SPCH)M
See figure 19, reference 3. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
See figure 19, reference 3. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 0.5tc(SPC)M
+ 0.5tc(LCO) + 0.5tc(LCO)
- 10
odd and SPIBRR > 3.)
0.5tc(SPC)M
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
15
TABLE I. Electrical performance characteristics - Continued.
Test
Delay time, SPICLK high
to SPISIMO valid
(clock polarity = 0)
Symbol
td(SPCHSIMO)M
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Unit
Min
Max
-10
10
-10
10
See figure 19, reference 4. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
-10
10
See figure 19, reference 4. 32/
(SPI when (SPIBRR + 1) is
-10
10
See figure 19, reference 4. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
9, 10, 11
All
See figure 19, reference 4. 32/
(SPI when (SPIBRR + 1) is
ns
odd and SPIBRR > 3.)
Delay time, SPICLK low
to SPISIMO valid
(clock polarity = 1)
td(SPCLSIMO)M
ns
odd and SPIBRR > 3.)
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 0)
tv(SPCLSIMO)M
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M
+ 0.5tc(LCO)
- 10
odd and SPIBRR > 3.)
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 1)
tv(SPCHSIMO)M
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M
- 10
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M
+ 0.5tc(LCO)
- 10
odd and SPIBRR > 3.)
Setup time, SPISOMI
before SPICLK low
(clock polarity = 0)
tsu(SOMISPCL)M
See figure 19, reference 8. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0
See figure 19, reference 8. 32/
(SPI when (SPIBRR + 1) is
0
ns
ns
ns
odd and SPIBRR > 3.)
Setup time, SPISOMI
before SPICLK high
(clock polarity = 1)
tsu(SOMISPCH)M
See figure 19, reference 8. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0
See figure 19, reference 8. 32/
(SPI when (SPIBRR + 1) is
0
ns
odd and SPIBRR > 3.)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
16
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 0)
tv(SPCLSOMI)M
See figure 19, reference 9. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
9, 10, 11
All
See figure 19, reference 9. 32/
(SPI when (SPIBRR + 1) is
tv(SPCHSOMI)M
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.25tc(SPC)M
- 10
See figure 19, reference 5. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M
- 0.5tc(LCO)
- 10
odd and SPIBRR > 3.)
SPI Master Mode External Timing (Clock Phase = 1)
Cycle time, SPICLK
tc(SPC)M
See figure 20, reference 1.
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
9, 10, 11
See figure 20, reference 1.
(SPI when (SPIBRR + 1) is
Max
0.25tc(SPC)M
- 10
ns
0.5tc(SPC)M
- 0.5tc(LCO)
- 10
odd and SPIBRR > 3.)
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 1)
Unit
ns
31/ 33/
All
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
odd and SPIBRR > 3.)
Pulse duration, SPICLK
high (clock polarity = 0)
tw(SPCH)M
See figure 20, reference 2. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M - 0.5tc(SPC)M
10
See figure 20, reference 2. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M - 0.5tc(SPC)M 0.5tc(LCO) - 0.5tc(LCO)
10
odd and SPIBRR > 3.)
Pulse duration, SPICLK
low (clock polarity = 1)
tw(SPCL)M
See figure 20, reference 2. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M - 0.5tc(SPC)M
10
See figure 20, reference 2. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M - 0.5tc(SPC)M 0.5tc(LCO) - 0.5tc(LCO)
10
odd and SPIBRR > 3.)
Pulse duration, SPICLK
low (clock polarity = 0)
tw(SPCL)M
See figure 20, reference 3. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M - 0.5tc(SPC)M
10
See figure 20, reference 3. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M + 0.5tc(SPC)M +
0.5tc(LCO) - 0.5tc(LCO)
10
odd and SPIBRR > 3.)
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
17
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Pulse duration, SPICLK
high (clock polarity = 1)
tw(SPCH)M
See figure 20, reference 3. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
See figure 20, reference 3. 32/
(SPI when (SPIBRR + 1) is
odd and SPIBRR > 3.)
Setup time, SPISIMO data
valid before SPICLK high
(clock polarity = 0)
tsu(SIMOSPCH)M
9, 10, 11
All
Unit
Max
0.5tc(SPC)M - 0.5tc(SPC)M
10
ns
0.5tc(SPC)M + 0.5tc(SPC)M +
0.5tc(LCO) - 0.5tc(LCO)
10
See figure 20, reference 6. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M 10
See figure 20, reference 6. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
Setup time, SPISIMO data
valid before SPICLK low
(clock polarity = 1)
tsu(SIMOSPCL)M
See figure 20, reference 6. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M 10
See figure 20, reference 6. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 0)
tv(SPCHSIMO)M
See figure 20, reference 7. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M 10
See figure 20, reference 7. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 1)
tv(SPCLSIMO)M
See figure 20, reference 7. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.5tc(SPC)M 10
See figure 20, reference 7. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
Setup time, SPISOMI
before SPICLK high
(clock polarity = 0)
tsu(SOMISPCH)M
See figure 20, reference 10. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0
See figure 20, reference 10. 32/
(SPI when (SPIBRR + 1) is
0
ns
odd and SPIBRR > 3.)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
18
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Setup time, SPISOMI
before SPICLK low
(clock polarity = 1)
tsu(SOMISPCL)M
See figure 20, reference 10. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
9, 10, 11
All
Unit
Max
ns
0
See figure 20, reference 10. 32/
(SPI when (SPIBRR + 1) is
0
odd and SPIBRR > 3.)
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
tv(SPCHSOMI)M
See figure 20, reference 11. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.25tc(SPC)M
- 10
See figure 20, reference 11. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
tv(SPCLSOMI)M
See figure 20, reference 11. 32/
(SPI when (SPIBRR + 1) is
even or SPIBRR = 0 or 2.)
0.25tc(SPC)M
- 10
See figure 20, reference 11. 32/
(SPI when (SPIBRR + 1) is
0.5tc(SPC)M 10
ns
odd and SPIBRR > 3.)
SPI Slave Mode Timing
SPI Slave Mode External Timing (Clock Phase = 0)
9, 10, 11
31/ 34/
All
Cycle time, SPICLK
tc(SPC)S
See figure 21, reference 12.
Pulse duration, SPICLK
high (clock polarity = 0)
tw(SPCH)S
See figure 21, reference 13.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
low (clock polarity = 1)
tw(SPCL)S
See figure 21, reference 13.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
low (clock polarity = 0)
tw(SPCL)S
See figure 21, reference 14.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
high (clock polarity = 1)
tw(SPCH)S
See figure 21, reference 14.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Delay time, SPICLK high
to SPISOMI valid
(clock polarity = 0)
td(SPCH-
See figure 21, reference 15.
35/
0.375tc(SPC)S
- 10
ns
Delay time, SPICLK low
to SPISOMI valid
(clock polarity = 1)
td(SPCL-
See figure 21, reference 15.
35/
0.375tc(SPC)S
- 10
ns
SOMI)S
SOMI)S
4tc(LCO)
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
19
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
0.75tc(SPC)S
ns
See figure 21, reference 16.
35/
0.75tc(SPC)S
ns
See figure 21, reference 19.
35/
0
ns
See figure 21, reference 19.
35/
0
ns
See figure 21, reference 20.
35/
0.5tc(SPC)S
ns
See figure 21, reference 20.
35/
0.5tc(SPC)S
ns
8tc(LCO)
ns
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 0)
tv(SPCL-
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 1)
tv(SPCH-
Setup time, SPISIMO
before SPICLK low
(clock polarity = 0)
tsu(SIMO-
Setup time, SPISIMO
before SPICLK high
(clock polarity = 1)
tsu(SIMO-
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 0)
tv(SPCL-
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 1)
tv(SPCH-
Cycle time, SPICLK
tc(SPC)S
See figure 22, reference 12.
Pulse duration, SPICLK
high (clock polarity = 0)
tw(SPCH)S
See figure 22, reference 13.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
low (clock polarity = 1)
tw(SPCL)S
See figure 22, reference 13.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
low (clock polarity = 0)
tw(SPCL)S
See figure 22, reference 14.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Pulse duration, SPICLK
high (clock polarity = 1)
tw(SPCH)S
See figure 22, reference 14.
35/
0.5tc(SPC)S - 0.5tc(SPC)S
10
ns
Setup time, SPISOMI
before SPICLK high
(clock polarity = 0)
tsu(SOMI-
See figure 22, reference 17.
35/
0.125tc(SPC)S
ns
Setup time, SPISOMI
before SPICLK low
(clock polarity = 1)
tsu(SOMI-
See figure 22, reference 17.
35/
0.125tc(SPC)S
ns
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
tv(SPCH-
See figure 22, reference 18.
35/
0.75tc(SPC)S
ns
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
tv(SPCL-
See figure 22, reference 18.
35/
0.75tc(SPC)S
ns
SOMI)S
SOMI)S
SPCL)S
SPCH)S
SIMO)S
SIMO)S
See figure 21, reference 16.
35/
9, 10, 11
SPI Slave Mode External Timing (Clock Phase = 1)
SPCH)S
SPCL)S
SOMI)S
SOMI)S
9, 10, 11
All
31/ 36/
All
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
20
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Setup time, SPISIMO
before SPICLK high
(clock polarity = 0)
tsu(SIMO-
Setup time, SPISIMO
before SPICLK low
(clock polarity = 1)
tsu(SIMO-
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 0)
tv(SPCH-
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 1)
tv(SPCL-
SPCH)S
SPCL)S
SIMO)S
SIMO)S
9, 10, 11
Max
0
ns
See figure 22, reference 21.
35/
0
ns
See figure 22, reference 22.
35/
0.5tc(SPC)S
ns
See figure 22, reference 22.
35/
0.5tc(SPC)S
ns
See figure 22, reference 21.
35/
All
Unit
External Interface Read Timing
External Memory Interface Read Switching Characteristics
Delay time, XCLKOUT
high to zone chip-select
active low
td(XCOH-
Delay time, XCLKOUT
high/low to zone
chip-select inactive high
td(XCOHL-
Delay time, XCLKOUT
high to address valid
td(XCOH-
Delay time, XCLKOUT
high/low to XRD active
low
td(XCOHL-
Delay time, XCLKOUT
high/low to XRD inactive
high
td(XCOHL-
Hold time, address valid
after zone chip-select
inactive high
th(XA)XZCSH
37/
ns
Hold time, address valid
after XRD inactive high
th(XA)XRD
37/
ns
See figure 23.
9, 10, 11
All
1
ns
3
ns
2
ns
1
ns
1
ns
XZCSL)
-2
XZCSH)
XA)
XRDL)
-2
XRDH)
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
21
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
External Memory Interface Read Timing Requirements
Access time, read data
from address valid
ta(A)
See figure 23.
9, 10, 11
All
(LR + AR)
- 14
38/
ns
Access time, read data
valid from XRD active
low
ta(XRD)
AR - 12
38/
ns
Setup time, read data
valid before XRD strobe
inactive high
tsu(XD)XRD
12
ns
Hold time, read data valid
after XRD inactive high
th(XD)XRD
0
ns
External Interface Write Timing
External Memory Interface Write Switching Characteristics
Delay time, XCLKOUT
high to zone chip-select
active low
td(XCOH-
Delay time, XCLKOUT
high or low to zone
chip-select inactive high
td(XCOHL-
Delay time, XCLKOUT
high to address valid
td(XCOH-
Delay time, XCLKOUT
high/low to XWE low
td(XCOHL-
Delay time, XCLKOUT
high/low to XWE high
td(XCOHL-
Delay time, XCLKOUT
high to XR/W low
td(XCOH-
Delay time, XCLKOUT
high/low to XR/W high
td(XCOHL-
Enable time, data bus
driven from XWE low
ten(XD)XWEL
Delay time, data valid
after XWE active low
td(XWEL-
Hold time, address valid
after zone chip-select
inactive high
th(XA)XZCSH
See figure 24.
9, 10, 11
All
1
ns
3
ns
2
ns
2
ns
2
ns
1
ns
1
ns
XZCSL)
-2
XZCSH)
XA)
XWEL)
XWEH)
XRNWL)
-2
XRNWH)
0
ns
4
ns
XD)
37/
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
22
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Hold time, write data valid
after XWE inactive high
th(XD)XWE
Data bus disabled after
XR/W inactive high
tdis(XD)
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
See figure 24.
9, 10, 11
All
Unit
Max
TW – 2
39/
ns
4
ns
XRNW
External Interface Ready-on-Read Timing With One External Wait State
External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
Delay time, XCLKOUT
high to zone chip-select
active low
td(XCOH-
Delay time, XCLKOUT
high/low to zone
chip-select inactive high
td(XCOHL-
Delay time, XCLKOUT
high to address valid
9, 10, 11
All
1
ns
3
ns
td(XCOH-XA)
2
ns
Delay time, XCLKOUT
high/low to XRD active
low
td(XCOHL-
1
ns
Delay time, XCLKOUT
high/low to XRD inactive
high
td(XCOHL-
1
ns
Hold time, address valid
after zone chip-select
inactive high
th(XA)XZCSH
37/
ns
Hold time, address valid
after XRD inactive high
th(XA)XRD
37/
sn
XZCSL)
-2
XZCSH)
XRDL)
-2
XRDH)
External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
Access time, read data
from address valid
ta(A)
9, 10, 11
All
(LR + AR)
- 14
38/
ns
Access time, read data
valid from XRD active
low
ta(XRD)
AR – 12
38/
ns
Setup time, read data
valid before XRD strobe
inactive high
tsu(XD)XRD
12
ns
Hold time, read data
valid after XRD inactive
high
tsu(XD)XRD
0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
23
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
Setup time, XREADY
(Synch) low before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Synch) low
th(XRDY
Earliest time XREADY
(Synch) can go high
before the sampling
XCLKOUT edge
te(XRDY
Setup time, XREADY
(Synch) high before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Synch) held high after
zone chip-select high
th(XRDY
See figure 25.
9, 10, 11
All
Unit
Max
40/
15
ns
12
ns
synchL)
XCOHL
synchL)
3
ns
synchH)
15
ns
0
ns
synchH)
XCOHL
synchH)
XZCSH
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
Setup time, XREADY
(Asynch) low before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Asynch) low
th(XRDY
Earliest time XREADY
(Asynch) can go high
before the sampling
XCLKOUT edge
te(XRDY
Setup time, XREADY
(Asynch) high before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Asynch) held high after
zone chip-select high
th(XRDY
See figure 26.
9, 10, 11
All
41/
11
ns
8
ns
asynchL)
XCOHL
asynchL)
3
ns
asynchH)
11
ns
0
ns
asynchH)
XCOHL
asynchH)
XZCSH
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
24
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
External Interface Ready-on-Write Timing With One External Wait State
External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
Delay time, XCLKOUT
high to zone chip-select
active low
td(XCOH-
Delay time, XCLKOUT
high or low to zone
chip-select inactive high
td(XCOHL-
Delay time, XCLKOUT
high to address valid
9, 10, 11
All
1
ns
3
ns
td(XCOH-XA)
2
ns
Delay time, XCLKOUT
high/low to XWE low
td(XCOHL-
2
ns
Delay time, XCLKOUT
high/low to XWE high
td(XCOHL-
2
ns
Delay time, XCLKOUT
high to XR/W low
td(XCOH-
1
ns
Delay time, XCLKOUT
high/low to XR/W high
td(XCOHL-
1
ns
Enable time, data bus
driven from XWE low
ten(XD)XWEL
Delay time, data valid
after XWE active low
td(XWEL-XD)
Hold time, address valid
after zone chip-select
inactive high
th(XA)XZCSH
Hold time, write data valid
after XWE inactive high
th(XD)XWE
Data bus disabled after
XR/W inactive high
tdis(XD)
XZCSL)
-2
XZCSH)
XWEL)
XWEH)
XRNWL)
-2
XRNWH)
0
ns
4
ns
37/
ns
TW – 2
39/
ns
4
ns
XRNW
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
25
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
Setup time, XREADY
(Synch) low before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Synch) low
th(XRDY
Earliest time XREADY
(Synch) can go high
before the sampling
XCLKOUT edge
te(XRDY
Setup time, XREADY
(Synch) high before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Synch) held high after
zone chip-select high
th(XRDY
See figure 27.
9, 10, 11
All
Unit
Max
42/
15
ns
12
ns
synchL)
XCOHL
synchL)
3
ns
synchH)
15
ns
0
ns
synchH)
XCOHL
synchH)
XZCSH
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
Setup time, XREADY
(Asynch) low before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Asynch) low
th(XRDY
Earliest time XREADY
(Asynch) can go high
before the sampling
XCLKOUT edge
te(XRDY
Setup time, XREADY
(Asynch) high before
XCLKOUT high/low
tsu(XRDY
Hold time, XREADY
(Asynch) held high after
zone chip-select high
th(XRDY
See figure 28.
9, 10, 11
All
43/
11
ns
8
ns
asynchL)
XCOHL
asynchL)
3
ns
asynchH)
11
ns
0
ns
asynchH)
XCOHL
asynchH)
XZCSH
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
26
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
XHOLD/XHOLDA Timing
XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
Delay time, XHOLD low
to Hi-Z on all Address,
Data, and Control
td(HL-HiZ)
Delay time, XHOLD low
to XHOLDA low
See figure 29.
9, 10, 11
Unit
Max
44/ 45/
All
4tc(XTIM)
ns
td(HL-HAL)
5tc(XTIM)
ns
Delay time, XHOLD high
to XHOLDA high
td(HH-HAH)
3tc(XTIM)
ns
Delay time, XHOLD high
to bus valid
td(HH-BV)
4tc(XTIM)
ns
4tc(XTIM) +
tc(XCO)
ns
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
See figure 30.
9, 10, 11
44/ 45/ 46/
All
Delay time, XHOLD low
to Hi-Z on all Address,
Data, and Control
td(HL-HiZ)
Delay time, XHOLD low
to XHOLDA low
td(HL-HAL)
4tc(XTIM) +
2tc(XCO)
ns
Delay time, XHOLD high
to XHOLDA high
td(HH-HAH)
4tc(XTIM)
ns
Delay time, XHOLD high
to bus valid
td(HH-BV)
6tc(XTIM)
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
27
TABLE I. Electrical performance characteristics - Continued.
Test
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Symbol
Group A Device
subgroups type
Limits
Min
Unit
Max
Analog-to-Digital Converter (ADC) Electrical Characteristics Over Recommended Operating Conditions
DC Specifications 47/
Resolution
1, 2, 3
All
12
ADC clock
48/
Bits
1
kHz
25
MHz
±1.5
LSB
±1
LSB
-80
80
LSB
-200
200
LSB
-50
50
LSB
ACCURACY
INL (Integral nonlinearity)
49/
1 – 18.75 MHz ADC clock
DNL (Differential
nonlinearity) 49/
1 – 18.75 MHz ADC clock
Offset error
1, 2, 3
All
50/
Overall gain error with
internal reference 51/
Overall gain error with
external reference 52/
If ADCREFP – ADCREFM =
1 V ±0.1%
Channel-to-channel
offset variation
±8 TYP
LSB
Channel-to-channel
gain variation
±8 TYP
LSB
ANALOG INPUT
1, 2, 3
Analog input voltage
(ADCINx to ADCLO) 53/
All
0
ADCLO
-5
Input capacitance
4
Input leakage current
INTERNAL VOLTAGE REFERENCE
3
V
5
mV
10 TYP
pF
1, 2, 3
±5
µA
2.1
V
51/
1, 2, 3
Accuracy, ADCVREFP
All
Accuracy, ADCVREFM
1.9
0.95
1.05
V
Voltage difference
ADCREFP – ADCREFM
1 TYP
V
Temperature coefficient
50 TYP
PPM
/°C
Reference noise
100 TYP
µV
EXTERNAL VOLTAGE REFERENCE
52/
1, 2, 3
Accuracy, ADCVREFP
All
1.9
2.1
V
Accuracy, ADCVREFM
0.95
1.05
V
Input voltage difference,
ADCREFP - ADCREFM
0.99
1.01
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
28
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
AC Specifications
Signal-to-noise ratio
+ distortion
SINAD
9, 10, 11
All
62 TYP
dB
Signal-to-noise ratio
SNR
62 TYP
dB
Total harmonic distortion
THD
(100 kHz)
-68 TYP
dB
Effective number of bits
ENOB
(SNR)
10.1 TYP
Bits
Spurious free dynamic
range
SDFR
69 TYP
dB
Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
Quiescent supply currents
IDDA
55/
IDDAIO
Mode A (Operational Mode):
- BG and REF enabled
- PWD disabled
9, 10, 11
All
IDDAIO
IDD1
IDDA
55/
IDDAIO
IDD1
IDDA
55/
IDDAIO
IDD1
40 TYP
mA
1 TYP
µA
0.5 TYP
mA
Mode B:
- ADC clock enabled
- BG and REF enabled
- PWD enabled
7 TYP
mA
0 TYP
µA
5 TYP
µA
Mode C:
- ADC clock enabled
- BG and REF disabled
- PWD enabled
1 TYP
µA
0 TYP
µA
5 TYP
µA
Mode D:
- ADC clock disabled
- BG and REF disabled
- PWD enabled
1 TYP
µA
0 TYP
µA
0 TYP
µA
IDD1
IDDA
55/
54/
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
29
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Unit
Min
Max
7
10
ADC Power-Up Control Bit Timing
ADC Power-Up Delays 56/
Delay time for band gap
reference to be stable
td(BGR)
See figure 31.
Bits 6 and 5 of the ADCTRL3
register (PWDNBG and
PWDNREF) are to be set to 1
before the ADCPWDN bit is
enabled.
Delay time for power-down
control to be stable
td(PWD)
See figure 31.
Bit 7 of the ADCTRL3 register
(ADCPWDN) is set to 1 before
any ADC conversions are
initiated.
9, 10, 11
All
ms
µs
20
1
ms
Sequential Sampling Mode (Single-Channel) (SMODE = 0)
Sequential Sampling Mode Timing
Delay time from event
trigger to sampling
td(SH)
See figure 32.
Sample n
Sample/Hold width/
Acquisition width
tSH
See figure 32.
Sample n
Acqps value = 0 – 15
ADCTRL1[8:11]
(1 + Acqps)*
tc(ADCCLK)
See figure 32.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
Acqps value = 0 – 15
ADCTRL1[8:11]
40 ns with Acqps = 0
Delay time for first result
to appear in the Result
register
td(schx n)
Delay time for successive
results to appear in the
Result register
td(schx n + 1) See figure 32.
Sample n + 1
9, 10, 11
2.5tc(ADCCLK)
All
See figure 32.
Sample n
4tc(ADCCLK)
160 ns
See figure 32.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
(2 + Acqps)*
tc(ADCCLK)
See figure 32.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
80 ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
30
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
Simultaneous Sampling Mode Timing
9, 10, 11
All
Delay time from event
trigger to sampling
td(SH)
See figure 33.
Sample n
Sample/Hold width/
Acquisition width
tSH
See figure 33.
Sample n
Acqps value = 0 – 15
ADCTRL1[8:11]
(1 + Acqps)*
tc(ADCCLK)
See figure 33.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
Acqps value = 0 – 15
ADCTRL1[8:11]
40 ns with Acqps = 0
Delay time for first result
to appear in the Result
register
td(schA0 n)
Delay time for first result
to appear in the Result
register
td(schB0 n)
Delay time for successive
results to appear in the
Result register
td(schA0 n
Delay time for successive
results to appear in the
Result register
td(schB0 n
2.5tc(ADCCLK)
See figure 33.
Sample n
4tc(ADCCLK)
See figure 33.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
160 ns
See figure 33.
Sample n
5tc(ADCCLK)
See figure 33.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
+ 1)
200 ns
See figure 33.
Sample n + 1
(3 + Acqps)*
tc(ADCCLK)
See figure 33.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
+ 1)
120 ns
See figure 33.
Sample n + 1
(3 + Acqps)*
tc(ADCCLK)
See figure 33.
At 25 MHz ADC clock,
tc(ADCCLK) = 40 ns
120 ns
See footnotes at end table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
31
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
Multichannel Buffered Serial Port (McBSP) Transmit and Receive Timing
McBSP Timing Requirements 57/ 58/
9, 10, 11
McBSP module clock
(CLKG, CLKX, CLKR)
range
All
1
kHz
20
McBSP module cycle time
(CLKG, CLKX, CLKR)
range
MHz
59/
50
ns
1
ms
Cycle time, CLKR/X
tc(CKRX)
See figure 34, reference M11.
CLKR/X ext
2P
ns
Pulse duration, CLKR/X
high or CLKR/X low
tw(CKRX)
See figure 34, reference M12.
CLKR/X ext
P-7
ns
Rise time, CLKR/X
tr(CKRX)
See figure 34, reference M13.
CLKR/X ext
7
ns
Fall time, CLKR/X
tf(CKRX)
See figure 34, reference M14.
CLKR/X ext
7
ns
Setup time, external FSR
high before CLKR low
tsu(FRH-
See figure 34, reference M15.
CLKR int
18
See figure 34, reference M15.
CLKR ext
2
See figure 34, reference M16.
CLKR int
0
See figure 34, reference M16.
CLKR ext
6
See figure 34, reference M17.
CLKR int
18
See figure 34, reference M17.
CLKR ext
2
See figure 34, reference M18.
CLKR int
0
See figure 34, reference M18.
CLKR ext
6
See figure 34, reference M19.
CLKX int
18
See figure 34, reference M19.
CLKX ext
2
See figure 34, reference M20.
CLKX int
0
See figure 34, reference M20.
CLKX ext
6
Hold time, external FSR
high after CLKR low
Setup time, DR valid
before CLKR low
Hold time, DR valid after
CLKR low
Setup time, external FSX
high before CLKX low
Hold time, external FSX
high after CLKX low
CKRL)
th(CKRLFRH)
tsu(DRVCKRL)
th(CKRLDRV)
tsu(FXHCKXL)
th(CKXLFXH)
ns
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
32
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
McBSP Switching Requirements
Unit
Max
57/ 60/
Cycle time, CLKR/X
tc(CKRX)
See figure 35, reference M1.
CLKR/X int
Pulse duration, CLKR/X
high
tw(CKRXH)
See figure 35, reference M2.
CLKR/X int
D–5
61/
D+5
61/
ns
Pulse duration, CLKR/X
low
tw(CKRXL)
See figure 35, reference M3.
CLKR/X int
C–5
61/
C+5
61/
ns
Delay time, CLKR high to
internal FSR valid
td(CKRH-
See figure 35, reference M4.
CLKR int
0
4
ns
See figure 35, reference M4.
CLKR ext
3
27
See figure 35, reference M5.
CLKX int
0
4
See figure 35, reference M5.
CLKX ext
3
27
Delay time, CLKX high to
internal FSX valid
FRV)
td(CKXHFXV)
Disable time, CLKX high
to DX high impedance
following last data bit
tdis(CKXH-
Delay time, CLKX high to
DX valid (This applies to
all bits except the first bit
transmitted.)
td(CKXH-
Delay time, CLKX high to
DX valid
Delay time, CLKX high to
DX valid (Only applies to
first bit transmitted when
in Data Delay 1 or 2
(XDATDLY = 01b or 10b)
modes.)
DXHZ)
DXV)
9, 10, 11
2P
All
ns
See figure 35, reference M6.
CLKX int
8
See figure 35, reference M6.
CLKX ext
14
See figure 35, reference M7.
CLKX int
9
See figure 35, reference M7.
CLKX ext
28
See figure 35, reference M7.
CLKX int, DXENA = 0
8
See figure 35, reference M7.
CLKX ext, DXENA = 0
14
See figure 35, reference M7.
CLKX int, DXENA = 1
P+8
See figure 35, reference M7.
CLKX ext, DXENA = 1
P + 14
ns
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
33
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Enable time, CLKX high to
DX driven
ten(CKXH-
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
DX)
Enable time, CLKX high to
DX driven (Only applies
to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY = 01b or 10b)
modes.)
Delay time, FSX high to
DX valid
td(FXHDXV)
Delay time, FSX high to
DX valid (Only applies
to first bit transmitted
when in Data Delay 0
(XDATDLY = 00b)
mode.)
Enable time, FSX high to
DX driven
Enable time, FSX high to
DX driven (Only applies
to first bit transmitted
when in Data Delay 0
(XDATDLY = 00b)
mode.)
ten(FXHDX)
See figure 35, reference M8.
CLKX int, DXENA = 0
9, 10, 11
Unit
Max
0
All
See figure 35, reference M8.
CLKX ext, DXENA = 0
6
See figure 35, reference M8.
CLKX int, DXENA = 1
P
See figure 35, reference M8.
CLKX ext, DXENA = 1
P+6
ns
ns
See figure 35, reference M9.
FSX int, DXENA = 0
8
See figure 35, reference M9.
FSX ext, DXENA = 0
14
See figure 35, reference M9.
FSX int, DXENA = 1
P+8
See figure 35, reference M9.
FSX ext, DXENA = 1
P + 14
See figure 35, reference M10.
FSX int, DXENA = 0
0
See figure 35, reference M10.
FSX ext, DXENA = 0
6
See figure 35, reference M10.
FSX int, DXENA = 1
P
See figure 35, reference M10.
FSX ext, DXENA = 1
P+6
ns
ns
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
34
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Unit
Max
McBSP as SPI Master or Slave Timing
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
Setup time, DR valid
before CLKX low
Hold time, DR valid after
CLKX low
tsu(DRVCKXL)
th(CKXLDRV)
Setup time, FSX low
before CLKX high
tsu(BFXL-
Cycle time, CLKX
tc(CKX)
CKXH)
See figure 36, reference M30.
Master
9, 10, 11
All
See figure 36, reference M30.
Slave
8P - 10
See figure 36, reference M31.
Master
P - 10
See figure 36, reference M31.
Slave
8P - 10
See figure 36, reference M32.
Slave
8P + 10
ns
See figure 36, reference M33.
Master
2P
ns
See figure 36, reference M33.
Slave
16P
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
Hold time, FSX low after
CLKX low
th(CKXL-
Delay time, FSX low to
CLKX high
td(FXL-
Disable time, DX high
impedance following last
data bit from FSX high
tdis(FXH-
Delay time, FSX low to
DX valid
td(FXL-
FXL)
CKXH)
DXHZ)
DXV)
ns
P - 10
9, 10, 11
See figure 36, reference M24.
Master
All
ns
62/
2P
ns
See figure 36, reference M25.
Master
P
ns
See figure 36, reference M28.
Master
6
ns
See figure 36, reference M28.
Slave
6P + 6
See figure 36, reference M29.
Master
6
See figure 36, reference M29.
Slave
4P + 6
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
35
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
Setup time, DR valid
before CLKX high
Hold time, DR valid after
CLKX high
tsu(DRVCKXH)
th(CKXHDRV)
Setup time, FSX low
before CLKX high
tsu(FXL-
Cycle time, CLKX
tc(CKX)
CKXH)
See figure 37, reference M39.
Master
9, 10, 11
All
th(CKXL-
Delay time, FSX low to
CLKX high
td(FXL-
Disable time, DX high
impedance following last
data bit from CLKX low
tdis(CKXL-
Delay time, FSX low to
DX valid
td(FXL-
FXL)
CKXH)
DXHZ)
DXV)
Max
62/
P - 10
ns
See figure 37, reference M39.
Slave
8P - 10
See figure 37, reference M40.
Master
P - 10
See figure 37, reference M40.
Slave
8P - 10
See figure 37, reference M41.
Slave
16P + 10
ns
See figure 37, reference M42.
Master
2P
ns
See figure 37, reference M42.
Slave
16P
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
Hold time, FSX low after
CLKX low
Unit
See figure 37, reference M34.
Master
9, 10, 11
All
ns
62/
P
ns
See figure 37, reference M35.
Master
2P
ns
See figure 37, reference M37.
Master
P+6
ns
See figure 37, reference M37.
Slave
7P + 6
See figure 37, reference M38.
Master
6
See figure 37, reference M38.
Slave
4P + 6
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
36
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
Setup time, DR valid
before CLKX high
Hold time, DR valid after
CLKX high
tsu(DRVCKXH)
th(CKXHDRV)
Setup time, FSX low
before CLKX low
tsu(FXL-
Cycle time, CLKX
tc(CKX)
CKXL)
See figure 38, reference M49.
Master
9, 10, 11
All
th(CKXH-
Delay time, FSX low to
CLKX low
td(FXL-
Disable time, DX high
impedance following last
data bit from FSX high
tdis(FXH-
Delay time, FSX low to
DX valid
td(FXL-
FXL)
CKXL)
DXHZ)
DXV)
Max
62/
P - 10
ns
See figure 38, reference M49.
Slave
8P - 10
See figure 38, reference M50.
Master
P - 10
See figure 38, reference M50.
Slave
8P - 10
See figure 38, reference M51.
Slave
8P + 10
ns
See figure 38, reference M52.
Master
2P
ns
See figure 38, reference M52.
Slave
16P
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
Hold time, FSX low after
CLKX high
Unit
See figure 38, reference M43.
Master
9, 10, 11
All
ns
62/
2P
ns
See figure 38, reference M44.
Master
P
ns
See figure 38, reference M47.
Master
6
ns
See figure 38, reference M47.
Slave
6P + 6
See figure 38, reference M48.
Master
6
See figure 38, reference M48.
Slave
4P + 6
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
37
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
Setup time, DR valid
before CLKX low
Hold time, DR valid after
CLKX low
tsu(DRVCKXL)
th(CKXLDRV)
Setup time, FSX low
before CLKX low
tsu(FXL-
Cycle time, CLKX
tc(CKX)
CKXL)
See figure 39, reference M58.
Master
9, 10, 11
All
th(CKXH-
Delay time, FSX low to
CLKX low
td(FXL-
Disable time, DX high
impedance following last
data bit from CLKX high
tdis(CKXH-
Delay time, FSX low to
DX valid
td(FXL-
FXL)
CKXL)
DXHZ)
DXV)
Max
62/
P - 10
ns
See figure 39, reference M58.
Slave
8P - 10
See figure 39, reference M59.
Master
P - 10
See figure 39, reference M59.
Slave
8P - 10
See figure 39, reference M60.
Slave
16P + 10
ns
See figure 39, reference M61.
Master
2P
ns
See figure 39, reference M61.
Slave
16P
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
Hold time, FSX low after
CLKX high
Unit
ns
62/
P
ns
See figure 39, reference M54.
Master 63/
2P
ns
See figure 39, reference M56.
Master 63/
P+6
ns
See figure 39, reference M56.
Slave
7P + 6
See figure 39, reference M57.
Master 63/
6
See figure 39, reference M57.
Slave
4P + 6
See figure 39, reference M53.
Master 63/
9, 10, 11
All
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
38
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 10/
-55°C ≤ TC ≤ +125°C
unless otherwise specified
Group A Device
subgroups type
Limits
Min
Flash Timing
Flash Parameters at 150-MHz SYSCLKOUT
Program time
Max
64/
35 TYP
µs
8K Sector
170 TYP
ms
16K Sector
320 TYP
ms
8K Sector
10
S
16K Sector
11
S
Erase
75
mA
Program
35
mA
16-Bit Word
Erase time
Unit
9, 10, 11
All
VDD3VFL current
consumption during the
Erase/Program cycle
IDD3VFLP
VDD current consumption
during Erase/Program
cycle
IDDP
140
mA
VDDIO current consumption
during Erase/Program
cycle
IDDIOP
20
mA
Paged Flash access time
ta(fp)
Flash/OTP Access Timing
65/
9, 10, 11
All
36
ns
Random Flash access time ta(fr)
36
ns
OTP access time
60
ns
ta(OTP)
See footnotes on next sheet.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
39
TABLE I. Electrical performance characteristics - Continued.
1/
The following pins have no internal pullup/pulldown: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12,
GPIOG4, and GPIOG5.
2/
The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
3/
Operational mode test conditions: All peripheral clocks are enabled. All PWM pins are toggled at 100 kHz. Data is
continuously transmitted out of the SCIA, SCIB, and CAN ports. The hardware multiplier is exercised. Code is running out
of flash with 5 wait-states.
4/
IDLE mode test conditions: Flash is powered down. XCLKOUT is turned off. All peripheral clocks are on, except ADC.
5/
STANDBY mode test conditions: Flash is powered down. Peripheral clocks are turned off. Pins without an internal
pullup/pulldown are tied high/low.
6/
HALT and STANDBY modes cannot be used when the PLL is disabled.
7/
HALT mode test conditions: Flash is powered down. Peripheral clocks are turned off. Pins without an internal
pullup/pulldown are tied high/low. Input clock is disabled.
8/
Max limit numbers are at +125°C, and max voltage (VDD = 2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
9/
IDDA includes current into VDDA1, VDDA2, VDD1, AVDDREFBG, and VDDAIO pins.
10/
See figure 3, herein. This test load circuit is used to measure all switching characteristics.
11/
The maximum value for ADCCLK frequency is25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
12/
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
13/
A load of 40 pF is assumed for these parameters.
14/
H = 0.5tc(XCO)
15/
The PLL must be used for maximum frequency operation.
16/
If external oscillator/clock sources are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
17/
Dependent on crystal/resonator and board design.
18/
The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash.
19/
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * tc(SCO)
20/
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an
ISR (triggered by the wake-up) signal involves additional latency.
21/
Minimum limit = (2 + QUALSTDBY) * tc(CI), where QUALSTDBY is a 6-bit field in the LPMCR0 register.
22/
PWM refers to all PWM outputs on EVA and EVB.
23/
See the GPIO output timing for fall/rise times for PWM pins.
24/
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
25/
PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
40
TABLE I. Electrical performance characteristics - Continued.
26/
The QUALPRD bit field can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification
sampling period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when
QUALPRD = 1, the qualification sampling period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2
SYSCLKOUT cycles). Six such samples will be taken over five sampling windows, each window being 2n SYSCLKOUT
cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles. However, since the
external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
27/
Maximum input frequency to the QEP = min[HSPCLK/2, 20MHz].
28/
XCLKOUT = SYSCLKOUT
29/
See figure 17 for an example diagram of the GPIO Input Qualifier for QUALPRD = 1.
30/
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
31/
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1); tc(LCO) = LSPCLK cycle time
32/
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed
limit (20 MHz).
33/
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
34/
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
35/
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
36/
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
37/
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
38/
LR = Lead period, read access. AR = Active period, read access.
39/
TW = Trail period, write access.
40/
The first XREADY (Synch) sample occurs with respect to E in figure 25:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL ;
where n is the sample number: n = 1, 2, 3, and so forth
41/
The first XREADY (Asynch) sample occurs with respect to E in figure 26:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL ;
where n is the sample number: n = 1, 2, 3, and so forth
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
41
TABLE I. Electrical performance characteristics - Continued.
42/
The first XREADY (Synch) sample occurs with respect to E in figure 27:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, the setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL ;
where n is the sample number: n = 1, 2, 3, and so forth
43/
The first XREADY (Asynch) sample occurs with respect to E in figure 28:
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL ;
where n is the sample number: n = 1, 2, 3, and so forth
44/
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a
high-impedance state.
45/
The state of XHOLD is latched on the rising edge of XTIMCLK.
46/
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising
edge of XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK cycle earlier than the maximum value specified.
47/
Tested at 12.5 MHz ADCCLK.
48/
If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2.
49/
The INL degrades for frequencies beyond 18.75 MHz – 25 MHz. Applications that require these sampling rates should use
a 20 kΩ resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the
ADC will be a few mA more than 24.9 kΩ bias.
50/
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
51/
A single internal band gap reference (±5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these
voltages track together. The ADC converter uses the difference between these two as its reference. The total gain error
will be the combination of the gain error shown here and the voltage reference accuracy (ADCREFP – ADCREFM). A
software-based calibration procedure is recommended for better accuracy.
52/
In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP –
ADCREFM) will determine the overall accuracy.
53/
Voltages above VDDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion of
another pin. To avoid this, the analog inputs should be kept within these limits.
54/
Test conditions:
55/
IDDA – includes current into VDDA1/VDDA2 and AVDDREFBG
56/
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are
initiated. If conversions are started without these delays, the ADC results will show a higher gain. For power down, all
three bits can be cleared at the same time.
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
42
TABLE I. Electrical performance characteristics - Continued.
57/
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
58/
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV).
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O
buffer switching speed.
59/
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than
the I/O buffer speed limit (20 MHz).
60/
2P = 1/CLKG in ns.
61/
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
62/
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM
= CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16, that is 4.5 MHz
and P = 13.3 ns.
63/
C = CLKX low pulse width = P
D = CLKX high pulse width = P
64/
Typical parameters as seen at room temperature using flash API V1 including function call overhead.
65/
For 150 MHz, PAGE WS = 5 and RANDOM WS = 5
For 135 MHz, PAGE WS = 4 and RANDOM WS = 4
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
43
Case outline:
Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Terminal
Symbol
VDDAIO
ADCINB0
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINB6
ADCINB7
ADCREFM
ADCREFP
AVSSREFBG
AVDDREFBG
VDDA1
VSSA1
ADCRESEXT
XMP/MC
XA[0]
MDRA
XD[0]
MDXA
VDD
XD[1]
MCLKRA
MFSXA
XD[2]
MCLKXA
MFSRA
XD[3]
VDDIO
VSS
XD[4]
SPICLKA
SPISTEA
XD[5]
VDD
VSS
XD[6]
SPISIMOA
SPISOMIA
XRD
XA[1]
XZCS0AND1
X
Terminal
Terminal
Terminal
Terminal
Terminal
Terminal
number
Symbol
number
Symbol
number
Symbol
44
PWM7
87
CANRXA
130
XZCS6AND7
45
PWM8
88
SCITXDB
131
TESTSEL
46
PWM9
89
SCIRXDB
132
TRST
47
PWM10
90
PWM1
133
TCK
48
PWM11
91
PWM2
134
EMU0
49
PWM12
92
PWM3
135
XA[12]
50
XR/W
93
PWM4
136
XD[14]
51
VSS
94
XD[12]
137
XF_XPLLDIS
52
T3PWM_T3CMP
95
XD[13]
138
XA[13]
53
XD[7]
96
PWM5
139
VSS
54
T4PWM_T4CMP
97
VSS
140
VDD
55
VDD
98
VDD
141
XA[14]
56
CAP4_QEP3
99
PWM6
142
VDDIO
57
VSS
100
T1PWM_T1CMP
143
EMU1
58
CAP5_QEP4
101
XA[4]
144
XD[15]
59
CAP6_QEPI2
102
T2PWM_T2CMP
145
XA[15]
60
C4TRIP
103
VSS
146
XINT1_XBIO
61
C5TRIP
104
CAP1_QEP1
147
XNMI_XINT13
62
C6TRIP
105
CAP2_QEP2
148
XINT2_ADCSOC
63
VDDIO
106
XA[5]
149
XA[16]
64
XD[8]
107
CAP3_QEPI1
150
VDD
65
TEST2
108
T1CTRIP_PDPINTA
151
SCITXDA
66
TEST1
109
XA[6]
152
XA[17]
67
XD[9]
110
VDD
153
SCIRXDA
68
VDD3VFL
111
VSS
154
XA[18]
69
TDIRB
112
VDDIO
155
XHOLD
70
TCLKINB
113
T2CTRIP/EVASOC
156
XRS
71
XD[10]
114
TDIRA
157
XREADY
72
XD[11]
115
TCLKINA
158
VDD1
73
VDD
116
XA[7]
159
VSS1
74
X2
117
XCLKOUT
160
ADCBGREFIN
75
X1/CLKIN
118
XA[8]
161
VSSA2
76
VSS
119
C1TRIP
162
VDDA2
77
T3CTRIP_PDPINTB
120
C2TRIP
163
ADCINA7
78
XA[2]
121
C3TRIP
164
ADCINA6
79
VDDIO
122
XA[9]
165
ADCINA5
80
XHOLDA
123
TMS
166
ADCINA4
81
T4CTRIP/EVBSOC
124
TDO
167
ADCINA3
82
XWE
125
VDD
168
ADCINA2
83
XA[3]
126
VSS
169
ADCINA1
84
VSS
127
XA[10]
170
ADCINA0
85
CANTXA
128
TDI
171
ADCLO
86
XZCS2
129
XA[11]
172
VSSAIO
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
44
NOTE: 45 of the possible 96 interrupts are used on the device.
FIGURE 2. Functional block diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
45
3.3-V Test Load Circuit
NOTE: Timing is provided at the device pin. For output timing analysis, the tester pin electronics and its transmission line
effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the
desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract
the transmission line delay (2 ns or longer) from the device timing.
Input requirements are tested with an input skew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
FIGURE 3. Timing waveforms and test circuits.
NOTES:
1. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on configuration.
2. XCLKOUT configured to reflect SYSCLKOUT.
FIGURE 4. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
46
NOTES:
1. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at
least 1 V and the 3.3-V supply reaches 2.5 V.
2. VDDAn – VDDA1/VDDA2 and AVDDREFBG.
3. Upon power-up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
4. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The Boot Mode pins should be held high/low for at least 2520 XCLKIN cycles
from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
FIGURE 5. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
47
NOTES:
1. Upon power-up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at
XCLKOUT. This explains why XCLKOUT = XCLKIN/8 during this phase.
2. The state of the GPIO pin is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at
least 1 V and the 3.3-V supply reaches 2.5 V.
FIGURE 6. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
48
NOTE: After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and
then samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination
memory or boot code function in ROM. The Boot Mode pins should be held high/low for at least 2520 XCLKIN cycles
from boot ROM execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is
based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or
without PLL enabled.
FIGURE 7. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
49
NOTES:
1. XCLKOUT = SYSCLKOUT
2. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
FIGURE 8. Timing waveforms and test circuits.
NOTES:
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake-up signal is driven active (negative edge triggered shown in example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device will respond to the interrupt (if enabled).
FIGURE 9. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
50
XCLKOUT = SYSCLKOUT
NOTES:
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned
off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations
to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode
and consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown, as an example), the oscillator is turned on; but the PLL is
not activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G. Normal operation resumes.
FIGURE 10. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
51
NOTE: XCLKOUT = SYSCLKOUT
FIGURE 11. Timing waveforms and test circuits.
NOTE: XCLKOUT = SYSCLKOUT
FIGURE 12. Timing waveforms and test circuits.
FIGURE 13. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
52
FIGURE 14. Timing waveforms and test circuits.
NOTES:
1. XCLKOUT = SYSCLKOUT
2. TxCTRIP – T1CTRIP, T2CTRIP, T3CTRIP, or T4CTRIP
CxTRIP
C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx PDPINTA or PDPINTB
3. PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP
pin). The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
FIGURE 15. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
53
FIGURE 16. Timing waveforms and test circuits.
NOTES:
1. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the
qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin will be
sampled). Six consecutive samples must be of the same value for a given input to be recognized.
2. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD X 2) SYSCLKOUT cycles. This would ensure six sampling windows for
detection to occur. Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable
recognition.
FIGURE 17. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
54
NOTE: The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC pins as well.
FIGURE 18. Timing waveforms and test circuits.
NOTE: In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 19. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
55
NOTE: In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the
SPISTE will go active 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 20. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
56
NOTE: In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 21. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
57
NOTE: In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
FIGURE 22. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
58
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. For USEREADY = 0, the external XREADY input signal is ignored.
4. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
FIGURE 23. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
59
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. For USEREADY = 0, the external XREADY input signal is ignored.
4. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
FIGURE 24. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
60
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
FIGURE 25. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
61
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE - 3+ n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE - 2) tc(XTIM)
FIGURE 26. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
62
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
FIGURE 27. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
63
NOTES:
1. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
2. During alignment cycles, all signals will transition to their inactive state.
3. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
4. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
5. Reference for the first sample is with respect to this point:
E = (XWRLEAD + XWRACTIVE - 2) tc(XTIM)
FIGURE 28. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
64
NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.
FIGURE 29. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
65
NOTES:
1. All pending XINTF accesses are completed.
2. Normal XINTF operation resumes.
FIGURE 30. Timing waveforms and test circuits.
FIGURE 31. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
66
FIGURE 32. Timing waveforms and test circuits.
FIGURE 33. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
67
FIGURE 34. Timing waveforms and test circuits.
FIGURE 35. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
68
FIGURE 36. Timing waveforms and test circuits.
FIGURE 37. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
69
FIGURE 38. Timing waveforms and test circuits.
FIGURE 39. Timing waveforms and test circuits.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
70
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
71
4.4.1 Group A inspection.
a.
Tests shall be as specified in table II herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table. For device classes Q and V,
subgroups 7 and 8 shall include verifying the functionality of the device.
c.
Subgroup 4 (CI and CO measurements) shall be measured only for initial test and after process or design changes
which may affect input or output capacitance.
TABLE II. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1, 7, 9
Device
class Q
1, 7, 9
Device
class V
1, 7, 9
1, 2, 3, 7, 8a, 8b
9, 10, 11 1/
1, 2, 3, 4, 7, 8a, 8b
9, 10, 11
1, 7, 9
1, 2, 3, 7, 8a, 8b
9, 10, 11 1/
1, 2, 3, 4, 7, 8a, 8b
9, 10, 11
1, 7, 9
1, 2, 3, 7, 8a, 8b
9, 10, 11 2/
1, 2, 3, 4, 7, 8a, 8b
9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
---
---
---
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
72
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table II herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
73
6.7 Signal descriptions.
Signal Descriptions.
Terminal
Name
Terminal
Number
XA[18]
I/O/Z
2/
PU/PD
3/
154
O/Z
-
XA[17]
152
O/Z
-
XA[16]
149
O/Z
-
XA[15]
145
O/Z
-
XA[14]
141
O/Z
-
XA[13]
138
O/Z
-
XA[12]
135
O/Z
-
XA[11]
129
O/Z
-
XA[10]
127
O/Z
-
XA[9]
122
O/Z
-
XA[8]
118
O/Z
-
XA[7]
116
O/Z
-
XA[6]
109
O/Z
-
XA[5]
106
O/Z
-
XA[4]
101
O/Z
-
XA[3]
83
O/Z
-
XA[2]
78
O/Z
-
XA[1]
42
O/Z
-
XA[0]
18
O/Z
-
XD[15]
144
I/O/Z
PU
XD[14]
144
I/O/Z
PU
XD[13]
144
I/O/Z
PU
XD[12]
144
I/O/Z
PU
XD[11]
144
I/O/Z
PU
XD[10]
144
I/O/Z
PU
XD[9]
144
I/O/Z
PU
XD[8]
144
I/O/Z
PU
XD[7]
144
I/O/Z
PU
XD[6]
144
I/O/Z
PU
XD[5]
144
I/O/Z
PU
XD[4]
144
I/O/Z
PU
XD[3]
144
I/O/Z
PU
XD[2]
144
I/O/Z
PU
XD[1]
144
I/O/Z
PU
XD[0]
144
I/O/Z
PU
1/
Description
XINTF Signals.
19-bit XINTF Address Bus
16-bit XINTF Data Bus
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
74
Signal Descriptions – Continued.
Terminal
Name
Terminal
Number
I/O/Z
2/
PU/PD
3/
1/
Description
XINTF Signals - Continued.
XMP/MC
17
I
PD
Microprocessor/Microcomputer Mode Select. Switches between
microprocessor and microcomputer mode. When high, Zone 7 is enabled on
the external interface. When low, Zone 7 is disabled from the external
interface, and on-chip boot ROM may be accessed instead. This signal is
latched into the XINTCNF2 register on a reset and the user can modify this
bit in software. The state of the XMP/MC pin is ignored after reset.
XHOLD
155
I
PU
External Hold Request. XHOLD, when active (low), requests the XINTF to
release the external bus and place all buses and strobes into a highimpedance state. The XINTF will release the bus when any current access is
complete and there are no pending accesses on the XINTF.
XHOLDA
80
O/Z
-
External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF
has granted a XHOLD request. All XINTF buses and strobe signals will be in
a high-impedance state. XHOLDA is released when the XHOLD signal is
released. External devices should only drive the external bus when XHOLDA
is active (low).
XZCS0AND1
43
O/Z
-
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is performed.
XZCS2
86
O/Z
-
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an access to the
XINTF Zone 2 is performed.
XZCS6AND7
130
O/Z
-
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is performed.
XWE
82
O/Z
-
Write Enable. Active-low write strobe. The write strobe waveform is
specified, per zone basis, by the Lead, Active, and Trail periods in the
XTIMINGx registers.
XRD
41
O/Z
-
Read Enable. Active-low read strobe. The read strobe waveform is
specified, per zone basis, by the Lead, Active, and Trail periods in the
XTIMINGx registers. NOTE: The XRD and XWE signals are mutually
exclusive.
XR/W
50
O/Z
-
Read Not Write Strobe. Normally held high. When low, XR/W indicates write
cycle is active; when high, XR/W indicates read cycle is active.
XREADY
157
I
PU
Ready Signal. Indicates peripheral is ready to complete the access when
asserted to 1. XREADY can be configured to be a synchronous or an
asynchronous input. See the timing diagrams for more details.
JTAG and Miscellaneous Signals.
X1/XCLKIN
75
I
Oscillator Input − input to the internal oscillator. This pin is also used to feed
an external clock. The 28x can be operated with an external clock source,
provided that the proper voltage levels be driven on the X1/XCLKIN pin. It
should be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V)
core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A
clamping diode may be used to clamp a buffered clock signal to ensure that
the logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator
may be used.
X2
74
O
Oscillator Output.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
75
Signal Descriptions – Continued.
Terminal
Name
Terminal
Number
I/O/Z
2/
PU/PD
3/
1/
Description
JTAG and Miscellaneous Signals - Continued.
XCLKOUT
117
O
-
Output clock derived from SYSCLKOUT to be used for external wait-state
generation and as a general-purpose clock source. XCLKOUT is either the
same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off
by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1.
TESTSEL
131
I
PD
Test Pin. Reserved for TI. Must be connected to ground.
XRS
156
I/O PU
PU
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will
point to the address contained at the location 0x3FFFC0. When XRS is
brought to a high level, execution begins at the location pointed to by the PC.
This pin is driven low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the watchdog reset
duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal pullup (100 µA,
typical). It is recommended that this pin be driven by an open-drain device.
TEST1
66
I/O
-
Test Pin. Reserved for TI. On F281x devices, TEST1 must be left
unconnected.
TEST2
65
I/O
-
Test Pin. Reserved for TI. On F281x devices, TEST2 must be left
unconnected.
TRST
132
I
PD
JTAG test reset with internal pulldown. TRST, when driven high, gives the
scan system control of the operations of the device. If this signal is not
connected or driven low, the device operates in its functional mode, and the
test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pulldown
device. In a low-noise environment, TRST can be left floating. In a highnoise environment, an additional pulldown resistor may be needed. The
value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it is recommended that each
target board is validated for proper operation of the debugger and the
application.
TCK
133
I
PU
JTAG test clock with internal pullup.
TMS
123
I
PU
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
TDI
128
I
PU
JTAG test data input (TDI) with internal pullup. TDI is clocked into the
selected register (instruction or data) on a rising edge of TCK.
TDO
124
O/Z
-
JTAG scan out, test data output (TDO). The contents of the selected
register (instruction or data) is shifted out of TDO on the falling edge of TCK.
EMU0
134
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to
or from the emulator system and is defined as input/output through the JTAG
scan.
EMU1
143
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to
or from the emulator system and is defined as input/output through the JTAG
scan.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
76
Signal Descriptions – Continued.
Terminal
Name
Terminal
Number
I/O/Z
2/
PU/PD
3/
1/
Description
ADC Analog Input Signals.
ADCINA7
163
I
ADCINA6
164
I
ADCINA5
165
I
ADCINA4
166
I
ADCINA3
167
I
ADCINA2
168
I
ADCINA1
169
I
ADCINA0
170
I
ADCINB7
9
I
ADCINB6
8
I
ADCINB5
7
I
ADCINB4
6
I
ADCINB3
5
I
ADCINB2
4
I
ADCINB1
3
I
8-Channel analog inputs for Sample-and-Hold A. The ADC pins should not
be driven before VDDA1, VDDA2, and VDDAIO pins have been fully
powered up.
8-Channel analog inputs for Sample-and-Hold B. The ADC pins should not
be driven before VDDA1, VDDA2, and VDDAIO pins have been fully
powered up.
ADCINB0
2
I
ADCREFP
11
O
ADC Voltage Reference Output (2 V). Requires a low ESR (50 mΩ − 1.5 Ω)
ceramic bypass capacitor of 10 µF to analog ground. (Can accept external
reference input (2 V) if the software bit is enabled for this mode. 1−10 µF
low ESR capacitor can be used in the external reference mode.)
ADCREFM
10
O
ADC Voltage Reference Output (1 V). Requires a low ESR (50 mΩ − 1.5 Ω)
ceramic bypass capacitor of 10 µF to analog ground. (Can accept external
reference input (1 V) if the software bit is enabled for this mode. 1−10 µF
low ESR capacitor can be used in the external reference mode.)
ADCRESEXT
16
O
ADC External Current Bias Resistor (24.9 kΩ ±5%).
ADCBGREFIN
160
I
Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG
12
I
ADC Analog GND.
AVDDREFBG
13
I
ADC Analog Power (3.3-V).
ADCLO
171
I
Common Low Side Analog Input. Connect to analog ground.
VSSA1
15
I
ADC Analog GND.
VSSA2
161
I
ADC Analog GND.
VDDA1
14
I
ADC Analog 3.3-V Supply.
VDDA2
162
I
ADC Analog 3.3-V Supply.
VSS1
159
I
ADC Digital GND.
I
VDD1
158
VDDAIO
1
VSSAIO
172
ADC Digital 1.8-V (or 1.9 V) Supply.
3.3-V Analog I/O Power Pin.
Analog I/O Ground Pin.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
77
Signal Descriptions – Continued.
Terminal
Name
Terminal
Number
I/O/Z
2/
PU/PD
3/
1/
Description
Power Signals.
VDD
22
VDD
36
VDD
55
VDD
73
VDD
98
VDD
110
VDD
125
VDD
140
VDD
150
VSS
31
VSS
37
VSS
51
VSS
57
VSS
76
VSS
84
VSS
97
VSS
103
VSS
111
VSS
126
VSS
139
VDDIO
30
VDDIO
63
VDDIO
79
VDDIO
112
VDDIO
142
VDD3VFL
68
1.8-V or 1.9-V Core Digital Power Pins.
Core and Digital I/O Ground Pins.
3.3-V I/O Digital Power Pins.
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all
times after power-up sequence requirements have been met. This pin is
used as VDDIO in ROM parts and must be connected to 3.3 V in ROM parts
as well.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
78
Signal Descriptions – Continued.
GPIO
Peripheral Signal
Terminal
Number
I/O/Z
2/
PU/PD
3/
4/
Description
GPIO or Peripheral Signals.
GPIOA or EVA Signals.
GPIOA0
PWM1 (O)
90
I/O/Z
PU
GPIO or PWM Output Pin #1.
GPIOA1
PWM2 (O)
91
I/O/Z
PU
GPIO or PWM Output Pin #2.
GPIOA2
PWM3 (O)
92
I/O/Z
PU
GPIO or PWM Output Pin #3.
GPIOA3
PWM4 (O)
93
I/O/Z
PU
GPIO or PWM Output Pin #4.
GPIOA4
PWM5 (O)
96
I/O/Z
PU
GPIO or PWM Output Pin #5.
GPIOA5
PWM6 (O)
99
I/O/Z
PU
GPIO or PWM Output Pin #6.
GPIOA6
T1PWM_T1CMP (I)
100
I/O/Z
PU
GPIO or Timer 1 Output.
GPIOA7
T2PWM_T2CMP (I)
102
I/O/Z
PU
GPIO or Timer 2 Output.
GPIOA8
CAP1_QEP1 (I)
104
I/O/Z
PU
GPIO or Capture Input #1.
GPIOA9
CAP2_QEP2 (I)
105
I/O/Z
PU
GPIO or Capture Input #2.
GPIOA10
CAP3_QEPI1 (I)
107
I/O/Z
PU
GPIO or Capture Input #3.
GPIOA11
TDIRA (I)
114
I/O/Z
PU
GPIO or Timer Direction.
GPIOA12
TCLKINA (I)
115
I/O/Z
PU
GPIO or Timer Clock Input.
GPIOA13
C1TRIP (I)
119
I/O/Z
PU
GPIO or Compare 1 Output Trip.
GPIOA14
C2TRIP (I)
120
I/O/Z
PU
GPIO or Compare 2 Output Trip.
GPIOA15
C3TRIP (I)
121
I/O/Z
PU
GPIO or Compare 3 Output Trip.
GPIOB0
PWM7 (O)
44
I/O/Z
PU
GPIO or PWM Output Pin #7.
GPIOB1
PWM8 (O)
45
I/O/Z
PU
GPIO or PWM Output Pin #8.
GPIOB2
PWM9 (O)
46
I/O/Z
PU
GPIO or PWM Output Pin #9.
GPIOB3
PWM10 (O)
47
I/O/Z
PU
GPIO or PWM Output Pin #10.
GPIOB4
PWM11 (O)
48
I/O/Z
PU
GPIO or PWM Output Pin #11.
GPIOB5
PWM12 (O)
49
I/O/Z
PU
GPIO or PWM Output Pin #12.
GPIOB6
T3PWM_T3CMP (I)
52
I/O/Z
PU
GPIO or Timer 3 Output.
GPIOB7
T4PWM_T4CMP (I)
54
I/O/Z
PU
GPIO or Timer 4 Output.
GPIOB8
CAP4_QEP3 (I)
56
I/O/Z
PU
GPIO or Capture Input #4.
GPIOB9
CAP5_QEP4 (I)
58
I/O/Z
PU
GPIO or Capture Input #5.
GPIOB10
CAP6_QEPI2 (I)
59
I/O/Z
PU
GPIO or Capture Input #6.
GPIOB11
TDIRB (I)
69
I/O/Z
PU
GPIO or Timer Direction.
GPIOB or EVB Signals.
GPIOB12
TCLKINB (I)
70
I/O/Z
PU
GPIO or Timer Clock Input.
GPIOB13
C4TRIP (I)
60
I/O/Z
PU
GPIO or Compare 4 Output Trip.
GPIOB14
C5TRIP (I)
61
I/O/Z
PU
GPIO or Compare 5 Output Trip.
GPIOB15
C6TRIP (I)
62
I/O/Z
PU
GPIO or Compare 6 Output Trip.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
79
Signal Descriptions – Continued.
GPIO
Peripheral Signal
Terminal
Number
I/O/Z
2/
PU/PD
3/
4/
Description
GPIOD or EVA Signals.
GPIOD0
T1CTRIP_PDPINTA
(I)
108
I/O/Z
PU
Timer 1 Compare Output Trip.
GPIOD1
T2CTRIP/EVASOC (I)
113
I/O/Z
PU
Timer 2 Compare Output Trip or External ADC
Start-of-Conversion EV-A.
GPIOD5
T3CTRIP_PDPINTB
(I)
77
I/O/Z
PU
Timer 3 Compare Output Trip.
GPIOD6
T4CTRIP/EVBSOC (I)
81
I/O/Z
PU
Timer 4 Compare Output Trip or External ADC
Start-of-Conversion EV-B.
GPIOE0
XINT1_XBIO (I)
146
I/O/Z
-
GPIO or XINT1 or XBIO input.
GPIOE1
XINT2_ADCSOC (I)
148
I/O/Z
-
GPIO or XINT2 or ADC start of conversion.
GPIOE2
XNMI_XINT13 (I)
147
I/O/Z
PU
GPIOD or EVB Signals.
GPIOE or Interrupt Signals.
GPIO or XNMI or XINT13.
GPIOF or SPI Signals.
GPIOF0
SPISIMOA (O)
39
I/O/Z
-
GPIO or SPI slave in, master out.
GPIOF1
SPISOMIA (I)
40
I/O/Z
-
GPIO or SPI slave out, master in.
GPIOF2
SPICLKA (I/O)
33
I/O/Z
-
GPIO or SPI clock.
GPIOF3
SPISTEA (I/O)
34
I/O/Z
-
GPIO or SPI slave transmit enable.
GPIOF4
SCITIXDA (O)
151
I/O/Z
PU
GPIO or SCI asynchronous serial port TX
data.
GPIOF5
SCIRXDA (I)
153
I/O/Z
PU
GPIO or SCI asynchronous serial port RX
data.
GPIOF or SCI-A Signals.
GPIOF or CAN Signals.
GPIOF6
CANTXA (O)
85
I/O/Z
PU
GPIO or eCAN transmit data.
GPIOF7
CANRXA (I)
87
I/O/Z
PU
GPIO or eCAN receive data.
GPIOF8
MCLKXA (I/O)
27
GPIOF or McBSP Signals.
I/O/Z
PU
GPIO or transmit clock.
GPIOF9
MCLKRA (I/O)
24
I/O/Z
PU
GPIO or receive clock.
GPIOF10
MFSXA (I/O)
25
I/O/Z
PU
GPIO or transmit frame synch.
GPIOF11
MFSRA (I/O)
28
I/O/Z
PU
GPIO or receive frame synch.
GPIOF12
MDXA (O)
21
I/O/Z
-
GPIOF13
MDRA (I)
19
I/O/Z
PU
GPIO or transmitted serial data.
GPIO or received serial data.
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
80
Signal Descriptions – Continued.
GPIO
Peripheral Signal
Terminal
Number
I/O/Z
2/
PU/PD
3/
4/
Description
GPIOF or XF CPU Output Signal.
GPIOF14
XF_XPLLDIS (O)
137
I/O/Z
PU
This pin has three functions:
1. XF - General-purpose output pin.
2. XPLLDIS - This pin will be sampled during
reset to check if the PLL needs to be disabled.
The PLL will be disabled if this pin is sensed
low. HALT and STANDBY modes cannot be
used when the PLL is disabled.
3. GPIO - GPIO function.
GPIOG4
SCITXDB (O)
88
I/O/Z
-
GPIO or SCI asynchronous serial port transmit
data.
GPIOG5
SCIRXDB (I)
89
I/O/Z
-
GPIO or SCI asynchronous serial port receive data.
GPIOG or SCI-B Signals.
1/
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1
pins, which are 8 mA.
2/
I = Input, O = Output, Z = High impedance.
3/
PU = Pin has internal pullup; PD = Pin has internal pulldown.
4/
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA
typical.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
81
Possible PLL Configuration Modes.
PLL Mode
Remarks
SYSCLKOUT
PLL Disabled
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
XCLKIN
PLL Bypassed
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the
clock input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
PLL Enabled
Achieved by writing a non-zero value “n” into PLLCR register. The /2
module in the PLL block now divides the output of the PLL by two before
feeding it to the CPU.
(XCLKIN * n)/2
Minimum Required Wait-States at Different Frequencies.
1/
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
150
6.67
5
5
120
8.33
4
4
100
10
3
3
75
13.33
2
2
50
20
1
1
30
33.33
1
1
25
40
0
1
15
66.67
0
1
4
250
0
1
Page Wait-State
1/
Random Wait-State
1/ 2/
Page Wait State = [ (ta(fp)/tc(SCO)) – 1 ] (round up to the next highest integer), or 0, whichever is larger.
Random Wait State = [ (ta(fr)/tc(SCO)) – 1 ] (round up to the next highest integer), or 1, whichever is larger.
2/
Random wait state must be greater than or equal to 1.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-06208
A
REVISION LEVEL
SHEET
82
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 06-09-25
Approved sources of supply for SMD 5962-06208 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
5962-0620801QXC
Vendor
CAGE
number
01295
Vendor
similar
PIN 2/
SMJ320F2812HFGM150
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
01295
Vendor name
and address
Texas Instruments, Inc.
Semiconductor Group
8505 Forest Lane
P.O. Box 660199
Dallas, TX 75243
Point of Contact:
U.S. Highway 75 South
P.O. Box 84, M/S 853
Sherman, TX 75090-9493
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
Similar pages