INTEGRATED CIRCUITS DATA SHEET 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1998 Feb 23 2003 Jul 10 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 FEATURES GENERAL DESCRIPTION • Wide supply voltage range from 2.0 to 6.0 V The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • Symmetrical output impedance • High noise immunity • Low power dissipation The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. • Balanced propagation delays • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V nCP to nQ, nQ 14 15 ns nSD to nQ, nQ 15 18 ns nRD to nQ, nQ 16 18 ns 76 59 MHz fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per flip-flop notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the condition is VI = GND to VCC. For 74HCT74 the condition is VI = GND to VCC − 1.5 V. 2003 Jul 10 HCT 2 3.5 3.5 pF 24 29 pF Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 FUNCTION TABLES Table 1 See note 1 INPUT Table 2 OUTPUT SD RD CP D Q Q L H X X H L H L X X L H L L X X H H See note 1 INPUT OUTPUT SD RD CP D Qn+1 Qn+1 H H ↑ L L H H H ↑ H H L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC74N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HCT74N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HC74D −40 to +125 °C 14 SO14 plastic SOT108-1 74HCT74D −40 to +125 °C 14 SO14 plastic SOT108-1 74HC74DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HCT74DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HC74PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HCT74PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HC74BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 74HCT74BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 2003 Jul 10 3 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 PINNING PIN SYMBOL DESCRIPTION 1 1RD asynchronous reset-direct input (active LOW) 2 1D data input 3 1CP clock input (LOW-to-HIGH, edge-triggered) 4 1SD asynchronous set-direct input (active LOW) 5 1Q true flip-flop output 6 1Q complement flip-flop output 7 GND ground (0 V) 8 2Q complement flip-flop output 9 2Q true flip-flop output 10 2SD asynchronous set-direct input (active LOW) 11 2CP clock input (LOW-to-HIGH, edge-triggered) 12 2D data input 13 2RD asynchronous reset-direct input (active LOW) 14 VCC positive supply voltage handbook, halfpage handbook, halfpage 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 1Q 5 10 2SD 1Q 6 9 GND 7 8 2Q 74 11 2CP 1RD VCC 1 14 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND(1) 2Q MNA417 Top view 7 8 GND 2Q MNB038 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14. 2003 Jul 10 Fig.2 Pin configuration DHVQFN14. 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger handbook, halfpage 4 10 handbook, halfpage 2 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 5 9 1 10 6 8 11 12 1RD 2RD 1 13 13 MNA418 4 2 3 1CP SD Q D 1Q 5 CP FF Q 1Q 6 RD 1 10 12 11 1RD 2SD 2D 2CP SD Q D 2Q 9 CP FF Q 2Q 8 RD 13 2RD MNA420 Fig.5 Functional diagram. 2003 Jul 10 5 C1 1D 6 R S 9 C1 1D 8 R Fig.4 IEC logic symbol. 1SD 1D S MNA419 Fig.3 Logic symbol. handbook, halfpage 4 3 1SD 2SD 2 12 3 11 74HC74; 74HCT74 5 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 handbook, full pagewidth Q C C C C C C D Q C C RD SD CP MNA421 C C Fig.6 Logic diagram (one flip-flop). 2003 Jul 10 6 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 RECOMMENDED OPERATING CONDITIONS 74HC74 SYMBOL PARAMETER 74HCT74 CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +125 −40 +25 +125 °C tr, tf input rise and fall times VCC = 2.0 V − − 1000 − − 500 ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − 500 ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 +7.0 V VI < −0.5 V or VI > VCC + 0.5 V; note 1 − ±20 mA output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V; note 1 − ±25 mA ICC, IGND VCC or GND current ±100 mA Tstg storage temperature Ptot power dissipation VCC supply voltage IIK input diode current IOK − Tamb = −40 to +125 °C; note 2 −65 +150 °C − 500 mW Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. For DIP14 packages: above 70 °C derate linearly with 12 mW/K. 2003 Jul 10 7 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 DC CHARACTERISTICS Family 74HC At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH VIL VOH 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V 4.5 − 0.15 0.33 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IO = 5.2 mA 6.0 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 40 µA 2.0 1.5 − − V 4.5 3.15 − − V 6.0 4.2 − − V 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V IO = 4.0 mA 4.5 − − 0.4 V IO = 5.2 mA 6.0 − − 0.4 V VOL IO = 4.0 mA Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 80 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 Jul 10 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 Family 74HCT At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 1.6 − V 4.5 to 5.5 − 1.2 0.8 V VI = VIH or VIL; IO = −4.0 mA 4.5 3.84 4.32 − V LOW-level output voltage VI = VIH or VIL; IO = 4.0 mA 4.5 0.33 0.15 − V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional quiescent supply current per input VI = VCC −2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − 100 450 µA − − V VIH HIGH-level input voltage 4.5 to 5.5 VIL LOW-level input voltage VOH HIGH-level output voltage VOL 2.0 Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −4.0 mA 4.5 3.7 − − V VOL LOW-level output voltage VI = VIH or VIL; IO = 4.0 mA 4.5 − − 0.4 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 80 µA ∆ICC additional quiescent supply current per input VI = VCC −2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 490 µA Note 1. All typical values are measured at Tamb = 25 °C. Remark to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table. 2003 Jul 10 INPUT UNIT LOAD COEFFICIENT nD 0.70 nRD 0.70 nSD 0.80 nCP 0.80 9 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 AC CHARACTERISTICS Family 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C tPHL/tPLH tTHL/tTLH tW propagation delay nCP to nQ, nQ see Fig.7 propagation delay nSD to nQ, nQ see Fig.8 propagation delay nRD to nQ, nQ see Fig.8 output transition time see Fig.7 clock pulse width HIGH or LOW see Fig.7 set or reset pulse width see Fig.8 LOW trem tsu th fmax 2003 Jul 10 removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency see Fig.8 see Fig.7 see Fig.7 see Fig.7 10 2.0 − 47 220 ns 4.5 − 17 44 ns 6.0 − 14 37 ns 2.0 − 50 250 ns 4.5 − 18 50 ns 6.0 − 14 43 ns 2.0 − 52 250 ns 4.5 − 19 50 ns 6.0 − 15 43 ns 2.0 − 19 95 ns 4.5 − 7 19 ns 6.0 − 6 16 ns 2.0 100 19 − ns 4.5 20 7 − ns 6.0 17 6 − ns 2.0 100 19 − ns 4.5 20 7 − ns 6.0 17 6 − ns 2.0 40 3 − ns 4.5 8 1 − ns 6.0 7 1 − ns 2.0 75 6 − ns 4.5 15 2 − ns 6.0 13 2 − ns 2.0 3 −6 − ns 4.5 3 −2 − ns 6.0 3 −2 − ns 2.0 4.8 23 − MHz 4.5 24 69 − MHz 6.0 28 82 − MHz Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C tPHL/tPLH tTHL/tTLH tW tW trem tsu th fmax 2003 Jul 10 propagation delay nCP to nQ, nQ see Fig.7 propagation delay nSD to nQ, nQ see Fig.8 propagation delay nRD to nQ, nQ see Fig.8 output transition time see Fig.7 clock pulse width HIGH see Fig.7 or LOW set or reset pulse width see Fig.8 LOW removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency see Fig.8 see Fig.7 see Fig.7 see Fig.7 11 2.0 − − 265 ns 4.5 − − 53 ns 6.0 − − 45 ns 2.0 − − 300 ns 4.5 − − 60 ns 6.0 − − 51 ns 2.0 − − 300 ns 4.5 − − 60 ns 6.0 − − 51 ns 2.0 − − 110 ns 4.5 − − 22 ns 6.0 − − 19 ns 2.0 120 − − ns 4.5 24 − − ns 6.0 20 − − ns 2.0 120 − − ns 4.5 24 − − ns 6.0 20 − − ns 2.0 45 − − ns 4.5 9 − − ns 6.0 8 − − ns 2.0 90 − − ns 4.5 18 − − ns 6.0 15 − − ns 2.0 3 − − ns 4.5 3 − − ns 6.0 3 − − ns 2.0 4.0 − − MHz 4.5 20 − − MHz 6.0 24 − − MHz Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 Family 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C propagation delay nCP to nQ, nQ see Fig.7 4.5 − 18 44 ns propagation delay nSD to nQ, nQ see Fig.8 4.5 − 23 50 ns propagation delay nRD to nQ, nQ see Fig.8 4.5 − 24 50 ns tTHL/tTLH output transition time see Fig.7 4.5 − 7 19 ns tW clock pulse width HIGH see Fig.7 or LOW 4.5 23 9 − ns set or reset pulse width see Fig.8 LOW 4.5 20 9 − ns trem removal time set or reset see Fig.8 4.5 8 1 − ns tsu set-up time nD to nCP see Fig.7 4.5 15 5 − ns th hold time nCP to nD see Fig.7 4.5 +3 −3 − ns fmax maximum clock pulse frequency see Fig.7 4.5 22 54 − MHz propagation delay nCP to nQ, nQ see Fig.7 4.5 − − 53 ns propagation delay nSD to nQ, nQ see Fig.8 4.5 − − 60 ns propagation delay nRD to nQ, nQ see Fig.8 4.5 − − 60 ns tTHL/tTLH output transition time see Fig.7 4.5 − − 22 ns tW clock pulse width HIGH see Fig.7 or LOW 4.5 27 − − ns set or reset pulse width see Fig.8 LOW 4.5 24 − − ns trem removal time set or reset see Fig.8 4.5 9 − − ns tsu set-up time nD to nCP see Fig.7 4.5 18 − − ns th hold time nCP to nD see Fig.7 4.5 3 − − ns fmax maximum clock pulse frequency see Fig.7 4.5 18 − − MHz tPHL/tPLH Tamb = −40 to +125 °C tPHL/tPLH 2003 Jul 10 12 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 AC WAVEFORMS VI handbook, full pagewidth VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL MNA422 The shaded areas indicate when the input is permitted to change for predictable output performance. 74HC74: VM = 50%; VI = GND to VCC. 74HCT74: VM = 1.3 V; VI = GND to 3 V. Fig.7 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency. 2003 Jul 10 13 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 VI handbook, full pagewidth VM nCP input GND t rem VI VM nSD input GND tW tW VI VM nRD input GND t PHL t PLH VOH nQ output VM VOL VOH VM nQ output VOL MNA423 t PHL t PLH 74HC74: VM = 50%; VI = GND to VCC. 74HCT74: VM = 1.3 V; VI = GND to 3 V. Fig.8 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nRD to nCP removal time. 2003 Jul 10 14 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 S1 handbook, full pagewidth VCC PULSE GENERATOR RL = VI VCC open GND 1 kΩ VO D.U.T. CL RT MNA183 TEST S1 tPZH GND tPZL VCC tPHZ GND tPLZ VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.9 Load circuitry for switching times. 2003 Jul 10 15 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 2003 Jul 10 16 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 2003 Jul 10 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 17 o 8 0o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 2003 Jul 10 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 18 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 2003 Jul 10 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 19 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- 2003 Jul 10 20 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jul 10 21 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp22 Date of release: 2003 Jul 10 Document order number: 9397 750 11259