PHILIPS P89LPC932A1FDH

P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB 3 V byte-erasable flash with 512-byte data EEPROM
Rev. 03 — 12 March 2007
Product data sheet
1. General description
The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based
on a high performance processor architecture that executes instructions in two to four
clocks, six times the rate of standard 80C51 devices. Many system-level functions have
been incorporated into the P89LPC932A1 in order to reduce component count, board
space, and system cost.
2. Features
2.1 Principal features
n 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
n 256-byte RAM data memory, 512-byte auxiliary on-chip RAM.
n 512-byte customer data EEPROM on chip allows serialization of devices, storage of
set-up parameters, etc.
n Two analog comparators with selectable inputs and reference source.
n Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
n Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
n CCU provides PWM, input capture, and output compare functions.
n High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 28-pin TSSOP, PLCC, HVQFN, and DIP packages with 23 I/O pins minimum and up to
26 I/O pins while using on-chip oscillator and reset options.
2.2 Additional features
n A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
n In-Circuit Programming (ICP) allows simple production coding with commercial
EPROM programmers. Flash security bits prevent reading of sensitive application
programs.
n Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
n In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
n Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
n Low voltage reset (brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
n Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 µA (total power-down with voltage comparators disabled).
n Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
n Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
n Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
n Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
n Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
n LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
n Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
n Only power and ground connections are required to operate the P89LPC932A1 when
internal reset option is selected.
n Four interrupt priority levels.
n Eight keypad interrupt inputs, plus two additional external interrupt inputs.
n Schmitt trigger port inputs.
n Second data pointer.
n Emulation support.
2.3 Comparison to the P89LPC932
The P89LPC932A1 includes several improvements compared to the P89LPC932. Please
see P89LPC932A1 User manual for additional detailed information.
n Byte-erasability has been added to the user code memory space.
n All of the errata described in the P89LPC932 Errata sheet have been fixed.
n Serial ICP has been added.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
2 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
n The RCCLK bit has been added to the TRIM register allowing the RCCLK to be
selected as the CPU clock (CCLK) regardless of the settings in UCFG1, allowing the
internal RC oscillator to be selected as the CPU clock without the need to reset the
device.
n Enhancements added to the ISP/IAP code to improve code safety and increase
ISP/IAP functionality. This may require slight changes to original P89LPC932 code
using IAP function calls. Some ISP/IAP settings are different than the original
P89LPC932. Tools designed to support the P89LPC932A1 should be used to program
this device, such as Flash Magic version 1.98, or later.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
P89LPC932A1FA
PLCC28
plastic leaded chip carrier; 28 leads
SOT261-2
P89LPC932A1FDH
TSSOP28
plastic thin shrink small outline package; 28 leads; body width
4.4 mm
SOT361-1
P89LPC932A1FHN
HVQFN28
plastic thermal enhanced very thin quad flat package; no leads; SOT788-1
28 terminals; body 6 × 6 × 0.85 mm
P89LPC932A1FN
DIP28
plastic dual in-line package; 28 leads (600 mil)
P89LPC932A1_3
Product data sheet
SOT117-1
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
3 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
4. Block diagram
P89LPC932A1
ACCELERATED 2-CLOCK 80C51 CPU
8 kB
CODE FLASH
UART
TXD
RXD
I2C-BUS
SCL
SDA
internal
bus
256-BYTE
DATA RAM
SPICLK
MISO
MOSI
SS
512-BYTE
AUXILIARY RAM
SPI
512-BYTE
DATA EEPROM
REAL-TIME CLOCK/
SYSTEM TIMER
P3[1:0]
PORT 3
CONFIGURABLE I/Os
TIMER 0
TIMER 1
P2[7:0]
PORT 2
CONFIGURABLE I/Os
P1[7:0]
PORT 1
CONFIGURABLE I/Os
P0[7:0]
PORT 0
CONFIGURABLE I/Os
T0
T1
ANALOG
COMPARATORS
CCU (CAPTURE/
COMPARE UNIT)
CMP2
CIN2A
CIN2B
CMP1
CIN1A
CIN1B
OCA
OCB
OCC
OCD
ICA
ICB
KEYPAD
INTERRUPT
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CRYSTAL
OR
RESONATOR
XTAL1
CONFIGURABLE
OSCILLATOR
XTAL2
CPU
clock
ON-CHIP
RC
OSCILLATOR
002aaa885
Fig 1. Block diagram
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
4 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
5. Functional diagram
VDD
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
CLKOUT
XTAL2
VSS
PORT 0
PORT 1
TXD
RXD
T0
INT0
INT1
RST
OCB
OCC
PORT 2
ICB
OCD
MOSI
MISO
SS
SPICLK
OCA
ICA
P89LPC932A1
PORT 3
XTAL1
SCL
SDA
002aaa890
Fig 2. Functional diagram of P89LPC932A1
6. Pinning information
6.1 Pinning
P2.0/ICB
1
28 P2.7/ICA
P2.1/OCD
2
27 P2.6/OCA
P0.0/CMP2/KBI0
3
26 P0.1/CIN2B/KBI1
P1.7/OCC
4
25 P0.2/CIN2A/KBI2
P1.6/OCB
5
24 P0.3/CIN1B/KBI3
P1.5/RST
6
23 P0.4/CIN1A/KBI4
VSS
7
P3.1/XTAL1
8
P3.0/XTAL2/CLKOUT
9
P89LPC932A1FDH
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
P1.4/INT1 10
19 P0.7/T1/KBI7
P1.3/INT0/SDA 11
18 P1.0/TXD
P1.2/T0/SCL 12
17 P1.1/RXD
P2.2/MOSI 13
16 P2.5/SPICLK
P2.3/MISO 14
15 P2.4/SS
002aaa886
Fig 3. P89LPC932A1 TSSOP28 pin configuration
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
5 of 64
P89LPC932A1
NXP Semiconductors
P2.0/ICB
1
26 P0.1/CIN2B/KBI1
P2.1/OCD
2
27 P2.6/OCA
P0.0/CMP2/KBI0
3
28 P2.7/ICA
P1.7/OCC
4
8-bit microcontroller with accelerated two-clock 80C51 core
P1.6/OCB
5
25 P0.2/CIN2A/KBI2
P1.5/RST
6
24 P0.3/CIN1B/KBI3
VSS
7
P3.1/XTAL1
8
P3.0/XTAL2/CLKOUT
9
23 P0.4/CIN1A/KBI4
P89LPC932A1FA
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
P1.4/INT1 10
19 P0.7/T1/KBI7
P1.1/RXD 17
P1.0/TXD 18
23 P2.6/OCA
22 P0.1/CIN2B/KBI1
P2.5/SPICLK 16
P2.4/SS 15
P2.3/MISO 14
P2.2/MOSI 13
P1.2/T0/SCL 12
P1.3/INT0/SDA 11
002aaa887
24 P2.7/ICA
25 P2.0/ICB
26 P2.1/OCD
terminal 1
index area
27 P0.0/CMP2/KBI0
28 P1.7/OCC
Fig 4. P89LPC932A1 PLCC28 pin configuration
P1.6/OCB
1
21 P0.2/CIN2A/KBI2
P1.5/RST
VSS
2
20 P0.3/CIN1B/KBI3
P3.1/XTAL1
4
P3.0/XTAL2/CLKOUT
5
17 VDD
P1.4/INT1
6
16 P0.6/CMP1/KBI6
P1.3/INT0/SDA
7
15 P0.7/T1/KBI7
19 P0.4/CIN1A/KBI4
3
P1.0/TXD 14
P1.1/RXD 13
P2.5/SPICLK 12
P2.2/MOSI
P2.4/SS 11
9
P2.3/MISO 10
8
P1.2/T0/SCL
P89LPC932A1FHN
18
P0.5/CMPREF/KBI5
002aaa889
Transparent top view
Fig 5. P89LPC932A1 HVQFN28 pin configuration
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
6 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
P2.0/ICB
1
28 P2.7/ICA
P2.1/OCD
2
27 P2.6/OCA
P0.0/CMP2/KBI0
3
26 P0.1/CIN2B/KBI1
P1.7/OCC
4
25 P0.2/CIN2A/KBI2
P1.6/OCB
5
24 P0.3/CIN1B/KBI3
P1.5/RST
6
23 P0.4/CIN1A/KBI4
VSS
7
P3.1/XTAL1
8
P3.0/XTAL2/CLKOUT
9
P89LPC932A1FN
P1.4/INT1 10
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
P1.3/INT0/SDA 11
18 P1.0/TXD
P1.2/T0/SCL 12
17 P1.1/RXD
P2.2/MOSI 13
16 P2.5/SPICLK
P2.3/MISO 14
15 P2.4/SS
002aac785
Fig 6. P89LPC932A1 DIP28 pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28,
DIP28
P0.0 to P0.7
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
During reset Port 0 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 7.13.1 “Port configurations”
and Table 8 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/
KBI0
3
P0.1/CIN2B/
KBI1
26
P0.2/CIN2A/
KBI2
P0.3/CIN1B/
KBI3
25
24
27
22
21
20
I/O
P0.0 — Port 0 bit 0.
O
CMP2 — Comparator 2 output.
I
KBI0 — Keyboard input 0.
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
I
KBI1 — Keyboard input 1.
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
I
KBI2 — Keyboard input 2.
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
I
KBI3 — Keyboard input 3.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
7 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28,
DIP28
P0.4/ CIN1A/
KBI4
23
P0.5/
CMPREF/
KBI5
22
P0.6/CMP1/
KBI6
20
P0.7/T1/KBI7
19
19
18
16
15
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
I
KBI4 — Keyboard input 4.
I/O
P0.5 — Port 0 bit 5.
I
CMPREF — Comparator reference (negative) input.
I
KBI5 — Keyboard input 5.
I/O
P0.6 — Port 0 bit 6.
O
CMP1 — Comparator 1 output.
I
KBI6 — Keyboard input 6.
I/O
P0.7 — Port 0 bit 7.
I/O
T1 — Timer/counter 1 external count input or overflow output.
I
KBI7 — Keyboard input 7.
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type,
[1]
except for three pins as noted below. During reset Port 1 latches are
configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends
upon the port configuration selected. Each of the configurable port pins
are programmed independently. Refer to Section 7.13.1 “Port
configurations” and Table 8 “Static characteristics” for details. P1.2 and
P1.3 are open drain when used as outputs. P1.5 is input only.
P1.0 to P1.7
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD
P1.1/RXD
P1.2/T0/SCL
P1.3/INT0/
SDA
P1.4/INT1
18
17
12
11
10
14
13
8
7
6
I/O
P1.0 — Port 1 bit 0.
O
TXD — Transmitter output for the serial port.
I/O
P1.1 — Port 1 bit 1.
I
RXD — Receiver input for the serial port.
I/O
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
T0 — Timer/counter 0 external count input or overflow output (open-drain
when used as output).
I/O
SCL — I2C serial clock input/output.
I/O
P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O
SDA — I2C serial data input/output.
I
P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
8 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28,
DIP28
P1.5/RST
P1.6/OCB
P1.7/OCC
6
5
4
2
1
28
P2.0 to P2.7
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system
power is removed VDD will fall below the minimum specified
operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD falls below the
minimum specified operating voltage.
I/O
P1.6 — Port 1 bit 6.
O
OCB — Output Compare B.
I/O
P1.7 — Port 1 bit 7.
O
OCC — Output Compare C.
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 7.13.1 “Port configurations”
and Table 8 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0/ICB
P2.1/OCD
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/OCA
1
2
13
14
15
16
27
25
26
9
10
11
12
23
I/O
P2.0 — Port 2 bit 0.
I
ICB — Input Capture B.
I/O
P2.1 — Port 2 bit 1.
O
OCD — Output Compare D.
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When configured as master, this pin is input, when configured as
slave, this pin is output.
I/O
P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
I/O
P2.6 — Port 2 bit 6.
O
OCA — Output Compare A.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
9 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TSSOP28, HVQFN28
PLCC28,
DIP28
P2.7/ICA
28
24
P3.0 to P3.1
I/O
P2.7 — Port 2 bit 7.
I
ICA — Input Capture A.
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.
During reset Port 3 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 3 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to Section 7.13.1 “Port configurations”
and Table 8 “Static characteristics” for details.
All pins have Schmitt trigger inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
P3.1/XTAL1
9
8
5
4
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator
option is selected via the flash configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK TRIM.6). It can be used if the CPU clock is the internal RC oscillator,
watchdog oscillator or external clock input, except when XTAL1/XTAL2 are
used to generate clock source for the RTC/system timer.
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits
(when selected via the flash configuration). It can be a port pin if internal
RC oscillator or watchdog oscillator is used as the CPU clock source, and
if XTAL1/XTAL2 are not used to generate the clock for the RTC/system
timer.
VSS
7
3
I
Ground: 0 V reference.
VDD
21
17
I
Power supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes.
[1]
Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
10 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
7. Functional description
Remark: Please refer to the P89LPC932A1 User manual for a more detailed functional
description.
7.1 Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with logic 0, but can return any
value when read (even if it was written with logic 0). It is a reserved bit and may be
used in future derivatives.
– Logic 0 must be written with logic 0, and will return a logic 0 when read.
– Logic 1 must be written with logic 1, and will return a logic 1 when read.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
11 of 64
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NXP Semiconductors
P89LPC932A1_3
Product data sheet
Table 3.
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr.
MSB
Hex
Binary
00
0000 0000
00
0000 00x0
F0H
00
0000 0000
BEH
00[1]
0000 0000
00[1]
0000 0000
Bit address
ACC*
Accumulator
AUXR1
Auxiliary function register
BRGR0
E7
E6
E5
E4
E3
E2
E1
E0
E0H
A2H
Bit address
B*
Reset value
LSB
B register
Baud rate generator rate low
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
F7
F6
F5
F4
F3
F2
F1
F0
Baud rate generator rate high
BFH
BRGCON
Baud rate generator control
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[1]
xxxx xx00
CCCRA
Capture compare A control
register
EAH
ICECA2
ICECA1
ICECA0
ICESA
ICNFA
FCOA
OCMA1
OCMA0
00
0000 0000
CCCRB
Capture compare B control
register
EBH
ICECB2
ICECB1
ICECB0
ICESB
ICNFB
FCOB
OCMB1
OCMB0
00
0000 0000
CCCRC
Capture compare C control
register
ECH
-
-
-
-
-
FCOC
OCMC1
OCMC0
00
xxxx x000
CCCRD
Capture compare D control
register
EDH
-
-
-
-
-
FCOD
OCMD1
OCMD0
00
xxxx x000
CMP1
Comparator 1 control register
ACH
-
-
CE1
CP1
CN1
OE1
CO1
CMF1
00[2]
xx00 0000
00[2]
xx00 0000
0E
0000 1110
Comparator 2 control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2
DEECON
Data EEPROM control
register
F1H
EEIF
HVERR
ECTL1
ECTL0
-
-
-
EADR8
DEEDAT
Data EEPROM data register
F2H
00
0000 0000
DEEADR
Data EEPROM address
register
F3H
00
0000 0000
DIVM
CPU clock divide-by-M
control
95H
00
0000 0000
DPTR
Data pointer (2 bytes)
DPH
Data pointer high
83H
00
0000 0000
DPL
Data pointer low
82H
00
0000 0000
I2ADR
I2C
DBH
00
0000 0000
I2CON*
I2C
00
x000 00x0
slave address register
Bit address
control register
D8H
I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC
DF
DE
DD
DC
DB
DA
D9
D8
-
I2EN
STA
STO
SI
AA
-
CRSEL
P89LPC932A1
12 of 64
© NXP B.V. 2007. All rights reserved.
CMP2
8-bit microcontroller with accelerated two-clock 80C51 core
Rev. 03 — 12 March 2007
BRGR1
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Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
I2DAT
I2C
I2SCLH
Serial clock generator/SCL
duty cycle register high
DDH
00
0000 0000
I2SCLL
Serial clock generator/SCL
duty cycle register low
DCH
00
0000 0000
I2STAT
I2C status register
D9H
F8
1111 1000
ICRAH
Input capture A register high
ABH
00
0000 0000
ICRAL
Input capture A register low
AAH
00
0000 0000
ICRBH
Input capture B register high
AFH
00
0000 0000
ICRBL
Input capture B register low
AEH
00
0000 0000
00
0000 0000
00[2]
00x0 0000
data register
DAH
Interrupt enable 0
IEN1*
Interrupt enable 1
A8H
Bit address
E8H
Bit address
IP0*
IP0H
Interrupt priority 0
B8H
Interrupt priority 0 high
B7H
Bit address
IP1*
Interrupt priority 1
F8H
STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0
AF
AE
AD
AC
AB
AA
A9
A8
EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0
EF
EE
ED
EC
EB
EA
E9
E8
EIEE
EST
-
ECCU
ESPI
EC
EKBI
EI2C
BF
BE
BD
BC
BB
BA
B9
B8
-
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0
00[2]
x000 0000
00[2]
x000 0000
-
PWDRT
H
PBOH
PSH/
PSRH
PT1H
PX1H
PT0H
PX0H
FF
FE
FD
FC
FB
FA
F9
F8
PIEE
PST
-
PCCU
PSPI
PC
PKBI
PI2C
00[2]
00x0 0000
00x0 0000
Interrupt priority 1 high
F7H
PIEEH
PSTH
-
PCCUH
PSPIH
PCH
PKBIH
PI2CH
KBCON
Keypad control register
94H
-
-
-
-
-
-
PATN
_SEL
KBIF
00[2]
xxxx xx00
KBMASK
Keypad interrupt mask
register
86H
00
0000 0000
KBPATN
Keypad pattern register
93H
FF
1111 1111
OCRAH
Output compare A register
high
EFH
00
0000 0000
OCRAL
Output compare A register
low
EEH
00
0000 0000
P89LPC932A1
13 of 64
© NXP B.V. 2007. All rights reserved.
IP1H
00[2]
8-bit microcontroller with accelerated two-clock 80C51 core
Rev. 03 — 12 March 2007
Bit address
IEN0*
NXP Semiconductors
P89LPC932A1_3
Product data sheet
Table 3.
Special function registers …continued
* indicates SFRs that are bit addressable.
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Name
Description
SFR Bit functions and addresses
addr.
MSB
Reset value
LSB
Hex
Binary
Output compare B register
high
FBH
00
0000 0000
OCRBL
Output compare B register
low
FAH
00
0000 0000
OCRCH
Output compare C register
high
FDH
00
0000 0000
OCRCL
Output compare C register
low
FCH
00
0000 0000
OCRDH
Output compare D register
high
FFH
00
0000 0000
OCRDL
Output compare D register
low
FEH
00
0000 0000
P0*
Port 0
80H
Bit address
P1*
Port 1
90H
Bit address
P2*
Port 2
P3*
Port 3
A0H
Bit address
P0M2
Port 0 output mode 1
Port 0 output mode 2
84H
85H
86
85
84
83
82
81
80
CMP1
/KB6
CMPREF
/KB5
CIN1A
/KB4
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
97
96
95
94
93
92
91
90
OCC
OCB
RST
INT1
INT0/
SDA
T0/SCL
RXD
TXD
97
96
95
94
93
92
91
90
ICA
OCA
SPICLK
SS
MISO
MOSI
OCD
ICB
B7
B6
B5
B4
B3
B2
B1
B0
-
-
-
-
-
-
XTAL1
XTAL2
[2]
[2]
[2]
[2]
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0)
FF[2]
1111 1111
(P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0)
00[2]
0000 0000
D3[2]
11x1 xx11
14 of 64
© NXP B.V. 2007. All rights reserved.
P1M1
Port 1 output mode 1
91H
(P1M1.7) (P1M1.6)
-
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0)
P1M2
Port 1 output mode 2
92H
(P1M2.7) (P1M2.6)
-
(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00[2]
00x0 xx00
(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0)
FF[2]
1111 1111
(P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0)
00[2]
0000 0000
03[2]
xxxx xx11
P2M1
P2M2
Port 2 output mode 1
Port 2 output mode 2
A4H
A5H
P3M1
Port 3 output mode 1
B1H
-
-
-
-
-
-
(P3M1.1) (P3M1.0)
P3M2
Port 3 output mode 2
B2H
-
-
-
-
-
-
(P3M2.1) (P3M2.0) 00[2]
xxxx xx00
PCON
Power control register
87H
SMOD1
SMOD0
BOPD
BOI
GF1
GF0
PMOD1
0000 0000
PMOD0
00
P89LPC932A1
P0M1
B0H
87
T1/KB7
8-bit microcontroller with accelerated two-clock 80C51 core
Rev. 03 — 12 March 2007
OCRBH
Bit address
NXP Semiconductors
P89LPC932A1_3
Product data sheet
Table 3.
Special function registers …continued
* indicates SFRs that are bit addressable.
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Name
PCONA
Description
SFR Bit functions and addresses
addr.
MSB
Power control register A
B5H
Bit address
Reset value
LSB
Hex
Binary
00[2]
0000 0000
RTCPD
DEEPD
VCPD
-
I2PD
SPPD
SPD
CCUPD
D7
D6
D5
D4
D3
D2
D1
D0
F0
RS1
RS0
OV
F1
P
00
0000 0000
-
00
xx00 000x
PSW*
Program status word
D0H
CY
AC
PT0AD
Port 0 digital input disable
F6H
-
-
RSTSRC
Reset source register
DFH
-
-
BOF
POF
R_BK
R_WD
R_SF
R_EX
RTCCON
Real-time clock control
D1H
RTCF
RTCS1
RTCS0
-
-
-
ERTC
RTCEN
RTCH
Real-time clock register high
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
[3]
60[2][4]
011x xx00
D2H
00[4]
0000 0000
D3H
00[4]
0000 0000
SADDR
Serial port address register
A9H
00
0000 0000
SADEN
Serial port address enable
B9H
00
0000 0000
SBUF
Serial Port data buffer
register
99H
xx
xxxx xxxx
9F
9E
9D
9C
9B
9A
99
98
SCON*
Serial port control
98H
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
00
0000 0000
SSTAT
Serial port extended status
register
BAH
DBMOD
INTLO
CIDIS
DBISEL
FE
BR
OE
STINT
00
0000 0000
SP
Stack pointer
81H
07
0000 0111
SPCTL
SPI control register
E2H
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
04
0000 0100
SPSTAT
SPI status register
E1H
SPIF
WCOL
-
-
-
-
-
-
00
00xx xxxx
SPDAT
SPI data register
E3H
00
0000 0000
TAMOD
Timer 0 and 1 auxiliary mode
00
xxx0 xxx0
00
0000 0000
TMOD21 TMOD20 00
0000 0000
PLLDV.1
8FH
Bit address
-
-
-
T1M2
-
-
-
T0M2
8F
8E
8D
8C
8B
8A
89
88
IE0
IT0
15 of 64
© NXP B.V. 2007. All rights reserved.
TCON*
Timer 0 and 1 control
88H
TF1
TR1
TF0
TR0
IE1
IT1
TCR20*
CCU control register 0
C8H
PLEEN
HLTRN
HLTEN
ALTCD
ALTAB
TDIR2
TCR21
CCU control register 1
F9H
TCOU2
-
-
-
PLLDV.3
PLLDV.2
PLLDV.0 00
0xxx 0000
TH0
Timer 0 high
8CH
00
0000 0000
TH1
Timer 1 high
8DH
00
0000 0000
TH2
CCU timer high
CDH
00
0000 0000
TICR2
CCU interrupt control register
C9H
TOIE2
TOCIE2D TOCIE2C TOCIE2B TOCIE2A
-
TICIE2B
TICIE2A 00
0000 0x00
TIFR2
CCU interrupt flag register
E9H
TOIF2
TOCF2D
-
TICF2B
TICF2A
0000 0x00
TOCF2C
TOCF2B
TOCF2A
00
P89LPC932A1
Real-time clock register low
8-bit microcontroller with accelerated two-clock 80C51 core
Rev. 03 — 12 March 2007
RTCL
Bit address
NXP Semiconductors
P89LPC932A1_3
Product data sheet
Table 3.
Special function registers …continued
* indicates SFRs that are bit addressable.
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Name
Description
SFR Bit functions and addresses
addr.
MSB
TISE2
CCU interrupt status encode
register
DEH
TL0
Timer 0 low
TL1
-
-
-
Reset value
LSB
-
-
ENCINT.
2
ENCINT.
1
Hex
Binary
ENCINT. 00
0
xxxx x000
8AH
00
0000 0000
Timer 1 low
8BH
00
0000 0000
TL2
CCU timer low
CCH
TMOD
Timer 0 and 1 mode
89H
TOR2H
CCU reload register high
TOR2L
0000 0000
0000 0000
CFH
00
0000 0000
CCU reload register low
CEH
00
0000 0000
TPCR2H
Prescaler control register
high
CBH
TPCR2L
Prescaler control register low
CAH
TRIM
Internal oscillator trim register
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
[5] [4]
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[6] [4]
WDL
Watchdog load
C1H
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
-
T1C/T
-
T1M1
-
T1M0
-
T0GATE
-
T0C/T
-
T0M1
T0M0
TPCR2H. TPCR2H. 00
1
0
TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. TPCR2L. 00
7
6
5
4
3
2
1
0
FF
xxxx xx00
0000 0000
1111 1111
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2]
All ports are in input only (high-impedance) state after power-up.
[3]
The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[4]
The only reset source that affects these SFRs is power-on reset.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
16 of 64
© NXP B.V. 2007. All rights reserved.
P89LPC932A1
[1]
8-bit microcontroller with accelerated two-clock 80C51 core
Rev. 03 — 12 March 2007
00
00
T1GATE
NXP Semiconductors
P89LPC932A1_3
Product data sheet
Table 3.
Special function registers …continued
* indicates SFRs that are bit addressable.
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
7.2 Enhanced CPU
The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC932A1 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 7) and can also be optionally divided to a slower frequency (see
Section 7.8 “CCLK modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
7.3.2 CPU clock (OSCCLK)
The P89LPC932A1 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
7.3.6 Clock output
The P89LPC932A1 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the RTC is not using the crystal oscillator as its clock
source. This allows external devices to synchronize to the P89LPC932A1. This output is
enabled by the ENCLK bit in the TRIM register.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
17 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC932A1 has a 6-bit TRIM register that can be used to tune the frequency of
the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed
value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature.
End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to
other frequencies.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed, VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
XTAL1
XTAL2
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
RTC
OSCCLK
DIVM
CCLK
CPU
RCCLK
RC
OSCILLATOR
÷2
(7.3728 MHz ±1 %)
PCLK
WDT
WATCHDOG
OSCILLATOR
(400 kHz
+20%
)
−30 %
PCLK
TIMER 0 AND
TIMER 1
I2C-BUS
32 × PLL
SPI
UART
CCU
(P89LPC932A1)
002aaa891
Fig 7. Block diagram of oscillator control
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
18 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
7.7 CCLK wake-up delay
The P89LPC932A1 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 µs to 100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.
7.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC932A1 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
7.10 Memory organization
The various P89LPC932A1 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
• XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC932A1 has 512 bytes of on-chip
XDATA memory.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
19 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC932A1 has 8 kB of on-chip Code memory.
The P89LPC932A1 also has 512 bytes of on-chip Data EEPROM that is accessed via
SFRs (see Section 7.27 “Data EEPROM”).
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 4.
Table 4.
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
XDATA
Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
512
7.12 Interrupts
The P89LPC932A1 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the many interrupt sources. The P89LPC932A1 supports
15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port Tx, serial port
Rx, combined serial port Rx/Tx, brownout detect, watchdog/RTC, I2C-bus, keyboard,
comparators 1 and 2, SPI, CCU, and data EEPROM write completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC932A1 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
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In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC932A1 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes” for details.
IE0
EX0
IE1
EX1
BOF
EBO
RTCF
ERTC
(RTCCON.1)
WDOVF
wake-up
(if in power-down)
KBIF
EKBI
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
interrupt
to CPU
SI
EI2C
SPIF
ESPI
any CCU interrupt(1)
ECCU
EEIF
EIEE
002aaa892
(1) See Section 7.19 “CCU”
Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources
7.13 I/O ports
The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1 and 2
are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends
upon the clock and reset options chosen, as shown in Table 5.
Table 5.
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(28-pin package)
On-chip oscillator or watchdog oscillator
No external reset (except during power-up)
26
External RST pin supported
25
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Table 5.
Number of I/O pins available …continued
Clock source
Reset option
External clock input
No external reset (except during power-up)
External RST pin
Low/medium/high speed oscillator
(external crystal or resonator)
[1]
Number of I/O pins
(28-pin package)
supported[1]
25
24
No external reset (except during power-up)
24
External RST pin supported[1]
23
Required for operation above 12 MHz.
7.13.1 Port configurations
All but three I/O port pins on the P89LPC932A1 may be configured by software to one of
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
7.13.1.1
Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC932A1 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.2
Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.3
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
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7.13.1.4
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
trigger input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC932A1 incorporates two Analog Comparators. In order to give the best
analog function performance and to minimize power consumption, pins that are being
used for analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-only (high-impedance)
mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.13.3 Additional port features
After power-up, all pins are in Input-only mode. Please note that this is different from
the LPC76x series of devices.
• After power-up, all I/O pins except P1.5, may be configured by software.
• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or
open-drain.
Every output on the P89LPC932A1 has been designed to sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 8 “Static characteristics” for detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC932A1 incorporates power monitoring functions designed to prevent
incorrect operation during initial power-up and power loss or reduction during operation.
This is accomplished with two hardware functions: Power-on detect and brownout detect.
7.14.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a brownout detection to cause a processor reset,
however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If brownout detection is the brownout condition occurs when VDD falls below the brownout
trip voltage, Vbo (see Table 8 “Static characteristics”), and is negated when VDD rises
above Vbo. If the P89LPC932A1 device is to operate with a power supply that can be
below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate
at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.
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For correct activation of brownout detect, the VDD rise and fall times must be observed.
Please see Table 8 “Static characteristics” for specifications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF flag in the RSTSRC register is set to indicate an
initial power-up condition. The POF flag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC932A1 supports three different power reduction modes. These modes are
Idle mode, Power-down mode, and Total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC932A1 exits Power-down mode via any reset, or certain interrupts. In Power-down
mode, the power supply voltage may be reduced to the data retention voltage VDDR. This
retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly
recommended to wake up the processor via reset in this case. VDD must be raised to
within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, Comparators (note that Comparators can be powered-down separately),
and RTC/System Timer. The internal RC oscillator is disabled unless both the RC
oscillator has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
7.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
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After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
•
•
•
•
•
•
External reset pin (during power-up or if user configured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC932A1 will fetch instructions from either address 0000H or
the Boot address. The Boot address is formed by using the Boot Vector as the high byte of
the address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC932A1 User manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC932A1 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
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7.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2
operation is the same for Timer 0 and Timer 1.
7.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
7.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
7.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
7.18 RTC/system timer
The P89LPC932A1 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered-down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded
again and the RTCF flag will be set. The clock source for this counter can be either the
CCLK or the XTAL oscillator, provided that the XTAL oscillator is not being used as the
CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the RTC and its associated SFRs to the
default state.
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7.19 CCU
This unit features:
• A 16-bit timer with 16-bit reload on overflow.
• Selectable clock, with prescaler to divide clock source by any integral number
between 1 and 1024.
•
•
•
•
Four Compare/PWM outputs with selectable polarity
Symmetrical/Asymmetrical PWM selection
Two Capture inputs with event counter and digital noise rejection filter
Seven interrupts with common interrupt vector (one Overflow, two Capture,
four Compare)
• Safe 16-bit read/write via shadow registers.
7.19.1 CCU clock
The CCU runs on the CCU Clock (CCUCLK), which is either PCLK in basic timer mode, or
the output of a Phase-Locked Loop (PLL). The PLL is designed to use a clock source
between 0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between
16 MHz and 32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a
4-bit divider to help divide PCLK into a frequency between 0.5 MHz and 1 MHz.
7.19.2 CCUCLK prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow.
7.19.3 Basic timer operation
The Timer is a free-running up/down counter with a direction control bit. If the timer
counting direction is changed while the counter is running, the count sequence will be
reversed. The timer can be written or read at any time.
When a reload occurs, the CCU Timer Overflow Interrupt Flag will be set, and an interrupt
generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.
7.19.4 Output compare
There are four output compare channels A, B, C and D. Each output compare channel
needs to be enabled in order to operate and the user will have to set the associated I/O
pin to the desired output mode to connect the pin. When the contents of the timer matches
that of a capture compare control register, the Timer Output Compare Interrupt Flag
(TOCFx) becomes set. An interrupt will occur if enabled.
7.19.5 Input capture
Input capture is always enabled. Each time a capture event occurs on one of the two input
capture pins, the contents of the timer is transferred to the corresponding 16-bit input
capture register. The capture event can be programmed to be either rising or falling edge
triggered. A simple noise filter can be enabled on the input capture by enabling the Input
Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of
the same value in order to recognize an edge as a capture event. An event counter can be
set to delay a capture by a number of capture events.
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7.19.6 PWM operation
PWM operation has two main modes, symmetrical and asymmetrical.
In asymmetrical PWM operation the CCU Timer operates in down-counting mode
regardless of the direction control bit.
In symmetrical mode, the timer counts up/down alternately. The main difference from
basic timer operation is the operation of the compare module, which in PWM mode is
used for PWM waveform generation.
As with basic timer operation, when the PWM (compare) pins are connected to the
compare logic, their logic state remains unchanged. However, since bit FCO is used to
hold the halt value, only a compare event can change the state of the pin.
TOR2
compare value
timer value
0x0000
non-inverted
inverted
002aaa893
Fig 9. Asymmetrical PWM, down-counting
TOR2
compare value
timer value
0
non-inverted
inverted
002aaa894
Fig 10. Symmetrical PWM
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7.19.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
TIMER VALUE
0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
002aaa895
Fig 11. Alternate output mode
7.19.8 PLL operation
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1.
PCLK
PLL frequency = -----------------(N + 1)
Where: N is the value of PLLDV[3:0].
(1)
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK⁄16.
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7.19.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
EA (IEN0.7)
ECCU (IEN1.4)
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
interrupt to
CPU
other
interrupt
sources
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
ENCINT.0
PRIORITY
ENCODER
ENCINT.1
ENCINT.2
002aaa896
Fig 12. Capture/compare unit interrupts
7.20 UART
The P89LPC932A1 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC932A1 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.20.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
7.20.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.20.5
“Baud rate generator and selection”).
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7.20.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.20.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 7.20.5 “Baud rate generator and selection”).
7.20.5 Baud rate generator and selection
The P89LPC932A1 enhanced UART has an independent Baud Rate Generator. The baud
rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 13). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
timer 1 overflow
(PCLK-based)
SMOD1 = 1
SBRGS = 0
÷2
baud rate modes 1 and 3
SMOD1 = 0
baud rate generator
(CCLK-based)
SBRGS = 1
002aaa897
Fig 13. Baud rate sources for UART (Modes 1, 3)
7.20.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
7.20.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
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7.20.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
7.20.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
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7.21 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves.
• Multi master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 14. The P89LPC932A1 device provides
a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
RP
RP
SDA
I2C-bus
SCL
P1.3/SDA
P1.2/SCL
P89LPC932A1
OTHER DEVICE
WITH I2C-BUS
INTERFACE
OTHER DEVICE
WITH I2C-BUS
INTERFACE
002aaa898
Fig 14. I2C-bus configuration
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8-bit microcontroller with accelerated two-clock 80C51 core
8
I2ADR
ADDRESS REGISTER
P1.3
COMPARATOR
INPUT
FILTER
P1.3/SDA
ACK
SHIFT REGISTER
OUTPUT
STAGE
I2DAT
BIT COUNTER /
ARBITRATION
AND SYNC LOGIC
INPUT
FILTER
P1.2/SCL
SERIAL CLOCK
GENERATOR
OUTPUT
STAGE
CCLK
TIMING
AND
CONTROL
LOGIC
interrupt
INTERNAL BUS
8
timer 1
overflow
P1.2
I2CON
I2SCLH
I2SCLL
CONTROL REGISTERS AND
SCL DUTY CYCLE REGISTERS
8
status bus
I2STAT
STATUS
DECODER
STATUS REGISTER
8
002aaa899
Fig 15. I2C-bus serial interface block diagram
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7.22 Serial Peripheral Interface (SPI)
The P89LPC932A1 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in
Master mode or up to 2 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
S
M
CPU clock
8-BIT SHIFT REGISTER
clock
MSTR
SPR0
SPICLK
P2.5
SS
P2.4
SPR0
SPR1
CPOL
CPHA
MSTR
SSIG
WCOL
DORD
MSTR
SPEN
SPI CONTROL
SPEN
SPR1
S
M
CLOCK LOGIC
MOSI
P2.2
SPEN
SPI clock (master)
SELECT
SPIF
PIN
CONTROL
LOGIC
READ DATA BUFFER
DIVIDER
BY 4, 16, 64, 128
MISO
P2.3
M
S
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI
interrupt
request
internal
data
bus
002aaa900
Fig 16. SPI block diagram
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
• SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 17 through Figure 19.
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8-bit microcontroller with accelerated two-clock 80C51 core
7.22.1 Typical SPI configurations
master
8-BIT SHIFT
REGISTER
slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
PORT
8-BIT SHIFT
REGISTER
SPICLK
SS
002aaa901
Fig 17. SPI single master single slave configuration
master
8-BIT SHIFT
REGISTER
slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
SS
8-BIT SHIFT
REGISTER
SPICLK
SS
SPI CLOCK
GENERATOR
002aaa902
Fig 18. SPI dual device configuration, where either can be a master or a slave
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8-bit microcontroller with accelerated two-clock 80C51 core
master
8-BIT SHIFT
REGISTER
slave
MISO
MISO
MOSI
MOSI
SPICLK
SPI CLOCK
GENERATOR
port
8-BIT SHIFT
REGISTER
SPICLK
SS
slave
MISO
MOSI
8-BIT SHIFT
REGISTER
SPICLK
port
SS
002aaa903
Fig 19. SPI single master multiple slaves configuration
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8-bit microcontroller with accelerated two-clock 80C51 core
7.23 Analog comparators
Two analog comparators are provided on the P89LPC932A1. Input and output options
allow use of the comparators in a number of different configurations. Comparator
operation is such that the output is a logic 1 (which may be read in a register and/or routed
to a pin) when the positive input (one of two selectable pins) is greater than the negative
input (selectable from a pin or an internal reference voltage). Otherwise the output is a
zero. Each comparator may be configured to cause an interrupt when the output value
changes.
The overall connections to both comparators are shown in Figure 20. The comparators
function to VDD = 2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt flag must be cleared
before the interrupt is enabled in order to prevent an immediate interrupt service.
CP1
OE1
comparator 1
(P0.4) CIN1A
(P0.3) CIN1B
CO1
CMP1 (P0.6)
(P0.5) CMPREF
change detect
Vref(bg)
CMF1
CN1
interrupt
change detect
EC
CP2
CMF2
comparator 2
(P0.2) CIN2A
(P0.1) CIN2B
CMP2 (P0.0)
CO2
OE2
CN2
002aaa904
Fig 20. Comparator input and output connections
7.23.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
VREF, is 1.23 V ± 10 %.
7.23.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is
set whenever the comparator output changes state. The flag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the flags to determine which comparator caused the interrupt.
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7.23.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
If a comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
Comparators consume power in Power-down and Idle modes, as well as in the normal
operating mode. This fact should be taken into account when system power consumption
is an issue. To minimize power consumption, the user can disable the comparators via
PCONA.5, or put the device in Total Power-down mode.
7.24 Keypad interrupt
The Keypad Interrupt function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can be
used for bus address recognition or keypad recognition. The user can configure the port
via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is
used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag
(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is
matched while the Keypad Interrupt function is active. An interrupt will be generated if
enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to
define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,
the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key
connected to Port 0 which is enabled by the KBMASK register will cause the hardware to
set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to
wake up the CPU from Idle or Power-down modes. This feature is particularly useful in
handheld, battery-powered systems that need to carefully manage power consumption
yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer
than six CCLKs.
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7.25 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt. Figure 21 shows the watchdog timer in Watchdog mode.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few µs to a few seconds. Please refer to the
P89LPC932A1 User manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
PCLK
÷32
8-BIT DOWN
COUNTER
PRESCALER
reset(1)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 21. Watchdog timer in Watchdog mode (WDTE = 1)
7.26 Additional features
7.26.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.26.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
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7.27 Data EEPROM
The P89LPC932A1 has 512 B of on-chip data EEPROM. The data EEPROM is SFR
based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can
read, write and fill the memory via SFRs and one interrupt. This data EEPROM provides
400000 minimum erase/program cycles for each byte.
• Byte mode: In this mode, data can be read and written one byte at a time.
• Row fill: In this mode, the addressed row (64 bytes) is filled with a single value. The
entire row can be erased by writing 00H.
• Sector fill: In this mode, all 512 bytes are filled with a single value. The entire sector
can be erased by writing 00H.
After the operation finishes, the hardware will set the EEIF bit, which if enabled will
generate an interrupt. The flag is cleared by software.
7.28 Flash program memory
7.28.1 General description
The P89LPC932A1 flash memory provides in-circuit electrical erasure and programming.
The flash can be erased, read, and written as bytes. The Sector and Page Erase functions
can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase
the entire program memory. ICP using standard commercial programmers is available. In
addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.
On-chip erase and write timing generation contribute to a user-friendly programming
interface. The P89LPC932A1 flash reliably stores memory contents even after
400000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC932A1 uses VDD as the supply voltage to
perform the Program/Erase algorithms.
7.28.2 Features
•
•
•
•
•
Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP.
Internal fixed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
• Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
•
•
•
•
•
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
400000 typical erase/program cycles for each byte.
20 year minimum data retention.
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7.28.3 Flash organization
The program memory consists of eight 1 kB sectors on the P89LPC932A1 device. Each
sector can be further divided into 64-byte pages. In addition to sector erase, page erase,
and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of
a given page to be programmed at the same time, substantially reducing overall
programming time.
7.28.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
7.28.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may
be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock - serial data interface. As shipped from
the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing
for the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
7.28.6 In-circuit programming
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC932A1 through a two-wire serial interface. The ICP facility has made ICP in an
embedded application—using commercially available programmers—possible with a
minimum of additional expense in components and circuit board area. The ICP function
uses five pins. Only a small connector needs to be available to interface your application
to a commercial programmer in order to use this feature. Additional details may be found
in the P89LPC932A1 User manual.
7.28.7 In-application programming
IAP is performed in the application under the control of the microcontroller’s firmware. The
IAP facility consists of internal hardware resources to facilitate programming and erasing.
The IAP facility has made IAP in an embedded application possible without additional
components. Two methods are available to accomplish IAP. A set of predefined IAP
functions are provided in a Boot ROM and can be called through a common interface,
PGM_MTP. Several IAP calls are available for use by an application program to permit
selective erasing and programming of flash sectors, pages, security bits, configuration
bytes, and device ID. These functions are selected by setting up the microcontroller’s
registers before making a call to PGM_MTP at FF00H. The Boot ROM occupies the
program memory space at the top of the address space from FF00H to FEFFH, thereby
not conflicting with the user program memory space.
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In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC932A1 User manual.
7.28.8 In-system programming
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC932A1 through the serial port. This firmware
is provided by NXP and embedded within each P89LPC932A1 device. The ISP facility has
made ISP in an embedded application possible with a minimum of additional expense in
components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD,
and RST). Only a small connector needs to be available to interface your application to an
external circuit in order to use this feature.
7.28.9 Power-on reset code execution
The P89LPC932A1 contains two special flash elements: the Boot Vector and the Boot
Status Bit. Following reset, the P89LPC932A1 examines the contents of the Boot Status
Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which
is the normal start address of the user’s application code. When the Boot Status Bit is set
to a value other than zero, the contents of the Boot Vector are used as the high byte of the
execution address and the low byte is set to 00H.
Table 6 shows the factory default Boot Vector settings for these devices. Note: These
settings are different than the original P89LPC932. Tools designed to support the
P89LPC932A1 should be used to program this device, such as Flash Magic version
1.98, or later. A factory-provided boot loader is preprogrammed into the address space
indicated and uses the indicated boot loader entry point to perform ISP functions. This
code can be erased by the user. Users who wish to use this loader should take
precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead,
the page erase function can be used to erase the first eight 64-byte pages located in
this sector. A custom boot loader can be written with the Boot Vector set to the custom
boot loader, if desired.
Table 6.
Default Boot Vector values and ISP entry points
Device
Default
Boot Vector
Default
boot loader
entry point
Default boot loader 1 kB sector
code range
range
P89LPC932A1
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
7.28.10 Hardware activation of the boot loader
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC932A1 User manual for specific information). This
has the same effect as having a non-zero status byte. This allows an application to be built
that will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the
factory preprogrammed ISP boot loader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
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7.29 User configuration bytes
Some user-configurable features of the P89LPC932A1 must be defined at power-up and
therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1. Please see the P89LPC932A1 User
manual for additional details.
7.30 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC932A1 device. Each byte
corresponds to one sector. Please see the P89LPC932A1 User manual for additional
details.
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8. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Tamb(bias)
Min
Max
Unit
operating bias ambient temperature
−55
+125
°C
Tstg
storage temperature range
−65
+150
°C
IOH(I/O)
HIGH-level output current per I/O pin
-
20
mA
IOL(I/O)
LOW-level output current per I/O pin
-
20
mA
II/O(tot)(max)
maximum total I/O current
-
100
mA
Vn
voltage on any pin (except VSS)
with respect to VDD
-
+3.5
V
Ptot(pack)
total power dissipation per package
based on package heat
transfer, not device power
consumption
-
1.5
W
[1]
Conditions
The following applies to Table 7 “Limiting values”:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
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9. Static characteristics
Table 8.
Static characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
IDD(oper)
Parameter
operating supply current
Conditions
VDD = 3.6 V;
fosc = 12 MHz
[2]
Min
Typ[1]
Max
Unit
-
11
18
mA
14
23
mA
3.25
5
mA
5
7
mA
VDD = 3.6 V;
fosc = 18 MHz
IDD(idle)
Idle mode supply current
VDD = 3.6 V;
fosc = 12 MHz
[2]
-
VDD = 3.6 V;
fosc = 18 MHz
IDD(pd)
power supply current,
Power-down mode, voltage
comparators powered-down
VDD = 3.6 V
[2]
-
55
80
µA
IDD(tpd)
total Power-down mode supply
current
VDD = 3.6 V
[3]
-
0.5
5
µA
(dV/dt)r
rise rate
of VDD
-
-
2
mV/µs
(dV/dt)f
fall rate
of VDD
-
-
50
mV/µs
VDDR
data retention voltage
1.5
-
-
V
Vth(HL)
HIGH-LOW threshold voltage
except SCL, SDA
0.22VDD
0.4VDD
-
V
VIL
LOW-level input voltage
SCL, SDA only
−0.5
-
0.3VDD
V
Vth(LH)
LOW-HIGH threshold voltage
except SCL, SDA
-
0.6VDD
0.7VDD
V
VIH
HIGH-level input voltage
SCL, SDA only
0.7VDD
-
5.5
V
Vhys
hysteresis voltage
Port 1
-
0.2VDD
-
V
VOL
LOW-level output voltage
IOL = 20 mA;
VDD = 2.4 V to 3.6 V;
all ports, all modes
except high-Z
[4]
-
0.6
1.0
V
IOL = 3.2 mA;
VDD = 2.4 V to 3.6 V;
all ports, all modes
except high-Z
[4]
-
0.2
0.3
V
IOH = −20 µA;
VDD = 2.4 V to 3.6 V;
all ports,
quasi-bidirectional mode
VDD − 0.3
VDD − 0.2
-
V
IOH = −3.2 mA;
VDD = 2.4 V to 3.6 V;
all ports, push-pull mode
VDD − 0.7
VDD − 0.4
-
V
VOH
HIGH-level output voltage
−0.5
-
+4.0
V
[5]
−0.5
-
+5.5
V
input capacitance
[6]
-
-
15
pF
IIL
logical 0 input current
VI = 0.4 V
[7]
-
-
−80
µA
ILI
input leakage current
VI = VIL, VIH, or Vth(HL)
[8]
-
-
±1
µA
Vxtal
voltage on XTAL1, XTAL2 pins
with respect to VSS
Vn
voltage on any pin (except
XTAL1, XTAL2, VDD)
with respect to VSS
Ciss
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
46 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 8.
Static characteristics …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
Conditions
VI = 1.5 V at VDD = 3.6 V
[9]
Min
Typ[1]
Max
Unit
−30
-
−450
µA
10
-
30
kΩ
2.40
-
2.70
V
ITL
logical 1-to-0 transition current,
all ports
RRST(int)
internal pull-up resistance on pin
RST
Vbo
brownout trip voltage
Vref(bg)
band gap reference voltage
1.19
1.23
1.27
V
TCbg
band gap temperature
coefficient
-
10
20
ppm/ °C
2.4 V < VDD < 3.6 V; with
BOV = 1, BOPD = 0
[1]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2]
The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators,
real-time clock, and watchdog timer.
[3]
The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[4]
See Section 8 “Limiting values” on page 45 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition,
VOL/VOH may exceed the related specification.
[5]
This specification can be applied to pins which have analog comparator input functions when the pin is not being used for those analog
functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to
VSS.
[6]
Pin capacitance is characterized but not tested.
[7]
Measured with port in quasi-bidirectional mode.
[8]
Measured with port in high-impedance mode.
[9]
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VI is approximately 2 V.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
47 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
10. Dynamic characteristics
Table 9.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
Parameter
fOSC(RC)
internal RC oscillator frequency
fOSC(WD)
internal watchdog oscillator
frequency
fosc
oscillator frequency
Tcy(CLK)
clock cycle time
fCLKLP
low power select clock frequency
Conditions
Variable clock
see Figure 23
fosc = 12 MHz
Min
Max
Min
7.189
7.557
7.189
280
480
280
Unit
Max
7.557 MHz
480
kHz
0
12
-
-
MHz
83
-
-
-
ns
0
8
-
-
MHz
Glitch filter
tgr
tsa
glitch rejection
signal acceptance
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
-
ns
External clock
tCHCX
clock HIGH time
see Figure 23
33
Tcy(CLK) − tCLCX
33
tCLCX
clock LOW time
see Figure 23
33
Tcy(CLK) − tCHCX
33
-
ns
tCLCH
clock rise time
see Figure 23
-
8
-
8
ns
tCHCL
clock fall time
see Figure 23
-
8
-
8
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
see Figure 22
16Tcy(CLK)
-
1333
-
ns
tQVXH
output data set-up to clock rising see Figure 22
edge time
13Tcy(CLK)
-
1083
-
ns
tXHQX
output data hold after clock rising see Figure 22
edge time
-
Tcy(CLK) + 20
-
103
ns
tXHDX
input data hold after clock rising
edge time
see Figure 22
-
0
-
0
ns
tXHDV
input data valid to clock rising
edge time
see Figure 22
150
-
150
-
ns
0
CCLK⁄6
0
2.0
MHz
-
CCLK⁄4
-
3.0
MHz
6⁄CCLK
-
500
-
ns
4⁄CCLK
-
333
-
ns
250
-
250
-
ns
SPI interface
fSPI
SPI operating frequency
slave
master
TSPICYC
SPI cycle time
slave
see Figure 24, 25,
26, 27
master
tSPILEAD
SPI enable lead time
see Figure 26, 27
2.0 MHz (slave)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
48 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 9.
Dynamic characteristics (12 MHz) …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
tSPILAG
Parameter
SPI enable lag time
Conditions
Variable clock
SPICLK HIGH time
master
Max
Min
Max
250
-
250
-
ns
2⁄CCLK
-
165
-
ns
3⁄CCLK
-
250
-
ns
2⁄CCLK
-
165
-
ns
3⁄CCLK
-
250
-
ns
see Figure 26, 27
see Figure 24, 25,
26, 27
slave
tSPICLKL
SPICLK LOW time
master
Unit
Min
2.0 MHz (slave)
tSPICLKH
fosc = 12 MHz
see Figure 24, 25,
26, 27
slave
tSPIDSU
SPI data set-up time (master or
slave)
see Figure 24, 25,
26, 27
100
-
100
-
ns
tSPIDH
SPI data hold time (master or
slave)
see Figure 24, 25,
26, 27
100
-
100
-
ns
tSPIA
SPI access time (slave)
see Figure 26, 27
0
120
0
120
ns
tSPIDIS
SPI disable time (slave)
see Figure 26, 27
0
240
-
240
ns
tSPIDV
SPI enable to output data valid
time
see Figure 24, 25,
26, 27
2.0 MHz
-
240
-
240
ns
3.0 MHz
-
167
-
167
ns
0
-
0
-
ns
-
100
-
100
ns
-
2000
-
2000
ns
-
100
-
100
ns
-
2000
-
2000
ns
tSPIOH
SPI output data hold time
see Figure 24, 25,
26, 27
tSPIR
SPI rise time
see Figure 24, 25,
26, 27
SPI outputs
(SPICLK, MOSI, MISO)
SPI inputs
(SPICLK, MOSI, MISO, SS)
tSPIF
SPI fall time
SPI outputs
(SPICLK, MOSI, MISO)
see Figure 24, 25,
26, 27
SPI inputs
(SPICLK, MOSI, MISO, SS)
[1]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
49 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 10. Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
Parameter
fOSC(RC)
internal RC oscillator frequency
fOSC(WD)
internal watchdog oscillator
frequency
fosc
oscillator frequency
Tcy(CLK)
clock cycle time
fCLKLP
low power select clock frequency
Conditions
Variable clock
fosc = 18 MHz
Unit
Min
Max
Min
7.189
7.557
7.189
280
480
280
480
kHz
0
18
-
-
MHz
55
-
-
-
ns
0
8
-
-
MHz
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
see Figure 23
Max
7.557 MHz
Glitch filter
tgr
tsa
glitch rejection
signal acceptance
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
see Figure 23
22
Tcy(CLK) − tCLCX
22
-
ns
tCLCX
clock LOW time
see Figure 23
22
Tcy(CLK) − tCHCX
22
-
ns
tCLCH
clock rise time
see Figure 23
-
5
-
5
ns
tCHCL
clock fall time
see Figure 23
-
5
-
5
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
see Figure 22
16Tcy(CLK)
-
888
-
ns
tQVXH
output data set-up to clock rising
edge time
see Figure 22
13Tcy(CLK)
-
722
-
ns
tXHQX
output data hold after clock rising
edge time
see Figure 22
-
Tcy(CLK) + 20
-
75
ns
tXHDX
input data hold after clock rising
edge time
see Figure 22
-
0
-
0
ns
tXHDV
input data valid to clock rising
edge time
see Figure 22
150
-
150
-
ns
slave
0
CCLK⁄6
0
3.0
MHz
master
-
CCLK⁄4
-
4.5
MHz
6⁄CCLK
-
333
-
ns
4⁄CCLK
-
222
-
ns
250
-
250
-
ns
250
-
250
-
ns
SPI interface
fSPI
TSPICYC
SPI operating frequency
SPI cycle time
slave
see Figure 24,
25, 26, 27
master
tSPILEAD
SPI enable lead time
see Figure 26, 27
2.0 MHz (slave)
tSPILAG
SPI enable lag time
see Figure 26, 27
2.0 MHz (slave)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
50 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
Table 10. Dynamic characteristics (18 MHz) …continued
VDD = 3.0 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol
tSPICLKH
Parameter
SPICLK HIGH time
master
Conditions
see Figure 24,
25, 26, 27
slave
tSPICLKL
SPICLK LOW time
master
see Figure 24,
25, 26, 27
slave
Variable clock
fosc = 18 MHz
Unit
Min
Max
Min
Max
2⁄CCLK
-
111
-
ns
3⁄CCLK
-
167
-
ns
2⁄CCLK
-
111
-
ns
3⁄CCLK
-
167
-
ns
tSPIDSU
SPI data set-up time (master or
slave)
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIDH
SPI data hold time (master or
slave)
see Figure 24,
25, 26, 27
100
-
100
-
ns
tSPIA
SPI access time (slave)
see Figure 26, 27
0
80
0
80
ns
tSPIDIS
SPI disable time (slave)
see Figure 26, 27
0
160
-
160
ns
tSPIDV
SPI enable to output data valid
time
see Figure 24,
25, 26, 27
2.0 MHz
-
160
-
160
ns
3.0 MHz
-
111
-
111
ns
0
-
0
-
ns
-
100
-
100
ns
-
2000
-
2000
ns
-
100
-
100
ns
-
2000
-
2000
ns
tSPIOH
SPI output data hold time
see Figure 24,
25, 26, 27
tSPIR
SPI rise time
see Figure 24,
25, 26, 27
SPI outputs
(SPICLK, MOSI, MISO)
SPI inputs
(SPICLK, MOSI, MISO, SS)
tSPIF
SPI fall time
SPI outputs
(SPICLK, MOSI, MISO)
see Figure 24,
25, 26, 27
SPI inputs
(SPICLK, MOSI, MISO, SS)
[1]
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
[2]
Parameters are valid over operating temperature range unless otherwise specified.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
51 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
10.1 Waveforms
TXLXL
clock
tXHQX
tQVXH
output data
0
write to SBUF
input data
1
2
3
4
5
6
7
tXHDX
set TI
tXHDV
valid
valid
valid
valid
valid
valid
valid
valid
clear RI
set RI
002aaa906
Fig 22. Shift register mode timing
VDD − 0.5 V
0.45 V
0.2VDD + 0.9 V
0.2VDD − 0.1 V
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 23. External clock timing
SS
TSPICYC
tSPIF
tSPICLKH
tSPICLKL
tSPIR
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
tSPIDV
MOSI
(output)
LSB/MSB in
MSB/LSB in
tSPIOH
tSPIDV
tSPIR
tSPIF
master MSB/LSB out
master LSB/MSB out
002aaa908
Fig 24. SPI master timing (CPHA = 0)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
52 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
SS
TSPICYC
tSPIF
tSPICLKL
tSPIR
tSPICLKH
SPICLK
(CPOL = 0)
(output)
tSPIF
tSPICLKL
tSPICLKH
SPICLK
(CPOL = 1)
(output)
tSPIDSU
MISO
(input)
tSPIDH
LSB/MSB in
MSB/LSB in
tSPIDV
MOSI
(output)
tSPIR
tSPIOH
tSPIDV
tSPIDV
tSPIF
tSPIR
master MSB/LSB out
master LSB/MSB out
002aaa909
Fig 25. SPI master timing (CPHA = 1)
SS
tSPIR
tSPIR
TSPICYC
tSPILEAD
tSPIF
tSPICLKH
tSPICLKL
tSPIR
tSPILAG
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPICLKL
tSPICLKH
SPICLK
(CPOL = 1)
(input)
tSPIA
MISO
(output)
tSPIOH
tSPIOH
tSPIDV
tSPIDV
tSPIOH
slave MSB/LSB out
tSPIDSU
MOSI
(input)
tSPIR
tSPIDH
slave LSB/MSB out
tSPIDSU
tSPIDSU
MSB/LSB in
tSPIDIS
not defined
tSPIDH
LSB/MSB in
002aaa910
Fig 26. SPI slave timing (CPHA = 0)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
53 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
SS
tSPIR
tSPILEAD
tSPIR
TSPICYC
tSPIF
tSPICLKL
tSPIR
tSPILAG
tSPICLKH
SPICLK
(CPOL = 0)
(input)
tSPIF
tSPIR
tSPICLKL
SPICLK
(CPOL = 1)
(input)
tSPICLKH
tSPIOH
tSPIOH
tSPIDV
tSPIDV
tSPIOH
tSPIDV
tSPIDIS
tSPIA
MISO
(output)
not defined
slave LSB/MSB out
slave MSB/LSB out
tSPIDSU
MOSI
(input)
tSPIDH
tSPIDSU
tSPIDSU
MSB/LSB in
tSPIDH
LSB/MSB in
002aaa911
Fig 27. SPI slave timing (CPHA = 1)
10.2 ISP entry mode
Table 11. Dynamic characteristics, ISP entry mode
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
tVR
tRH
tRL
Conditions
Min
Typ
Max
Unit
VDD active to RST active delay time
50
-
-
µs
RST HIGH time
1
-
32
µs
RST LOW time
1
-
-
µs
VDD
tVR
tRH
RST
tRL
002aaa912
Fig 28. ISP entry waveform
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
54 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
11. Other characteristics
11.1 Comparator electrical characteristics
Table 12. Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
VIO
input offset voltage
VIC
common-mode input voltage
CMRR
common-mode rejection ratio
Conditions
[1]
Min
Typ
Max
Unit
-
-
±10
mV
0
-
VDD − 0.3
V
-
-
−50
dB
tres(tot)
total response time
-
250
500
ns
t(CE-OV)
chip enable to output valid time
-
-
10
µs
ILI
input leakage current
-
-
±10
µA
[1]
0 V < VI < VDD
This parameter is characterized, but not tested in production.
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
55 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
12. Package outline
PLCC28: plastic leaded chip carrier; 28 leads
SOT261-2
eD
y
eE
X
A
19
25
b1
ZE
18
26
bp
w M
28
1
E
HE
pin 1 index
e
A
A4 A1
12
4
β
(A 3)
k
5
11
Lp
v M A
ZD
e
D
detail X
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
b1 D(1) E(1)
bp
A3
eD
eE
e
HD
UNIT A
max.
min.
4.57
4.19
mm
inches
0.51
0.180
0.02
0.165
0.53
0.33
0.81
0.66
HE
k
10.92 10.92 12.57 12.57 1.22
11.58 11.58
1.27
9.91 9.91 12.32 12.32 1.07
11.43 11.43
0.25
3.05
0.01
0.021 0.032 0.456 0.456
0.05
0.12
0.013 0.026 0.450 0.450
0.43
0.39
0.43
0.39
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.495 0.495 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.485 0.485 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT261-2
112E08
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-15
Fig 29. Package outline SOT261-2 (PLCC28)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
56 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
D
SOT361-1
E
A
X
c
HE
y
v M A
Z
15
28
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
1
L
14
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
9.8
9.6
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.8
0.5
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT361-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 30. Package outline SOT361-1 (TSSOP28)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
57 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
HVQFN28: plastic thermal enhanced very thin quad flat package; no leads;
28 terminals; body 6 x 6 x 0.85 mm
B
D
SOT788-1
A
terminal 1
index area
A
E
A1
c
detail X
C
e1
e
14
y
y1 C
v M C A B
w M C
b
8
L
7
15
e
e2
Eh
21
1
terminal 1
index area
28
22
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.35
0.25
0.2
6.1
5.9
4.25
3.95
6.1
5.9
4.25
3.95
0.65
3.9
3.9
0.75
0.50
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT788-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-22
Fig 31. Package outline SOT788-1 (HVQFN28)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
58 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
seating plane
DIP28: plastic dual in-line package; 28 leads (600 mil)
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4
1.7
1.3
0.53
0.38
0.32
0.23
36
35
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.2
0.02
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.1
0.6
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT117-1
051G05
MO-015
SC-510-28
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 32. Package outline SOT117-1 (DIP28)
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
59 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
13. Abbreviations
Table 13.
Acronym list
Acronym
Description
CCU
Capture/Compare Unit
CPU
Central Processing Unit
CRC
Cyclic Redundancy Check
EPROM
Erasable Programmable Read-Only Memory
EEPROM
Electrically Erasable Programmable Read-Only Memory
EMI
ElectroMagnetic Interference
LED
Light Emitting Diode
PLL
Phase-Locked Loop
PWM
Pulse Width Modulator
RAM
Random Access Memory
RC
Resistance-Capacitance
RTC
Real-Time Clock
SFR
Special Function Register
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
60 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
P89LPC932A1_3
20070312
Product data sheet
-
P89LPC932A1_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Added new part type P89LPC932A1FN.
P89LPC932A1_2
20050510
Product data sheet
-
P89LPC932A1_1
P89LPC932A1_1
20040720
Product data sheet
-
-
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
61 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
62 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
17. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
2.3
Comparison to the P89LPC932 . . . . . . . . . . . . 2
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7
Functional description . . . . . . . . . . . . . . . . . . 11
7.1
Special function registers . . . . . . . . . . . . . . . . 11
7.2
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3.1
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 17
7.3.2
CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 17
7.3.3
Low speed oscillator option . . . . . . . . . . . . . . 17
7.3.4
Medium speed oscillator option . . . . . . . . . . . 17
7.3.5
High speed oscillator option . . . . . . . . . . . . . . 17
7.3.6
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4
On-chip RC oscillator option . . . . . . . . . . . . . . 18
7.5
Watchdog oscillator option . . . . . . . . . . . . . . . 18
7.6
External clock input option . . . . . . . . . . . . . . . 18
7.7
CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 19
7.8
CCLK modification: DIVM register . . . . . . . . . 19
7.9
Low power select . . . . . . . . . . . . . . . . . . . . . . 19
7.10
Memory organization . . . . . . . . . . . . . . . . . . . 19
7.11
Data RAM arrangement . . . . . . . . . . . . . . . . . 20
7.12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.12.1
External interrupt inputs . . . . . . . . . . . . . . . . . 20
7.13
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.13.1
Port configurations . . . . . . . . . . . . . . . . . . . . . 22
7.13.1.1 Quasi-bidirectional output configuration . . . . . 22
7.13.1.2 Open-drain output configuration . . . . . . . . . . . 22
7.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 22
7.13.1.4 Push-pull output configuration . . . . . . . . . . . . 23
7.13.2
Port 0 analog functions . . . . . . . . . . . . . . . . . . 23
7.13.3
Additional port features. . . . . . . . . . . . . . . . . . 23
7.14
Power monitoring functions. . . . . . . . . . . . . . . 23
7.14.1
Brownout detection . . . . . . . . . . . . . . . . . . . . . 23
7.14.2
Power-on detection . . . . . . . . . . . . . . . . . . . . . 24
7.15
Power reduction modes . . . . . . . . . . . . . . . . . 24
7.15.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.15.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . 24
7.15.3
Total Power-down mode . . . . . . . . . . . . . . . . . 24
7.16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.16.1
7.17
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5
7.17.6
7.18
7.19
7.19.1
7.19.2
7.19.3
7.19.4
7.19.5
7.19.6
7.19.7
7.19.8
7.19.9
7.20
7.20.1
7.20.2
7.20.3
7.20.4
7.20.5
7.20.6
7.20.7
7.20.8
7.20.9
7.20.10
7.21
7.22
7.22.1
7.23
7.23.1
7.23.2
7.23.3
7.24
7.25
7.26
7.26.1
7.26.2
7.27
7.28
7.28.1
7.28.2
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers/counters 0 and 1 . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer overflow toggle output . . . . . . . . . . . . .
RTC/system timer. . . . . . . . . . . . . . . . . . . . . .
CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU clock . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCUCLK prescaling . . . . . . . . . . . . . . . . . . . .
Basic timer operation . . . . . . . . . . . . . . . . . . .
Output compare . . . . . . . . . . . . . . . . . . . . . . .
Input capture . . . . . . . . . . . . . . . . . . . . . . . . .
PWM operation . . . . . . . . . . . . . . . . . . . . . . .
Alternating output mode . . . . . . . . . . . . . . . . .
PLL operation. . . . . . . . . . . . . . . . . . . . . . . . .
CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . .
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud rate generator and selection . . . . . . . . .
Framing error . . . . . . . . . . . . . . . . . . . . . . . . .
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . .
Double buffering . . . . . . . . . . . . . . . . . . . . . . .
Transmit interrupts with double buffering
enabled (modes 1, 2 and 3) . . . . . . . . . . . . . .
The 9th bit (bit 8) in double buffering
(modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . .
I2C-bus serial interface. . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI). . . . . . . . . . .
Typical SPI configurations . . . . . . . . . . . . . . .
Analog comparators . . . . . . . . . . . . . . . . . . . .
Internal reference voltage. . . . . . . . . . . . . . . .
Comparator interrupt . . . . . . . . . . . . . . . . . . .
Comparators and power reduction modes . . .
Keypad interrupt . . . . . . . . . . . . . . . . . . . . . . .
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . .
Additional features . . . . . . . . . . . . . . . . . . . . .
Software reset . . . . . . . . . . . . . . . . . . . . . . . .
Dual data pointers . . . . . . . . . . . . . . . . . . . . .
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . .
Flash program memory . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
26
26
26
26
26
27
27
27
27
27
27
28
29
29
30
30
30
30
31
31
31
31
31
32
32
32
33
35
36
38
38
38
39
39
40
40
40
40
41
41
41
41
continued >>
P89LPC932A1_3
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 03 — 12 March 2007
63 of 64
P89LPC932A1
NXP Semiconductors
8-bit microcontroller with accelerated two-clock 80C51 core
7.28.3
7.28.4
7.28.5
7.28.6
7.28.7
7.28.8
7.28.9
7.28.10
7.29
7.30
8
9
10
10.1
10.2
11
11.1
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Flash organization . . . . . . . . . . . . . . . . . . . . .
Using flash as data storage . . . . . . . . . . . . . .
Flash programming and erasing . . . . . . . . . . .
In-circuit programming . . . . . . . . . . . . . . . . . .
In-application programming . . . . . . . . . . . . . .
In-system programming . . . . . . . . . . . . . . . . .
Power-on reset code execution. . . . . . . . . . . .
Hardware activation of the boot loader . . . . . .
User configuration bytes . . . . . . . . . . . . . . . . .
User sector security bytes . . . . . . . . . . . . . . .
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics. . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . .
Other characteristics . . . . . . . . . . . . . . . . . . . .
Comparator electrical characteristics . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
42
42
42
43
43
43
44
44
45
46
48
52
54
55
55
56
60
61
62
62
62
62
62
62
63
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 March 2007
Document identifier: P89LPC932A1_3