INTEGRATED CIRCUITS DATA SHEET TDA4665 Baseband delay line Product specification Supersedes data of 1995 Oct 30 File under Integrated Circuits, IC02 1996 Dec 17 Philips Semiconductors Product specification Baseband delay line TDA4665 FEATURES GENERAL DESCRIPTION • Two comb filters, using the switched-capacitor technique, for one line delay time (64 µs) The TDA4665 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders with colour-difference signal outputs ±(R−Y) and ±(B−Y). • Adjustment-free application • No crosstalk between SECAM colour carriers (diaphoty) • Handles negative or positive colour-difference input signals • Clamping of AC-coupled input signals (±(R−Y) and ±(B−Y)) • VCO without external components • 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 µs line) • Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal • Addition of delayed and non-delayed output signals • Output buffer amplifiers • Comb filtering functions for NTSC colour-difference signals to suppress cross-colour. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP1 analog supply voltage (pin 9) 4.5 5 6 V VP2 digital supply voltage (pin 1) 4.5 5 6 V IP(tot) total supply current − 5.5 7.0 mA Vi(p-p) ±(R−Y) input signal PAL/NTSC (peak-to-peak value; pin 16) − 525 − mV ±(B−Y) input signal PAL/NTSC (peak-to-peak value; pin 14) − 665 − mV ±(R−Y) input signal SECAM (peak-to-peak value; pin 16) − 1.05 − V ±(B−Y) input signal SECAM (peak-to-peak value; pin 14) − 1.33 − V V11 / V16 for PAL and NTSC 5.3 5.8 6.3 dB V12 / V14 for PAL and NTSC 5.3 5.8 6.3 dB V11 / V16 for SECAM −0.6 −0.1 +0.4 dB V12 / V14 for SECAM −0.6 −0.1 +0.4 dB Gv gain Vo / Vi of colour-difference output signals ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA4665 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 TDA4665T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1996 Dec 17 2 1996 Dec 17 3 VP1 sandcastle pulse input ±(B−Y) colour-difference input signals ±(R−Y) handbook, full pagewidth 5 9 14 16 GND1 10 SANDCASTLE DETECTOR analog supply SIGNAL CLAMPING SIGNAL CLAMPING 1 VP2 digital supply LP DIVIDER BY 192 LINE MEMORY 6 MHz CCO 3 MHz shifting clock SAMPLEAND-HOLD SAMPLEAND-HOLD 11 GND2 3 TDA4665 4, 8 7 2 6 13 15 12 addition output stages buffers DIVIDER BY 2 LP LP MED848 i.c. n.c. n.c. n.c. n.c. ±(B−Y) colour-difference output signals ±(R−Y) Baseband delay line Fig.1 Block diagram. FREQUENCY PHASE DETECTOR pre-amplifiers LINE MEMORY Philips Semiconductors Product specification TDA4665 BLOCK DIAGRAM Philips Semiconductors Product specification Baseband delay line TDA4665 PINNING SYMBOL PIN DESCRIPTION VP2 1 +5 V supply voltage for digital part n.c. 2 not connected GND2 3 ground for digital part (0 V) i.c. 4 internally connected SAND 5 sandcastle pulse input n.c. 6 not connected i.c. 7 internally connected SAND 5 12 Vo(B−Y) i.c. 8 internally connected n.c. 6 11 Vo(R−Y) VP1 9 +5 V supply voltage for analog part i.c. 7 GND1 10 ground for analog part (0 V) i.c. 8 Vo(R−Y) 11 ±(R−Y) output signal Vo(B−Y) 12 ±(B−Y) output signal n.c. 13 not connected Vi(B−Y) 14 ±(B−Y) input signal n.c. 15 not connected Vi(R−Y) 16 ±(R−Y) input signal handbook, halfpage VP2 1 16 Vi(R−Y) n.c. 2 15 n.c. GND2 3 14 Vi(B−Y) i.c. 4 13 n.c. TDA4665 10 GND1 9 VP1 MED849 Fig.2 Pin configuration. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together. SYMBOL PARAMETER MIN. MAX. UNIT VP1 analog supply voltage (pin 9) −0.5 +7 V VP2 digital supply voltage (pin 1) −0.5 +7 V V5 voltage on pin 5 −0.5 VP + 1.0 V Vn voltage on pins 11, 12, 14 and 16 −0.5 VP V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 70 °C VESD electrostatic handling for all pins; note 1 − ±500 V Note 1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Dec 17 PARAMETER VALUE UNIT SOT38-4 75 K/W SOT109-1 220 K/W thermal resistance from junction to ambient in free air 4 Philips Semiconductors Product specification Baseband delay line TDA4665 CHARACTERISTICS VP = 5.0 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz; Tamb = 25 °C; measurements taken in Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP1 analog supply voltage (pin 9) 4.5 5 6 V VP2 digital supply voltage (pin 1) 4.5 5 6 V IP1 analog supply current − 4.8 6.0 mA IP2 digital supply current − 0.7 1.0 mA ±(R−Y) PAL and NTSC (pin 16) − 525 − mV ±(B−Y) PAL and NTSC (pin 14) − 665 − mV ±(R−Y) SECAM (pin 16) − 1.05 − V ±(B−Y) SECAM (pin 14) − 1.33 − V 1 − − V Colour-difference input signals Vi(p-p) Vi(max)(p-p) input signal (peak-to-peak value) note 1 maximum symmetrical input signal (peak-to-peak value) ±(R−Y) or ±(B−Y) for PAL and NTSC before clipping ±(R−Y) or ±(B−Y) for SECAM before clipping R14, 16 input resistance during clamping C14, 16 input capacitance V14, 16 input clamping voltage 2 − − V − − 40 kΩ − − 10 pF proportional to VP 1.3 1.5 1.7 V ±(R−Y) on pin 11 all standards − 1.05 − V ±(B−Y) on pin 12 all standards − 1.33 − V 0 +0.4 dB Colour-difference output signals Vo(p-p) output signal (peak-to-peak value) V11/V12 ratio of output amplitudes at equal input signals Vi(14,16)(p-p) = 1.33 V −0.4 proportional to VP 2.5 2.9 3.3 V − 330 400 Ω V11, 12 DC output voltage R11, 12 output resistance Gv gain for PAL and NTSC ratio Vo/Vi 5.3 5.8 6.3 dB gain for SECAM ratio Vo/Vi −0.6 −0.1 +0.4 dB Vn/Vn+1 ratio of delayed to non-delayed output signals (pins 11 and 12) Vi(14,16)(p-p) = 1.33 V; SECAM signals −0.1 0 +0.1 dB Vn(rms) noise voltage (RMS value; pins 11 and 12) Vi(14,16) = 0 V; note 2 − − 1.2 mV meander − − 5 mV spikes − − 10 mV − 54 − dB 63.94 64 64.06 µs V(11,12)(p-p) unwanted signals (line-locked) (peak-to-peak value) S/N(W) weighted signal-to-noise ratio (pins 11 and 12) ∆td time difference between non-delayed and delayed output signals (pins 11 and 12) 1996 Dec 17 Vi(14,16) = 0 V; active video; RS = 300 Ω Vo(p-p) = 1 V; note 2 5 Philips Semiconductors Product specification Baseband delay line SYMBOL TDA4665 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT td delay of non-delayed signals 40 60 80 ns ttr transient time of delayed signal on pins 11 300 ns transient of respectively 12 SECAM signal − 350 − ns transient time of non-delayed signal on pins 11 respectively 12 − 320 − ns 14.2 15.625 17.0 kHz 4.0 300 ns transient of SECAM signal Sandcastle pulse input (pin 5) fBK burst-key frequency/sandcastle frequency V5 top pulse voltage − VP + 1.0 V Vslice internal slicing level V5 − 1.0 − V5 − 0.5 V I5 input current − − 10 µA C5 input capacitance − − 10 pF note 3 Notes 1. For SECAM the signal must be blanked line-sequentially. The blanking level must be equal to the non-colour signal. For SECAM, PAL and NTSC the input signal must be equal to the non-colour signal during the internal clamping of TDA4665 (3 to 1 µs before the leading edge of the top pulse of V5). 2. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 Ω. 3. The leading edge of the burst-key pulse or top pulse is used for timing. 1996 Dec 17 6 1996 Dec 17 7 22 nF 28 27 26 25 15 14 23 22 nF 12 22 13 HUE off 11 17 PLL off 10 8 3.3 kΩ 6.8 kΩ 18 kΩ 7 X1 30 pF 5 X2 30 pF 10 nF 19 6 7.2 MHz 10 nF 21 8.8 MHz 27 pF 10 kΩ HUE control VP TDA4650 330 Ω 2 18 0.1 µF 47 nF 20 4 220 pF 3.3 kΩ 0.33 µF 24 3 1 220 pF Fig.3 Application circuit with TDA4650. 9 330 Ω coil: Toko 119LN-A3753 GO 10 kΩ 10 kΩ SSC (12V) Vi−(B−Y) 1 nF 1 nF Vi−(R−Y) colourdifference signals 5 14 16 22 µF 100 nF 10 (1) 10 Ω 11 560 Ω 3 15 13 2 6 7 8 4 12 5.1 V 100 nF (1) +5.1 V 1 10 Ω +5.1 V 9 LINE-LOCKED PLL / PULSE PROCESSING VCO ±(B−Y) comb filtering LINE DELAY LINE DELAY ±(R−Y) comb filtering TDA4665 MED850 +12 V n.c. n.c. n.c. n.c. i.c. Vo−(B−Y) Vo−(R−Y) Baseband delay line (1) Capacitors positioned close to pins 9 and 10, 1 and 3. colour standard switching signals NTSC-4.43 NTSC-3.58 PAL SECAM S-VHS (Y, C) CVBS 220 pF 10 nF 16 27 pF 120 pF 10 µH 680 Ω full pagewidth PAL/NTSC SECAM NTSC FILTERS chrominance signal 20 to 400 mV (p-p) Y 0.33 µF 10 nF VP = +12 V 470 Ω Philips Semiconductors Product specification TDA4665 APPLICATION INFORMATION Philips Semiconductors Product specification Baseband delay line TDA4665 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.030 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-14 SOT38-4 1996 Dec 17 EUROPEAN PROJECTION 8 Philips Semiconductors Product specification Baseband delay line TDA4665 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0098 0.39 0.014 0.0075 0.38 0.16 0.15 0.050 0.24 0.23 0.041 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.0098 0.057 0.0039 0.049 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1996 Dec 17 EIAJ EUROPEAN PROJECTION ISSUE DATE 91-08-13 95-01-23 9 o 8 0o Philips Semiconductors Product specification Baseband delay line TDA4665 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 Dec 17 10 Philips Semiconductors Product specification Baseband delay line TDA4665 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/03/pp12 Date of release: 1996 Dec 17 Document order number: 9397 750 01376