LTP5901-IPM/LTP5902-IPM
SmartMesh IP Node 2.4GHz
802.15.4e Wireless Mote Module
Network Features
Description
Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
n SmartMesh® Networks Incorporate:
n Time Synchronized Network-Wide Scheduling
n Per Transmission Frequency Hopping
n Redundant Spatially Diverse Topologies
n Network-Wide Reliability and Power Optimization
n NIST Certified Security
n SmartMesh Networks Deliver:
n>99.999% Network Reliability Achieved in the
Most Challenging RF Environments
n Sub 50µA Routing Nodes
n Compliant to 6LoWPAN Internet Protocol (IP) and
IEEE 802.15.4e Standards
SmartMesh IP™ wireless sensor networks are self managing, low power Internet Protocol (IP) networks built
from wireless nodes called motes. The LTP™5901-IPM/
LTP5902-IPM is the IP mote product in the Eterna®* family
of IEEE 802.15.4e printed circuit board assembly solutions,
featuring a highly-integrated, low power radio design by
Dust Networks® as well as an ARM Cortex-M3 32-bit
microprocessor running Dust’s embedded SmartMesh IP
networking software. Both the LTP5901-IPM (with chip
antenna), at 24mm × 42mm, and the LTP5902-IPM (with
MMCX connector), at 24mm × 37mm, are designed for
surface mount assembly.
n
LTP5901-IPM/LTP5902-IPM
Features
Industry-Leading Low Power Radio Technology with
4.5mA to Receive and 9.7mA to Transmit at 8dBm
n RF Modular Certification Include USA, Canada, EU,
Japan, Taiwan, Korea, India, Australia and New Zealand
n PCB Assembly with Chip Antenna (LTP5901-IPM) or
with MMCX Antenna Connector (LTP5902-IPM). QFN
Version (LTC®5800-IPM) Available
n Micrium µCOS-II Real Time Operating System Based
On-Chip Software Development Kit
n
With Dust’s time-synchronized SmartMesh IP networks,
all motes in the network may route, source or terminate
data, while providing many years of battery powered
operation. The SmartMesh IP software provided with the
LTP5901-IPM/LTP5902-IPM is fully tested and validated,
and is readily configured via a software Application Programming Interface.
SmartMesh IP motes deliver a highly flexible network
with proven reliability and low power performance in an
easy-to-integrate platform.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and
Eterna are registered trademarks and LTP, the Dust Networks logo and SmartMesh IP are
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,
7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
Typical Application
LTP5901-IPM
LTP5901-IPR/
LTP5902-IPR
ANTENNA
IN+
LTC2379-18 SPI
SENSOR
µCONTROLLER
UART
UART
IN–
HOST
APPLICATION
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LTP5901-IPM/LTP5902-IPM
Table of Contents
Network Features........................................... 1
LTP5901-IPM/LTP5902-IPM Features.................... 1
Typical Application ......................................... 1
Description.................................................. 1
Table of Contents ........................................... 2
SmartMesh Network Overview............................ 3
Absolute Maximum Ratings............................... 4
Pin Configuration........................................... 4
Order Information........................................... 5
Recommended Operating Conditions.................... 5
DC Characteristics.......................................... 5
Radio Specifications....................................... 6
Radio Receiver Characteristics........................... 6
Radio Transmitter Characteristics........................ 7
Digital I/O Characteristics................................. 7
Temperature Sensor Characteristics..................... 8
Analog Input Chain Characteristics...................... 8
System Characteristics.................................... 8
UART AC Characteristics................................... 9
TIMEn AC Characteristics................................. 10
Radio_Inhibit AC Characteristics........................ 10
Flash AC Characteristics.................................. 11
Flash SPI Slave AC Characteristics..................... 11
SPI Master AC Characteristics........................... 12
I2C AC Characteristics..................................... 13
1-Wire Master.............................................. 13
Flash SPI Slave AC Characteristics..................... 14
Typical Performance Characteristics................... 15
Pin Functions............................................... 20
Operation................................................... 24
Power Supply........................................................... 24
Supply Monitoring and Reset..................................25
Precision Timing......................................................25
Application Time Synchronization...........................25
Time References......................................................25
Radio.......................................................................26
UARTs......................................................................26
Autonomous MAC.................................................... 27
Security................................................................... 27
Temperature Sensor................................................ 27
RADIO INHIBIT........................................................ 27
Software Installation................................................ 27
Flash Data Retention................................................ 28
State Diagram.......................................................... 28
I2C Master...............................................................30
SPI Master...............................................................30
1-Wire Master..........................................................30
Applications Information................................. 31
Modes of Operation................................................. 31
Regulatory and Standards Compliance.................... 31
Soldering Information.............................................. 32
Related Documentation................................... 32
Package Description...................................... 33
Revision History........................................... 35
Typical Application........................................ 36
Related Parts............................................... 36
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LTP5901-IPM/LTP5902-IPM
SmartMesh Network Overview
A SmartMesh network consists of a self-forming multi-hop
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping (TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into time slots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
A network begins to form when the network manager
instructs its on-board Access Point (AP) radio to begin
sending advertisements—packets that contain information
that enables a device to synchronize to the network and
request to join. This message exchange is part of the security handshake that establishes encrypted communications
between the manager or application, and mote. Once motes
have joined the network, they maintain synchronization
through time corrections when a packet is acknowledged.
The Network Manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep in
between scheduled communications and draw very little
power in this state. Motes are only active in time slots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization software in the Network Manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network—even busy
routing ones—can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
HOST
APPLICATION
SNO 02
NETWORK MANAGER
AP
Mote
1
Mote
2
Mote
3
SNO 01
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks performance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
to the network manager in packets called health reports.
At the heart of SmartMesh motes and network managers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),
featuring Dust Networks’ highly integrated, low power
radio design, plus an ARM Cortex-M3 32-bit microprocessor running SmartMesh networking software. The
SmartMesh networking software comes fully compiled
yet is configurable via a rich set of Application Programming Interfaces (APIs) which allows a host application
to interact with the network, e.g. to transfer information
to a device, to configure data publishing rates on one or
more motes, or to monitor network state or performance
metrics. Data publishing can be uniform or different for
each device, with motes being able to publish infrequently
or faster than once per second as needed.
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LTP5901-IPM/LTP5902-IPM
Absolute Maximum Ratings
Pin Configuration
(Note 1)
Pin functions shown in italics are currently not supported in software.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
UARTC0_TX 31
UARTC0_RX 32
IPCS_MISO / GPIO6 33
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions be
observed when handling the LTP5901-IPM/LTP5902-IPM.
GND
RESERVED
NC
GPIO17
GPIO18
GPIO19
AI_2
AI_1
AI_3
AI_0
GND
RESERVED
NC
NC
RESETn
TDI
TDO
TMS
TCK
GND
DP4 (GPIO23)
RESERVED
RESERVED
RESERVED
DP3 (GPIO22) / TIMER8_IN
DP2 (GPIO21) / LPTIMER_IN
SLEEPn / GPIO14
DP0 (GPIO0) / SPIM_SS_2n
NC
GND
GND
NC
RADIO_INHIBIT / GPIO15
TIMEn / GPIO1
UART_TX
UART_TX_CTSn
UART_TX_RTSn
UART_RX
UART_RX_CTSn
UART_RX_RTSn
GND
VSUPPLY
RESERVED
NC
NC
FLASH_P_ENn / GPIO2
SPIS_SSn / SDA
SPIS_SCK / SCL
SPIS_MOSI / GPIO26 / UARTC1_RX
SPIS_MISO / 1_WIRE / UARTC1_TX
PWM0 / GPIO16
DP1 (GPIO20) / TIMER16_IN
SPIM_SS_0n / GPIO12
SPIM_SS_1n / GPIO13
GND
SPIM_SCK / GPIO9
SPIM_MOSI / GPIO10
IPCS_SSn / GPIO3
SPIM_MISO / GPIO11
GND
GND 34
IPCS_MOSI / GPIO5 35
IPCS_SCK / GPIO4 36
Supply Voltage on VSUPPLY...................................4.20V
Input Voltage on AI_0/1/2/3 Inputs.........................1.98V
Voltage on Any Digital
I/O pin..................................... –0.3V to VSUPPLY + 0.3V
Input RF Level..................................................... +10dBm
Storage Temperature Range (Note 3)...... –55°C to 105°C
Operating Temperature Range
LTP5901I/LPT5902I..............................–40°C to 85°C
PC PACKAGE
66-LEAD PCB
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LTP5901-IPM/LTP5902-IPM
Order Information
LEAD FREE FINISH†
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTP5901IPC-IPMA#PBF
LTP5901IPC-IPMA#PBF
66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna
–40°C to 85°C
LTP5902IPC-IPMA#PBF
LTP5902IPC-IPMA#PBF
66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX Connector –40°C to 85°C
†This product ships with the flash erased at the time of order. OEMs will need to program devices during development and manufacturing.
For legacy part numbers and ordering information go to: http://www.linear.com/product/LTP5901-IPM#orderinfo or
http://www.linear.com/product/LTP5902-IPM#orderinfo
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
Recommended Operating Conditions
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VSUPPLY
Supply Voltage
Including Noise and Load Regulation
l
Supply Noise
50Hz to 2MHz
l
250
mV
Operating Relative Humidity
Non-Condensing
l
10
90
% RH
Temperature Ramp Rate
While Operating in Network
l
–8
+8
°C/min
2.1
MAX
UNITS
3.76
V
DC Characteristics
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
OPERATION/STATE
CONDITIONS
Power-on Reset
During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time
from 1V to 1.9V
MIN
TYP
12
MAX
UNITS
mA
Doze
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Active
1.2
µA
Deep Sleep
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Inactive
0.8
µA
In-Circuit Programming
RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz
20
mA
Peak Operating Current
+8dBm
+0dBm
System Operating at 14.7MHz, Radio Transmitting, During Flash
Write. Maximum Duration 4.33 ms.
30
26
mA
mA
Active
ARM Cortex M3, RAM and Flash Operating, Radio and All Other
Peripherals Off. Clock Frequency of CPU and Peripherals Set to
7.3728MHz, VCORE = 1.2V
1.3
mA
Flash Write
Single Bank Flash Write
3.7
mA
Flash Erase
Single Bank Page or Mass Erase
2.5
mA
Radio Tx
+0dBm
+8dBm
Current with Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
5.4
9.7
mA
mA
Radio Rx
Current with Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
4.5
mA
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LTP5901-IPM/LTP5902-IPM
Radio Specifications
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.4000
MAX
UNITS
2.4835
GHz
Frequency Band
l
Number of Channels
l
15
Channel Separation
l
5
MHz
l
2405 + 5•(k-11)
MHz
l
250
kbps
Channel Center Frequency
Where k = 11 to 25, as Defined by IEEE 802.15.4
Modulation
IEEE 802.15.4 Direct Sequence Spread Spectrum (DSSS)
Raw Data Rate
Antenna Pin ESD Protection
HBM per JEDEC JESD22-A114F (Note 2)
Range (Note 4)
Indoor
Outdoor
Free Space
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
±6000
V
100
300
1200
m
m
m
Radio Receiver Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Receiver Sensitivity
Packet Error Rate (PER) = 1% (Note 5)
MIN
–93
dBm
Receiver Sensitivity
PER = 50%
–95
dBm
Saturation
Maximum Input Level the Receiver Will
Properly Receive Packets
0
dBm
Adjacent Channel Rejection (High Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
22
dBc
Adjacent Channel Rejection (Low Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
19
dBc
Alternate Channel Rejection
(High Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Above the Desired Signal, PER = 1% (Note 5)
40
dBc
Alternate Channel Rejection (Low Side) Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Below the Desired Signal, PER = 1% (Note 5)
36
dBc
Second Alternate Channel Rejection
Desired Signal at –82dBm, Second Alternate Modulated Channel
Either 15MHz Above or Below, PER = 1% (Note 5)
42
dBc
Co-Channel Rejection
Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
–6
dBc
LO Feed Through
–55
dBm
Frequency Error Tolerance (Note 6)
±50
ppm
Symbol Error Tolerance
Received Signal Strength Indicator
(RSSI) Input Range
TYP
MAX
UNITS
±50
ppm
–90 to –10
dBm
RSSI Accuracy
±6
dB
RSSI Resolution
1
dB
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LTP5901-IPM/LTP5902-IPM
Radio Transmitter Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Output Power
High Calibrated Setting
Low Calibrated Setting
Delivered to a 50Ω load
Spurious Emissions
Conducted Measurement with a 50Ω Single-Ended Load,
+8dBm Output Power. All Measurements Made with Max
Hold.
30MHz to 1000MHz
1GHz to 12.75GHz
2.4GHz ISM Upper Band Edge (Peak)
2.4GHz ISM Upper Band Edge (Average)
2.4GHz ISM Lower Band Edge
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
Harmonic Emissions
2nd Harmonic
3rd Harmonic
Conducted Measurement Delivered to a 50Ω Load,
Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz
MIN
TYP
MAX
UNITS
8
0
dBm
dBm
<–70
–45
–37
–49
–45
dBm
dBm
dBm
dBm
dBc
–50
–45
dBm
dBm
Digital I/O Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS (Note 7)
MIN
TYP
MAX
UNITS
VIL
Low Level Input Voltage
l
–0.3
0.6
V
VIH
High Level Input Voltage
(Note 8)
l
VSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOL
Low Level Output Voltage
Type 1, IOL(MAX) = 1.2mA
l
0.4
V
Type 2, Low Drive, IOL(MAX) = 2.2mA
l
0.4
V
Type 2, High Drive, IOL(MAX) = 4.5mA
l
0.4
V
Type 1, IOH(MAX) = –0.8mA
l
VSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
Type 2, Low Drive, IOH(MAX) = –1.6mA
l
VSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
Type 2, High Drive, IOH(MAX) = –3.2mA
l
VSUPPLY
– 0.3
VSUPPLY
+ 0.3
V
VOH
High Level Output Voltage
Input Leakage Current
Input Driven to VSUPPLY or GND
Pull-Up/Pull-Down Resistance
50
nA
50
kΩ
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LTP5901-IPM/LTP5902-IPM
Temperature Sensor Characteristics
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Offset
Temperature Offset Error at 25°C
MIN
Slope Error
TYP
MAX
UNITS
±0.25
°C
±0.033
°C/°C
Analog
Input Chain Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Variable Gain Amplifier
Gain
Gain Error
DNL
DNL
INL
TYP
1
Offset-Digital to Analog Converter (DAC)
Full-Scale
Resolution
Differential Non-Linearity
Analog to Digital Converter (ADC)
Full-Scale, Signal
Resolution
Offset
Differential Non-Linearity
Integral Non-Linearity
Settling Time
Conversion Time
Current Consumption
1.80
1.8
1.4
10kΩ Source Impedance
40
Analog Inputs (Note 9)
Load
Series Input Resistance
UNITS
8
2
1.80
4
Mid-Scale
MAX
2.7
12
1
1
10
20
20
1
%
V
Bits
mV
V
mV
LSB
LSB
LSB
µs
µs
µA
pF
kΩ
System Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Doze to Active State Transition
Doze to Radio Tx or Rx
QCCA
Charge to Sample RF Channel RSSI
Charge Consumed Starting from Doze State
and Completing an RSSI Measurement
QMAX
Largest Atomic Charge Operation
Flash Erase, 21ms Max Duration
RESETn Pulse Width
MAX
UNITS
5
µs
1.2
ms
4
µC
200
l
l
TYP
125
µC
µs
Total Capacitance
Note 13
l
6
µF
Total Inductance
Note 13
l
3
µH
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LTP5901-IPM/LTP5902-IPM
UART AC Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
Permitted RX Baud Rate Error
Both Application Programming
Interface (API) and Command Line
Interface (CLI) UARTs
l
MIN
–2
TYP
MAX
2
Generated TX Baud Rate Error
Both API and CLI UARTs
UNITS
%
l
–1
1
%
tRX_RTS to RX_CTS
Assertion of UART_RX_RTSn to Assertion
of UART_RX_CTSn, or Negation of UART_
RX_RTSn to Negation of UART_RX_CTSn
l
0
2
ms
tRX_CTS to RX
Assertion of UART_RX_CTSn to Start of
Byte
l
0
20
ms
tEOP to RX_RTS
End of Packet (End of the Last Stop Bit) to
Negation of UART_RX_RTSn
l
0
22
ms
tBEG_TX_RTS to TX_CTS
Assertion of UART_TX_RTSn to Assertion
of UART_TX_CTSn
l
0
22
ms
tEND_TX_CTS to TX_RTS
Negation of UART_TX_CTSn to Negation
of UART_TX_RTSn
tTX_CTS to TX
Assertion of UART_TX_CTSn to Start of
Byte
l
0
2
Bit Period
tEOP to TX_RTS
End of Packet (End of the Last Stop Bit) to
Negation of UART_TX_RTSn
l
0
1
Bit Period
2
Bit Period
tRX_INTERBYTE
Receive Inter-Byte Delay
l
tRX_INTERPACKET
Receive Inter-Packet Delay
l
20
100
ms
ms
tTX_INTERPACKET
Transmit Inter-Packet Delay
l
1
Bit Period
tTX to TX_CTS
Start of Byte to Negation of
UART_TX_CTSn
l
0
ns
tEOP TO RX_RTS
UART_RX_RTSn
tRX_RTS TO RX_CTS
UART_RX_CTSn
tRX_CTS TO RX
UART_RX
tRX_RTS TO RX_CTS
tRX_INTERBYTE
BYTE 0
BYTE 1
tEOP TO TX_RTS
UART_TX_RTSn
UART_TX_CTSn
tBEG_TX_RTS TO TX_CTS
tTX TO TX_CTS
tEND_TX_CTS TO TX_RTS
tEND_TX_RTS TO TX_CTS
tTX_CTS TO TX
UART_TX
BYTE 0
BYTE 1
59012ipm F01
Figure 1. API UART Timing
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9
LTP5901-IPM/LTP5902-IPM
TIMEn AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tSTROBE
TIMEn Signal Strobe Width
CONDITIONS
l
MIN
125
tRESPONSE
Delay from Rising Edge of TIMEn to the Start
of Time Packet on API UART
l
0
tTIME_HOLD
Delay from End of Time Packet on API UART
to Falling Edge of Subsequent TIMEn
l
0
Timestamp Resolution (Note 10)
l
1
µs
Network-Wide Time Accuracy (Note 11)
l
±5
µs
tSTROBE
TYP
MAX
UNITS
µs
100
ms
ns
tTIME_HOLD
TIMEn
tRESPONSE
UART_TX
TIME INDICATION PAYLOAD
59012ipm F02
Figure 2. Timestamp Timing
Radio_Inhibit AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tRADIO_OFF
tRADIO_INHIBIT_STROBE
CONDITIONS
MIN
TYP
MAX
UNITS
Delay from Rising Edge of
RADIO_INHIBIT to Radio Disabled
l
20
ms
Maximum RADIO_INHIBIT Strobe Width
l
2
s
tRADIO_INHIBIT_STROBE
RADIO_INHIBIT
tRADIO_OFF
RADIO STATE
ACTIVE/OFF
OFF
ACTIVE/OFF
59012ipm F03
Figure 3. RADIO_INHIBIT Timing
59012ipmfa
10
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Flash AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tWRITE
tPAGE_ERASE
tMASS_ERASE
CONDITIONS
MIN
TYP
MAX
UNITS
Time to Write a 32-Bit Word (Note 12)
l
21
µs
Time to Erase a 2kB Page (Note 12)
l
21
ms
Time to Erase 256kB Flash Bank (Note 12)
Data Retention
21
l
25°C
85°C
105°C
100
20
8
ms
Years
Years
Years
Flash SPI Slave AC Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
tFP_EN_to_RESET
Setup from Assertion of FLASH_P_ENn to
Assertion of RESETn
l
0
ns
tFP_ENTER
Delay from the Assertion RESETn to the
First Falling Edge of IPCS_SSn
l
125
µs
tFP_EXIT
Delay from the Completion of the Last
Flash SPI Slave Transaction to the
Negation of RESETn and FLASH_P_ENn
l
10
µs
tSSS
IPCS_SSn Setup to the Leading Edge of
IPCS_SCK
l
15
ns
tSSH
IPCS_SSn Hold from Trailing Edge of
IPCS_SCK
l
15
ns
tCK
IPCS_SCK Period
l
300
ns
tDIS
IPCS_MOSI Data Setup
l
15
ns
tDIH
IPCS_MOSI Data Hold
l
5
ns
tDOV
IPCS_MISO Data Valid
l
–5
30
ns
tOFF
IPCS_MISO Data Tri-State from Trailing
Edge of IPCS_SSn
l
0
30
ns
FLASH_P_ENn
RESETn
MIN
TYP
MAX
UNITS
tFP_EN_TO_RESET
tFP_EXIT
tFP_ENTER
tSSS
tSSH
IPCS_SSn
tCK
IPCS_SCK
tDIS
IPCS_MOSI
tDIH
59012ipm F04
Figure 4. Flash Programming Interface Timing
59012ipmfa
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SPI Master AC Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tSSS
SPIM_SSXn Setup to the Leading Edge of
SPIM_SCK
CONDITIONS
l
tCK-30
MIN
TYP
MAX
UNITS
ns
tSSH
SPIM_SSXn Hold from Trailing Edge of
SPIM_SCK
l
tCK-30
ns
tCK
SPIM_SCK Period
l
268
ns
tDIS
SPIM_MOSI Data Setup
l
30
ns
5
tDIH
SPIM_MOSI Data Hold
l
tDOV
SPIM_MISO Data Valid
l
–5
30
ns
tOFF
SPIM_MISO Data Tri-State from Trailing
Edge of SPIM_SSXn
l
0
30
ns
tSSS
ns
tSSH
SPIM_SSXn
tCK
SPIM_SCK
CPOL = 0
CPOL = 1
tDIS
tDIH
SPIM_MISO
tDOV
tOFF
SPIM_MOSI
59012ipm F05
Figure 5. SPI Master Timing - CPHA = 0
tSSS
tSSH
SPIM_SSXn
tCK
SPIM_SCK
CPOL = 0
CPOL = 1
tDIS
tDIH
SPIM_MISO
tDOV
tOFF
SPIM_MOSI
59012ipm F06
Figure 6. SPI Master Timing - CPHA = 1
59012ipmfa
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I2C AC Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
CONDITIONS
fSCL
SCL Frequency
184kHz Operation
92kHz Operation
l
MIN
TYP
MAX
UNITS
184.3
92.2
188
94
kHz
kHz
tHD_STA
Start Hold Time (SCL from SDA)
184kHz Operation
92kHz Operation
l
1
2
µs
µs
tSU_STA
Setup Time for a Repeated Start
184kHz Operation, 750ns SCL Rise Time
92kHz Operation, 1.5µs SCL Rise Time
l
300
600
ns
ns
tHD_DAT
Data Hold Time
184kHz Operation
92kHz Operation
l
1
2
µs
µs
tSU_DAT
Data Setup Time
184kHz Operation
92kHz Operation
l
1
2
µs
µs
tSU_STO
Setup Time for Stop Condition
184kHz Operation
92kHz Operation
l
1
2
µs
µs
tSU_STA
tHD_STA
tHD_STA
SDA
SCL
tSU_DAT
tHD_DAT
tHD_DAT
59012ipm F07
Figure 7. I2C Master Timing
1-Wire Master
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)
SYMBOL
PARAMETER
tRSTL
Reset Low
tPS
tBIT_PERIOD
CONDITIONS
MIN
TYP
MAX
UNITS
l
527
556
584
µs
Presence Sample
l
60.1
69.4
79
µs
1_WIRE Data Bit Period
l
82
86.8
92
µs
tLOW0
1_WIRE Write Data 0 Low Width
l
65
69
82
µs
tLOW1
1_WIRE Write Data 1 Low Width
l
8.2
8.7
9.2
µs
tLOWR
1_WIRE Read Data Low Width
l
8.2
8.7
9.2
µs
tRS
Read Sample from 1_WIRE Low
l
13.2
14.6
15.0
µs
59012ipmfa
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Flash SPI Slave AC Characteristics
tRSTL
tPS
1-WIRE
1-WIRE
tBIT_PERIOD
tLOW1
tBIT_PERIOD
tLOW0
1-WIRE
tBIT_PERIOD
tRS
1-WIRE
tLOWR
59012ipm F08
Figure 8. 1-Wire Master Timing
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ESD (electrostatic discharge) sensitive device. ESD protection
devices are used extensively internal to Eterna. However, high electrostatic
discharge can damage or degrade the device. Use proper ESD handling
precautions.
Note 3: Extended storage at high temperature is discouraged, as this
negatively affects the data retention of Eterna’s calibration data. See the
FLASH Data Retention section for details.
Note 4: Actual RF range is subject to a number of installation-specific
variables including, but not restricted to ambient temperature, relative
humidity, presence of active interference sources, line-of-sight obstacles,
and near-presence of objects (for example, trees, walls, signage, and so
on) that may induce multipath fading. As a result, range varies.
Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) Specifications for LowRate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.
org/findstds/standard/802.15.4-2011.html.
Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a
frequency tolerance of better than ±40 ppm.
Note 7: Per-pin I/O types are provided in the Pin Functions section.
Note 8: VIH maximum voltage input must respect the VSUPPLY maximum
voltage specification.
Note 9: The analog inputs to the ADC can be modeled as a series resistor
to a capacitor. At a minimum the entire circuit, including the source
impedance for the signal driving the analog input should be designed
to settle to within ¼ LSB within the sampling window to match the
performance of the ADC.
Note 10: See the SmartMesh IP Mote API Guide for the time indication
notification definition.
Note 11: Network time accuracy is a statistical measure and varies over
the temperature range, reporting rate and the location of the device
relative to the manager in the network. See the Typical Performance
Characteristics section for a more detailed description.
Note 12: Code execution from flash banks being written or erased is
suspended until completion of the flash operation.
Note 13: Guaranteed by design. Not production tested.
59012ipmfa
14
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Typical Performance Characteristics
Network motes typically route through at least two parents
the traffic destined for the manager. The supply current
graphs shown in Figure 9 include a parameter called descendants. In these graphs the term descendants is short
for traffic-weighted descendants and refers to an amount
of activity equivalent to the number of descendants if all
of the network traffic directed to the mote in question.
Generally the number of descendants of a parent is more,
typically 2x or more, than the number of traffic-weighted
descendants. For example, with reference to Figure 10.
Network Graph mote P1 has 0.75 traffic-weighted descendants. To obtain this value notice that mote D1 routes
half its packets through mote P1 adding 0.5 to the trafficweighted descendant value; the other half of D1’s traffic is
routed through its other parent, P2. Mote D2 routes half
its packets through mote D1 (the other half going through
parent P3), which we know routes half its packets to mote
P1, adding another 0.25 to the traffic-weighted descendant
value for a total traffic-weighted descendant value of 0.75.
was performed with the 1-hop mote inside a temperature
chamber. Timing errors due to temperature changes and
temperature differences both between the manager and
this mote and between this mote and its descendents
therefore propagated down through the network. The synchronization of the 3-hop and 5-hop motes to the manager
was then affected by the temperature ramps even though
they were at room temperature. For 2°C/minute testing
the temperature chamber was cycled between –40°C and
85°C at this rate for 24 hours. For 8°C/minute testing, the
temperature chamber was rapidly cycled between 85°C and
45°C for 8 hours, followed by rapid cycling between –5°C
and 45°C for 8 hours, and lastly, rapid cycling between
–40°C and 15°C for 8 hours.
As described in the Application Time Synchronization
section, Eterna provides two mechanisms for applications
to maintain a time base across a network. The synchronization performance plots that follow were generated
using the more precise TIMEn input. Publishing rate is
the rate a mote application sends upstream data. Synchronization improves as the publishing rate increases.
Baseline synchronization performance is provided for a
network operating with a publishing rate of zero. Actual
performance for applications in network will improve
as publishing rates increase. All synchronization testing
100
80
60
40
20
0
–60
4.0
P1
P2
3.0
2 HOP
D1
D2
3 HOP
58012ipm F10
Figure 10. Example Network Graph
5 HOPS
4 HOPS
3 HOPS
2 HOPS
1 HOP
3.5
1 HOP
P3
5 DESCENDANTS
2 DESCENDANTS
1 DESCENDANTS
0 DESCENDANTS
200
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
120
2 DESCENDANTS 5sec REPORTING
5 DESCENDANTS 30sec REPORTING
2 DESCENDANTS 30sec REPORTING
0 DESCENDANTS 5sec REPORTING
0 DESCENDANTS 30sec REPORTING
MEDIAN LATENCY (sec)
140
MANAGER
2.5
2.0
1.5
1.0
100
0.5
–10
40
TEMPERATURE (°C)
90
0
0
10
20
REPORTING INTERVAL (sec)
30
0
0
58012ipm F09b
58012ipm F09a
10
20
REPORTING INTERVAL (sec)
30
58012ipm F09c
Figure 9
59012ipmfa
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Typical Performance Characteristics
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
25
µ = –0.2
σ = 1.7
N = 89699
20
15
10
5
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G01
10
5
40
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
15
14
12
µ = 0.9
σ = 3.9
N = 93846
8
6
4
2
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G04
8
6
4
2
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
8
6
4
2
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G07
14
12
40
7
6
µ = 1.0
σ = 7.7
N = 93845
5
4
3
2
1
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G06
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 8°C/Min
µ = 1.1
σ = 3.8
N = 88179
10
8
6
4
2
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G03
58012ipm G05
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
10
10
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 8°C/Min
µ = 3.6
σ = 5.0
N = 88144
µ = –0.2
σ = 3.6
N = 89698
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, 2°C/Min
10
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 8°C/Min
12
12
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, 2°C/Min
µ = 1.5
σ = 3.3
N = 93812
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
14
58012ipm G02
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, 2°C/Min
20
40
NORMALIZED FREQUENCY OF OCCURRENCE (%)
40
30
NORMALIZED FREQUENCY OF OCCURRENCE (%)
50
µ = 0.0
σ = 0.9
N = 89700
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
5 Hops, Room Temperature
40
NORMALIZED FREQUENCY OF OCCURRENCE (%)
60
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
3 Hops, Room Temperature
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
TIMEn Synchronization Error
0 Packet/s Publishing Rate,
1 Hop, Room Temperature
7
6
µ = 1.0
σ = 7.4
N = 88178
5
4
3
2
1
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G08
40
58012ipm G09
59012ipmfa
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Typical Performance Characteristics
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
50
µ = –0.2
σ = 1.2
N = 17008
40
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G10
µ = 0.5
σ = 1.9
N = 85860
25
20
15
10
5
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
45
40
35
µ = 0.1
σ = 1.5
N = 85858
25
20
15
10
5
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G13
40
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G16
60
50
40
35
30
µ = 0.1
σ = 1.5
N = 85855
25
20
15
10
5
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G15
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 8°C/Min
µ = 0.0
σ = 1.3
N = 33930
40
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
40
58012ipm G12
58012ipm G14
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
50
30
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 8°C/Min
µ = 0.2
σ = 1.4
N = 33932
µ = –0.2
σ = 1.2
N = 17007
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, 2°C/Min
30
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 8°C/Min
60
40
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, 2°C/Min
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
30
50
58012ipm G11
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, 2°C/Min
35
40
NORMALIZED FREQUENCY OF OCCURRENCE (%)
40
60
NORMALIZED FREQUENCY OF OCCURRENCE (%)
50
µ = 0.0
σ = 1.2
N = 22753
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
5 Hops, Room Temperature
40
NORMALIZED FREQUENCY OF OCCURRENCE (%)
60
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
3 Hops, Room Temperature
NORMALIZED FREQUENCY OF OCCURRENCE (%)
NORMALIZED FREQUENCY OF OCCURRENCE (%)
TIMEn Synchronization Error
1 Packet/s Publishing Rate,
1 Hop, Room Temperature
50
40
µ = –1.0
σ = 1.3
N = 33929
30
20
10
0
–40 –30 –20 –10 0
10 20 30
SYNCHRONIZATION ERROR (µs)
58012ipm G17
40
58012ipm G18
59012ipmfa
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LTP5901-IPM/LTP5902-IPM
Typical Performance Characteristics
As described in the SmartMesh Network Overview section, devices in network spend the vast majority of their
time inactive in their lowest power state (doze). On a
synchronous schedule a mote will wake to communicate
with another mote. Regularly occurring sequences which
wake, perform a significant function and return to sleep
are considered atomic. These operations are considered
atomic as the sequence of events can not be separated
into smaller events while performing a useful function.
For example, transmission of a packet over the radio is an
atomic operation. Atomic operations may be characterized
in either charge or energy. In a time slot where a mote
successfully sends a packet, an atomic transmit includes
setup prior to sending the message, sending the message,
receiving the acknowledgment and the post processing
needed as a result of the message being sent. Similarly in
a time slot when a mote successfully receives a packet, an
atomic receive includes setup prior to listening, listening
until the start of the packet transition, receiving the packet,
sending the acknowledge and the post processing required
due to the arrival of the packet.
To ensure reliability each mote in the network is provided
multiple time slots for each packet it nominally will send
and forward. The time slots are assigned to communicate
upstream with at least two different motes. When combined
with frequency hopping this provides temporal, spacial
and spectral redundancy. Given this approach a mote will
often listen for a message that it will never receive, since
the time slot is not being used by the transmitting mote.
It has already successfully transmitted the packet. Since
typically 3 time slots are scheduled for every 1 packet to
be sent or forwarded, motes will perform more of these
atomic “idle listens” than atomic transmit or atomic receive
sequences. Examples of transmit, receive and idle listen
atomic operations are shown in Figure 11.
59012ipmfa
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Typical Performance Characteristics
Figure 11
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Pin Functions
Pin functions shown in italics are currently not supported in software.
The following table organizes the pins by functional
groups. For those I/O with multiple functions the alternate
functions are shown on the second and third line in their
respective row. The No column provides the pin number.
The second column lists the function. The Type column
NO POWER SUPPLY
1
TYPE
I/O
lists the I/O type. The I/O column lists the direction of the
signal relative to Eterna. The Pull column shows which
signals have a fixed passive pull-up or pull-down. The
Description column provides a brief signal description.
PULL DESCRIPTION
GND
Power
-
-
Ground Connection
11 GND
Power
-
-
Ground Connection
20 GND
Power
-
-
Ground Connection
30 GND
Power
-
-
Ground Connection
34 GND
Power
-
-
Ground Connection
37 GND
Power
-
-
Ground Connection
42 GND
Power
-
-
Ground Connection
56 GND
Power
-
-
Ground Connection
66 GND
Power
-
-
Ground Connection
55 VSUPPLY
Power
-
-
Power Supply Input to Eterna
NO RADIO
TYPE
I/O
1 (Note 14)
I
-
Radio Inhibit
64 RADIO_INHIBIT
PULL DESCRIPTION
4
GPIO17
1
I/O
-
General Purpose Digital I/O
5
GPIO18
1
I/O
-
General Purpose Digital I/O
6
GPIO19
-
ANTENNA
NO ANALOG
1
I/O
-
General Purpose Digital I/O
N/A
N/A
-
Chip Antenna (LTP5901) or MMCX Connector (LPT5902)
TYPE
I/O
PULL DESCRIPTION
7
AI_2
Analog
I
-
Analog Input 2
8
AI_1
Analog
I
-
Analog Input 1
9
AI_3
Analog
I
-
Analog Input 3
10 AI_0
Analog
I
-
Analog Input 0
NO RESET
TYPE
I/O
15 RESETn
1
I
NO JTAG
TYPE
I/O
16 TDI
1
I
UP
JTAG Test Data In
17 TDO
1
O
-
JTAG Test Data Out
18 TMS
1
I
19 TCK
1
I
PULL DESCRIPTION
UP
Reset Input, Active Low
PULL DESCRIPTION
UP
JTAG Test Mode Select
DOWN JTAG Test Clock
59012ipmfa
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Pin Functions
NO GPIOs
Pin functions shown in italics are currently not supported in software.
TYPE
I/O
21 DP4 (GPIO23)
1
I/O
-
General Purpose Digital I/O
25 DP3 (GPIO22)
TIMER8_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to 8-Bit Timer/Counter
26 DP2 (GPIO21)
LPTIMER_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to Low Power Timer/Counter
28 DP0 (GPIO0)
SPIM_SS_2n
1
I/O
O
-
General Purpose Digital I/O
SPI Master Slave Select 2, Active Low
45 DP1 (GPIO20)
TIMER16_EXT
1
I/O
I
-
General Purpose Digital I/O
External Input to 16-Bit Timer/Counter
NO SPECIAL PURPOSE
PULL DESCRIPTION
TYPE
I/O
1 (Note 14)
I
-
Deep Sleep, Active Low
2
O
O
I/O
-
Pulse Width Modulator 0
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
1 (Note 14)
I
-
Time Capture Request, Active Low
TYPE
I/O
31 UARTC0_TX
2
O
-
CLI UART 0 Transmit
32 UARTC0_RX
1
I
UP
CLI UART 0 Receive
NO SPI MASTER
TYPE
I/O
38 SPIM_MISO
GPIO11
1
I
I/O
-
SPI Master (MISO) Master In Slave Out Port
General Purpose Digital I/O
40 SPIM_MOSI
GPIO10
2
O
I/O
-
SPI Master (MOSI) Master Out Slave In Port
General Purpose Digital I/O
41 SPIM_SCK
GPIO9
2
O
I/O
-
SPI Master (SCK) Serial Clock Port
General Purpose Digital I/O
43 SPIM_SS_1n
GPIO13
1
O
I/O
-
SPI Master Slave Select 1, Active Low
General Purpose Digital I/O
44 SPIM_SS_0n
GPIO12
1
O
I/O
-
SPI Master Slave Select 0, Active Low
General Purpose Digital I/O
27 SLEEPn
46 PWM0
TIMER16_OUT
GPIO16
63 TIMEn
NO CLI
PULL DESCRIPTION
PULL DESCRIPTION
PULL DESCRIPTION
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21
LTP5901-IPM/LTP5902-IPM
Pin Functions
Pin functions shown in italics are currently not supported in software.
NO IPCS SPI/FLASH PROGRAMMING (NOTE 15)
TYPE
I/O
33 IPCS_MISO
TIMER16_OUT
GPIO6
2
I
O
I/O
-
SPI Flash Emulation (MISO) Master In Slave Out Port
16-Bit Timer/Counter Match Output/PWM Output
General Purpose Digital I/O
35 IPCS_MOSI
TIMER16_EXT
GPIO5
1
I
I
I/O
-
SPI Flash Emulation (MOSI) Master Out Slave In Port
External Input to 16-Bit Timer/Counter
General Purpose Digital I/O
36 IPCS_SCK
TIMER8_EXT
GPIO4
1
I
I
I/O
-
SPI Flash Emulation (SCK) Serial Clock Port
External Input to 8-Bit Timer/Counter
General Purpose Digital I/O
39 IPCS_SSn
LPTIMER_EXT
GPIO3
1
I
I
I/O
-
SPI Flash Emulation Slave Select, Active Low
External Input to Low Power Timer/Counter
General Purpose Digital I/O
51 FLASH_P_ENn
1
I
UP
NO I2C/1-WIRE/SPI SLAVE
PULL DESCRIPTION
Flash Program Enable, Active Low
TYPE
I/O
47 SPIS_MISO
UARTC1_TX
1_WIRE
2
O
O
I/O
-
SPI Slave (MISO) Master In Slave Out Port
CLI UART 1 Transmit
1 Wire Master
48 SPIS_MOSI
UARTC1_RX
GPIO26
1
I
I
I/O
-
SPI Slave (MOSI) Master Out Slave In Port
CLI UART 1 Receive
General Purpose Digital I/O
49 SPIS_SCK
SCL
2
I
I/O
-
SPI Slave (SCK) Serial Clock Port
I2C Serial Clock
50 SPIS_SSn
SDA
2
I
I/O
-
SPI Slave Select, Active Low
I2C Serial Data
NO API UART
PULL DESCRIPTION
TYPE
I/O
57 UART_RX_RTSn
1 (Note 14)
I
-
UART Receive (RTS) Request to Send, Active Low
58 UART_RX_CTSn
1
O
-
UART Receive (CTS) Clear to Send, Active Low
59 UART_RX
PULL DESCRIPTION
1 (Note 14)
I
-
UART Receive
60 UART_TX_RTSn
1
O
-
UART Transmit (RTS) Request to Send, Active Low
61 UART_TX_CTSn
1 (Note 14)
I
-
UART Transmit (CTS) Clear to Send, Active Low
2
O
-
UART Transmit
62 UART_TX
Note 14: These inputs are always enabled and must be driven or pulled to
a valid state to avoid leakage.
Note 15: Embedded programming over the IPCS SPI bus is only avaliable
when RESETn is asserted.
59012ipmfa
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Pin Functions
VSUPPLY: System and I/O Power Supply. Provides power
to the module. The digital-interface I/O voltages are also
set by this voltage.
ANTENNA: Multiplexed Receiver Input and Transmitter
Output Pin. The impedance presented to the MMCX connector should be 50Ω, single-ended with respect to ground.
AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are
multiplexed to the analog input chain. The analog input
chain, as shown in Figure 12, is software-configurable
and includes a variable-gain amplifier, an offset-DAC for
adjusting input range, and a 10-bit ADC. Valid input range
is between 0V to 1.8V. Analog inputs can be sampled as
described in section Signal/Data Acquisition and Control.
ANALOG INPUT
+
3-BIT
VGA
10-BIT ADC
4-BIT DAC
59012ipm F12
Figure 12. Analog Input Chain
RESETn: The asynchronous reset signal is internally pulled
up. Resetting Eterna will result in the ARM Cortex M3
rebooting and loss of network connectivity. Use of this
signal for resetting Eterna is not recommended, except
during power-on and in-circuit programming.
RADIO_INHIBIT: RADIO_INHIBIT provides a mechanism
for an external device to temporarily disable radio operation.
Failure to observe the timing requirements defined in the
RADIO_INHIBIT AC Characteristics section, may result
in unreliable network operation. In designs where the
RADIO_INHIBIT function is not needed the input must
either be tied, pulled or actively driven low to avoid excess
leakage.
TMS, TCK, TDI, TDO: JTAG Port Supporting Software
Debug and Boundary Scan.
SLEEPn: The SLEEPn function is not currently supported
in software. The SLEEPn input must either be tied, pulled
or actively driven high to avoid excess leakage.
UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX,
UART_TX_RTSn, UART_TX_CTSn: The API UART interface
includes bidirectional wake up and flow control. Unused
input signals must be driven or pulled to their inactive state.
TIMEn: Strobing the TIMEn input is the most accurate
method to acquire the network time maintained by Eterna.
Eterna latches the network time stamp with sub-microsecond resolution on the rising edge of the TIMEn signal
and produces a packet on the API serial port containing
the timing information.
UARTC0_RX, UARTC0_TX: The CLI UART provides a
mechanism for monitoring, configuration and control of
Eterna during operation. For a complete description of
the supported commands see the SmartMesh IP Mote
CLI Guide.
GPIO0, GPIO3 to GPIO6, GPIO9 to GPIO13, GPIO16,
GPIO20 to GPIO23, GPIO26: General purpose I/Os that
can be sampled or driven as described in the On-Chip
Software Development Kit (On-Chip SDK).
FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,
IPCS_SSn: The In-Circuit Programming Control System
(IPCS) bus enables in-circuit programming of Eterna’s flash
memory. IPCS_SCK is a clock and should be terminated
appropriately for the driving source to prevent overshoot
and ringing.
SPIM_CLK, SPIM_MISO, SPIM_MOSI, SPIM_SS_0n,
SPIM_SS_1n, SPIM_SS_4n: The SPI Master bus with
support for up to three SPI slave devices, via the On-Chip
Software Development Kit (On-Chip SDK) provides an
interface to SPI peripheral slave devices. The SPI interface
is synchronous to SPIM_CLK, which should be treated as
a clock signal and terminated appropriately .
1-WIRE: The 1-Wire master clock/data/power signal. See
the On-Chip Software Development Kit (On-Chip SDK) for
details on operating the 1-Wire Master controller.
SCL, SDA: The I2C bus SCL and SDA should be externally
pulled to VSUPPLY with a 10k resistor. See the On-Chip
Software Development Kit (On-Chip SDK) for details on
operating the 1-Wire Master controller.
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23
LTP5901-IPM/LTP5902-IPM
Operation
Power Supply
The LTP5901-IPM/LTP5902-IPM is the world’s most energy
efficient IEEE 802.15.4 compliant platform, enabling battery and energy harvested applications. With a powerful
32-bit ARM Cortex-M3, best-in-class radio, flash, RAM
and purpose-built peripherals, Eterna provides a flexible,
scalable and robust networking solution for applications
demanding minimal energy consumption and data reliability
in even the most challenging RF environments.
Eterna is powered from a single pin, VSUPPLY, which
powers the I/O cells and is also used to generate internal
supplies. Eterna’s two on-chip DC/DC converters minimize
Eterna’s energy consumption while the device is awake. To
conserve power the DC/DC converters are disabled when
the device is in low power state. Eterna’s power supply
conditioning architecture, including the two integrated DC/
DC converters and three integrated low dropout regulators, provides excellent rejection of supply noise. Eterna’s
operating supply voltage range is high enough to support
direct connection to lithium-thionyl chloride (Li-SOCl2)
sources and wide enough to support battery operation
over a broad temperature range.
Shown in Figure 13, Eterna integrates purpose-built
peripherals that excel in both low operating-energy consumption and the ability to rapidly and precisely cycle
between operating and low-power states. Items in the
gray shaded region labeled Analog Core correspond to
the analog/RF components.
32kHz
DIGITAL CORE
ANALOG CORE
32kHz, 20MHz
TIMERS
SCHED
VOLTAGE REFERENCE
PRIMARY
DC/DC
CONVERTER
SRAM
72kB
CORE REGULATOR
CLOCK REGULATOR
PMU/
CLOCK
CONTROL
FLASH
512kB
RELAXATION
OSCILLATOR
ANALOG REGULATOR
PA
DC/DC
CONVERTER
PoR
FLASH
CONTROLLER
802.15.4
MOD
AES
CODE
LPF
DAC
PA
802.15.4
FRAMING
DMA
AUTO
MAC
802.15.4
DEMOD
SYSTEM
20MHz
PLL
ADC
LIMITER
BPF
PPF
LNA
AGC
RSSI
IPCS
SPI
SLAVE
CLI
UART
(2-PIN)
API
UART
(6-PIN)
ADC
CTRL
10-BIT
ADC
BAT
LOAD
VGA
PTAT
4-BIT
DAC
59012ipm F13
Figure 13. Eterna Block Diagram
59012ipmfa
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Operation
Supply Monitoring and Reset
Eterna integrates a Power-on Reset (PoR) circuit. As the
RESETn input pin is nominally configured with an internal
pull-up resistor, no connection is required. For a graceful
shutdown, the software and the networking layers should
be cleanly halted via API commands prior to assertion of
the RESETn pin. See the SmartMesh IP Mote API Guide
for details on the disconnect and reset commands. Eterna
includes a soft brown-out monitor that fully protects the
flash from corruption in the event that power is removed
while writing to flash. Integrated flash supervisory functionality, in conjunction with a fault tolerant file system,
yields a robust nonvolatile storage solution.
Precision Timing
A major feature of Eterna over competing 802.15.4 product offerings is its low-power dedicated timing hardware
and timing algorithms. This functionality provides timing
precision two to three orders of magnitude better than
any other low-power solution available at the time of
publication. Improved timing accuracy allows motes to
minimize the amount of radio listening time required to
ensure packet reception thereby lowering even further
the power consumed by SmartMesh networks. Eterna’s
patented timing hardware and timing algorithms provide
superior performance over rapid temperature changes,
further differentiating Eterna’s reliability when compared
with other wireless products. In addition, precise timing
enables networks to reduce spectral dead time, increasing
total network throughput.
Application Time Synchronization
In addition to coordinating time slots across the network,
which is transparent to the user, Eterna’s timing management is used to support two mechanisms to share network
time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to
be performed in a synchronized fashion across a network.
Eterna will send a time packet through its serial interface
when one of the following occurs:
The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware
relative to the rising edge of TIMEn. If an API request is
used, due to packet processing, the value of the timestamp
may be captured several milliseconds after receipt of
the packet due to packet processing. See the TIMEn AC
Characteristics section for the time function’s definition
and specifications.
Time References
Eterna includes three clock sources: an internal relaxation
oscillator, a low power oscillator designed for a 32.768kHz
crystal, and the radio reference oscillator designed for a
20MHz crystal.
Relaxation Oscillator
The relaxation oscillator is the primary clock source
for Eterna, providing the clock for the CPU, memory
subsystems, and all peripherals. The internal relaxation
oscillator is dynamically calibrated to 7.3728 MHz. The
internal relaxation oscillator typically starts up in a few
μs, providing an expedient, low energy method for duty
cycling between active and low power states. Quick start-up
from the doze state, defined in the State Diagram section,
allows Eterna to wake up and receive data over the UART
and SPI interfaces by simply detecting activity on the
appropriate signals.
32.768kHz Crystal
Once Eterna is powered up and the 32.768kHz crystal
source has begun oscillating, the 32.768kHz crystal remains operational while in the active state, and is used as
the timing basis when in doze state. See the State Diagram
section for a description of Eterna’s operational states.
20MHz Crystal
The 20 MHz crystal source provides a frequency reference
for the radio, and is automatically enabled and disabled
by Eterna as needed.
Eterna receives an API request to read time
n
The TIMEn signal is asserted
n
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LTP5901-IPM/LTP5902-IPM
Operation
Radio
UART Mode 4
Eterna includes the lowest power commercially available
2.4GHz IEEE 802.15.4e radio by a substantial margin.
(Please refer to the Radio Specifications section for
power consumption numbers.). Eterna’s integrated power
amplifier is calibrated and temperature compensated to
consistently provide power at a limit suitable for worldwide
radio certifications. Additionally, Eterna uniquely includes
a hardware-based autonomous MAC that handles precise
sequencing of peripherals, including the transmitter, the
receiver, and Advanced Encryption Standard (AES) peripherals. The hardware-based autonomous Media Access
Controller (MAC) minimizes CPU activity, thereby further
decreasing power consumption.
UART Mode 4 incorporates level sensitive flow control
on the TX channel and requires no flow control on the
RX channel, supporting 115200 baud. The use of levelsensitive flow control signals enables data rates above
9600 baud with the option of using a reduced set of
the flow control signals; however, Mode 4 has specific
limitations. First, the use of the RX flow control signals
(UART_RX_RTSn and UART_RX_CTSn) for Mode 4
are optional provided the use is limited to the industrial
temperature range (–40°C to 85°C); otherwise, the flow
control is mandatory. If RX flow control signals are
not used, UART_RX_RTSn should be tied to VSUPPLY
(inactive) and UART_RX_CTSn should be left unconnected.
Second, unless the companion processor is always ready
to receive a packet, the companion processor must negate
UART_TX_CTSn prior to the end of the current packet.
Failure to negate UART_TX_CTSn prior to the end of a packet
may result in back to back packets. Third, the companion
processor must wait at least tRX_RTS to RX_CTS between
transmmitting packets on UART_RX. See the UART AC
Characteristics section for complete timing specifications.
Packets are HDLC encoded with one stop bit and no parity
bit. The flow control signals for the TX channel are shown
in Figure 14. Transfers are initiated by Eterna asserting
UART_TX_RTSn. The UART_TX_CTSn signal may be
actively driven by the companion processor when ready to
receive a packet or UART_TX_CTSn may be tied low if the
companion processor is always ready to receive a packet.
After detecting a logic ‘0’ on UART_TX_CTSn Eterna sends
the entire packet. Following the transmission of the final
byte in the packet Eterna negates UART_TX_RTSn and waits
for tTX_INTERPACKET, defined in the UART AC Characteristics
section before asserting UART_TX_RTSn again.
UARTs
The principal network interface is through the application
programming interface (API) UART. A Command-Line
Interface (CLI) is also provided for support of test and
debug functions. Both UARTs sense activity continuously,
consuming virtually no power until data is transferred over
the port and then automatically returning to their lowest
power state after the conclusion of a transfer. The definition for packet encoding on the API UART interface can
be found in the SmartMesh IP Mote API Guide and the
CLI command definitions can be found in the SmartMesh
IP Mote CLI Guide.
API UART Protocol
The API UART protocol was created with the goal of
supporting a wide range of companion Multipoint Control
Units (MCUs) while reducing power consumption of the
system. The receive half of the API UART protocol includes
two additional signals in addition to UART_RX: UART_RX_
RTSn and UART_RX_CTSn. The transmit half of the API
UART protocol includes two additional signals in addition
to UART_TX: UART_TX_RTSn and UART_TX_CTSn. The
API UART protocol is referred to as Mode 4.
In the Figures accompanying the protocol descriptions,
signals driven by the companion processor are drawn
in black and signals driven by Eterna are drawn in blue.
UART_TX_RTSn
UART_TX_CTSn
UART_TX
BYTE 0
BYTE 1
59012ipm F14
Figure 14. UART Mode 4 Transmit Flow Control
59012ipmfa
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Operation
For details on the timing of the UART protocol, see the
UART AC Characteristics section.
CLI UART
The Command Line Interface (CLI) UART port is a two
wire protocol (TX and RX) that operates at a fixed 9600
baud rate with one stop bit and no parity. The CLI UART
interface is intended to support command line instructions
and response activity.
Autonomous MAC
Eterna was designed as a system solution to provide a
reliable, ultralow power, and secure network. A reliable
network capable of dynamically optimizing operation
over changing environments requires solutions that are
far too complex to completely support through hardware
acceleration alone. As described in the Precision Timing
section, proper time management is essential for optimizing
a solution that is both low power and reliable. To address
these requirements Eterna includes the autonomous MAC,
which incorporates a coprocessor for controlling all of
the time critical radio operations. The autonomous MAC
provides two benefits: first, preventing variable software
latency from affecting network timing and second, greatly
reducing system power consumption by allowing the CPU
to remain inactive during the majority of the radio activity.
The autonomous MAC, provides software independent
timing control of the radio and radio related functions,
resulting in superior reliability and exceptionally low power.
Security
Network security is an often overlooked component of a
complete network solution. Proper implementation of security protocols is significant in terms of both engineering
effort and market value in an OEM product. Eterna system
solutions provide a FIPS-197 validated encryption scheme
that includes authentication and encryption at the MAC
and network layers with separate keys for each mote.
This not only yields end-to-end security, but if a mote is
somehow compromised, communication from other motes
is still secure. A mechanism for secure key exchange allows keys to be kept fresh. To prevent physical attacks,
Eterna includes hardware support for electronically locking
devices, thereby preventing access to Eterna’s flash and
RAM memory and thus the keys and code stored therein.
Temperature Sensor
Eterna includes a calibrated temperature sensor on chip.
The temperature readings are available locally through
Eterna’s serial API, in addition to being available via the
network manager. The performance characteristics of
the temperature sensor can be found in the Temperature
Sensor Characteristics section.
RADIO INHIBIT
The RADIO_INHIBIT input enables an external controller
to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to
radio interference). When RADIO_INHIBIT is asserted
the software radio drivers will disallow radio operations
including clear channel assessment, packet transmits,
or packet receipts. If the radio is active in the current
timeslot when RADIO_INHIBIT is asserted the radio will be
diabled after the present operation completes. For details
on the timing associated with RADIO_INHIBIT, see the
RADIO_INHIBIT AC Characteristics section.
Software Installation
Devices are supplied with the flash erased, requiring programming as part of the OEMs manufacturing procedure.
The US Department of Commerce places restrictions on
export of systems and software supporting encryption.
All of Linear/Dust product software produced to date
contains encryption and is subject to export regulations
and may be provided only via MyLinear, https://www.
linear.com/mylinear. Customers purchasing SmartMesh
products will receive a certificate containing a registration
key and registration instructions with their order. After
registering with the key, customers will be able to
download SmartMesh software images from MyLinear.
Once registered, customers will receive automated e-mail
notifications as software updates are made available.
Linear Technology offers the DC9010, in circuit programmer for the Eterna based products. While the DC9010, is
provided as a finished product, the design documents are
provided as a reference for customers.
59012ipmfa
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27
LTP5901-IPM/LTP5902-IPM
Operation
Once software has been loaded, devices can be configured
via either the CLI or API ports. Configuration commands
and settings are defined in SmartMesh IP Mote API Guide
and SmartMesh IP Mote CLI Guide.
Flash Data Retention
Eterna contains internal flash (nonvolatile memory) to
store calibration results, unique ID, configuration settings
and software images. Flash retention over the operating
temperature range. See Electrical Characteristics and
Absolute Maximum Ratings sections.
Non destructive storage above the operating temperature
range of –40°C to 85°C is possible; although, this may
result in a degradation of retention characteristics.
The degradation in flash retention for temperatures >85°C
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
AF = e
Ea
1
1
−
•
k TUSE +273 TSTRESS +273
State Diagram
In order to provide capabilities and flexibility in addition
to ultralow power, Eterna operates in various states, as
shown in Figure 11. Eterna State Diagram and described
in this section. State transitions shown in red are not
recommended.
Start-Up
Start-up occurs as a result of either crossing the power-on
reset threshold or asserting RESETn. After the completion
of power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its fuse table which,
as described in the previous section, includes setting
I/O direction. In this state, Eterna checks the state of
the FLASH_P_ENn and RESETn and enters the serial
flash emulation mode if both signals are asserted. If the
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the active state.
Where:
Serial Flash Emulation
AF = acceleration factor
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Ea = activation energy = 0.6eV
k = 8.625 • 10–5eV/°K
TUSE = is the specified temperature retention in °C
TSTRESS = actual storage temperature in °C
Example: Calculate the effect on retention when storing
at a temperature of 105°C.
TSTRESS = 105°C
TUSE = 85°C
AF = 2.8
So the overall retention of the flash would be degraded
by a factor of 2.8, reducing data retention from 20 years
at 85°C to 7.1 years at 105°C.
Operation
Once Eterna has completed start-up, Eterna transitions to
the operational group of states (active/CPU active, active/
CPU inactive, and Doze). There, Eterna cycles between the
various states, automatically selecting the lowest possible power state while fulfilling the demands of network
operation.
Active State
In the active state, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM Cortex-M3
59012ipmfa
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Operation
cycles between CPU-active and CPU-inactive (referred
to in the ARM Cortex-M3 literature as sleep now mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between active state and
doze state minimizes the time the CPU is active, significantly reducing Eterna’s energy consumption.
POWER-ON
RESET
Doze State
The doze state consumes orders of magnitude less current than the active state and is entered when all of the
peripherals and the CPU are inactive. In the doze state
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the doze state the 32.768kHz oscillator and associated timers are active.
VSUPPLY > PoR
RESETn LOW AND
FLASH_P_ENn LOW
LOAD FUSE
SETTINGS
RESETn LOW AND
FLASH_P_ENn HIGH
SET RESETn HIGH AND
FLASH_P_ENn HIGH
FOR 125µs, THEN
SET RESETn LOW
SERIAL FLASH
EMULATION
RESETn HIGH
AND
FLASH_P_ENn
HIGH
RESET
DEASSERT
RESETn
BOOT
START-UP
ASSERT RESETn
DOZE
ASSERT RESETn
CPU AND
PERIPHERALS
INACTIVE
HW OR PMU EVENT
OPERATION
ASSERT RESETn
CPU
ACTIVE
ACTIVE
CPU
INACTIVE
DEEP SLEEP
LOW POWER SLEEP
COMMAND
INACTIVE
59012ipm F15
Figure 15. Eterna State Diagram
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LTP5901-IPM/LTP5902-IPM
Operation
I2C Master
The I2C Master enables control of I2C slave devices,
including support for clock stretching slaves. I2C Multimaster and bus arbitration protocols are not supported.
For implementation details refer to the On-Chip Software
Development Kit (On-Chip SDK).
SPI Master
The Eterna SPI master controller supports all configurations
of clock polarity and phase, supporting shift clock frequencies of 460.8kHz, 921.6kHz, 1.8432MHz, or 3.6864MHz.
In addition the SPI master controller can be configured to
repetitively issue commands and capture the correspond-
ing output, enabling repetitive sampling of signals from a
SPI ADC or SPI sensor based upon a clock reference of
better than ±50ppm. For implementation details refer to
the On-Chip Software Development Kit (On-Chip SDK).
1-Wire Master
The Eterna 1-Wire Master controller supports the reset,
presence detect, read and write 1-Wire protocol operations,
incorporating an active pull-up. The active pull-up becomes
active when the passive pull-up raises the voltage on the
1_WIRE pin nominally above 1.4V, driving the 1_WIRE
signal as specified in Digital I/O Characteristics. For
implementation details refer to the On-Chip Software
Development Kit (On-Chip SDK).
59012ipmfa
30
For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
LTP5901-IPM/LTP5902-IPM
Applications Information
Modes of Operation
General Purpose Input-Output (GPIO) pins
n Analog-to-Digital Converter (ADC)
n Universal Asynchronous Receiver/Transmitter
(UART)
n Serial Peripheral Interface (SPI) Master
n Inter-Integrated Circuit (I2C) Master
n
The SmartMesh IP Mote software can be operated in three
distinct modes, namely, namely Slave, Master, and OnChip SDK. Mode selection should be considered during
the architecture/design phase of the development process.
Slave Mode
In Slave mode, the Eterna is connected to an external
microprocessor through the API UART and is solely used
as a networking device. None of the built in I/Os are accessible in this mode. Refer to the SmartMesh IP User's
Guide for more detailed information.
Master Mode
In Master mode, no external µProcessor is required and a
limited set of functionality is made available with no programming required on the device. The following features
are available
n On-Chip Temperature Sensor
n4 Analog Inputs
n4 Digital Inputs
n3 Digital Outputs
Refer to the SmartMesh IP User's Guide for more detailed
information.
On-Chip SDK (OCSDK)
The SmartMesh IP On-Chip Software Development Kit (OnChip SDK) enables development of C-code applications for
execution on the LTC5800-IPM, running Micrium’s µCOS-II
real-time operating system. With the On-Chip SDK, users
may quickly and easily develop application code without
the need for an external microprocessor.
Applications written within the On-Chip SDK may send
and receive wireless messages through the mesh network;
process data, such as statistical analysis; execute local
decision-making and control; and manage the following
peripherals:
1-Wire Master
n
Network connectivity and quality of service is handled by
the SmartMesh IP protocol stack. The SmartMesh IP stack
comes as a pre-compiled library and delivers >99.999%
data reliability while providing ultra low power operation.
Regulatory and Standards Compliance
Radio Certification
The LTP5901 and LTP5902 have been certified under a
single modular certification, with the module name of
ETERNA2. Following the regulatory requirements provided in the ETERNA2 User’s Guide enables customers
to ship products in the supported geographies, by simply
completing an unintentional radiator scan of the finished
product(s). The ETERNA2 User’s Guide also provides
the technical information needed to enable customers
to further certify either the modules or products based
upon the modules in geographies that have not or do not
support modular certification.
Compliance to Restriction of Hazardous Substances
(RoHS)
Restriction of Hazardous Substances 2 (RoHS 2) is a
directive that places maximum concentration limits on
the use of certain hazardous substances in electrical and
electronic equipment. Linear Technology is committed to
meeting the requirements of the European Community
directive 2011/65/EU.
59012ipmfa
For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
31
LTP5901-IPM/LTP5902-IPM
Applications Information
This product has been specifically designed to utilize
RoHS-compliant materials and to eliminate or reduce the
use of restricted materials to comply with 2011/65/EU.
The RoHS-compliant design features include:
RoHS-compliant solder for solder joints
Note: Customers may elect to use certain types of leadfree solder alloys in accordance with the European Community directive 2011/65/EU. Depending on the type of
solder paste chosen, a corresponding process change to
optimize reflow temperatures may be required.
n
RoHS-compliant base metal alloys
Soldering Information
RoHS-compliant precious metal plating
The LTP5901 and LTP5902 are suitable for both eutectic
PbSn and RoHS-6 reflow. The maximum reflow soldering temperature is 260°C. A more detailed description of
layout recommendations, assembly procedures and design
considerations is included in the LTP5901 and LTP5902
Hardware Integration Guide.
n
n
RoHS-compliant cable assemblies and connector
choices
n
RoHS-compliant and 245°C reflow compatible
n
Related Documentation
TITLE
LOCATION
DESCRIPTION
SmartMesh IP Users Guide
http://www.linear.com/docs/41880
Theory of operation for SmartMesh IP networks and motes
SmartMesh IP Mote API Guide
http://www.linear.com/docs/41886
Definitions of the applications interface commands available over
the API UART
SmartMesh IP Mote CLI Guide
http://www.linear.com/docs/41885
Definitions of the command line interface commands available
over the CLI UART
LTP5901 and LTP5902 Hardware
Integration Guide
http://www.linear.com/docs/41877
Recommended practices for designing with the LTP5901 and
LTP5902
ETERNA2 User’s Guide
http://www.linear.com/docs/42916
The ETERNA2 module user’s guide includes certification
requirements applicable to certified geographies and support
documentation enabling customer certification in additional
geographies for the LTP5901 and LTP5902
SmartMesh IP Tools Guide
http://www.linear.com/docs/42453
The user’s guide for all IP related tools, and specifically the
definition for the On-chip Application Protocol (OAP)
59012ipmfa
32
For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
LTP5901-IPM/LTP5902-IPM
Package Description
Please refer to http://www.linear.com/product/LTP5901#packaging for the most recent package drawings.
1
2
4
3
5
PC Package
66-Lead PCB (24mm × 42mm)
(Reference LTC DWG # 05-08-10002 Rev A)
D
.100
2.54
.039
1.00
.945
24.00
.039
1.00
1.57
40.00
.039
1.00
C
1.213
30.80
1.122
28.50
1.102
28.00
1.063
27.00
1.031
26.20
R.010 TYP
0.25
1.654
42.00
.039 TYP
1.00
B
.079
2.00
4X
.039
1.00
.035
0.90
0
0.00
.039
1.00
.87
22.00
.728
18.50
.630
16.00
.591
15.00
.551
14.00
.444
11.28
.394
10.00
.197
5.00
.236
6.00
.344
8.74
A
0
0.00
.157
4.00
.039
1.00
.08
2.00
.08
2.00
LTP5901 Mechanical Drawing
1
2
3
PROPRIETARY AND CONFIDENTIAL
THE INFORMATION CONTAINED IN THIS DRAWING IS THE S
PROPERTY OF LINEAR INCORPORATED. ANY REPRODUCT
IN PART OR AS A WHOLE WITHOUT THE WRITTEN PERMISS
OF LINEAR INCORPORATED IS PROHIBITED.
4
5
59012ipmfa
For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
33
LTP5901-IPM/LTP5902-IPM
Package Description
Please refer to http://www.linear.com/product/LTP5902#packaging for the most recent package drawings.
1
2
4
3
5
6
PC Package
66-Lead PCB (24mm × 37.5mm)
(Reference LTC DWG # 05-08-10003 Rev A)
D
.100
2.54
.177
4.50
.039
1.00
.945
24.00
.039
1.00
.029
0.73
1.40
35.50
1.272
32.30
C
.039
1.00
1.213
30.80
1.122
28.50
1.102
28.00
1.063
27.00
1.031
26.20
R.010 TYP
0.25
1.476
37.50
.039 TYP
1.00
B
4X
.035
0.90
.079
2.00
.039
1.00
0
0.00
.866
22.00
.591
15.00
.630
16.00
.728
18.50
.551
14.00
.394
10.00
.444
11.28
.344
8.73
.197
5.00
.236
6.00
.157
4.00
A
0
0.00
.071
1.80
.039
1.00
.078
2.0
.039
1.00
.079
2.01
DRN BY:
CHK:
APPD:
LTP5902 Mechanical Drawing
1
2
3
APPD:
PROPRIETARY AND CONFIDENTIAL
4
THE INFORMATION CONTAINED IN THIS DRAWING IS THE SOLE
PROPERTY OF LINEAR TECHNOLOGY CORPORATION. ANY
REPRODUCTION IN PART OR AS A WHOLE WITHOUT THE
WRITTEN PERMISSION OF LINEAR TECHNOLOGY
CORPORATION IS PROHIBITED.
5
6
59012ipmfa
34
For more information www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
PROJ MGR
PROD R
ENG
LTP5901-IPM/LTP5902-IPM
Revision History
REV
DATE
DESCRIPTION
A
11/15
Updated ordering part number
PAGE NUMBER
Added On-Chip SDK section
Added Software Installation section
5
23, 30, 31
27
59012ipmfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representationmore
that theinformation
interconnection
of its circuits as described herein will
infringe on existing patent rights.
For
www.linear.com/LTP5901-IPM
or not
www.linear.com/LTP5902-IPM
35
LTP5901-IPM/LTP5902-IPM
Typical Application
Mesh Network Thermistor
TADIRAN TL-5903
Li-SOCI2
LTP5902-IPM
ANTENNA
VSUPPLY
LT6654
VIN
IPCS_MISO
VOUT
0.1µF
0.1µF
GND2
5k
0.1%
AI_0
1000pF
59012ipm TA02
10k, 0.2C
OMEGA 4406
5k
0.1%
AI_1
GND
GND1
1000pF
5k
0.1%
RT = 5k • AI_0 / (2 • AI_1 – AI_0)
T(°C) = 1 / {A + B [Ln(RT)] + C[Ln(RT)]3} – 273.15
A = 1.032 • 10–3
B = 2.387 • 10–4
C = 1.580 • 10–7
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTC5800-IPM
IP Wireless Mote
Ultralow Power Mote, 72-Lead 10mm × 10mm QFN
LTP5901-IPR
IP Wireless Mesh Manager PCB Module with Chip Includes Modular Radio Certification in the United States, Canada, Europe, Japan,
Antenna
South Korea, Taiwan, India, Australia and New Zealand
LTP5902-IPR
IP Wireless Mesh Manager PCB Module with
MMCX Antenna Connector
LT6654
Precision High Output Drive Low Noise Reference 1.6ppm Peak-to-Peak Noise (0.1Hz to 10Hz, Sink/Source ±10mA, 5ppm/°C Max Drift
LTC2379-18
18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial,
Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC
LTC3388-1/
LTC3388-3
20V High Efficiency Nanopower Step-Down
Regulator
860nA IQ in Sleep, 2.7V to 20V Input, VOUT = 1.2V to 5V, Enable and Standby Pins
LTC3588-1
Piezoelectric Energy Generator with Integrated
High Efficiency Buck Converter
VIN = 2.7V to 20V, VOUT(MIN) = Fixed to 1.8V/2.5V/3.3V/3.6V, IQ = 0.95μA,
3mm × 3mm DFN-10 and MSOP-10E Packages
LTC3108-1
Ultralow Voltage Step-Up Converter and Power
Manager
VIN = 0.02V to 1V, VOUT = 2.5V/3V/3.7V/4.5V Fixed, IQ = 6μA, 3mm × 4mm DFN-12
and SSOP-16 Packages
LTC3459
Micropower Synchronous Boost Converter
VIN = 1.5V to 5.5V, VOUT(MAX) = 10V, IQ = 10μA, 2mm × 2mm DFN,
2mm × 3mm DFN or SOT-23 Package
Includes Modular Radio Certification in the United States, Canada, Europe, Japan,
South Korea, Taiwan, India, Australia and New Zealand
59012ipmfa
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas,
CA 95035-7417
For more information
www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTP5901-IPM or www.linear.com/LTP5902-IPM
LT 1115 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014