AN-1080:利用简单时序控制器ADM108x进行上电和关断时序控制

AN-1080
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Power-Up and Power-Down Sequencing Using the ADM108x Simple Sequencer
by Naiqian Ren
INTRODUCTION
The ADM108x simple sequencer can achieve simple sequencing
for two voltage rails during power-up with capacitor programmable
time delay. With the help of another device in the same family, a
simple circuit can achieve sequencing for both power-up and
power-down for two voltage rails with separate programmable
time delay, as shown in Figure 1. This application note describes
how to design such a circuit.
V
V1
T
POWER UP
POWER DOWN
Figure 1. Typical Sequencing Requirement for Power-Up and Power-Down
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09127-001
V2
AN-1080
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Timing Diagram ............................................................................4
Revision History ............................................................................... 2
Verification .........................................................................................5
Implementation................................................................................. 3
Schematic........................................................................................5
Circuit Design ............................................................................... 3
Test Results .....................................................................................6
REVISION HISTORY
6/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Application Note
AN-1080
IMPLEMENTATION
During power-up, C1 controls the time delay between VOUT1
and VOUT2, and during power-down, C2 controls the time delay
between VOUT2 and VOUT1.
CIRCUIT DESIGN
Figure 2 shows the block diagram of the circuit. The main
components of the circuit consist of two power regulators,
an N-type signal MOSFET, an ADM1085, and an ADM1087.
This circuit supports most dc-to-dc regulators with enable input.
An auxiliary supply, VAUX, is used to provide power separately
for the sequencing circuit. This can be substituted by VIN and
the details of the effect are described in the Timing Diagram
section.
The resistor divider at the input of the ADM1085 is used to
accurately monitor the first supply output, VOUT1. It ensures
that the first supply powers on before enabling VOUT2, which is the
second supply output. Alternatively, the VIN pin of the ADM1085
can connect directly to the power good output of the first regulator,
if available.
The initiation of the power-up and power-down sequencing is
controlled by the UP/DOWN logic signal.
VIN
VIN
VOUT1
VOUT1
VAUX
VIN
DC/DC
VOUT2
DC/DC
VCC ENOUT
VIN
EN1
VOUT2
EN2
ADM1085
ENIN
CEXT
VAUX
VAUX
C1
VN
VIN
VCC ENOUT
ADM1087
ENIN
CEXT
C2
Figure 2. Circuit Block Diagram
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09127-002
UP/DOWN
AN-1080
Application Note
TIMING DIAGRAM
TD
VAUX
VIN
UP/DOWN
EN1/ENOUT
T2
T2
VOUT1
T1
ENOUT/EN2
VOUT2
INITIAL
POWER UP
POWER UP
POWER DOWN
09127-003
VN
Figure 3. Circuit Timing Diagram
Figure 3 is an overview of the timing diagram for the circuit. It
consists of three phases: initial power-up, power-up sequencing,
and power-down sequencing.
During the initial power-up phase, the UP/DOWN signal is kept
low. After VAUX goes high, the ENOUT output of the ADM1087
goes high for the duration of T2, which is controlled by C2, and
then goes low. During this period, the first regulator may be briefly
enabled because EN1 is tied to ENOUT. The duration of the
first regulator being enabled during the initial power-up phase,
TON, is dependent on TD, the power-up delay between VAUX and
VIN, and T2 with the relationship TON = T2 − TD.
If TD > T2, for example, VAUX is powered up more than T2 seconds
before VIN, then the first regulator is not enabled during the initial
power-up phase. If the user chooses to substitute VAUX for VIN,
then TD is zero, and the regulator enables for the T2 duration
during the initial power-up phase.
In a system where a brief pulse of the first supply, during initial
power-up, does not cause any problems, it is recommend to use
VIN only for the circuit supply.
In the power-up sequencing phase, the sequencing is initiated by
pulling UP/DOWN high, which causes ENOUT of the ADM1087
to go high and thus enables the first regulator. When the output
of the first regulator is detected by the VIN pin of the ADM1085,
its ENOUT pin goes high after T1 seconds to enable the second
regulator. T1 is controlled by C1, which creates a programmable
delay between the two output voltages, VOUT1 and VOUT2, during
power-up. In this phase, the sequencing method is standard usage
of the ADM108x simple sequencer.
During the power-down sequencing phase, the sequencing
is initiated by the UP/DOWN signal being pulled low. The
immediate effect of this is that the ENIN pin of the ADM1085
goes low, and thus, so does its ENOUT pin. This disables the
second regulator through the EN2 pin as well as turns off the
NMOSFET by driving its gate low. When the FET is off, the VIN
pin of the ADM1087 goes high, and because ENIN is already
low, after T2 seconds its ENOUT output will go low, turning off the
first regulator through EN1. C2 controls T2, which creates a
programmable delay between the two output voltages, VOUT2
and VOUT1, during power-down.
Another option is for the user to tie the UP/DOWN signal to
VIN, in which case, the first regulator turns on autonomously
after VIN rises, and the second regulator is enabled T2 seconds
after the output of the first regulator becomes good.
Rev. 0 | Page 4 of 8
Rev. 0 | Page 5 of 8
GND
TP4
GND
2.2uF
GND
TP5
Vin
ADP1712
EN
GND
IN
U1
2.2uF
C2
3
2
1
GND
Vin
3
2
1
Figure 4. Schematic for Verification Circuit
4
ADP1712
EN
GND
IN
U2
ADJ
OUT
5
ADJ
OUT
4
5
GND
R4
3.3k
R1
10k
R6
10k
R3
9.1k
GND
GND
R5
3.3k
R2
10k
GND
C3
2.2uF
Vout1
GND
C4
2.2uF
Vout2
GND
GND
R9
200
3V3
GND
R1 0
200
1V5
3
2
1
ADM1085/6
VIN
GND
ENIN
U3
UP/DOWN
ENOUT
CE XT
VCC
C5
4 2.2 nF
5
Vaux
6
Vcc
TP1
Vin
GND
GND
GND
Vaux
TP3
3
2
1
GND
Q1
FET-N_SOT-23
R7
10k
Vaux
NO POP
R8
Vaux
TP2
ADM1087/8
VIN
GND
ENIN
U4
Gnd
ENOUT
CE XT
VCC
C6
4 4.7 nF
5
Vaux
6
GND
09127-004
C1
Application Note
AN-1080
VERIFICATION
SCHEMATIC
AN-1080
Application Note
TEST RESULTS
Channel 1: VOUT1 (gold), Channel 2: VOUT2 (pink), Channel 3: UP/DOWN (blue), and Channel 4: VIN (green).
C3
C1
DC1M
1.00V/DIV
–3.040V OFST
3.174V
2.285V
Δy
–889mV
C2
DC1M
1.00V/DIV
–3.050V OFST
746mV
16mV
Δy
–730mV
P2: AMPL (C2)
1.437V
C3
P3: AMPL (C3)
4.739V
P4: DELAY (C1)
1.1µs
DC1M
P5: DELAY (C2)
10.4797ms
P6:– –
TBASE
–40.0ms TRIGGER C1 DC
10.0ms/DIV NORMAL
1.58V
10.0kS
100kS/s EDGE
POSITIVE
X1 =
40.06ms
ΔX = 23.57ms
63.63ms
X2 =
1/ΔX = 42.43Hz
2.00V/DIV
–6.080V OFST
–12V
–38V
Δy
–26V
09127-005
P1: AMPL (C1)
3.176V
MEASURE
VALUE
STATUS
Figure 5. Test Plot Overview
C3
C1
P1: AMPL (C1)
3.188V
DC1M
1.00V/DIV
–3.040V OFST
2.920V
3.225V
305mV
Δy
C2
DC1M
1.00V/DIV
–3.050V OFST
10mV
1.447V
1.437V
Δy
P2: AMPL (C2)
1.437V
C3
P3: AMPL (C3)
4.762V
P4: DELAY (C1)
1.60µs
DC1M
P5: DELAY (C2)
10.48083ms
P6:– –
TBASE
–8.00ms TRIGGER C1 DC
2.00ms/DIV NORMAL
1.58V
10.0kS
500kS/s EDGE
POSITIVE
X1 =
12µs
ΔX = 10.482ms
X2 = 10.494ms
1/ΔX = 95.40Hz
2.00V/DIV
–6.080V OFST
4.743V
4.743V
0mV
Δy
Figure 6. Close-Up Look at the Power-Down Phase
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09127-006
MEASURE
VALUE
STATUS
Application Note
AN-1080
C3
C1
P1: AMPL (C1)
3.188V
DC1M
1.00V/DIV
–3.040V OFST
3.200V
1.600V
–1.600V
Δy
C2
DC1M
1.00V/DIV
–3.050V OFST
1.429V
0mV
–1.429V
Δy
P2: AMPL (C2)
1.435V
C3
P3: AMPL (C3)
4.759V
P4: DELAY (C1)
23.48255ms
DC1M
P5: DELAY (C2)
–123.48µs
P6:– –
TBASE
–20.0ms TRIGGER C1 DC
5.00ms/DIV NORMAL
400mV
10.0kS
200kS/s EDGE
POSITIVE
X1 =
–260µs
ΔX = 23.745ms
X2 = 23.485ms
1/ΔX = 42.114Hz
2.00V/DIV
–6.080V OFST
1.495V
0mV
–1.495V
Δy
09127-007
MEASURE
VALUE
STATUS
Figure 7. Close-Up Look at the Power-Up Phase
C3
C1
P1: AMPL (C1)
3.196V
DC1M
1.00V/DIV
–3.040V OFST
2.438V
2.054V
–384mV
Δy
C2
DC1M
1.00V/DIV
–3.050V OFST
36mV
4mV
–32mV
Δy
P2: AMPL (C2)
224mV
C4
P3: AMPL (C3)
384mV
P4: DELAY (C1)
1.16µs
DC1M
P5: DELAY (C2)
–––
!
P6:– –
TBASE
–12.9ms TRIGGER C1 DC
5.00ms/DIV NORMAL
1.58V
10.0kS
200kS/s EDGE
POSITIVE
X1 =
60µs
ΔX = 22.240ms
X2 = 22.300ms
1/ΔX = 44.96Hz
2.00V/DIV
–6.080V OFST
2.356V
4.940V
2.584V
Δy
Figure 8. Initial Power-Up Phase
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09127-008
MEASURE
VALUE
STATUS
AN-1080
Application Note
NOTES
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AN09127-0-6/10(0)
Rev. 0 | Page 8 of 8
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