Lithium Ion Battery Safety Monitor AD8280 Data Sheet FEATURES GENERAL DESCRIPTION Wide supply voltage range: 6.0 V to 30.0 V Multiple inputs can monitor 3 to 6 cell voltages and 2 temperatures Adjustable threshold levels: overvoltage, undervoltage, overtemperature Alarm options: separate or shared alarms Extended temperature range performance −40°C ≤ TA ≤ +105°C Can be daisy-chained Internal reference Powered from battery stack LDO available to power isolator Qualified for automotive applications Extensive self-test feature aids in meeting ASIL/SIL requirements The AD8280 is a hardware-only safety monitor for lithium ion battery stacks. The part has inputs to monitor six battery cells and two temperature sensors (either NTC or PTC thermistors). The part is designed to be daisy-chained with other AD8280 devices to monitor a stack of significantly more than six cells without the need for numerous isolators. Its output can be configured for an independent or shared alarm state. The AD8280 functions independently from a primary monitor and contains its own reference and LDO, both of which are powered completely from the battery cell stack. The reference, in conjunction with external resistor dividers, is used to establish trip points for the overvoltages and undervoltages. Each cell channel contains programmable deglitching circuitry to prevent alarms from transient input levels. The AD8280 also has two digital pins that can be used to select various combinations of inputs in the case where fewer than six cells are to be monitored. Most important, it has a self-test feature, making it suitable for high reliability applications, such as automotive hybrid electric vehicles or higher voltage industrial usage, such as uninterruptible power supplies. The AD8280 can function over a temperature range of −40°C to +105°C. APPLICATIONS Lithium ion battery backup monitor and threshold detection Electric and hybrid electric vehicle Industrial vehicle Uninterruptible power supply Wind and solar FUNCTIONAL BLOCK DIAGRAM OT AIINOV AIINUV AIINOT ENBO VTOP LDO LDOS REF FB UV TESTO OV DGT0 VTOPS LEVEL SHIFTER VBOT2 VBOT2S LDO REF DGT1 DGT2 VBOT1 GND2 VBOT1S VIN6 GND1 C6O DEGLITCHING C6U DEGLITCHING LEVEL SHIFTER I/V CONVERTER SELFTEST GENERATOR VCC VCCS VIN5 TOP VIN4 BOT VIN3 VIN2 SEL0 VIN1 DEGLITCHING C1U DEGLITCHING CT1 DEGLITCHING CT2 DEGLITCHING LEVEL SHIFTER SEL 1 AVOUTOV AVOUTUV VT1 AVOUTOT V/I CONVERTER VT2 NPTC AD8280 ALRMSEL OT OT AIOUTOV AIOUTUV AIOUTOT ENBI TESTI 08911-001 VIN0 C1O ALARM LOGIC Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8280 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Number of Cells Selection......................................................... 17 Applications ....................................................................................... 1 Threshold Inputs ........................................................................ 17 General Description ......................................................................... 1 Top and Bottom Part Designation ........................................... 18 Functional Block Diagram .............................................................. 1 Typical Daisy-Chain Connections ........................................... 18 Revision History ............................................................................... 2 Shared or Separate Alarms ........................................................ 18 Specifications..................................................................................... 3 Deglitching Options ................................................................... 18 Absolute Maximum Ratings............................................................ 5 Enabling and Disabling the AD8280 ....................................... 20 Thermal Resistance ...................................................................... 5 Alarm Output ............................................................................. 20 ESD Caution .................................................................................. 5 Self-Test ....................................................................................... 20 Pin Configuration and Function Descriptions ............................. 6 Protection Components and Pull-Up/Pull-Down Resistors ..... 23 Typical Performance Characteristics ............................................. 8 EMI Considerations ................................................................... 23 Theory of Operation ...................................................................... 15 System Accuracy Calculation ................................................... 23 Applications Information .............................................................. 16 Outline Dimensions ....................................................................... 24 Typical Connections .................................................................. 16 Ordering Guide .......................................................................... 24 Cell Inputs ................................................................................... 16 Automotive Products ................................................................. 24 Temperature Inputs and Thermistor Selection ...................... 16 REVISION HISTORY 8/14—Rev. C to Rev. D Changes to Table 2 ............................................................................ 5 7/11—Rev. B to Rev. C Changes to Self-Test Completion Time, tST Parameter and SelfTest Valid Time, tSTV Parameter in Table 1 .................................... 3 6/11—Rev. A to Rev. B Changes to Table 1, Dynamic Performance, Self-Test Valid Time, tstv Parameter ................................................................ 4 Change to Figure 36, Figure 37, and Figure 39 ........................... 13 7/10—Rev. 0 to Rev. A Change to Logic 1 Voltage Input, VIH Parameter in Table 1 ........3 Changes to Temperature Inputs and Thermistor Selection Section.............................................................................................. 17 Added Figure 46; Renumbered Figures Sequentially ................ 17 Changes to Endnote 1 in Table 6 .................................................. 18 Changes to Ordering Guide .......................................................... 24 4/10—Revision 0: Initial Version Rev. D | Page 2 of 24 Data Sheet AD8280 SPECIFICATIONS VTOP = 7.5 V to 30 V, TA = −40°C to +105°C, unless otherwise noted. Table 1. Parameter TRIP POINT ERRORS Undervoltage Trip Point Error Overvoltage Trip Point Error Overtemperature Trip Point Error Hysteresis for Overvoltage, Undervoltage, and Overtemperature Trip Points CELL INPUTS (VIN0 TO VIN6) Input Bias Current Input Offset Current Input Voltage Range Input Common-Mode Range TEMPERATURE INPUTS (VT1, VT2) Input Bias Current Input Voltage Range OVERVOLTAGE THRESHOLD INPUT (OV) Input Bias Current Input Voltage Range UNDERVOLTAGE THRESHOLD INPUT (UV) Input Bias Current Input Voltage Range OVERTEMPERATURE THRESHOLD INPUT (OT) Input Bias Current Input Voltage Range INPUT/OUTPUT CHARACTERISTICS Logic 1 Current Logic 0 Current Logic 1 Voltage Input, VIH All Pins Except TOP and BOT TOP and BOT Pins Logic 0 Voltage Input, VIL All Pins Except TOP and BOT TOP and BOT Pins Logic 1 Voltage Output, VOH Logic 0 Voltage Output, VOL Input Bias Current REFERENCE AND LDO Reference Voltage Reference Source Current LDO Voltage LDO Source Current DYNAMIC PERFORMANCE Fault Detection (Deglitch) Time Range Fault Detection (Deglitch) Accuracy Propagation Delay Time Start-Up Time Test Conditions/Comments Min Typ Max Unit 50 +25 +15 +25 60 mV mV mV mV 0 0 0 0 20 20 5 Top of stack nA nA V V −10 0 +10 5 nA V 0 3.6 20 4.6 nA V 0 1.4 20 3.3 nA V 0 1.5 20 4 nA V 200 50 µA µA LDO V V 0.8 VBOT 0.2 1 V V V V µA 5.05 250 5.35 5.0 V µA V mA 12.8 sec +20 % µs ms −25 −15 −25 40 One cell AIINxx, AIOUTxx AIINxx, AIOUTxx With respect to VBOTx 100 10 150 30 2.0 VTOP With respect to VBOTx With respect to VBOTx With respect to VBOTx SEL0, SEL1, DGT0, DGT1, DGT2, NPTC, ALRMSEL 4.2 4.95 5.0 0 mA ≤ LDO source current ≤ 10.0 mA 4.85 5.1 Seven settings: 0.0 sec, 0.1 sec, 0.8 sec, 1.6 sec, 3.2 sec, 6.4 sec, and 12.8 sec 0.0 −20 No capacitor on daisy chain From application enabled to LDO = 90% of value Rev. D | Page 3 of 24 4.0 3.0 AD8280 Parameter Self-Test Completion Time, tST Self-Test Valid Time, tSTV Delay Time for Self-Test Start, tRE Delay Time for Data Valid, tFE Rise Time for Self-Test Pulse, tR POWER SUPPLY Supply Voltage Range Quiescent Current Power Supply Enabled Power Supply Disabled Data Sheet Test Conditions/Comments Deglitch time = 0.0 sec Deglitch time > 0.0 sec Min 40 800 0.0 10 4.0 TESTI VTOP with respect to VBOTx LDO source current = 10.0 mA LDO source current = 0.0 mA Excluding LDO source current Rev. D | Page 4 of 24 7.5 6.0 Typ Max 50 1000 3.5 100 5.0 1.0 Unit ms ms µs ns µs ms 30 30 V V 2.0 1.0 mA µA Data Sheet AD8280 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VTOP to VBOTx VIN0 to VBOTx VIN1 Through VIN5 Voltage to VBOTx VIN6 to VBOTx VIN6 to VTOP VTx to VBOTx TESTI, ENBI to GNDx DGTx, SELx, NPTC to GNDx AVOUTxx to GNDx TOP, BOT to VBOTx Rating −0.3 V to +33 V −0.3 V to LDO + 0.3 V −0.3 V to VTOP + 0.3 V −0.3 V to VTOP + 1.0 V −0.3 V to + 1.0 V −0.3 V to LDO + 0.3 V −0.3 V to LDO + 0.3 V −0.3 V to LDO + 0.3 V −0.3 V to LDO + 0.3 V −0.3 V to VTOP + 0.3 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 48-Lead LQFP (ST-48) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 5 of 24 θJA 54 θJC 15 Unit °C/W AD8280 Data Sheet TOP BOT TESTO AIINOV AIINUV AIINOT ENBO REF FB LDOS LDO VCCS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 VBOT2 1 36 VCC VBOT2S 2 35 GND1 VBOT1S 3 34 GND2 VBOT1 4 33 NPTC VIN0 5 32 ALRMSEL VIN1 6 VIN2 7 30 DGT1 VIN3 8 29 SEL0 VIN4 9 28 SEL1 VIN5 10 27 AVOUTOV VIN6 11 26 AVOUTUV VTOP 12 25 AVOUTOT PIN 1 19 20 21 22 23 24 OV UV OT DGT2 VT2 18 ENBI VT1 17 AIOUTOT VTOPS 16 AIOUTUV 15 AIOUTOV 14 TESTI 13 08911-002 31 DGT0 AD8280 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mnemonic VBOT2 VBOT2S VBOT1S VBOT1 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VTOP VTOPS VT1 VT2 TESTI AIOUTOV AIOUTUV AIOUTOT ENBI OV UV OT DGT2 AVOUTOT AVOUTUV AVOUTOV Description Lowest Potential of Six-Cell Stack. Lowest Potential of Six-Cell Stack. Tie to VBOT2. Lowest Potential of Six-Cell Stack. Tie to VBOT1. Lowest Potential of Six-Cell Stack. Input Voltage for Bottom of Cell 1. Input Voltage for Bottom of Cell 2/Top of Cell 1. Input Voltage for Bottom of Cell 3/Top of Cell 2. Input Voltage for Bottom of Cell 4/Top of Cell 3. Input Voltage for Bottom of Cell 5/Top of Cell 4. Input Voltage for Bottom of Cell 6/Top of Cell 5. Input Voltage for Top of Cell 6. Highest Potential of Six-Cell Stack. Highest Potential of Six-Cell Stack. Tie to VTOP. Temperature Input 1. Temperature Input 2. Test Input. Alarm Current Output, Overvoltage. Used in daisy-chain configuration. Alarm Current Output, Undervoltage. Used in daisy-chain configuration. Alarm Current Output, Overtemperature. Used in daisy-chain configuration. Enable Input. When ENBI is logic high, the part is enabled; when ENBI is logic low, the part is disabled. Overvoltage Trip Point. Undervoltage Trip Point. Overtemperature Trip Point. Digital Select Pin 2. Used with DGT0 and DGT1 to select deglitch time (see Table 7). Alarm Voltage Output, Overtemperature. Alarm Voltage Output, Undervoltage. Alarm Voltage Output, Overvoltage. Rev. D | Page 6 of 24 Data Sheet Pin No. 28 29 30 31 32 Mnemonic SEL1 SEL0 DGT1 DGT0 ALRMSEL 33 NPTC 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 GND2 GND1 VCC VCCS LDO LDOS FB REF ENBO AIINOT AIINUV AIINOV TESTO BOT TOP AD8280 Description Digital Select Pin 1. Used with SEL0 to select channels to be used (see Table 5). Digital Select Pin 0. Used with SEL1 to select channels to be used (see Table 5). Digital Select Pin 1. Used with DGT0 and DGT2 to select deglitch time (see Table 7). Digital Select Pin 0. Used with DGT1 and DGT2 to select deglitch time (see Table 7). Selects three separate alarms or one shared alarm. When ALRMSEL is logic high, three separate alarms are selected; when ALRMSEL is logic low, one shared alarm is selected. Selects NTC or PTC thermistor for VTx inputs. When NPTC is tied to logic high (LDO pin), a PTC thermistor is selected; when NPTC is tied to logic low (VBOTx pin), an NTC thermistor is selected. Ground. Tie to same potential as VBOT1 and VBOT2. Ground. Tie to same potential as VBOT1 and VBOT2. Supply Voltage. Tie to LDO. Supply Voltage Sense. Tie to LDO. LDO Output. Tie to VCC, VCCS, and LDOS. LDO Output Sense. Tie to LDO. Feedback Pin. Tie to REF. Reference Output. Tie to FB. Enable Output. Alarm Current Input, Overtemperature. Used in daisy-chain configuration. Alarm Current Input, Undervoltage. Used in daisy-chain configuration. Alarm Current Input, Overvoltage. Used in daisy-chain configuration. Test Output. Used to identify part at lowest potential in daisy chain (see Table 6). Used to identify part at highest potential in daisy chain (see Table 6). Rev. D | Page 7 of 24 AD8280 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS SAMPLE SIZE = 2726 SAMPLE SIZE = 2726 1400 1800 UNDERVOLTAGE OVERVOLTAGE 1200 NUMBER OF HITS UNDERVOLTAGE OVERVOLTAGE 1200 900 600 800 600 400 200 08911-003 300 0 –30 1000 –20 –10 0 10 20 0 –30 30 08911-006 NUMBER OF HITS 1500 –20 Figure 3. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN0 and VIN1 UNDERVOLTAGE OVERVOLTAGE 1000 800 600 400 2400 SAMPLE SIZE = 2726 2100 UNDERVOLTAGE OVERVOLTAGE 1500 1200 900 08911-004 –20 –10 0 10 20 300 0 –30 30 –20 TRIP POINT ERROR (mV) –10 0 10 20 30 TRIP POINT ERROR (mV) Figure 4. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN1 and VIN2 Figure 7. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN4 and VIN5 1800 SAMPLE SIZE = 2726 SAMPLE SIZE = 2726 1800 UNDERVOLTAGE OVERVOLTAGE 1500 UNDERVOLTAGE OVERVOLTAGE NUMBER OF HITS 1500 1200 900 600 1200 900 600 300 –20 –10 0 10 20 0 –30 30 TRIP POINT ERROR (mV) 08911-008 300 08911-005 NUMBER OF HITS 30 600 200 0 –30 20 1800 NUMBER OF HITS NUMBER OF HITS 1200 0 –30 10 Figure 6. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN3 and VIN4 SAMPLE SIZE = 2726 1400 0 08911-007 1600 –10 TRIP POINT ERROR (mV) TRIP POINT ERROR (mV) –20 –10 0 10 20 TRIP POINT ERROR (mV) Figure 5. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN2 and VIN3 Figure 8. Overvoltage and Undervoltage Trip Point Error, Voltage Between VIN5 and VIN6 Rev. D | Page 8 of 24 30 Data Sheet AD8280 SAMPLE SIZE = 2726 SAMPLE SIZE = 2726 250 180 150 NUMBER OF HITS NUMBER OF HITS 200 150 100 120 90 60 50 0 –5 –4 –3 –2 –1 08911-012 08911-009 30 0 4.8 0 4.9 5.0 TRIP POINT ERROR (mV) Figure 9. Overtemperature Trip Point Error 180 300 150 120 90 250 200 150 60 100 30 50 47 48 49 50 0 1.2 51 08911-113 NUMBER OF HITS 350 08911-010 NUMBER OF HITS 5.4 SAMPLE SIZE = 2726 210 1.3 1.4 Figure 10. Overvoltage, Undervoltage, and Overtemperature Hysteresis 1.7 1.8 1.9 0.04 0.05 600 SAMPLE SIZE = 2726 500 400 400 NUMBER OF HITS 500 300 200 100 5.00 5.02 5.04 300 200 0 –0.02 5.06 REFERENCE VOLTAGE (V) 08911-114 100 08911-011 4.98 1.6 Figure 13. Supply Current SAMPLE SIZE = 2726 4.96 1.5 SUPPLY CURRENT (mA) HYSTERESIS (mV) NUMBER OF HITS 5.3 400 SAMPLE SIZE = 2726 0 4.94 5.2 Figure 12. LDO Voltage 240 0 5.1 LDO VOLTAGE (V) –0.01 0 0.01 0.02 0.03 SHUTDOWN CURRENT (µA) Figure 14. Supply Current, Power-Down Mode Figure 11. Reference Voltage Rev. D | Page 9 of 24 AD8280 Data Sheet 75 25 VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 15 10 5 VIN1 TO VIN2 AND VIN5 TO VIN6 0 –5 –10 –15 65 60 55 50 45 40 35 –10 30 10 50 70 90 110 TEMPERATURE (°C) 25 –50 08911-013 –30 50 70 90 110 15 10 VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 70 UNDERVOLTAGE HYSTERESIS (mV) 5 0 –5 –10 VIN2 TO VIN3 AND VIN3 TO VIN4 –15 65 60 55 50 45 40 35 –10 30 10 50 70 90 110 TEMPERATURE (°C) 25 –50 08911-014 –30 70 OVERTEMPERATURE HYSTERESIS (mV) 75 8 6 4 2 0 –2 VT2 VT1 –10 10 30 50 TEMPERATURE (°C) 70 90 110 08911-015 –8 –30 10 30 50 70 90 110 Figure 19. Undervoltage Hysteresis vs. Temperature 10 –6 –10 TEMPERATURE (°C) Figure 16. Undervoltage Error vs. Temperature –4 –30 08911-017 30 –20 Figure 17. Overtemperature Error vs. Temperature 65 60 55 VT1 50 45 VT2 40 35 30 25 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 20. Overtemperature Hysteresis vs. Temperature Rev. D | Page 10 of 24 110 08911-018 UNDERVOLTAGE ERROR (mV) 30 75 VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 20 OVERTEMPERATURE ERROR (mV) 10 Figure 18. Overvoltage Hysteresis vs. Temperature 25 –10 –50 –10 TEMPERATURE (°C) Figure 15. Overvoltage Error vs. Temperature –25 –50 –30 08911-016 30 –20 –25 –50 VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 70 OVERVOLTAGE HYSTERESIS (mV) OVERVOLTAGE ERROR (mV) 20 AD8280 ENABLED SUPPLY CURRENT (mA) TRIP POINT ERROR (mV) 10 VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 5 0 –5 –15 6 10 14 18 22 26 30 STACK VOLTAGE (V) 2.5 2.0 2.0 1.5 1.0 1.0 DISABLED 0.5 0.5 0 0 6 10 14 18 22 26 30 STACK VOLTAGE (V) Figure 24. Supply Current vs. Stack Voltage (VIN6 – VIN0) Figure 21. Overvoltage Trip Point Error vs. Stack Voltage (VIN6 – VIN0) 1.40 5 0 1.35 SUPPLY CURRENT (mA) TRIP POINT ERROR (mV) 1.5 ENABLED 08911-019 –10 2.5 08911-022 15 DISABLED SUPPLY CURRENT (µA) Data Sheet VOLTAGE BETWEEN VIN0 AND VIN1 VIN1 AND VIN2 VIN2 AND VIN3 VIN3 AND VIN4 VIN4 AND VIN5 VIN5 AND VIN6 –5 –10 –15 1.30 STACK VOLTAGE = 7.5V STACK VOLTAGE = 18V STACK VOLTAGE = 29.8V 1.25 1.20 6 10 14 18 22 26 30 STACK VOLTAGE (V) 1.15 –50 08911-020 –25 –10 –30 30 50 10 TEMPERATURE (°C) 70 90 110 08911-023 –20 Figure 25. Enabled Supply Current vs. Temperature for Various Stack Voltages (VIN6 – VIN0) Figure 22. Undervoltage Trip Point Error vs. Stack Voltage (VIN6 – VIN0) 10 5.5 8 5.0 6 4.5 LDO 4.0 2 3.5 0 3.0 –2 6 10 14 18 22 26 30 STACK VOLTAGE (V) 2.5 0 5 10 15 20 25 30 SOURCE CURRENT (mA) Figure 26. LDO and Reference Voltage vs. LDO Source Current, Stack Voltage = 7.5 V Figure 23. Input Bias Current vs. Stack Voltage (VIN6 – VIN0) Rev. D | Page 11 of 24 08911-029 VOLTAGE (V) 4 08911-123 BIAS CURRENT (nA) REF AD8280 Data Sheet 5.5 5.08 LDO 5.07 LDO 5.0 5.06 REF 5.05 VOLTAGE (V) VOLTAGE (V) 4.5 4.0 5.04 5.03 5.02 3.5 5.01 5.00 3.0 REF 4.99 5 15 10 20 25 30 SOURCE CURRENT (mA) 4.98 Figure 27. LDO and Reference Voltage vs. LDO Source Current, Stack Voltage = 18.0 V 10 6 14 22 18 30 STACK VOLTAGE (V) Figure 30. LDO and Reference Voltage vs. Stack Voltage (VIN6 – VIN0) 10 35 VIN0 VIN2 VIN4 VIN6 VT1 UV 8 30 LDO 6 25 BIAS CURRENT (nA) SOURCE CURRENT (mA) 26 08911-033 0 08911-030 2.5 20 15 10 REF 4 VIN1 VIN3 VIN5 VT2 OV OT 2 0 –2 –4 –6 5 –10 30 10 50 70 90 110 TEMPERATURE (°C) 08911-031 –30 –10 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) Figure 28. LDO and Reference Source Current vs. Temperature 110 08911-034 –8 0 –50 Figure 31. Input Bias Current vs. Temperature 5.11 5.09 LDO 5V/DIV 5.05 5.03 OV 1 5.01 REF 4.99 4.95 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) 110 20ns/DIV Figure 32. Alarm Rise Time Figure 29. LDO and Reference Voltage vs. Temperature Rev. D | Page 12 of 24 08911-035 4.97 08911-032 VOLTAGE (V) 5.07 Data Sheet AD8280 OV 1 5V/DIV OV UV 1 2 OT TESTI 4 Figure 33. Alarm Fall Time CH1 5V CH3 5V M200ms 1.25ks/s A CH4 2.4V 800µs/pt Figure 36. TESTI and AVOUTxx, Deglitch Time = 0.1 sec, Self-Test Passes OV OV 1 1 UV 2 UV 2 OT OT 3 TESTI 4 20ms/DIV 08911-024 3 TESTI 4 Figure 34. TESTI and AVOUTxx, Deglitch Time = 0.0 sec, Self-Test Passes CH1 5V CH3 5V CH2 5V CH4 5V M200ms 1.25ks/s A CH4 2.4V 800µs/pt 08911-049 5V/DIV CH2 5V CH4 5V 08911-048 20ns/DIV 08911-036 3 Figure 37. TESTI and AVOUTxx, Deglitch Time = 0.1 sec, Self-Test Fails (UV) OV OV 1 UV TESTI 5V/DIV 5V/DIV 1 2 2 OT 20ms/DIV Figure 35. TESTI and AVOUTxx, Deglitch Time = 0.0 sec, Self-Test Fails (UV) Rev. D | Page 13 of 24 4µs/DIV Figure 38. TESTI Edge and AVOUTxx, Self-Test Fails (Enlarged) 08911-038 TESTI 4 08911-025 3 AD8280 Data Sheet OV OV 1 5V/DIV 1 UV 2 CELL ALARM TRIPPED 2 OT CH1 5V CH3 5V CH2 5V CH4 5V M400ms 625s/s A CH4 2.4V 1.6ms/pt 200ms/DIV Figure 39. Alarm Condition Entering Self-Test, Part Passes Self-Test 08911-139 TESTI 4 08911-050 3 Figure 42. Cell Voltage Change to Trip Alarm, Deglitch Time = 800 ms TESTI 4 OV 5V/DIV 5V/DIV 1 OV 1 CELL 2 ALARM TRIPPED UV OT 3 1sec/DIV 4µs/DIV Figure 40. Alarm Condition Entering Self-Test, Part Passes Self-Test (Enlarged) Figure 43. Cell Voltage Change to Trip Alarm, Deglitch Time = 3.2 sec 1 ENBI OV 5V/DIV 2 REF 3 TESTI 08911-028 4 1ms/DIV 08911-140 08911-143 2 Figure 41. Start-Up Time Rev. D | Page 14 of 24 Data Sheet AD8280 THEORY OF OPERATION Figure 44 shows a block diagram of the AD8280. The AD8280 is a threshold monitor that can be used to monitor up to six cell voltages and two temperature voltages. The part can also be used in a daisy-chain configuration to monitor as many cells as required. The benefit of the daisy-chain configuration is that isolation is required to bring the alarm signal away from the high voltage environment on only the bottom part of the chain, reducing system cost and minimizing the board space required. The part also contains its own LDO and reference. The LDO can be used to drive external components such as thermistors or isolators, whereas the reference can be used with the voltage dividers to establish the trip points. The cell and temperature voltage inputs are connected to the part using the VIN0 through VIN6 inputs and the VT1 and VT2 inputs, respectively. Because the six-cell stack voltage can be up to 30 V, the input voltages are level-shifted and referenced to the lowest potential (part ground or VBOTx) of the AD8280. These voltages are then input into window comparators and compared to trip points set by external resistor dividers. The AD8280 has the following unique features and capabilities: Three, four, five, or six cells can be monitored. Negative or positive temperature coefficient thermistors can be used. Multiple parts can be configured in a daisy chain to monitor hundreds of cells. Information about the status of the alarms on the entire daisy chain, as well as input signals that enable the part and initiate self-test, are all communicated via the bottom, or master, part in the chain. Alarm outputs for overvoltage, undervoltage, and overtemperature status can be shared, with each output indicating the same status for any of the occurring alarm conditions, or the alarm outputs can function as separate entities with each indicating the status of the specific condition. An extensive self-test feature ensures that the internal components are functioning correctly. The self-test is initiated upon request to the TESTI pin. If the cell or temperature voltage inputs exceed or fall below the selected trip points, an alarm, in the form of a digital voltage level, changes state at the voltage output (AVOUTxx) of the part. The alarm state also exists in the form of a current output (AIOUTxx) used to communicate to the other devices when multiple parts are used in a daisy-chain configuration. The part contains programmable deglitching circuitry to ensure that transient voltages appearing at the cell inputs are ignored. OT LDOS REF VTOP LDO FB UV OV AIINOV AIINUV AIINOT ENBO TESTO DGT0 VTOPS LEVEL SHIFTER VBOT2 VBOT2S LDO REF DGT1 DGT2 VBOT1 GND2 VBOT1S VIN6 VIN5 C6O DEGLITCHING C6U DEGLITCHING LEVEL SHIFTER I/V CONVERTER SELFTEST GENERATOR GND1 VCC VCCS TOP VIN4 BOT VIN3 VIN2 SEL0 VIN1 DEGLITCHING C1U DEGLITCHING CT1 DEGLITCHING CT2 DEGLITCHING LEVEL SHIFTER SEL 1 AVOUTOV VT1 VT2 AVOUTUV AVOUTOT V/I CONVERTER NPTC AD8280 OT ALRMSEL OT AIOUTOV AIOUTUV AIOUTOT Figure 44. Functional Block Diagram Rev. D | Page 15 of 24 ENBI TESTI 08911-039 VIN0 C1O ALARM LOGIC AD8280 Data Sheet APPLICATIONS INFORMATION TYPICAL CONNECTIONS TEMPERATURE INPUTS AND THERMISTOR SELECTION Figure 45 is a block diagram of the AD8280 typical connections. VT1 and VT2 are voltage inputs and are designed to work with thermistors that are configured as resistor dividers, as shown in Figure 45. The voltage at the top of the thermistor divider should be the +5 V output of the LDO. The LDO pin can source more current than the REF pin and is better suited to drive the thermistor dividers. CELL INPUTS The battery stack of six cells should be connected to VIN0 through VIN6, with the highest potential connected to VIN6 and the lowest to VIN0. The connections should be made through a low-pass filter consisting of a 10 kΩ resistor and a 10 nF capacitor, as shown in Figure 45. The lowest potential of the six-cell stack should also be connected to VBOT1, VBOT1S, VBOT2, and VBOT2S as well, whereas the highest potential should be connected through a diode to VTOP and VTOPS. It is recommended that decoupling capacitors of 0.1 μF and 10 μF be used at the VTOP pin. If a voltage source other than that of the AD8280 LDO is used to drive the thermistor bridge (VTH), it is important that the VT1 and VT2 voltages be brought to 0 V when the AD8280 is disabled or powered down because the VT1 and VT2 inputs must be at 0 V when the LDO is also at 0 V. 100nF Z1 10µF 0.1µF PART GROUND VTOP VTOPS AIINOV AIINUV AIINOT ENBO TESTO UV OV OT FB REF VCC VCCS 0.1µF 10kΩ 10nF + + + + + + LDO AVOUTOV LDOS AVOUTUV UV REF OV REF OT REF 2.2µF AVOUTOT VIN6 VIN5 0.1µF VIN4 VIN3 AD8280 TOP BOT VIN2 ALRMSEL VIN1 DGT2 VIN0 DGT1 VT1 VT2 DGT0 VBOT2S NPTC VBOT2 SEL0 VBOT1S SEL1 VBOT1 AIOUTOV AIOUTUV AIOUTOT ENBI TESTI GND1 GND2 22pF PART GROUND 08911-040 NOTES 1. PART IS CONFIGURED AS FOLLOWS: MIDDLE PART IN DAISY CHAIN ALARMS ARE SHARED DEGLITCH TIME SET TO 0.0 SECONDS NTC THERMISTOR INPUTS 6 CELL INPUTS Figure 45. Typical Connections of the AD8280 Rev. D | Page 16 of 24 Data Sheet AD8280 Also, if the resistor (RTOP) used in the top of the thermistor bridge circuit is less than 10 kΩ, another resistor (RIN) must be added in series to the input to the VTx pin (see Figure 46). The two resistors together must be greater than 10 kΩ (RTOP + RIN > 10 kΩ). This configuration is required only if VTH is not the AD8280 LDO. + VIN5 + VIN4 + VIN3 + VIN2 VTH VIN1 VIN0 RIN AD8280 VTx THERMISTOR 08911-042 RTOP VIN6 Figure 48. Four-Cell Connections for the AD8280 08911-047 AD8280 VIN6 Figure 46. Input Configuration for VTx When Not Using the LDO for VTH VIN5 The part can work with both negative temperature coefficient (NTC) and positive temperature coefficient (PTC) thermistors. For NTC, the NPTC pin should be tied to logic low (VBOTx pin); for PTC, the NPTC pin should be tied to logic high (LDO pin). If the part is set to NTC mode, the OT alarm is tripped when the voltages at VT1 and VT2 drop below the trip point. If the part is set to PTC mode, the OT alarm is tripped when the voltages at VT1 and VT2 rise above the trip point. NUMBER OF CELLS SELECTION The part can be configured to work with three, four, five, or six cells. Table 5 describes how to program the SEL0 and SEL1 pins to determine the number of cells being monitored. A logic low represents VBOTx, and a logic high represents the LDO output voltage. Figure 47 through Figure 49 show how to connect the cells to the part in a five-cell, four-cell, or three-cell application. Table 5. SELx Pin Programming Number of Cells Used 6 cells 5 cells (VIN5 shorted) 4 cells (VIN4 and VIN5 shorted) 3 cells (VIN3, VIN4, and VIN5 shorted) + + SEL0 0 0 1 1 SEL1 0 1 0 1 VIN6 VIN5 VIN4 VIN3 + VIN2 AD8280 08911-041 VIN1 VIN0 + VIN3 VIN2 + AD8280 08911-043 VIN1 VIN0 Figure 49. Three-Cell Connections for the AD8280 THRESHOLD INPUTS The thresholds (or trip points) are set externally with a voltage divider providing maximum flexibility. The desired trip point voltage is connected to the following pins: OV (overvoltage trip point), UV (undervoltage trip point), and OT (overtemperature trip point). The +5 V output of either the reference (REF) or the LDO can be used as the top voltage of the divider. However, because the reference output is more accurate than the LDO output, the reference output is better suited to power the trip point setting dividers. If the thermistor dividers used for temperature sensing are driven from the LDO output, it is recommended that the LDO be used to drive the OT trip point divider as well for better temperature drift performance. Decoupling capacitors (0.1 µF) should be used with the bottom leg of each divider in addition to a 2.2 µF capacitor at the REF output, as shown in Figure 45. + + VIN4 + The REF pin should be loaded with no more than 25 kΩ of resistance. Therefore, when using REF to drive three voltage dividers (OV, UV, and OT), it is recommended that the resistance of each divider total at least 75 kΩ. If driving only two dividers (OV and UV) with the reference, each divider should total no less than 50 kΩ. Figure 47. Five-Cell Connections for the AD8280 Rev. D | Page 17 of 24 AD8280 Data Sheet TOP AND BOTTOM PART DESIGNATION When configured in a daisy chain, the AD8280 operates differently, depending on where it is in the chain: top part (highest potential), middle part, or bottom part (lowest potential). The TOP and BOT pins are used to designate the location of each part in the daisy chain. Table 6 is the logic table for identifying the location of the part in the daisy chain or, when not used in a daisy chain, identifying it as a single (standalone) part. The logic high and logic low for the TOP and BOT pins are different from those of the other logic pins of the AD8280. The TOP and BOT pins are referenced to VTOP (logic high) and VBOTx (logic low), respectively. Table 6. Designation of the AD8280 in Daisy-Chain and Standalone Configurations Desired Condition Middle part (middle potential part) Bottom part (lowest potential part) Top part (highest potential part) Single part (highest and lowest potential part) 1 TOP1 0 0 1 1 BOT1 0 1 0 1 For the TOP and BOT pins only, Logic 1 is VTOP and Logic 0 is VBOTx. Bottom Part in Daisy-Chain Configuration The bottom part in a daisy-chain configuration is the master part and accepts voltage inputs into the ENBI and TESTI pins. The AIINOV, AIINUV, and AIINOT pins of the bottom part are connected to the AIOUTOV, AIOUTUV, and AIOUTOT pins, respectively, of the next higher potential part in the daisy chain. The AIOUTOV, AIOUTUV, and AIOUTOT pins of the bottom part can be left floating, or they can be tied to part ground (VBOTx). Middle Part in Daisy-Chain Configuration When the AD8280 is designated as a middle part, the AIINOV, AIINUV, AIINOT, ENBO, and TESTO pins are connected to the AIOUTOV, AIOUTUV, AIOUTOT, ENBI, and TESTI pins, respectively, of the AD8280 above it. Top Part in Daisy-Chain Configuration When the AD8280 is designated as a top part, the AIINOV, AIINUV, AIINOT, ENBO, and TESTO pins can be left floating, or they can be tied to VTOP. Standalone Part When the AD8280 is designated as a single part (used as a standalone part), the AIOUTOV, AIOUTUV, and AIOUTOT pins can be left floating, or they can be tied to part ground (VBOTx). The AIINOV, AIINUV, AIINOT, ENBO, and TESTO pins can be left floating or tied to VTOP. The AD8280 accepts voltage inputs into the ENBI and TESTI pins. Alarm Signals in Daisy-Chain Configuration Regardless of the part designation, the alarm signals are available as voltage outputs on any part in the chain on the AVOUTOV, AVOUTUV, and AVOUTOT pins. These signals indicate the status of the part where the voltage alarms are monitored, as well as the status of the parts above it in the daisy chain. Make sure to use isolators to bring those signals outside the high voltage battery environment. TYPICAL DAISY-CHAIN CONNECTIONS Figure 50 shows the typical connections for configuring the part in a daisy chain. SHARED OR SEPARATE ALARMS The AD8280 can be configured for three separate alarms or for one shared alarm. Tying the ALRMSEL pin to a 5 V logic high forces the part into separate alarm mode. In this mode, each alarm trips only for its designated monitoring function. That is, the OV alarm trips only if an overvoltage condition exists at any of the cell inputs, the UV alarm trips only if an undervoltage condition exists at any of the cell inputs, and the OT alarm trips only if an overtemperature condition exists at either of the temperature inputs. In shared alarm mode, any of the three conditions—overvoltage, undervoltage, or overtemperature—trips the alarm on all three signal chains. In shared mode, it is necessary to monitor only one alarm because all three contain the same signal. DEGLITCHING OPTIONS The deglitching circuitry is available so that the part is immune to transients occurring at the cell inputs. If a transient voltage of a high or low enough level to trip an alarm occurs at the input to the part, the alarm state does not occur if the transient voltage is present for less than the selected deglitch time. The DGT0, DGT1, and DGT2 pins are used to establish the deglitch time. Table 7 shows the options available and the corresponding logic levels to use when setting the deglitch time with the DGT0, DGT1, and DGT2 pins. Table 7. Fault Detection Time Pin Programming Deglitch Time 0.0 sec 0.1 sec 0.8 sec 1.6 sec 3.2 sec 6.4 sec 12.8 sec DGT0 0 0 0 0 1 1 1 DGT1 0 0 1 1 0 0 1 DGT2 0 1 0 1 0 1 0 Do not tie all three deglitching pins (DGT0, DGT1, and DGT2) to logic high (111); this setting is used only during the testing of the part at the factory. Setting the deglitch time to 0.0 sec (000) allows the use of an external deglitching circuit, if desired. Additionally, when the deglitch time is set to 0.0 sec, the time required to ensure that the part has completed its self-test is significantly reduced (see the Self-Test section). The DGTx pins should be tied to a fixed logic level and not toggled or changed during operation of the AD8280. Rev. D | Page 18 of 24 Data Sheet AD8280 100nF 10µF 0.1µF T1/T2 VTOPx UV OV OT TESTO AIINxx ENBO T1 NTC T2 10kΩ 10nF + VIN6 + VIN5 + VIN4 + VIN3 + VIN2 SEL1 VIN1 BOT VIN0 TOP + 1.0µF VCCx LDOx UV REF REF/FB 10kΩ DGT0 OV REF OT REF 2.2µF DGT1 AD8280 SEL0 100nF ALRMSEL/ AVOUTxx VT1 DGT2/ VT2 VBOTx NPTC TESTI AIOUTxx ENBI GNDx 22pF VTOPx UV OV OT TESTO AIINxx ENBO T3 + VIN6 + VIN5 + VIN4 + + T4 + VIN3 T3/T4 VCCx LDOx UV REF REF/FB OV REF OT REF DGT0 DGT1 AD8280 SEL0 VIN2 SEL1 VIN1 BOT VIN0 VT1 TOP ALRMSEL/ AVOUTxx DGT2/ VT2 VBOTx NPTC TESTI AIOUTxx ENBI GNDx VTOPx UV OV OT TESTO AIINxx ENBO T5 + VIN6 + VIN5 + VIN4 T6 + + VIN3 REF/FB DGT0 UV OV OT REF REF REF DGT1 AD8280 SEL0 VIN2 SEL1 VIN1 BOT TOP ALRMSEL/ AVOUTxx DGT2/ VT2 VBOTx NPTC TESTI AIOUTxx ENBI GNDx VIN0 VT1 VOUT ENBI TEST Figure 50. Typical Daisy-Chain Connections Rev. D | Page 19 of 24 08911-044 + T5/T6 VCCx LDOx AD8280 Data Sheet ENABLING AND DISABLING THE AD8280 The AD8280 can be disabled or put into a standby mode by bringing the ENBI pin to logic low, lowering the quiescent current of the AD8280 from a maximum of 2.0 mA to 1.0 µA and dropping the LDO and reference output to 0 V. Bringing the ENBI pin to a logic high takes the part out of standby mode and enables it. When the AD8280 is used in a daisy-chain configuration, the enable/disable signal is a voltage logic level that is sent to the part designated as the bottom part (the bottom part monitors the lowest voltage cells). The bottom part transfers the enable/ disable signal up the daisy chain via a current out of the ENBO pin and into the ENBI pin of the next higher part in the daisy chain. All the parts in the daisy chain are enabled by sending a logic high to the ENBI pin of the bottom, or master, part. All the parts in the daisy chain are disabled by sending a logic low to the ENBI pin of the bottom part. ALARM OUTPUT The alarm status of the AD8280 appears as a voltage logic level at the AVOUTOV, AVOUTUV, and AVOUTOT pins. When the AD8280 is in a daisy-chain configuration, the alarm status is passed from the AIOUTxx pins of one part to the AIINxx pins of the next lower potential part in the daisy chain. Figure 51 shows the output state when the part is in an unalarmed (logic low) or alarmed (logic high) state. If the AD8280 is configured for the shared alarm mode, the status of all three voltage output pins (AVOUTxx) is the same. In shared alarm mode, the unused pins can be left floating, they can be tied to ground through a high resistance to limit the current draw, or they can be tied together. SELF-TEST The AD8280 has the unique capability of extensively testing its internal components to ensure that they are functioning correctly. This feature is very important to the designer who is concerned with meeting the difficult safety integrity level guidelines of IEC 61508 or ISO 26262. The part produces internal fault conditions and compares the results to what is expected. The status of the alarm signals is interrupted during the self-test, and the pass/fail status of the self-test is communicated via the alarm status signal pins (AVOUTxx and AIOUTxx). Because the AD8280 uses an internal reference to perform its self-test, the self-test detects open circuits and short circuits at the threshold pins, as well. See Figure 51 for a timing diagram and Figure 52 for timing definitions related to the self-test feature. To initiate a self-test, the TESTI pin is prompted with a rising edge from a 5 V logic level pulse (test pulse). The pulse applied at TESTI must stay high for a minimum time (tST min). Following the rising edge of the pulse to initiate the self-test, the alarm status for any AVOUTxx or AIOUTxx pin goes into a logic high status while the part performs its internal self-test. After sufficient time to perform the test has elapsed and assuming that the part passes self-test, the alarm status reverts to the unalarmed state, a logic low. If the part fails self-test, the alarm remains in a logic high state when the falling edge of the test pulse applied at TESTI occurs. The minimum tST is dependent on the status of the DGTx pins. If all three DGTx pins are tied to a logic low, the self-test ignores the deglitch function of the part and completes the self-test in a shorter time (50 ms max). When at least one DGTx pin is set to logic high, the AD8280 defaults to the minimum deglitch time of 100 ms during the self-test. Because the self-test includes multiple layers and passes, this minimum time is specified as 700 ms. Therefore, if a faster self-test is required, the user should set the internal deglitch time to 0.0 sec and use an external deglitch circuit if deglitch is required. Self-Test in Daisy-Chain Configuration The self-test can also be used when multiple AD8280 parts are configured in a daisy chain. The test pulse is applied to the TESTI pin of the bottom part as a voltage and then travels up the chain as a current. The self-test for each part is started as soon as the part sees the rising edge of the test pulse, virtually simultaneously. When the highest part in the chain passes its self-test, it sends that information to the next lower part in the daisy chain. Even if that part has already completed its self-test, it cannot pass its own result on to the next part in the daisy chain until it receives the pass signal from the part above it. This process continues with each part lower down the chain. Therefore, when a pass signal appears at the bottom part in the daisy chain, it indicates that every part in the daisy chain passed the self-test. If any part in the chain fails the self-test, the part below the failing part never receives a pass signal, and, subsequently, the bottom part never receives a pass signal either. Therefore, regardless of whether the bottom part passes self-test, the AVOUTxx signals at the bottom part never change state from the logic high that occurred when the self-test was initiated, and the user will know that there is a failed part in the chain. Rev. D | Page 20 of 24 Data Sheet AD8280 NORMAL OPERATION UNALARMED AIOUTxx/AVOUTxx ALARMED AIOUTxx/AVOUTxx DURING SELF-TEST MODE TESTI AIOUTxx/AVOUTxx TEST OK AIOUTxx/AVOUTxx TEST FAILS HIGH AT FALLING EDGE OF TESTI: PART FAILS SELF-TEST LOW AT FALLING EDGE OF TESTI: PART PASSES SELF-TEST 08911-045 AIOUTxx/AVOUTxx ALARMED TEST OK Figure 51. Timing Diagram for Alarms at AIOUTxx and AVOUTxx Self-Test and Alarm Conditions Self-Test Timing and Monitoring Strategy If an alarm occurs just prior to or just after the self-test pulse is initiated, the alarm causes the self-test to fail. The time span for this condition depends on the deglitch time. When monitoring the signals for self-test on the AD8280, note the following items: Deglitch time = 0.0 sec. The part fails self-test if an alarm occurs in the time period from 20 ms before the leading edge of the self-test pulse to 20 ms after the leading edge of the self-test pulse. Deglitch time > 0.0 sec. The part fails self-test if an alarm occurs in the time period from 120 ms before the leading edge of the self-test pulse to 120 ms after the leading edge of the self-test pulse. Therefore, in the unusual circumstance that the part fails selftest and there is an alarm condition state after the self-test, it is recommended that the user retest the part to ensure that an alarm did not occur just prior to or just after initiating the self-test. The self-test works when the part is in the shared alarm mode or in the separate alarm mode. When the part is in the separate alarm mode, the self-test status on an output pertains only to that portion of the internal circuit relevant to the condition being monitored: overvoltage, undervoltage, or overtemperature. Rev. D | Page 21 of 24 After initiating a self-test of the AD8280 with a rising edge on the TESTI pin, the alarm appearing at the AVOUTxx pin remains valid up to tRE max. When the rising edge of the TESTI pulse occurs, the user should monitor the AVOUTxx pin to make sure that it is in the high state after the tRE max time has elapsed. After the tST max time has elapsed, the user can verify that the AVOUTxx pin has changed to the low state, indicating that the part or parts passed the self-test. The user must also ensure that the minimum length of the TESTI pulse is greater than tST max. The status of the self-test on the AVOUTxx pin is valid until tSTV min after the trailing edge of the TESTI pulse. The alarm state is valid again tFE max after the trailing edge of the pulse. AD8280 Data Sheet NO ALARM WHEN SELF-TEST IS INITIATED 1 TESTI 0 1 AVOUTxx SELF-TEST PASS 0 tSTV 1 AVOUTxx SELF-TEST FAIL 0 tFE tRE tST ALARM WHEN SELF-TEST IS INITIATED 1 TESTI 0 1 AVOUTxx SELF-TEST PASS 0 tSTV 1 AVOUTxx SELF-TEST FAIL tRE 0 tST NOTES 1. tRE IS THE TIME FROM THE RISING EDGE OF THE TEST PULSE (TESTI) TO THE START OF THE SELF-TEST. 2. tST IS THE TIME FROM THE RISING EDGE OF THE TEST PULSE UNTIL THE PART COMPLETES ITS SELF-TEST (TEST PULSE MUST BE LONGER THAN tST MAX). 3. tSTV IS THE TIME FROM THE FALLING EDGE OF THE TEST PULSE THAT THE SELF-TEST INDICATION REMAINS VALID (LOW = PASS, HIGH = FAIL). 4. tFE IS THE TIME FROM THE FALLING EDGE OF THE TEST PULSE UNTIL THE SELF-TEST DATA IS CLEARED AND THE ALARM DATA IS AGAIN VALID. Figure 52. Timing Definitions Rev. D | Page 22 of 24 08911-046 tFE Data Sheet AD8280 Sample Calculation PROTECTION COMPONENTS AND PULL-UP/ PULL-DOWN RESISTORS As shown in Figure 45, several devices are added to provide protection in a high voltage environment. Zener Diode Z1 ensures that the six-cell stack voltage does not significantly exceed the maximum 30 V across the part. It is recommended that a 33 V rated Zener diode be used for Z1. The user can also use diodes in the daisy-chain lines (anode to cathode from higher potential to lower potential) to protect the parts in the event that an open circuit appears on the battery connections, causing a high reverse voltage across the AD8280 (these diodes are not shown in Figure 45). The diodes should have a reverse voltage rating comparable to the highest voltage of the battery system. If diodes are used in the daisy chain, it is also recommended that a diode be used between the top cell in the stack (anode) and VTOP (cathode) of the top part, as well as between VBOTx (anode) of each part and VTOP (cathode) of the next lowest potential part in the daisy chain. Because there are no pull-up or pull-down resistors internal to the part, the user may want to pull down the TESTI pin of the bottom part through a 10 kΩ resistor to VBOTx (part ground). The addition of this resistor ensures that the part is not locked in self-test mode if the line opens. Also, the user may want to pull up the ENBI pin on the bottom part of a daisy chain so that if the line opens, the chain stays in the enabled (powered up) mode. EMI CONSIDERATIONS To increase immunity to electromagnetic interference (EMI), use the following components and layout schemes (see Figure 50). Use a 22 pF capacitor on each of the daisy-chain lines. Route the daisy-chain lines on an inner PCB layer. Use ground planes (connected to VBOTx from the higher potential part) both over and under the daisy-chain lines to shield them. Route the connections from VBOTx to VTOP to best ensure a low impedance connection between them. Use ferrite beads on the VTOP lines as shown in Figure 50. Use 100 nF capacitors across each of the six-cell battery stacks. Place the AD8280 parts as close together as possible on the board to minimize the length of the daisy-chain lines. SYSTEM ACCURACY CALCULATION When calculating system accuracy, there are four error sources to consider: Trip point error (see Table 1) Reference voltage error (see Table 1) Resistor tolerance Resistor temperature coefficient Following is a sample calculation for overvoltage accuracy. In this calculation, the following conditions are assumed: Resistors used in the external resistor divider to set the trip points are ±1%, 100 ppm/°C resistors. Temperature range is −40°C to +85°C. Desired overvoltage trip point is 4.0 V (resistor values selected should be 15 kΩ and 60 kΩ). The resulting sources of error are described in this section. Maximum Trip Point Error The maximum trip point error is ±15 mV. Maximum Reference Error The maximum reference error is as follows: (60/(60 + 15)) × ±50 mV = ±40 mV Maximum Resistor Tolerance Error The maximum resistor tolerance error depends on the values of the resistors. If one resistor is high and the other is low, the worst-case error is as follows: (60.6/(60.6 + 14.85)) × 5.00 V = 4.016 V (error of +16 mV) (59.4/(59.4 + 15.15)) × 5.00 V = 3.984 V (error of −16 mV) In this sample calculation, the maximum resistor tolerance error is ±16 mV. Maximum Temperature Coefficient Error If one resistor drifts high and the other resistor drifts low, the worst-case error is as follows: 60 kΩ + (100 ppm/°C × (25°C − (−40°C)) × 60 kΩ) = 60.39 kΩ 15 kΩ − (100 ppm/°C × (25°C − (−40°C)) × 15 kΩ) = 14.9 kΩ (60.39/(60.39 + 14.90)) × 5.00 V = 4.010 V (error of +10 mV) or 60 kΩ − (100 ppm/°C × (25°C − (−40°C)) × 60 kΩ) = 59.61 kΩ 15 kΩ + (100 ppm/°C × (25°C − (−40°C)) × 15 kΩ) = 15.1 kΩ (59.61/(59.61 + 15.10)) × 5.00 V = 3.990 V (error of −10 mV) In this sample calculation, the maximum temperature coefficient error is ±10 mV. Total System Accuracy The system accuracy, or the sum of all the errors, is ±81 mV. If the resistor pair coefficients are matched so that drift is in the same direction, that portion of the error can be ignored, and the total system accuracy would be ±71 mV. Rev. D | Page 23 of 24 AD8280 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 1.45 1.40 1.35 Figure 53. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD8280WASTZ AD8280WASTZ-RL AD8280-EVALZ 1 2 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 48-Lead Low Profile Quad Flat Package [LQFP] 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board with Two AD8280WASTZ Devices Package Option ST-48 ST-48 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8280W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08911-0-8/14(D) Rev. D | Page 24 of 24