AD6642 Evaluation Board Schematic File PDF

8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
DUT
D
D
VIN+A
DUT_CSB
DUT_SDIO
DUT_SCLK
PDWN
SYNC
MODE
VIN+D
VCMB
VCMC
VIN-B
VIN+B
AGND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
CLKCLK+
VIN+C
VIN-C
AVDD
AGND30
VIN_POS_C
VIN_NEG_C
AGND29
AVDD20
CLK_NEG
CLK_POS
AVDD19
AGND28
VIN_NEG_B
VIN_POS_B
AGND27
AGND26
AGND25
VCMC
AGND24
AVDD18
AVDD17
AVDD16
AVDD15
AGND23
VCMB
AGND22
AGND21
VIN_POS_D
AGND20
AGND19
CSB
SDIO
SCLK
PDWN
SYNC
MODE
AGND18
AGND17
VIN_POS_A
LAYOUT: DECOUPLING QUANTITY MAY VARY LAYOUT DEPENDING
D0_POS_CD
D2_POS_CD
D4_POS_CD
D6_POS_CD
D8_POS_CD
D10_POS_CD
D0_POS_AB
D2_POS_AB
D4_POS_AB
D6_POS_AB
D8_POS_AB
D10_POS_AB
D1_NEG_CD
D3_NEG_CD
D5_NEG_CD
D7_NEG_CD
D9_NEG_CD
DCO_NEG_CD
D1_NEG_AB
D3_NEG_AB
D5_NEG_AB
D7_NEG_AB
D9_NEG_AB
DCO_NEG_AB
D1_POS_CD
D3_POS_CD
D5_POS_CD
D7_POS_CD
D9_POS_CD
DCO_POS_CD
D1_POS_AB
D3_POS_AB
D5_POS_AB
D7_POS_AB
D9_POS_AB
DCO_POS_AB
D10_NEG_AB
D8_NEG_AB
D6_NEG_AB
D4_NEG_AB
D2_NEG_AB
D0_NEG_AB
D10_NEG_CD
D8_NEG_CD
D6_NEG_CD
D4_NEG_CD
D2_NEG_CD
D0_NEG_CD
DRVDD01
DRVDD02
DRVDD03
DRVDD04
DRVDD05
DRVDD06
DRVDD07
DRVDD08
DRVDD09
DRVDD10
DRVDD11
DRVDD12
DRGND01
DRGND02
DRGND03
DRGND04
DRGND05
DRGND06
DRGND07
DRGND08
DRGND09
DRGND10
DRGND11
DRGND12
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
B
AD6657
AGND01
AGND02
AGND03
AGND04
AGND05
AGND06
AGND07
AGND08
AGND09
AGND10
AGND11
AGND12
AGND13
AVDD01
AVDD02
AVDD03
AVDD04
AVDD05
AVDD06
AVDD07
AVDD08
AVDD09
AVDD10
AGND14
VIN_NEG_A
VCMA
AGND15
AVDD11
AVDD12
KP_ICELL
KP_VDDIO
AVDD13
AVDD14
AGND16
VCMD
VIN_NEG_D
C
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DCO+AB
D9+AB
D7+AB
D5+AB
D3+AB
D1+AB
DCO+CD
D9+CD
D7+CD
D5+CD
D3+CD
D1+CD
DCO-AB
D9-AB
D7-AB
D5-AB
D3-AB
D1-AB
DCO-CD
D9-CD
D7-CD
D5-CD
D3-CD
D1-CD
D10+AB
D8+AB
D6+AB
D4+AB
D2+AB
D0+AB
D10+CD
D8+CD
D6+CD
D4+CD
D2+CD
D0+CD
DRVDD
C102
.1UF
C103
.1UF
C104
.1UF
C105
.1UF
C106
.1UF
C107
1UF
C108
1UF
C121
1UF
C122
1UF
AVDD
DGND
KP_VDDIO
KP_ICELL
C
VCMA
VIN-A
AVDD
C109
.1UF
C110
.1UF
C111
.1UF
C112
.1UF
C113
.1UF
C114
.1UF
C115
.1UF
C116
.1UF
C117
1UF
C118
1UF
C119
.1UF
C120
.1UF
AGND
B
AD6657_PRELIM
DGND
DRVDD
C101
.1UF
AGND
J12
J11
J10
J9
J8
J7
J6
J5
J4
J3
J2
J1
H12
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
D10-AB
D8-AB
D6-AB
D4-AB
D2-AB
D0-AB
D10-CD
D8-CD
D6-CD
D4-CD
D2-CD
D0-CD
U101
VIN-D
VCMD
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 1
1
OF 11
8
6
7
5
4
2
3
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
POWER
1
2
3
4
6
5
CR202
A
C
VIN
D
SK33A-TP
A
E208
1
2
3P3V_DIGITAL
10UF
N
C216
3P3V_DIGITAL_IN
Z5.531.3625.0
DRVDD_IN
E209
1
2
DRVDD
P
AGND
DGND
AVDD_IN
100MHZ
N
1
2
3
4
5
6
10UF
P202
0.1UF
C219
R201
AGND
C218
PGND
261
100MHZ
0.1UF
C217
P
C
CR201
A
C
N
PJ-202A
10UF
C201
D
F201
1
2
1.1A
P
1
2
3
FL201
BNX016-01
CR203
P201
DGND
DGND
E210
1
2
AGND
10UF
C221
N
E201
2
1
5
6
C
E211
1
2
5V_SUPPORT
10UF
N
C222
100MHZ
AGND
0.1UF
C223
P
2 PAD
AGND
5V_SUPPORT_IN
100MHZ
4.7UF
4.7UF
C202
1.91K
10K
R202
R203
C
EN
SENSE
IN
OUT
IN2
OUT2
ADJ
GND1 PAD
C203
1
7
3
4
8
VIN
100MHZ
U201
C220
ADP1708ARDZ-R7
0.1UF
P
AVDD
AGND
100MHZ
DNI
E203
2
1
AGND
B
4.7UF
3P3V_DIGITAL_IN
100MHZ
GROUND PLANE TIES
DGND
AGND
4.7UF
E205
2
1
RS201
0
AVDD_IN
RS202
0
DNI
RS203
0
DNI
RS204
0
DNI
DGND
AGND
100MHZ
DNI
100MHZ
E206
1
2
C212
S2A-TP
C210
S2A-TP
CR206
C
A
4.7UF
CR205
C
A
ADP1706ARDZ-1.8-R7
U204
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
SS
GND1 PAD
C211
0.01UF 2 PAD
P
N
3P3V_ANALOG_IN
0.1UF
C225
100MHZ
Z5.531.3425.0
E204
1
2
C209
4.7UF
C207
B
3P3V_ANALOG
100MHZ
AGND
ADP1706ARDZ-3.3-R7
U203
1
EN
7
SENSE
3
5
OUT
IN
4
6
IN2
OUT2
8
SS
GND1 PAD
C208
0.01UF 2 PAD
3P3V_ANALOG_IN
AGND
E212
1
2
C224
E202
2
1
4.7UF
4.7UF
C204
S2A-TP
C206
CR204
A
C
ADP1706ARDZ-3.3-R7
U202
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
SS
GND1 PAD
C205
2 PAD
0.01UF
5V_SUPPORT_IN
1
2
3
4
10UF
P203
AGND
TO EVALUATE SHARING OF AVDD AND DVDD
RS205
0
RS206
0
DNI
RS207
0
DNI
RS208
0
DNI
RS209
0
DNI
DGND
A
E207
1
2
4.7UF
ADP1706ARDZ-1.8-R7
U205
1
EN
7
SENSE
3
5
IN
OUT
4
6
IN2
OUT2
8
SS
GND1 PAD
C214
2 PAD
0.01UF
C215
C213
4.7UF
A
DRVDD_IN
AN A LOG
DEV CES
100MHZ
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
DGND
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
<DESIGN_VIEW>
OF ANALOG DEVICES.
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
7
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
8
REV
DRAWING NO.
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 2
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ANALOG INPUT
D
AMP_OUT_A+
8.2PF
PASSIVE PATH A
AMP_IN_A+
C303
D
AGND
DNI
R319
0
R309
R308
0
DNI
3
DNI
5
DNI
AGND
AGND
DNI
1
R305
R306
0
0
L301
AGND
AGND
R314
36
R310
R316
0.1UF
R320
0
DNI
R307
0
AGND
82NH
0.1UF
DNI
R304
49.9
2 3 4 5
ETC1-1-13
T302
VCMA
SHARE PADS
VIN+A
33
R312
0
AGND
R318
49.9
DNI
AGND
C304
AMP_IN_A-
AMP_OUT_A-
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
AMP_OUT_B+
DNI
J304
1
DNI
2 3 4 5
R325
R326
0
0
DNI
R324
49.9
DNI
DNI
1
4
ADT1-1WT+
T305
1
PRI
SEC
4
3
ETC1-1-13
DNI
R340
0
R328
0
DNI
L302
VCMB
0.1UF
82NH
AGND
AGND
R334
36
R330
0.1UF
SHARE PADS
AGND
AGND
R333
36
C305
C306
2 VCMB
AGND
5
B
VIN+B
33
0.1UF
T306
ETC1-1-13
DNI
AGND
AIN_B
3
T304
6
R335
3
DNI
AGND
DNI
4
R327
0
SEC
R321
49.9
2 3 4 5
R337
49.9
R331
0
R329
PRI
0
1
0
SHARE PADS
5
1
B
R323
AGND
DNI
R339
0
R322
C307
AGND
PASSIVE PATH B
AMP_IN_B+
J303
C
8.2PF
J302
3
4
1
4
ADT1-1WT+
T301
T303
DNI
8.2PF
DNI
SEC
R313
36
C301
8.2PF
DNI
PRI
4
2 VCMA
C
1
PRI
AGND
33
0.1UF
6
VIN-A
8.2PF
R301
49.9
2 3 4 5
R315
C302
0
ETC1-1-13
0
3
R303
SEC
R302
5
AIN_A
R317
49.9
R311
0
SHARE PADS
1
J301
1
DNI
R336
DNI
VIN-B
33
R332
0
R338
49.9
AGND
8.2PF
C308
AMP_IN_B-
AMP_OUT_B-
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
AGND
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 3
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ANALOG INPUT
D
0
0
R409
AGND
DNI
DNI
J402
1
1
4
ADT1-1WT+
DNI
R405
R406
0
0
5
1
PRI
SEC
4
3
ETC1-1-13
DNI
R404
49.9
2 3 4 5
2 VCMC
R420
0 DNI
DNI
T403
0.1UF
ETC1-1-13
AGND
T402
R413
36
C401
DNI
VCMC
L401
82NH
0.1UF
AGND
AGND
R414
36
R410
R416
DNI
0.1UF
R407
0
AGND
VIN-C
33
3
DNI
AGND
T401
6
4
3
SEC
DNI
PRI
R408
0
R401
49.9
2 3 4 5
R415
8.2PF
R403
C402
R402
R417
49.9
R411
0
SHARE PADS
1
1
AGND
DNI
5
AIN_C
AMP_OUT_C+
R419
0 DNI
J401
C403
PASSIVE PATH C
AMP_IN_C+
8.2PF
D
SHARE PADS
VIN+C
33
R412
0
R418
49.9
AGND
AMP_IN_C-
C
C
C404
AMP_OUT_C-
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
T404
6
3
DNI
AGND
2
AGND
J404
AIN_D
DNI
R425
0
2 3 4 5
R424
49.9
DNI
1
4
ADT1-1WT+
R426
AGND
1
PRI
SEC
4
3
ETC1-1-13
DNI
VCMD
L402
82NH
8.2PF
AGND
R434
36
AGND
R430
AGND
R433
36
C405
0.1UF
0
DNI
R440
0 DNI
DNI
VCMD
5
VIN+D
33
0.1UF
T406
T405
B
8.2PF
AGND
1
R435
C406
R427
0
DNI
ETC1-1-13
R421
49.9
2 3 4 5
C407
R429
DNI
3
0
4
0
SEC
R423
R437
49.9
R431
0
SHARE PADS
PRI
R422
AGND
DNI
1
1
AMP_OUT_D+
R439
0 DNI
5
B
J403
AGND
PASSIVE PATH D
AMP_IN_D+
8.2PF
AGND
R428
0
R436
DNI
0.1UF
SHARE PADS
VIN-D
33
R432
0
R438
49.9
AGND
8.2PF
C408
AMP_IN_D-
AMP_OUT_D-
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
AGND
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 4
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ACTIVE PATH - CHANNEL A
3P3V_ANALOG
D
D
C505
10UF
C504
0.1UF
AGND
AGND
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
C501
R501
40.2
AMP_IN_A+
PRI
SEC
0
R505
AMP_IN_A-
4
3
AGND
ETC1-1-13
0
0.1UF
10
11
VON
VOP
PD_N_A
12
ENBL
DNI
VCOM
GND
ADL5562_PRELIM
R502
40.2
DNI
1JP501 2
JPR0402
PAD
DNI
C503
0.1UF
0.1UF
DNI
AGND
VCMA
0
L506
DNI
DNI
82NH
DNI
C507
DNI
R512
DNI
C510
5PF
C509
5PF
0 DNI
L504
L502
DNI
AMP_OUT_A-
0.1UF
AGND
3P3V_ANALOG
C508
R511
1.00K
L505
82NH
DNI
VCMA
DNI
DNI
R510
1.00K
0 DNI
R509
9
120NH
120NH
0.1UF
R508
VIN2
0
R506
C502
AMP_OUT_A+
VCC
1
VIP2
2
VIP1
3
VIN1
4
L503
L501
U501
5
6
7
8
5
C506
0 DNI
R504
0.1UF
13
14
15
16
PAD
1 T501
R503
120NH
120NH
DNI
DNI
DNI
AGND
AGND
R507
1.1K
P501
PD_N_A
1
2
C
C
AGND
ACTIVE PATH - CHANNEL B
3P3V_ANALOG
C524
0.1UF
AGND
C525
10UF
AGND
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
C521
5
0.1UF
1
R521
40.2
AMP_IN_B+
PRI
AMP_IN_B-
SEC
4
0
AGND
PD_N_B
12
0 DNI
0.1UF
R528
10
VON
11
VOP
ENBL
VCOM
GND
ADL5562_PRELIM
R522
40.2
9
0.1UF
DNI
DNI
0
R529
VIN2
0
R526
C522
U502
VCC
1
VIP2
2
VIP1
3
VIN1
4
R525
3
ETC1-1-13
C526
0 DNI
R524
5
6
7
8
T521
B
R523
1JP502 2
JPR0402
C523
0.1UF
AGND
AGND
L533
120NH
120NH
DNI
DNI
VCMB
R531
1.00K
C527
DNI
DNI
0.1UF
DNI
AMP_OUT_B+
L535
82NH
C528
C529
5PF
0 DNI
0.1UF
AGND
L531
R530
1.00K
DNI
PAD
13
14
15
16
PAD
B
AGND
C530
5PF
DNI
DNI
L532
L534
120NH
120NH
DNI
DNI
DNI
R532
VCMB
0
L536
DNI
82NH
DNI
AMP_OUT_B-
3P3V_ANALOG
R527
1.1K
P502
PD_N_B
A
1
2
A
AGND
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 5
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ACTIVE PATH - CHANNEL C AND D
5V_SUPPORT
5V_SUPPORT
AGND
AGND
AGND
T601
C
AGND
3 0.1UF
TC3-1T+
4
ENBB
B0
B1
B2
B3
B4
11 IPB_P
GNDA
21 28
TC3-1T+
4
AGND
0 DNI
3
C614
1UH
0.1UF
L603
L605
120NH
120NH
16
18
15
17
13 20 PAD
C616
C618
22PF
C617
2.7PF
DNI
DNI
L604
L606
120NH
120NH
AMP_OUT_D+
1200PF
DNI
DNI
C
5V_SUPPORT
AD8376ACPZ
AGND
AGND
DNI
DNI
DNI
AMP_OUT_D-
AGND
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
DNI
AGND
0.1UF
AMP_IN_C+
1200PF
DNI
AGND
2
6
OPB1_N
OPB2_N
OPB1_P
OPB2_P
GNDB
PAD
DNI
0.1UF
C604
T602
23
25
24
26
C605
R606
AMP_IN_C-
C615
R612
300
OPA1_N
OPA2_N
OPA1_P
OPA2_P
29 IPA_N
0.1UF
DNI
0
12 IPB_N
0
0
R611
C603
DNI
R610
DNI
30 IPA_P
R604
AMP_IN_D+
R605
130
U601
0.1UF
DNI
2
19
10
9
8
7
6
27
C620
C601
ENB_B
AD8376_B0
AD8376_B1
AD8376_B2
AD8376_B3
AD8376_B4
14
1UH
0.1UF
1
ENB_A
AD8376_A0
AD8376_A1
AD8376_A2
AD8376_A3
AD8376_A4
22
31
32
1
2
3
5
VCMA VCMB VCCB VCCA
ENBA
A0
A1
A2
A3
A4
L608
6
AGND
0
0
DNI
THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS...
1UH
AGND
C602
R603
AGND
AGND
4
AMP_IN_D-
1UH
AGND
R613
AGND
1
2
C612
10UF
L602
ENB_B
C611
0.1UF
C608
0.1UF
L607
1
2
P602
L601
P601
ENB_A
5V_SUPPORT
R602
1.1K
0.1UF
R601
1.1K
0
AGND
D
R609
C607
0.1UF
0.1UF
5V_SUPPORT
C613
5V_SUPPORT
C610
10UF
C619
D
C609
0.1UF
R608
130
R614
1
0
C606
R607
DNI
0
1200PF
L609
L611
120NH
120NH
DNI
DNI
AMP_OUT_C-
DNI
0.1UF
DNI
C621
R616
300
R615
0
DNI
DNI
DNI
DNI
B
C624
22PF
C623
2.7PF
L610
C622
B
L612
AMP_OUT_C+
120NH
1200PF
120NH
DNI
DNI
DNI
THIS HEADER IS USED TO SET THE GAIN OF THE AD8376
THIS HEADER IS USED TO SET THE GAIN OF THE AD8376
5V_SUPPORT
R617
10K
R618
10K
R619
10K
R620
10K
5V_SUPPORT
R621
10K
R622
10K
R623
10K
R624
10K
R625
10K
J601
AD8376_A0
A
1
2
3
4
5
6
7
8
9
10
AD8376_A1
AD8376_A2
AD8376_A3
AD8376_A4
AD8376_B0
AD8376_B1
AD8376_B2
AD8376_B3
AD8376_B4
TSW-105-08-G-D
R626
10K
J602
10
9
8
7
6
5
4
3
2
1
A
AN A LOG
DEV CES
TSW-105-08-G-D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
AGND
AGND
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 6
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
AVDD
R721
0
DESCRIPTION
DATE
APPROVED
MAIN PASSIVE CLOCK
KP_ICELL
D
CLK+_CPC
D
TO CUSTOMER PASSIVE CLOCK
CLK+
0
0.1UF
DNI
49.9
DNI R701
AGND
R713
R703
T701
ADT1-1WT+
3
6
C707
AGND
AGND
2
1
4
5
1
PRI
SEC
4
0.1UF
C
AGND
ETC1-1-13
AGND
2
3
R710
24.9
T702
R714
CLK-
0
0.1UF
R728
0
0
49.9
DNI R702
AGND
1
0.1UF
R715
100
CR701
DNI
R704
0.1UF
2 3 4 5
C703
DNI
C702
R706 DNI
CLK
R709
24.9
3
DNI
J702
1
0.1UF
DNI
0
0
C701
J701
1
2 3 4 5
R727
0 DNI
DNI
R705
DNI
R726
DNI
KP_ICELL
DNI
C
CLK-_CPC
AGND
AGND
TO CUSTOMER PASSIVE CLOCK
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
MISC
KILOPASS VOLTAGE
AVDD
DNI
SA
SB
ADG734BRUZ
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
AVDD
1
B
J703
1
IN
R719
2.0K
R716
49.9
SA
SB
ADG734BRUZ
DNI
C705
0.1UF
DNI
0.1UF
2 3 4 5
0
DNI
SYNC
KP_VDDIO
R725
U701D 3
C704
R717
0
AGND
3P3V_DIGITAL
R723
0
R718
2.0K
SYNC
2
4
9
7
B
DGND
R720
49.9
10
3P3V_DIGITAL
IN
DNI
U701
D
8
AGND
DNI
C706
0.1UF
AGND
AVDD
P702
PDWN
R724
10K
PDWN
1
2
1
2
11
U701
16
12
14
DGND
VDD
IN
DNI
ADG734BRUZ
U701 D 13
DNI
P701
MODE
ADG734BRUZ
SA
SB
15 NC15
6 GND
5 VSS
KP_V_CTRL
DNI
DGND
DGND
NSR ON
DNI
AGND
ADG734BRUZ
20
SA
SB
19
17
IN
U701 D 18
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
A
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 7
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
CUSTOMER PASSIVE CLOCK
D
D
CLK_OUT+
0
0
0
SEC
4
C804
3
0.1UF
AGND
ETC1-1-13
AGND
R816
0
0
0
DNI
R811
SHARE PADS
CLK_INAGND
AGND
0
DNI
R817
3
R812
SHARE PADS
0
2
R814
24.9
DNI
R808
D801
1
R820
CLK-_CPC
0.1UF
C
0
PRI
0.1UF
R813
24.9
SHARE PADS
0
49.9
AGND
DNI R805
2 3 4 5
1
0
0.1UF
DNI
C
R807
R806
CLK
C802
DNI
4
0.1UF
5
CLK+_CPC
DNI
AGND
1
DNI
T802
ADT1-1WT+
6 T801
3
C803
DNI
2
R819
R818
DNI
DNI
J802
0
R815
AGND
1
DNI
R810
R804
DNI R801
AGND
R803
49.9
0.1UF
SHARE PADS
SHARE PADS
0
1
2 3 4 5
R809
0
SHARE PADS
C801
J801
CLK_IN+
DNI
R802
CLK_IN+
CLK_OUT-
CLK_IN-
LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER
B
B
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 8
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
ACTIVE CLOCK PATH
WHT
D
D
TP907
1
C905
DNI
3P3V_ANALOG
3P3V_ANALOG
CLK_IN+
0.1UF
CLK_IN-
48
REFIN_REF1
47
C902
REFIN_N_REF2
0.1UF
R903
1.00K
R904
1.00K
AGND
9
BYPASS_LDO
AGND
C904
DNI
8
LF
SEC
4
3
ETC1-1-13
AGND
AGND
DNI
BYPASS
STATUS
LF
AD9517-4BCPZ
CLK_N
C903
R924
24.9
LD
CP
11
CLK
12
0.1UF
57.6
2 3 4 5
R905
PRI
J901
C
R923
24.9
1 9517_CLK
3P3V_ANALOG
R902
1.00K
T901
1
5
P901
1
2
3
4
5
6
7
8
REF_SEL
0.1UF
18
PD_N
7
SYNC_N
17
RESET_N
3P3V_ANALOG
TSW-104-08-T-D
AGND
R922
1.00K
R906
USB_CSB2
13
SCLK
16
SDIO
14
SCLK
SDI
VCP
RSET
REFMON
CPRSET
CS_N
OUT0
OUT0_N
OUT1
OUT1_N
OUT2
OUT2_N
OUT3
OUT3_N
OUT4_OUT4A
OUT4_N_OUT4B
OUT5_OUT5A
OUT5_N_OUT5B
OUT6_OUT6A
OUT6_N_OUT6B
OUT7_OUT7A
OUT7_N_OUT7B
SDO
0
VCC
1 A1
Y1
TP902
Y2
4
C
A
SML-LXT0805IW-TR
R908
WHT
1
200
3 A2
CR901
R910
6
GND
TP903
4.12K
AGND
1
NC7WZ16P6X
R907
5.11K
44
1
46
AGND
2
AGND
AGND
AGND
2
4
CP
CLK_OUT+
5
R912
200
42
41
39
38
19
20
22
23
35
34
33
32
26
27
28
29
15
R911
C
0
AGND
DNI
PECL_OUT1
PECL_OUT1_N
R913
200
CLK_OUT-
TP904
SDO
1
6
VS
U902
0
U901
3
10
24
25
30
31
36
37
43
45
21
40
VS_LVPECL
C901
1
3P3V_ANALOG
R901
1.00K
R909
TP901
WHT
0 DNI
3P3V_ANALOG
0.1UF
5
WHT
DNI
R925
PECL/CML/LVDS CLK CIRCUITRY
AGND
R926
0
GND
WHT
PAD
R914
100
AGND
1
TP905
WHT
C906
PECL_OUT1
B
5 4 3 2
B
200
R915
0.1UF
J902
1
AGND
CHARGE PUMP FILTER
AGND
DNI
C912
DNI
C909
DNI
R918
200
DNI
C918
0.1UF
C914
0.1UF
C919
0.1UF
LF
5 4 3 2
AGND
AGND
DNI
0.1UF
C920
0.1UF
C915
.033UF
AGND
1500PF
C908
DNI
1500PF
2 3 4 5
0
DNI
DNI
C913
J903
1
200
100
0
R921
R916
R919
0.1UF
R927
C910
J904
1
DNI
3P3V_ANALOG
R920
0
CP
R917
0
C907
PECL_OUT1_N
DNI
0.1UF
C916
0.1UF
C921
0.1UF
C917
0.1UF
C922
0.1UF
0.1UF
C923
A
0.1UF
C911
BYPASS_LDO
DNI
AGND
AGND
A
0.1UF
AGND
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 9
1
OF 11
8
6
7
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
SPI
D
D
DRVDD
R933
1.1K
3P3V_DIGITAL
DNI
DRVDD
SA
SB
ADG734BRUZ
2
4
FPGA_SDI
1 A1
Y1 6
3 A2
Y2
U932D 3
SDI
C
DGND
4
SDO
3P3V_DIGITAL
DNI
GND
100K
DGND
U931
NC7WZ07P6X
SA
SB
ADG734BRUZ
2
9
7
FPGA_SDO
USB_SDO
10
DGND
IN
DGND
SPI_PATH
D
8
C931
0.1UF
DNI
SA
SB
ADG734BRUZ
12
14
DGND
U932 D 13
0
IN
DNI
DNI
ADG734BRUZ
FPGA_SCLK
R938
11
DGND
VDD
USB_SCLK
R935
10K
U932
16
SDO
15 NC15
6 GND
5 VSS
U932
DNI
0
DUT_SDIO
R931
R930
C
10K
SDI
5
VCC
IN
R937
R932
1.1K
0
1
C930
0.1UF
R934
1.1K
R936
USB_SDI
SCLK
DGND
DNI
SA
SB
ADG734BRUZ
19
17
FPGA_CSB
USB_CSB
100K
5
CSB
R942
DGND
U933
VCC
CSB
1 A1
Y1
6
SCLK
3 A2
Y2
4
DGND
100K
NC7WZ16P6X 2
R943
10K
R941
NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC
DUT_CSB
DUT_SCLK
GND
DGND
B
0
U932 D 18
C932
0.1UF
10K
R940
B
IN
R939
20
DRVDD
DGND
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 10 OF 11
1
8
7
6
2
3
4
5
1
REVISIONS
REV
DESCRIPTION
DATE
APPROVED
FIFO5 CONNECTION
D1+CD
D3+CD
D5+CD
D7+CD
D9+CD
DCO+CD
D0+CD
D2+CD
D4+CD
D6+CD
D8+CD
D10+CD
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D1-CD
D3-CD
D5-CD
D7-CD
D9-CD
DCO-CD
USB_CSB2
USB_CSB
FPGA_SDO
FPGA_CSB
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
D1-AB
D3-AB
D5-AB
D7-AB
D9-AB
DCO-AB
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
D
P953
P953
P952P952
PLUG HEADER
D0+AB
D2+AB
D4+AB
D6+AB
D8+AB
D10+AB
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
P951
PLUG HEADER
D1+AB
D3+AB
D5+AB
D7+AB
D9+AB
DCO+AB
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
PLUG HEADER
P951
PLUG HEADER
D
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
KP_V_CTRL
SPI_PATH
USB_SDO
USB_SDI
USB_SCLK
FPGA_SDI
FPGA_SCLK
C
DGND
P951P951
6469169-1
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DGND
DGND
P952
P952P952
6469169-1
P953
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DGND
DGND
PLUG HEADER
D0-CD
D2-CD
D4-CD
D6-CD
D8-CD
D10-CD
PLUG HEADER
PLUG HEADER
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
P953
PLUG HEADER
P952
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
P951
PLUG HEADER
D0-AB
D2-AB
D4-AB
D6-AB
D8-AB
D10-AB
PLUG HEADER
PLUG HEADER
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
PLUG HEADER
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
PLUG HEADER
P951
PLUG HEADER
PLUG HEADER
P953P953
C
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
6469169-1
DGND
B
B
A
A
AN A LOG
DEV CES
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
SCHEMATIC
<DRAWING_TITLE_HEADER>
AD6657
<PRODUCT_1>
DESIGN VIEW
REV
DRAWING NO.
<DESIGN_VIEW>
B
6657CE01
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
OF ANALOG DEVICES.
SIZE
PTD ENGINEER
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
8
7
6
5
4
3
<PTD_ENGINEER>
2
D
SCALE
-
SHEET 11 OF 11
1
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