2M × 32-Bit Dynamic RAM Module (Hyper Page Mode - EDO Version) HYM 322005S/GS-50/-60 • SIMM modules with 2 097 152 words by 32-bit organization for PC main memory application • Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) • Hyper page mode - EDO capability with 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) • Single + 5 V (± 10 %) supply • Low power dissipation max. 2200 mW active (-50 version) max. 1980 mW active (-60 version) CMOS – 22 mW standby TTL – 44 mW standby • CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh • 4 decoupling capacitors mounted on substrate • All inputs, outputs and clock fully TTL compatible • 72 pin Single in-Line Memory Module • Utilizes four 1M × 16 -DRAMs in SOJ-42 packages • 1024 refresh cycles / 16 ms • Optimized for use in byte-write non-parity applications • Tin-Lead contact pad HYM 322005S • Gold-Lead contact pad HYM 322005GS • single sided module with 20.32 mm (800 mil) height Semiconductor Group 1 9.96 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module The HYM 322005S/GS-50/-60 is a 8 MByte EDO - DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5118160BSJ 1M × 16 EDO - DRAMs in 400 mil wide SOJ-packages mounted together with four 0.2 µF ceramic decoupling capacitors on a PC board. Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use presence detect pins. The common I/O feature on the HYM 322005S/GS-50/-60 dictates the use of early write cycles. Ordering Information Type Ordering Code Package Descriptions HYM 322005S-50 Q67100-Q2066 L-SIM-72-10 EDO - DRAM module (access time 50 ns) HYM 322005S-60 Q67100-Q2067 L-SIM-72-10 EDO - DRAM module (access time 60 ns) HYM 322005GS-50 Q67100-Q2068 L-SIM-72-10 EDO - DRAM module (access time 50 ns) HYM 322005GS-60 Q67100-Q2069 L-SIM-72-10 EDO - DRAM module (access time 60 ns) Semiconductor Group 2 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module Pin Names VSS DQ16 DQ17 DQ18 DQ19 N.C. A1 A3 A5 N.C. DQ20 DQ21 DQ22 DQ23 N.C. A8 RAS3 N.C. 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 N.C. 36 N.C. VSS CAS2 CAS1 RAS1 WE DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 PD0 PD2 N.C. 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 N.C. 38 CAS0 40 CAS3 42 RAS0 44 N.C. 46 N.C. 48 DQ24 50 DQ25 52 DQ26 54 DQ27 56 DQ28 58 DQ29 60 DQ30 62 DQ31 64 N.C. 66 PD1 68 PD3 70 VSS 72 A0-A9 Address Inputs DQ0-DQ31 Data Input/Output CAS0 - CAS3 Column Address Strobe RAS0 - RAS3 Row Address Strobe WE Read/Write Input VCC Power (+ 5 V) VSS Ground PD Presence Detect Pin N.C. No Connection Presence Detect Pins -50 -60 PD0 N.C. N.C. PD1 N.C. N.C PD2 VSS N.C. PD3 VSS N.C. Pin Configuration Semiconductor Group 3 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module RAS1 RAS0 CAS0 CAS1 UCAS LCAS RAS UCAS LCAS RAS DQ0-DQ7 I/O1-I/O8 I/O1-I/O8 DQ8-DQ15 I/O9-I/O16 I/O9-I/O16 OE OE D1 RAS3 RAS2 CAS2 CAS3 UCAS LCAS RAS DQ16-DQ23 DQ24-DQ31 I/O1-I/O8 I/O9-I/O16 I/O9-I/O16 D2 A0 - A9 D1 - D4 WE D1 - D4 VCC C1 -C4 Block Diagram Semiconductor Group UCAS LCAS RAS I/O1-I/O8 OE VSS D3 4 OE D4 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 °C Storage temperature range...................................................................................... – 55 to + 125 °C Input/output voltage ........................................................................................................ – 1 to + 7 V Power supply voltage...................................................................................................... – 1 to + 7 V Power dissipation................................................................................................................... 2.52 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage ( IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage ( IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current (0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA 1) Average VCC supply current: ICC1 – – 400 360 mA mA 2) 3) 4) – 8 mA – – – 400 360 mA mA 2) 4) – – 180 150 mA mA 2) 3) 4) -50 ns version -60 ns version (RAS, CAS, address cycling: tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) ICC2 Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version (RAS cycling, CAS = VI,H, tRC = tRC min.) ICC3 Average VCC supply current,during hyper page ICC4 mode (EDO): -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: (tHPC = tHPC min.) Semiconductor Group 5 2) 3) 4) 2) 4) 2) 3) 4) HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 2 ns Parameter Symbol Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC min.) ICC6 Limit Values min. max. Unit Test Condition – 4 mA 1) – – 400 360 mA mA 2) 4) 2) 4) Capacitance TA = 0 to 70 °C; VCC = 5 V ± 10 %; f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A9) CI1 – 35 pF Input capacitance (RAS0, RAS2) CI2 – 20 pF Input capacitance (CAS0-CAS3) CI3 – 20 pF Input capacitance (WE) CI4 – 35 pF I/O capacitance (DQ0-DQ31) CIO1 – 25 pF Semiconductor Group 6 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 Unit Note -60 min. max. min. max. common parameters Random read or write cycle time tRC 84 – 104 – ns RAS precharge time tRP 30 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 8 10k 10 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 8 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 8 – 10 – ns RAS to CAS delay time tRCD 12 37 14 45 ns RAS to column address delay time tRAD 10 25 12 30 ns RAS hold time tRSH 13 15 – ns CAS hold time tCSH 40 50 – ns CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 1 50 1 50 ns Refresh period tREF – 16 – 16 ms Access time from RAS tRAC – 50 – 60 ns 8, 9 Access time from CAS tCAC – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8,10 Column address to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 7 Read Cycle Semiconductor Group 7 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns Parameter Limit Values Symbol -50 Unit Note -60 min. max. min. max. Early Write Cycle Write command hold time tWCH 8 – 10 – ns Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – ns Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS 0 – 0 – ns 14 Data hold time tDH 8 – 10 – ns 14 Hyper page mode (EDO) cycle time tHPC 20 – 25 – ns CAS precharge time tCP 8 – 10 – ns Access time from CAS precharge tCPA – 27 – 32 ns Output data hold time tCOH 5 – 5 – ns RAS pulse width in hyper page mode tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHCP 27 – 32 – ns CAS setup time tCSR 10 – 10 – ns CAS hold time tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – ns 13 Hyper Page Mode (EDO) Cycle CAS before RAS Refresh Cycle Semiconductor Group 8 7 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module Notes 1) All voltages are referenced to VSS. Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50% points with amplitude measured peak to the DC reference. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA. t CAC is measured from tristate. . 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge. Semiconductor Group 9 HYM 322005S/GS-50/-60 2M × 32-Bit EDO-Module L-SIM-72-10 Module package (single in-line memory module) GLS58332 Semiconductor Group 10