1M x 16-Bit Dynamic RAM (4k-Refresh) HYB5116160BSJ-50/-60/-70 Advanced Information • • • • • • • • • • • • 1 048 576 words by 16-bit organization 0 to 70 °C operating temperature Performance: -50 -60 -70 tRAC RAS access time 50 60 70 ns tCAC CAS access time 13 15 20 ns tAA Access time from address 25 30 35 ns tRC Read/Write cycle time 90 110 130 ns tPC Fast page mode cycle time 35 40 45 ns Single + 5 V (± 10 %) supply Low power dissipation max. 550 active mW (-50 version) max. 495 active mW (-60 version) max. 440 active mW (-70 version) 11 mW standby (TTL) 5.5. mW standby (MOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and self refresh Fast page mode capability 2 CAS / 1 WE All inputs, outputs and clocks fully TTL-compatible 4096 refresh cycles/64 ms Plastic Package: P-SOJ-42-1 400 mil Semiconductor Group 1 1.96 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM The HYB 5116160BSJ is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The HYB 5116160BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5116160BSJ to be packaged in a standard SOJ 42 400 mil plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL. Ordering Information Type Ordering Code Package HYB 5116160BSJ-50 on request P-SOJ-42-1 400 mil DRAM (access time 50 ns) HYB 5116160BSJ-60 on request P-SOJ-42-1 400 mil DRAM (access time 60 ns) HYB 5116160BSJ-70 on request P-SOJ-42-1 400 mil DRAM (access time 70 ns) Pin Names A0 to A11 Row Address Inputs A0 to A7 Column Addess Inputs RAS Row Address Strobe OE Output Enable I/O1-I/O16 Data Input/Output UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe WE Read/Write Input VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. not connected Semiconductor Group 2 Descriptions HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM P-SOJ-42 (400 mil) Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS A11 A10 A0 A1 A2 A3 Vcc 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 Vss Pin Configuration Truth Table RAS LCAS UCAS WE OE I/O1-I/O8 I/O9-I/O16 Operation H H H H H High-Z High-Z Standby L H H H H High-Z High-Z Refresh L L H H L Dout High-Z Lower byte read L H L H L High-Z Dout Upper byte read L L L H L Dout Dout Word read L L H L H Din Don't care Lower byte write L H L L H Don't care Din Upper byte write L L L L H Din Din Word write L L L H H High-Z High-Z NOP Semiconductor Group 3 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM I/O16 I/O1 I/O2 WE UCAS LCAS & . . Data in Buffer No. 2 Clock Generator 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Data out Buffer 16 16 Column Address Buffer(8) OE Column 8 Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 16 256 x16 12 Row 12 RAS Address Buffers(12) Row Decoder 4096 12 No. 1 Clock Generator Voltage Down Generator Block Diagram Semiconductor Group Memory Array 4096x256x16 4 VCC VCC (internal) HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 °C Storage temperature range.........................................................................................– 55 to 150 °C Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V Power supply voltage...................................................................................................-1.0V to 7.0 V Power dissipation..................................................................................................................... 1.0 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 Vcc+0.5 V 1) Input low voltage VIL – 0.5 0.8 V 1) Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1) Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1) Input leakage current,any input (0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V) II(L) – 10 10 µA 1) Output leakage current (DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V) IO(L) – 10 10 µA 1) Average VCC supply current: ICC1 – – – 100 90 80 mA mA mA 2) 3) 4) Standby VCC supply current (RAS = CAS = VIH) ICC2 – 2 mA – Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version -70 ns version – – – 100 90 80 mA mA mA 2) 4) -50 ns version -60 ns version -70 ns version 2) 3) 4) 2) 3) 4) (RAS, CAS, address cycling, tRC = tRC min.) ICC3 (RAS cycling: CAS = VIH, tRC = tRC min.) Semiconductor Group 5 2) 4) 2) 4) HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %, tT = 5 ns Parameter Average VCC supply current, during fast page mode: -50 ns version -60 ns version -70 ns version Symbol Limit Values min. max. Unit Test Condition – – – 40 35 30 mA mA mA – 1 mA – – – 100 90 80 mA mA mA _ 1 mA ICC4 2) 3) 4) 2) 3) 4) 2) 3) 4) (RAS = VIL, CAS, address cycling, tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC – 0.2 V) ICC5 Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version -70 ns version ICC6 1) 2) 4) 2) 4) 2) 4) (RAS, CAS cycling, tRC = tRC min.) Average Self Refresh Current ICC7 (CBR cycle with tRAS>TRASSmin., CAS held low, WE=Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) Capacitance TA = 0 to 70 °C,VCC = 5 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A11) CI1 – 5 pF Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2 – 7 pF I/O capacitance (I/O1-I/O16) CIO – 7 pF Semiconductor Group 6 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM AC Characteristics 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. common parameters Random read or write cycle time tRC 90 – 110 – 130 – ns RAS precharge time tRP 30 – 40 – 50 – ns RAS pulse width tRAS 50 10k 60 10k 70 10k ns CAS pulse width tCAS 13 10k 15 10k 20 10k ns Row address setup time tASR 0 – 0 – 0 – ns Row address hold time tRAH 8 – 10 – 10 – ns Column address setup time tASC 0 – 0 – 0 – ns Column address hold time tCAH 10 – 15 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 20 50 RAS to column address delay time tRAD 13 25 15 30 15 35 ns RAS hold time tRSH 13 15 – 20 – ns CAS hold time tCSH 50 60 – 70 – ns CAS to RAS precharge time tCRP 5 – 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 3 50 ns Refresh period tREF – 64 – 64 – 64 ms Access time from RAS tRAC – 50 – 60 – 70 ns 8, 9 Access time from CAS tCAC – 13 – 15 – 20 ns 8, 9 Access time from column address tAA – 25 – 30 – 35 ns 8,10 OE access time – 13 – 15 – 20 ns Column address to RAS lead time tRAL 25 – 30 – 35 – ns Read command setup time tRCS 0 – 0 – 0 – ns Read command hold time tRCH 0 – 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – 0 – ns 11 CAS to output in low-Z tCLZ 0 – 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 0 20 ns 12 7 Read Cycle Semiconductor Group tOEA 7 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 Unit Note -60 -70 min. max. min. max. min. max. Output buffer turn-off delay from OE tOEZ 0 13 0 15 0 20 ns 12 Data to OE low delay tDZO 0 – 0 – 0 – ns 13 CAS high to data delay tCDD 13 – 15 – 20 – ns 14 OE high to data delay tODD 13 – 15 – 20 – ns 14 Write command hold time tWCH 8 – 10 – 10 – ns Write command pulse width tWP 8 – 10 – 10 – ns Write command setup time tWCS 0 – 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – 20 – ns Write command to CAS lead time tCWL 13 – 15 – 20 – ns Data setup time tDS 0 – 0 – 0 – ns 16 Data hold time tDH 10 – 10 – 15 – ns 16 Data to CAS low delay tDZC 0 – 0 – 0 – ns 13 Read-write cycle time tRWC 126 – 150 – 180 – ns RAS to WE delay time tRWD 68 – 80 – 95 – ns 15 CAS to WE delay time tCWD 31 – 35 – 45 – ns 15 Column address to WE delay time tAWD 43 – 50 – 60 – ns 15 OE command hold time tOEH 13 – 15 – 20 – ns Fast page mode cycle time tPC 35 – 40 – 45 – ns CAS precharge time tCP 10 – 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 – 40 ns RAS pulse width tRAS 50 200k 60 200k 70 200k ns CAS precharge to RAS Delay tRHPC 30 – – – Write Cycle 15 Read-Modify-Write Cycle Fast Page Mode Cycle Semiconductor Group 8 35 40 ns 7 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM AC Characteristics (cont’d) 5)6) TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns Parameter 16F Limit Values Symbol -50 min. Unit Note -60 -70 max. min. max. min. max. Fast Page Mode Read-Modify-Write Cycle Fast page mode read-write cycle time tPRWC 71 – 80 – 95 – ns CAS precharge to WE tCPWD 48 – 55 – 65 – ns CAS setup time tCSR 10 – 10 – 10 – ns CAS hold time tCHR 10 – 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – 10 – ns tCPT 35 – 40 – 40 – ns RAS pulse width tRASS 100k _ 100k _ 100k _ ns 17 RAS precharge time tRPS 95 _ 110 _ 130 _ ns 17 CAS hold time tCHS -50 _ -50 _ -50 _ ns 17 CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Self Refresh Cycle Semiconductor Group 9 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM Notes: 1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13)Either tDZC or tDZO must be satisfied. 14)Either tCDD or tODD must be satisfied. 15)tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16)These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. Semiconductor Group 10 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRAS RAS V IH VIL tCSH V IH VIL tRAD tASR tCRP tRSH tCAS tRCD UCAS LCAS tRP tRAL tCAH tASC tASR V Address IH VIL Column Address Row Address Row Address tRCH tRAH tRCS WE tRRH V IH VIL tAA tOEA V OE IH VIL tCDD tDZC tODD tDZO V I/O1-I/O16 IH (Inputs) V tCAC IL tCLZ V I/O1-I/O16 OH Hi Z (Outputs) V Valid Data Out OL tRAC “H” or “L” Read Cycle Semiconductor Group tOFF tOEZ 11 Hi Z HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD tRSH tCAS V IH UCAS LCAS VIL tRAD tASR Address V IH VIL OE . tWCS V WE tASR Column Address Row Address tRAH tRAL tCAH tASC Row Address tCWL t WP IH VIL tWCH tRWL V IH VIL tDS tDH V I/O1-I/O16 IH (Inputs) V Valid Data In IL V I/O1-I/O16 OH (Outputs) V Hi Z OL “H” or “L” Write Cycle (Early Write) Semiconductor Group tCRP 12 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCSH tRCD V IH UCAS LCAS VIL tRAD tASR tCRP tRSH tCAS tCAH tASC tRAL tASR . V Address IH VIL Row Address Column Address Row Address tCWL tRWL tWP tRAH V WE IH VIL tOEH V OE IH VIL tODD tDZO tDZC tDS tOEZ V I/O1-I/O16 IH (Inputs) V tDH Valid Data IL tCLZ tOEA V I/O1-I/O16 OH (Outputs) V Hi-Z Hi-Z OL “H” or “L” Write Cycle (OE Controlled Write) Semiconductor Group 13 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRWC tRAS tRP V IH RAS VIL tCSH tRSH tCAS tRCD UCAS LCAS V IH tCRP VIL tCAH tRAH tASR tASC tASR V IH Address VIL Column Address Row Address Row Address tCWL tRWL tAWD tRAD tCWD tRWD tWP V IH WE VIL tAA tOEA tRCS tOEH V IH OE VIL tDZO tDS tDZC tDH V IH Valid Data in I/O1-I/O16 (Inputs) VIL tCLZ tCAC tOEZ V I/O1-I/O16 OH Data Out (Outputs) VOL tRAC “H” or “L” Read-Write (Read-Modify-Write) Cycle Semiconductor Group tODD 14 Semiconductor Group Fast Page Mode Read-Modify-Write Cycle 15 IH IH IH IH V IH V IL V V IL V V IL V V IL V V IL IH OL I/O1-I/O16 OH (Outputs) V V I/O1-I/O16 (Inputs) V IL OE WE Address UCAS LCAS RAS V tASR tRAC tCAS tAA tOEA tCAC Data In tDS tOEH tCAC tCLZ tOEZ tWP tDS tDH Data In tODD Data Out tOEA tAWD tCPA tAA tDZC tCAS tPRWC tCPWD tCWD tCAH Column Address tASC tCP tCWL tWP tOEZ tDH tODD Data Out tAWD tRWD tCWD Column Address tASC tCAH tDZC tCLZ tDZO tRCS “H” or “L” Row Address tRAD tRAH tRCD tCSH tRASP tOEH tDZC tCWL tAWD tAA tCLZ tCPA tRAL Data Out tDS tDH tOEH tRWL tCWL tWP Data In tODD tCPWD tCWD tOEA Column Address tASC tCAH tCAS tRSH tCRP Row Address tASR tRP HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRASP tRP V IH RAS VIL UCAS LCAS tCP tCAS V IH VIL tASR Address VIL tCAS tCAS tCRP tCSH tRAH V IH tRHCP tRSH tPC tRCD tCAH tASC Row Addr tASC Column Address tCAH tCAH tASR tASC Column Address Column Address tRAD Row Address tRCH tRCH tRCS tRCS tRCS tCPA tAA tCPA tAA tOEA V IH WE VIL tAA tOEA V tOEA tRRH IH OE VIL IL tCAC tOFF tCLZ tOFF tOEZ tCAC tCAC tOFF tCLZ tOEZ V I/O1-I/O16 OH (Outputs) V Valid Data Out OL “H” or “L” Fast Page Mode Read Cycle Semiconductor Group 16 tODD tODD tODD I/O1-I/O16 IH (Inputs) V tCDD tDZO tDZO tDZO V tDZC tDZC tDZC Valid Data Out tCLZ tOFF tOEZ Valid Data Out HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRASP tRP V IH RAS VIL tPC tCAS tRCD UCAS LCAS V IH VIL tRAL tRAH tCAH tASC V IH VIL Row Addr Column Address tASC tCAH Column Address tWCS tWCH tWP V IH tASC tCAH Column Address tCWL tRWL tWCS tCWL tWCS tCWL tRAD WE tCRP tCP tASR Address tRSH tCAS tCAS tWCH tWP tWCH tWP tDH tDH VIL V OE IH VIL tDH tDS tDS tDS V I/O1-I/O16 IH (Inputs) V IL Valid Data In Valid Data In Valid Data In V I/O1-I/O16 OH (Outputs) V HI-Z OL “H” or “L” Fast Page Mode Early Write Cycle Semiconductor Group 17 tASR Column Address HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRAS tRP V IH RAS VIL tCRP tRPC UCAS LCAS V IH VIL tRAH tASR tASR V Address IH Row Address VIL Row Address V I/O1-I/O16 OH (Outputs) V HI-Z OL “H” or “L” RAS-Only Refresh Cycle Semiconductor Group 18 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRP tRP tRAS V RAS IH VIL tCRP tRPC tCSR UCAS LCAS V IH VIL tRPC tCHR tCP tWRP tWRH V WE IH VIL tOEZ V IH OE VIL tCDD V I/O1-I/O16 IH (Inputs) V IL tODD V I/O1-I/O16 OH (Outputs)VOL HI-Z tOFF “H” or “L” CAS-Before-RAS Refresh Cycle Semiconductor Group 19 HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRC RAS tRP tRAS V tRP tRAS IH VIL tRCD tRSH tCRP tCHR UCAS LCAS V IH tRAD VIL tASC tRAH tASR tWRP tASR tWRH tCAH V Address IH VIL Column Address Row Addr Row Address tRRH tRCS V WE IH VIL tAA tOEA V OE IH VIL tDZC tCDD tDZO tODD V I/O1-I/O16 IH (Inputs) V IL tOFF tCAC tCLZ tOEZ tRAC V I/O1-I/O16 OH (Outputs) V Valid Data Out OL “H” or “L” Hidden Refresh Cycle (Read) Semiconductor Group 20 HI-Z HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRC tRC tRP RAS IH tRSH tCRP IH VIL tRAD tRAH tASC tCAH V IH VIL Row Addr tASR Row Address Column Address tWCS tWRP tWCH tWP V WE tCHR V tASR Address tRAS VIL tRCD UCAS LCAS tRP tRAS V IH VIL tDS tDH V I/O1-I/O16 IH (Input) V IL Valid Data V I/O1-I/O16 OH (Output) V OL HI-Z “H” or “L” Hidden Refresh Cycle (Early Write) Semiconductor Group 21 tWRH HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM tRP RAS tRASS tRPS V IH VIL tRPC tCHS tCSR V UCAS LCAS IH tCP VIL tWRP tWRH V WE IH VIL tOEZ OE V IH VIL tCDD V I/O1-I/O16 IH (Inputs) V IL tODD V I/O1-I/O16 OH (Outputs) V OL HI-Z tOFF “H” or “L” CAS before RAS Self Refresh Cycle Semiconductor Group 22 tCRP HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM V RAS V IL tCHR tCSR UCAS LCAS V V IH V tWRP V tASR Row Address Column Address IL tRCS tWRH V tRAL tCAH tASC IH Read Cycle WE tRSH tCAS tCPT IL V Address tRP tRAS IH tAA tRRH tRCH tCAC IH IL tOEA V IH OE V I/O1-I/O16 (Inputs) IL V V tDZC tDZO IH IL tOFF tCLZ I/O1-I/O16 (Outputs) V OH V OL Write Cycle V Valid Data Out tWCS tWRP tRWL tCWL tWCH IH IL V OE V IH IL tDH tDS I/O1-I/O16 (Inputs) I/O1-I/O16 (Outputs) V V IH V V IH IL V V I/O1-I/O16 (Inputs) I/O1-I/O16 (Outputs) HI-Z tRCS tWRH tAA tOEH IH tDS tDZC tDZO tDH IH Data In IL tCLZ V OH V tWP tOEA IL V tCWL tRWL tAWD tCWD tCAC IL V V tWRP IH V OE Valid Data In IL Read-Modify-Write Cycle WE tOEZ tWRH V WE tCDD tODD OL D.Out HI-Z CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group tODD tOEZ tCAC 23 HI-Z HYB 5116160BSJ-50/-60/-70 1M x 16-DRAM Package Outlines Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD) 1) 10.3 -0.3 B 0.81 max. 1.27 0.43 9.4 +- 0.1 0.18 A 0.08 42x 11.2 + - 0.25 +- 0.15 25.4 42 22 1 GPJ05853 21 1) 27.43 -0.25 A Index marking 1) does not include plastic or metal protusion of 0.15 max per side Semiconductor Group 24 0.18 B