INFINEON C540U

Microcomputer Components
8-Bit CMOS Microcontroller
C540U / C541U
Data Sheet 10.97
C540U/C541U Data Sheet
Revision History :
1997-10-01
Previous Releases :
none (Original Version)
Page / Chapters
Subjects (changes since last revision)
Edition 1997-10-01
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C540U
C541U
8-Bit CMOS Microcontroller
Advance Information
•
•
•
•
On-Chip Emulation Support Module
•
Enhanced 8-bit C500 CPU
– Full software/toolset compatible to standard 80C51/80C52 microcontrollers
12 MHz external operating frequency
– 500 ns instruction cycle
Built-in PLL for USB synchronization
On-chip OTP program memory
– C540U : 4K byte
– C541U : 8K byte
– Alternatively up to 64K byte external program memory
– Optional memory protection
On-chip USB module
– Compliant to USB specification
– Full speed or low speed operation
– Five endpoints : one bidirectional control endpoint
four versatile programmable endpoints
– Registers are located in special function register area
– On-chip USB transceiver
Oscillator
Watchdog
SSC
Power
Saving
Modes
RAM
256 x 8
Watchdog
Timer
T0
I/O
Port 1
I/O
Port 2
I/O
Port 3
I/O
CPU
USB
Module
USB Transceiver
D+
T1
OTP Prog. Memory
C540U : 4 k x 8
C541U : 8 k x 8
D-
The shaded units are not available in the C540U.
Semiconductor Group
Port 0
3
MCA03373
1997-10-01
C540U
C541U
Features (cont’d) :
•
•
•
•
•
•
•
•
•
•
•
•
Up to 64K byte external data memory
256 byte on-chip RAM
Four parallel I/O ports
– P-LCC-44 package : three 8-bit ports and one 6-bit port
– P-SDIP-52 package : four 8-bit ports
– LED current drive capability for 3 pins (10 mA)
Two 16-bit timer/counters (C501 compatible)
SSC synchronous serial interface (SPI compatible) (only C541U)
– Master and slave capable
– Programmable clock polarity / clock-edge to data phase relation
– LSB/MSB first selectable
– 1.5 MBaud transfer rate at 12 MHz operating frequency
7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels
Enhanced fail safe mechanisms
– Programmable watchdog timer (only C541U)
– Oscillator watchdog
Power saving modes
– idle mode
– software power down mode with wake-up capability through INT0 pin or USB
On-chip emulation support logic (Enhanced Hooks Technology TM)
P-LCC-44 and P-SDIP-52 packages
Power supply voltage range : 4.0V to 5.5V
TA = 0 to 70 °C
Temperature Range :
SAB-C540U
TA = 0 to 70 °C
SAB-C541U
Table 1
Ordering Information
Type
Ordering Code
Package
Description
(8-Bit CMOS microcontroller)
SAB-C540U-EN
Q67126-C2042
P-LCC-44-2
8-Bit CMOS microcontroller (12 MHz)
SAB-C540U-EP
Q67120-C2043
P-SDIP-52-1
8-Bit CMOS microcontroller (12 MHz)
SAB-C541U-1EN
Q67126-C2001
P-LCC-44-2
8-Bit CMOS microcontroller (12 MHz)
SAB-C541U-1EP
Q67120-C2021
P-SDIP-52-1
8-Bit CMOS microcontroller (12 MHz)
Semiconductor Group
4
1997-10-01
C540U
C541U
V CC
V SS
XTAL2
Port 0
8-Bit Digital I / O
XTAL1
Port 1
P-LCC-44 : 6-Bit Digital I / O
P-SDIP-52 : 8-Bit Digital I / O
ALE
PSEN
EA
C540U
C541U
Port 2
8-Bit Digital I / O
RESET
Port 3
8-Bit Digital I / O
D+
D-
MCL03374
Figure 2
Logic Symbol
Additional Literature
For further information about the C540U/C541U the following literature is available :
Title
Ordering Number
C540U/C541U 8-Bit CMOS Microcontroller User’s Manual
B158-H????-X-X-7600
C500 Microcontroller Family
Architecture and Instruction Set User’s Manual
B158-H6987-X-X-7600
C500 Microcontroller Family - Pocket Guide
B158-H6986-X-X-7600
Semiconductor Group
5
1997-10-01
P1.1 / LED1
P1.0 / LED0
DD+
V SSU
V CCU
P1.5 / SLS
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
C540U
C541U
6 5 4 3 2 1 44 43 42 41 40
P1.2 / SCLK
V CC
V SS
RESET
P3.0 / LED2
P1.3 / SRI
P3.1 / DADD
P3.2 / INT0
P3.3 / INT1
P3.4 / T0
P3.5 / T1
7
8
9
10
11
12
13
14
15
16
17
C540U
C541U
39
38
37
36
35
34
33
32
31
30
29
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
EA
P1.4 / STO
ALE
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P3.6 / WR
P3.7 / RD
XTAL2
XTAL1
V SS
V CC
P2.0 / A8
P2.1 / A9
P2.2 / A10
P2.3 / A11
P2.4 / A12
18 19 20 21 22 23 24 25 26 27 28
This pin functionality ist not available for the C540U.
MCP03343
Figure 3
Pin Configuration P-LCC-44 Package (top view)
Semiconductor Group
6
1997-10-01
C540U
C541U
V CCU
1
52
N.C.
V SSU
2
51
P1.5 / SLS
D+
3
50
P0.0 / AD0
D-
4
49
P0.1 / AD1
N.C.
5
48
P0.2 / AD2
N.C.
6
47
P0.3 / AD3
P1.0 / LED0
7
46
P0.4 / AD4
P1.1 / LED1
8
45
P0.5 / AD5
P1.2 / SCLK
9
44
P0.6 / AD6
V CC
10
43
P0.7 / AD7
V SS
11
42
EA
RESET
12
41
P1.4 / STO
P3.0 / LED2
13
40
P1.7
P1.3 / SRI
14
39
ALE
P1.6
15
38
PSEN
P3.1 / DADD
16
37
N.C.
P3.2 / INT0
17
36
N.C.
P3.3 / INT1
18
35
P2.7 / A15
P3.4 / T0
19
34
P2.6 / A14
P3.5 / T1
20
33
P2.5 / A13
P3.6 / WR
21
32
P2.4 / A12
P3.7 / RD
22
31
P2.3 / A11
XTAL2
23
30
P2.2 / A10
XTAL1
24
29
P2.1 / A9
V SS
25
28
P2.0 / A8
V CC
26
27
N.C.
C540U
C541U
MCP03344
This pin functionality ist not available for the C540U.
Figure 4
Pin Configuration P-SDIP-52 Package (top view)
Semiconductor Group
7
1997-10-01
C540U
C541U
Table 2
Pin Definitions and Functions
Symbol
Pin Numbers
I/O*) Function
P-LCC-44
P-SDIP-52
D+
3
3
I/O
USB D+ Data Line
The pin D+ can be directly connected to USB cable
(transceiver is integrated on-chip).
D-
4
4
I/O
USB D- Data Line
The pin D- can be directly connected to USB cable
(transceiver is integrated on-chip).
P1.0 - P1.4
7 - 9, 14, 41, I/O
5 - 7,
12, 34, 44 51, 15, 40
Port 1
is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasibidirectional I/O port with internal pullup resistors.
Port 1 pins that have 1's written to them are pulled
high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins
being externally pulled low will source current (I IL,
in the DC characteristics) because of the internal
pullup resistors.
Port 1 also contains two outputs with LED drive
capability as well as the four pins of the SSC
(C541U only). The output latch corresponding to a
secondary function must be programmed to a one
(1) for that function to operate (except when used
for the compare functions). The secondary
functions are assigned to the port 1 pins as follows :
P1.0 / LED0 LED0 output
P1.1 / LED1 LED1 output
P1.2 / SCLK SSC Master Clock Output /
SSC Slave Clock Input (C541U only)
P1.3 / SRI SSC Receive Input (C541U only)
P1.4 / STO SSC Transmit Output (C541U only)
P1.5 / SLS SSC Slave Select Inp. (C541U only)
P1.6
(P-SDIP-52 only)
P1.7
(P-SDIP-52 only)
RESET
5
6
7
7
8
9
12
34
44
–
–
13
41
51
15
40
10
12
I
RESET
A high level on this pin for the duration of two
machine cycles while the oscillator is running
resets the C540U/C541U. A small internal pulldown
resistor permits power-on reset using only a
capacitor connected to VCC .
*) I = Input
O = Output
Semiconductor Group
8
1997-10-01
C540U
C541U
Table 2
Pin Definitions and Functions
Symbol
(cont’d)
Pin Numbers
P-LCC-44
I/O*) Function
P-SDIP-52
P3.0 - P3.7
11, 13 - 19 13, 16 - 22
I/O
Port 3
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 3 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 3 pins being externally pulled low will source
current (I IL, in the DC characteristics) because of
the internal pullup resistors. Port 3 also contains
the interrupt, timer, serial port and external memory
strobe pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function
to operate. The secondary functions are assigned
to the pins of port 3, as follows:
P3.0 / LED2
LED2 output
P3.1 / DADD
Device attached input
External interrupt 0 input /
P3.2 / INT0
timer 0 gate control input
P3.3 / INT1
External interrupt 1 input /
timer 1 gate control input
P3.4 / T0
Timer 0 counter input
P3.5 / T1
Timer 1 counter input
P3.6 / WR
WR control output; latches the
data byte from port 0 into the
external data memory
RD control output; enables the
P3.7 / RD
external data memory
XTAL2
20
23
–
XTAL2
is the output of the inverting oscillator amplifier.
This pin is used for the oscillator operation with
crystal or ceramic resonator.
XTAL1
21
24
–
XTAL1
is the input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left
unconnected. Minimum and maximum high and
low times as well as rise/fall times specified in the
AC characteristics must be observed.
*) I = Input
O = Output
Semiconductor Group
9
1997-10-01
C540U
C541U
Table 2
Pin Definitions and Functions
Symbol
(cont’d)
Pin Numbers
I/O*) Function
P-LCC-44
P-SDIP-52
P2.0 - P2.7
24 - 31
28 - 35
I/O
Port 2
is an 8-bit quasi-bidirectional I/O port with internal
pullup resistors. Port 2 pins that have 1's written to
them are pulled high by the internal pullup resistors,
and in that state can be used as inputs. As inputs,
port 2 pins being externally pulled low will source
current (I IL, in the DC characteristics) because of
the internal pullup resistors.
Port 2 emits the high-order address byte during
fetches from external program memory and during
accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullup resistors when issuing
1's. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 issues the
contents of the P2 special function register.
PSEN
32
38
O
The Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator
periods except during external data memory
accesses. The signal remains high during internal
program execution.
ALE
33
39
O
The Address Latch enable
output is used for latching the address into external
memory during normal operation. It is activated
every six oscillator periods except during an
external data memory access.
EA
35
42
I
External Access Enable
When held high, the C540U/C541U executes
instructions from the internal ROM as long as the
PC is less than 1000H for the C540U or less than
2000H for the C541U. When held low, the C540U/
C541U fetches all instructions from external
program memory. For the C540U-L/C541U-L this
pin must be tied low.
*) I = Input
O = Output
Semiconductor Group
10
1997-10-01
C540U
C541U
Table 2
Pin Definitions and Functions
Symbol
(cont’d)
Pin Numbers
I/O*) Function
P-LCC-44
P-SDIP-52
P0.0 - P0.7
44 - 36
50 - 43
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0
pins that have 1's written to them float, and in that
state can be used as high-impedance inputs. Port 0
is also the multiplexed low-order address and data
bus during accesses to external program and data
memory. In this application it uses strong internal
pullup resistors when issuing 1's.
VCCU
1
1
–
Supply voltage
for the on-chip USB transceiver circuitry.
VSSU
2
2
–
Ground (0V)
for the on-chip USB transceiver circuitry.
VCC
8, 23
10, 26
–
Supply voltage
for ports and internal logic circuitry during normal,
idle, and power down mode.
VSS
9, 22
11, 25
–
Ground (0V)
for ports and internal logic circuitry during normal,
idle, and power down mode.
*) I = Input
O = Output
Semiconductor Group
11
1997-10-01
C540U
C541U
Oscillator Watchdog
XTAL2
OSC & Timing
XTAL1
OTP Memory
RAM
256 x 8
4k x 8 (C540U)
8k x 8 (C541U)
ALE
CPU
PSEN
Progr. Watchdog
Timer (C541U only)
Emulation
Support
Logic
Timer 0
Port 0
Port 0
8-Bit Digit. I/O
Port 1
Port 1
1)
6- / 8-Bit Digit. I/O
Port 2
Port 2
8-Bit Digit. I/O
Port 3
Port 3
8-Bit Digit. I/O
EA
RESET
Timer 1
D+
D-
Transceiver
SSC (SPI) Interface
(C541U only)
PLL
USB
Module
C540U
C541U
Interrupt Unit
1)
P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port
MCB03345
Figure 5
Block Diagram of the C540U/C541U
Semiconductor Group
12
1997-10-01
C540U
C541U
CPU
The C540U/C541U is efficient both as a controller and as an arithmetic processor. It has extensive
facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of
program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and
15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns.
Special Function Register PSW (Address D0H)
Reset Value : 00H
Bit No. MSB
D0H
LSB
D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0
General Purpose Flag
RS1
RS0
Register Bank Select Control Bits
These bits are used to select one of the four register banks.
PSW
RS1
RS0
Function
0
0
Bank 0 selected, data address 00H-07H
0
1
Bank 1 selected, data address 08H-0FH
1
0
Bank 2 selected, data address 10H-17H
1
1
Bank 3 selected, data address 18H-1FH
OV
Overflow Flag
Used by arithmetic instruction.
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
13
1997-10-01
C540U
C541U
Memory Organization
The C540U/C541U CPU manipulates operands in the following four address spaces:
–
–
–
–
–
8 or 4 KByte on-chip OTP program memory
Totally up to 64 Kbyte internal/external program memory
up to 64 Kbyte of external data memory
256 bytes of internal data memory
a 128 byte special function register area
Figure 6 illustrates the memory address spaces of the C540U/C541U.
FFFF H
FFFF H
External
Indirect
Addr.
External
FF H
80 H
1FFF H 1)
Internal
(EA = 1)
80 H
7F H
External
(EA = 0)
Internal
RAM
0000 H
"Code Space"
FF H
Special
Function
Register
Internal
RAM
2000 H 1)
Direct
Addr.
0000 H
"External Data Space"
1) For the C504U the int. / ext. program memory boundary is at 0FFF H / 1000 H .
00 H
"Internal Data Space"
MCD03375
Figure 6
C540U/C541U Memory Map Memory Map
Semiconductor Group
14
1997-10-01
C540U
C541U
Reset and System Clock
The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VCC via a capacitor. Figure 7 shows the possible reset circuitries.
VCC
+
a)
b)
C540U
C541U
RESET
VCC
&
VCC
+
C540U
C541U
RESET
c)
C540U
C541U
RESET
MCD03376
Figure 7
Reset Circuitries
Semiconductor Group
15
1997-10-01
C540U
C541U
The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-8. The crystal
oscillator generates the system clock for the microcontroller. The USB module can be provided with
the following clocks :
– Full speed operation : 48 MHz with a data rate of 12 Mbit/s
– Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s
The low speed clock is generated by a dividing the system clock by 2. The full speed clock is
generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled
or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit
SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general
enable bit for the USB clock.
XTAL1
Pin
12 MHz
XTAL2
Pin
System Clock
of the
Microcontroler
Crystal 12 MHz
Oscillator
Divider
by 2
Enable
PLL
x4
PCLK
DCR.0
6 MHz
48 MHz
1
0
to USB
Module
SPEED
DCR.7
C540U / C541U
UCLK
DCR.1
MCB03377
Figure 8
Block Diagram of the Clock Generation Circuitry
Semiconductor Group
16
1997-10-01
C540U
C541U
The clock generator provides the internal clock signals to the chip. These signals define the internal
phases, states and machine cycles. Figure 9 shows the recommended oscillator circuits for crystal
and external clock operation.
C
XTAL2
C540U
C541U
12 MHz
C
XTAL1
C = 20 pF 10 pF for crystal operation
C540U
C541U
V CC
N.C.
External
Clock
Signal
XTAL2
XTAL1
MCD03378
Figure 9
Recommended Oscillator Circuitries
Semiconductor Group
17
1997-10-01
C540U
C541U
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.
ICE-System Interface
to Emulation Hardware
RESET
EA
ALE
PSEN
SYSCON
PCON
TCON
C500
MCU
RSYSCON
RPCON
RTCON
EH-IC
Enhanced Hooks
Interface Circuit
Port 0
Port 2
Optional
I/O Ports
Port 3
Port 1
RPort 2 RPort 0
Target System Interface
TEA TALE TPSEN
MCS02647
Figure 10
Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.
Semiconductor Group
18
1997-10-01
C540U
C541U
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. One special
function register of the C540U/C541U (PCON1) is located in the mapped special function register
area. All other SFRs are located in the standard special function register area.
For accessing PCON1 in the mapped special function register area, bit RMAP in special function
register SYSCON must be set.
Special Function Register SYSCON (Address B1H)
Bit No. MSB
7
B1H
–
Reset Value : XX10XXXXB
6
5
4
3
2
1
LSB
0
–
EALE
RMAP
–
–
–
–
SYSCON
The functions of the shaded bits are not described in this section.
Bit
Function
RMAP
Special function register map bit
RMAP = 0 : The access to the non-mapped (standard) special function
register area is enabled.
RMAP = 1 : The access to the mapped special function register area
(PCON1) is enabled.
As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not
cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed,
the bit RMAP must be cleared/set by software, respectively each.
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H,
88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.
The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide
an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U
are listed in table 3 to table 4. In table 3 they are organized in groups which refer to the functional
blocks of the C540U/C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric
order of their addresses.
Semiconductor Group
19
1997-10-01
C540U
C541U
Table 3
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address Contents after
Reset
CPU
ACC
B
DPH
DPL
PSW
SP
VR0
VR1
VR2
SYSCON
Accumulator
B Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
Version Register 0
Version Register 1
Version Register 2
System Control Register
E0H 1)
F0H 1)
83H
82H
D0H 1)
81H
FCH
FDH
FEH
B1H
00H
00H
00H
00H
00H
07H
C5H
C1H
YYH 3)
XX10XXXXB 2)
Interrupt
System
IEN0
IEN1
IP0
IP1
ITCON
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
External Interrupt Trigger Condition Register
A8H1)
A9H
B8H 1)
B9H)
9AH
0XXX0000B 2)
XXXXX000B 2)
XXXX0000B 2)
XXXXX000B 2)
XXXX1010B 2)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H 1)
90H 1)
A0H 1)
B0H 1)
FFH
FFH
FFH
FFH
Timer 0 /
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
SSC
Interface
(C541U
only)
SSCCON
STB
SRB
SCF
SCIEN
SSCMOD
SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register
93H 1)
94H
95H
ABH 1)
ACH
96H
07H
XXH 2)
XXH 2)
XXXXXX00B 2)
XXXXXX00B 2)
00H
Watchdog Timer Control Register
Watchdog Timer Reload Register
C0H 1)
86H
XXXX0000B 2)
00H
Watchdog WDCON
(C541U
WDTREL
only)
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01H for the first step)
4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be
set.
Semiconductor Group
20
1997-10-01
C540U
C541U
Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address Contents after
Reset
Pow.
Sav.
Modes
PCON
PCON1
Power Control Register
Power Control Register 1
87H
88H 4)
X00X0000B 2)
0XX0XXXXB 2)
USB
Module
EPSEL
USBVAL
ADROFF
GEPIR
DCR
DPWDR
DIER
DIRR
FNRL
FNRH
EPBCn 1)
EPBSn 1)
EPIEn 1)
EPIRn 1)
EPBAn 1)
EPLENn 1)
USB Endpoint Select Register
USB Data Register
USB Address Offset Register
USB Global Endpoint Interrupt Request Reg.
USB Device Control Register
USB Device Power Down Register
USB Device Interrupt Control Register
USB Device Interrupt Request Register
USB Frame Number Register, Low Byte
USB Frame Number Register, High Byte
USB Endpoint n Buffer Control Register
USB Endpoint n Buffer Status Register
USB Endpoint n Interrupt Enable Register
USB Endpoint n Interrupt Request Register
USB Endpoint n Base Address Register
USB Endpoint n Buffer Length Register
D2H
D3H
D4H
D6H
C1H
C2H
C3H
C4H
C6H
C7H
C1H
C2H
C3H
C4H
C5H
C6H
80H
00H
00H 2)
00H
000X0000B
00H
00H
00H
XXH
00000XXXB
00H
20H
00H
10H 3)
00H
0XXXXXXXB
1) These register are multiple registers (n=0-4) with the same SFR address; selection of register “n“ is done by
SFR EPSEL.
2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
3) The reset value of EPIR0 is 11H.
Semiconductor Group
21
1997-10-01
C540U
C541U
Table 4
Contents of the SFRs, SFRs in numeric order of their addresses
Addr Register Reset
Bit 7
Value1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80H 2) P0
FFH
.7
.6
.5
.4
.3
.2
.1
.0
81H
SP
.7
.6
.5
.4
.3
.2
.1
.0
82H
DPL
07H
00H
.7
.6
.5
.4
.3
.2
.1
.0
83H
DPH
.7
.6
.5
.4
.3
.2
.1
.0
86H 4)
00H
WDTREL 00H
WDT
PSEL
.6
.5
.4
.3
.2
.1
.0
87H
PCON
X00X0000B
–
PDS
IDLS
–
GF1
GF0
PDE
IDLE
00H
0XX0XXXXB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
EWPD –
–
WS
–
–
–
–
00H
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
.7
.6
.5
.4
.3
.2
.1
.0
00H
00H
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
00H
FFH
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
SLS
STO
SRI
SCLK
LED1
LED0
SCEN
TEN
MSTR
CPOL
CPHA
BRS2
BRS1
BRS0
.7
.6
.5
.4
.3
.2
.1
.0
.7
.6
.5
.4
.3
.2
.1
.0
96H 4)
XXH
SSCMOD 00H
LOOPB TRIO
0
0
0
0
0
LSBSM
9AH
ITCON
XXXX1010B
–
–
–
–
I1ETF
I1ETR
I0ETF
I0ETR
A0H2) P2
FFH
.7
.6
.5
.4
.3
.2
.1
.0
A8H2) IEN0
0XXX0000B
EA
–
–
–
ET1
EX1
ET0
EX0
A9H
IEN1
XXXXX000B
–
–
–
–
–
EUDI
EUEI
ESSC
ABH SCF
XXXXXX00B
–
–
–
–
–
–
WCOL TC
88H 2) TCON
88H
PCON1
2) 3)
89H
TMOD
8AH
TL0
8BH
TL1
8CH
TH0
8DH
TH1
90H2) P1
93H 4) SSCCON 07H
XXH
94H 4) STB
95H
4)
4)
SRB
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) This SFR is only available in the C541U.
Semiconductor Group
22
1997-10-01
C540U
C541U
Table 4
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
Addr Register Reset
Bit 7
Value1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ACH SCIEN
4)
B0H2) P3
B1H
Bit 0
XXXXXX00B
–
–
–
–
–
–
WCEN TCEN
FFH
RD
WR
T1
T0
INT1
INT0
DADD
LED2
–
–
EALE
RMAP
–
–
–
–
SYSCON XX10XXXXB
B8H2) IP0
XXXX0000B
–
–
–
–
PT1
PX1
PT0
PX0
B9H
XXXX0000B
–
–
–
–
–
PUDI
PUEI
PSSC
XXXX0000B
–
2)
C1H to C7H
USB Device and Endpoint Register definition see table 3-4
D0H
00H
C0H
IP1
WDCON
PSW
4)
–
–
–
OWDS WDTS WDT
SWDT
CY
AC
F0
RS1
RS0
OV
F1
P
EPS7
0
0
0
0
EPS2
EPS1
EPS0
.7
.6
.5
.4
.3
.2
.1
.0
0
0
AO5
AO4
AO3
AO2
AO1
AO0
0
0
0
EPI4
EPI3
EPI2
EPI1
EPI0
.7
.6
.5
.4
.3
.2
.1
.0
2)
D2H
D3H
D4H
EPSEL
80H
USBVAL 00H
ADROFF 00H
D6H GEPIR
00H
E0H2) ACC
00H
F0H2) B
FCH VR0
7)
00H
C5H
.7
.6
.5
.4
.3
.2
.1
.0
1
1
0
0
0
1
0
1
C1H
1
1
0
0
0
0
0
1
6)
.7
.6
.5
.4
.3
.2
.1
.0
3) 5)
FDH VR1
3) 5)
FEH
VR2
3) 5)
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
4) This SFR respectively bit is only available in the C541U.
5) These are read-only registers
6) The content of this SFR varies with the actual of the step C517A (e.g. 01H for the first step)
7) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
Semiconductor Group
23
1997-10-01
C540U
C541U
Table 5
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H)
Addr Register Reset
Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EPSEL = 1XXX.XXXXB Device Registers
C1H DCR
000X.
0000B
SPEED
DA
SWR
SUSP
DINIT
RSM
UCLK
PCLK
C2H DPWDR 00H
C3H DIER
00H
0
0
0
0
0
0
TPWD
RPWD
SE0IE
DAIE
DDIE
SBIE
SEIE
STIE
SUIE
SOFIE
C4H DIRR
SE0I
DAI
DDI
SBI
SEI
STI
SUI
SOFI
FNR6
FNR5
FNR4
FNR3
FNR2
FNR1
FNR0
0
0
0
0
FNR10
FNR9
FNR8
0
DBM0
00H
C5H reserved
C6H FNRL
C7H FNRH
FNR7
XXH
0
0000.
0XXXB
EPSEL = 0XXX.X000B
Endpoint 0 Registers
C1H EPBC0
00H
20H
STALL0 0
0
GEPIE0
SOFDE0 INCE0
UBF0
CBF0
DIR0
ESP0
SETRD0 SETWR0 CLREP0 DONE0
00H
11H
AIE0
NAIE0
RLEIE0
–
DNRIE0 NODIE0 EODIE0 SODIE0
ACK0
NACK0
RLE0
–
DNR0
NOD0
EOD0
SOD0
0
0
0
A06
A05
A04
A03
L06
L05
L04
L03
L02
L01
L00
0
DBM1
C2H EPBS0
C3H EPIE0
C4H EPIR0
C5H EPBA0
PAGE0
00H
C6H EPLEN0 0XXX. 0
XXXXB
C7H reserved
EPSEL = 0XXX.X001B
Endpoint 1 Registers
C1H EPBC1
00H
20H
STALL1 0
0
GEPIE1
SOFDE1 INCE1
UBF1
CBF1
DIR1
ESP1
SETRD1 SETWR1 CLREP1 DONE1
00H
10H
AIE1
NAIE1
RLEIE1
–
DNRIE1 NODIE1 EODIE1 SODIE1
ACK1
NACK1
RLE1
–
DNR1
NOD1
EOD1
SOD1
0
0
0
A16
A15
A14
A13
L16
L15
L14
L13
L12
L11
L10
C2H EPBS1
C3H EPIE1
C4H EPIR1
C5H EPBA1
PAGE1
00H
C6H EPLEN1 0XXX. 0
XXXXB
C7H reserved
Semiconductor Group
24
1997-10-01
C540U
C541U
Table 5
Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H) (cont’d)
Addr Register Reset
Value
Bit 7
EPSEL = 0XXX.X010B
Endpoint 2 Registers
C1H EPBC2
00H
20H
STALL2 0
UBF2
00H
10H
C2H EPBS2
C3H EPIE2
C4H EPIR2
Bit 4
Bit 3
0
GEPIE2
SOFDE2 INCE2
CBF2
DIR2
ESP2
SETRD2 SETWR2 CLREP2 DONE2
AIE2
NAIE2
RLEIE2
–
DNRIE2 NODIE2 EODIE2 SODIE2
ACK2
NACK2
RLE2
–
DNR2
NOD2
EOD2
SOD2
0
0
0
A62
A52
A42
A32
L62
L52
L42
L32
L22
L12
L02
0
DBM3
C5H EPBA2
PAGE2
00H
C6H EPLEN2 0XXX. 0
XXXXB
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
0
DBM2
C7H reserved
EPSEL = 0XXX.X011B
Endpoint 3 Registers
C1H EPBC3
00H
20H
STALL3 0
0
GEPIE3
SOFDE3 INCE3
UBF3
CBF3
DIR3
ESP3
SETRD3 SETWR3 CLREP3 DONE3
00H
10H
AIE3
NAIE3
RLEIE3
–
DNRIE3 NODIE3 EODIE3 SODIE3
ACK3
NACK3
RLE3
–
DNR3
NOD3
EOD3
SOD3
0
0
0
A63
A52
A43
A33
L63
L53
L43
L33
L23
L13
L03
0
DBM4
C2H EPBS3
C3H EPIE3
C4H EPIR3
C5H EPBA3
PAGE3
00H
C6H EPLEN3 0XXX. 0
XXXXB
C7H reserved
EPSEL = 0XXX.X100B
Endpoint 4 Registers
C1H EPBC4
00H
20H
STALL4 0
0
GEPIE4
SOFDE4 INCE4
UBF4
CBF4
DIR4
ESP4
SETRD4 SETWR4 CLREP4 DONE4
00H
10H
AIE4
NAIE4
RLEIE4
–
DNRIE4 NODIE4 EODIE4 SODIE4
ACK4
NACK4
RLE4
–4
DNR4
NOD4
EOD4
SOD4
0
0
0
A64
A54
A44
A34
L64
L54
L44
L34
L24
L14
L04
C2H EPBS4
C3H EPIE4
C4H EPIR4
C5H EPBA4
PAGE4
00H
C6H EPLEN4 0XXX. 0
XXXXB
C7H reserved
Semiconductor Group
25
1997-10-01
C540U
C541U
Digital I/O Ports
The C540U/C541U in the P-SDIP-52 package has four 8-bit I/O ports. In the P-LCC-44 package
port 1 is a 6-bit I/O port only. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are
quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs,
ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float
when configured as input.
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time
multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET.
Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the
capability of driving external LEDs in the output low state.
Semiconductor Group
26
1997-10-01
C540U
C541U
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :
Table 6
Timer/Counter 0 and 1 Operating Modes
Mode
Description
TMOD
Input Clock
M1
M0
internal
external (max)
fOSC/6x32
fOSC/12x32
fOSC/6
fOSC/12
0
8-bit timer/counter with a
divide-by-32 prescaler
0
0
1
16-bit timer/counter
1
1
2
8-bit timer/counter with
8-bit autoreload
1
0
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
1
1
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the
input clock logic.
OSC
÷6
f OSC /6
C/T = 0
Timer 0/1
Input Clock
C/T = 1
P3.4/T0
P3.5/T1
Gate
(TMOD)
Control
TR0
TR1
=1
&
<_ 1
P3.2/INT0
P3.3/INT1
MCS03117
Figure 11
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
27
1997-10-01
C540U
C541U
SSC Interface (C541U only)
The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface. Figure 12 shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.
Pin
P1.2 / SCLK
Pin
P1.3 / SRI
Pin
P1.4 / STO
Pin
P1.5 / SLS
f OSC
Clock Divider
STB
...
Clock Selection
Pin
Control
Logic
Shift Register
SRB
Receive Buffer Register
Interrupt
SCIEN
Int. Enable Reg.
Control Logic
SSCCON
Control Register
SCF
Status Register
Internal Bus
MCB03379
Figure 12
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P1.5 / SLS.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
Semiconductor Group
28
1997-10-01
C540U
C541U
USB Module
The USB module in the C540U/C541U handles all transactions between the serial USB bus and the
internal (parallel) bus of the microcontroller. The USB module includes several units which are
required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB
memory with two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU
memory access control, the UDC device core for USB protocol handling, the microcontroller
interface with the USB specific special function registers and the interrupt control logic. A clock
generation unit provides the clock signal for the USB module for full speed and low speed USB
operation. Figure 13 shows the block diagram of the functional units of the USB module with their
interfaces.
XTAL1
Pin
XTAL2
Pin
USB
D+
Pin
Bus
DPin
Osc.
12 MHz
7F
H
Transceiver
(On-chip)
x4
PLL
48 MHz
7F
H
Page 1
Page 0
USB
Memory
00 H
(128 x 8)
2
USB
Module
00 H
6 MHz
Data
Data
USB
Device
Core
MCU
Interface
Internal
Bus
Address
11
SFR
Addr.
MMU
(UDC)
Control
USB Memory
Management
Control
Interrupt Generation
MCB03380
Figure 13
USB Module Block Diagram
Semiconductor Group
29
1997-10-01
C540U
C541U
USB Registers
Two different kinds of registers are implemented in the USB module. The global registers (GEPIR,
EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can
be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are
needed to control the USB module inside the C540U/C541U, device registers and endpoint
registers are mapped into an SFR address block of seven SFR addresses (C1H to C7H). The
endpoint specific functionality of the USB module is controlled via the device registers DCR,
DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is available for each
endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure 14 explains the
structure of the USB module registers.
Global Registers
GEPIR (D6 H )
USBVAL (D3 H )
.7 .6 .5 .4 .3 .2 .1 .0
0 0 0 .4 .3 .2 .1 .0
ADROFF (D4 H )
EPSEL (D2 H )
0 0 .5 .4 .3 .2 .1 .0
.7 0 0 0 0 .2 .1 .0
Decoder
Endpoint 0
Registers
Endpoint 1
Registers
Endpoint 2
Registers
Endpoint 3
Registers
Endpoint 4
Registers
C1 H EPBC0
C1 H EPBC1
C1 H EPBC2
C1 H EPBC3
C1 H EPBC4
C2 H DPWDR
C2 H EPBS0
C2 H EPBS1
C2 H EPBS2
C2 H EPBS3
C2 H EPBS4
C3 H
DIER
C3 H
EPIE0
C3 H
EPIE1
C3 H
EPIE2
C3 H
EPIE3
C3 H
EPIE4
C4 H
DIRR
C4 H
EPIR0
C4 H
EPIR1
C4 H
EPIR2
C4 H
EPIR3
C4 H
EPIR4
Device
Registers
C1 H
DCR
C5 H reserved
C5 H EPBA0
C5 H EPBA1
C5 H EPBA2
C5 H EPBA3
C5 H EPBA4
C6 H
FNRL
C6 H EPLEN0
C6 H EPLEN1
C6 H EPLEN2
C6 H EPLEN3
C6 H EPLEN4
C7 H
FNRH
C7 H reserved
C7 H reserved
C7 H reserved
C7 H reserved
C7 H reserved
MCD03312
Figure 14
Register Structure of the USB Module
Semiconductor Group
30
1997-10-01
C540U
C541U
Interrupt System
The C541U provides seven (C540U : six) interrupt sources with two priority levels. Five interrupts
can be generated by the on-chip peripherals (timer 0, timer 1, SSC interface, and USB module), and
two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1).
Figure 15 to 17 give a general overview of the interrupt sources and illustrate the request and
control flags which are described in the next sections.
Low Priority
Timer 0 Overflow
High Priority
TF0
TCON.5
ET0
000BH
PT0
IP0.1
IEN0.1
TF1
Timer 1 Overflow
TCON.7
ET1
001BH
PT1
IP0.3
IEN0.3
P3.2 /
INT0
≥1
IE0
IT0
ITCON.0
TCON.1
TCON.0
EX0
0003H
PX0
IP0.0
IEN0.0
ITCON.1
P3.3 /
INT1
≥1
IE0
IT1
ITCON.2
TCON.3
TCON.2
EX1
0013H
PX1
IP0.2
IEN0.2
EA
ITCON.3
IEN0.7
Bit addressable
Request Flag is cleared by hardware
Figure 15
Interrupt Request Sources (Part 1)
Semiconductor Group
31
1997-10-01
C540U
C541U
Endpoint Interrupts
Endpoint 4 Interrupts
Endpoint 3 Interrupts
Endpoint 2 Interrupts
Endpoint 1 Interrupts
Endpoint 0 Interrupts
ACK0
AIE0
EPIE0.7
EPIR0.7
NACK0
NAIE0
EPIE0.6
EPIR0.6
RLE0
RLEIE0
EPIE0.5
EPIR0.5
DNR0
>1
EPI0
DNRIE0
EPIE0.3
EPIR0.3
NOD0
GEPIR.0
>1
NODIE0
EPIE0.2
EPIR0.2
EOD0
High Priority
EUEI
GEPIE0
EODIE0
EPIE0.1
EPIR0.1
SOD0
Low Priority
004B H
PUEI
IEN1.1
EPBC0.4
IP1.1
SODIE0
EPIE0.0
EPIR0.0
WCOL
SSC
Interrupts
(C541U only)
SCF.1
WCEN
>1
SCIEN.1
ESSC
IEN1.0
TC
SCF.0
0043 H
TCEN
PSSC
EA
SCIEN.0
IP1.0
IEN0.7
Bit addressable
Request flag is cleared by hardware after the corresponding register has been read.
MCB03382
Figure 16
Interrupt Request Sources (Part 2)
Semiconductor Group
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1997-10-01
C540U
C541U
Device Interrupts
SE0I
DIRR.7
DAI
DIRR.6
DDI
DIRR.5
SBI
DIRR.4
SEI
DIRR.3
SE0IE
DIER.7
DAIE
DIER.6
DDIE
DIER.5
>1
Low Priority
SBIE
DIER.4
High Priority
EUDI
SEIE
DIER.3
0053 H
PUDI
IE1.2
IP1.2
STI
DIRR.2
SUI
DIRR.1
SOFI
DIRR.0
STIE
DIER.2
SUIE
DIER.1
SOFIE
DIER.0
EA
IE0.7
Bit addressable
Request flag is cleared by hardware after the corresponding register has been read.
MCB03383
Figure 17
Interrupt Request Sources (Part 3)
Table 7
Interrupt Source and Vectors
Interrupt Source
Interrupt Vector Address
Interrupt Request Flags (SFRs)
External Interrupt 0
0003H
IE0
Timer 0 Overflow
000BH
0013H
TF0
TF1
SSC Interrupt (C541U only)
001BH
0043H
USB Endpoint Interrupt
004BH
in SFRs EPIR0-4 and GEIPR
USB Device Interrupt
0053H
in SFRs DIRR
Wake-up from power down
007BH
–
External Interrupt 1
Timer 1 Overflow
Semiconductor Group
IE1
TC, WCOL
33
1997-10-01
C540U
C541U
Fail Save Mechanisms
The C540U/C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure :
– a programmable watchdog timer (WDT), with variable time-out period from 256 µs up to
approx. 0.55 µs at 12 MHz. The WDT is not available in the C540U.
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of fOSC/12
or fOSC/192. The system clock of the C517A is divided by two prescalers, a divide-by-two and a
divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the
watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-18
shows the block diagram of the watchdog timer unit.
0
f OSC / 6
7
16
2
WDTL
14
WDT Reset-Request
8
WDTH
WDCON (CO H )
-
-
-
-
OWDS WDTS
WDT
SWDT
WDTPSEL
Control Logic
7 6
0
External HW Reset
WDTREL
MCB03384
Figure 18
Block Diagram of the Watchdog Timer
The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active
mode of the C541U. If the software fails to refresh the running watchdog timer an internal reset will
be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR
WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of
two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external
reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted,
however, that the watchdog timer is halted during the idle mode and power down mode of the
processor.
Semiconductor Group
34
1997-10-01
C540U
C541U
Oscillator Watchdog
The oscillator watchdog unit serves for three functions:
– Monitoring of the on-chip oscillator's function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.
– Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.
– Control of external wake-up from software power-down mode (description see chapter 9)
When the power-down mode is left by a low level at the INT0 pin or by the USB, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the powerdown wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.
Semiconductor Group
35
1997-10-01
C540U
C541U
EWPD
(PCON1.7)
WS
(PCON1.4)
Power - Down
Mode Activated
Power-Down Mode
Wake - Up Interrupt
Activity on
USB Bus
P3.2 / INT0
Control
Logic
Control
Logic
Internal Reset
Start /
Stop
RC
Oscillator
f RC
3 MHz
Start /
Stop
XTAL1
XTAL2
10
f1
f2
Frequency
Comparator
f 2 <f 1
Delay
On-Chip
Oscillator
>1
WDCON (C0 H )
OWDS
Int. Clock
MCD03385
Figure 19
Functional Block Diagram of the Oscillator Watchdog
Semiconductor Group
36
1997-10-01
C540U
C541U
Power Saving Modes
The C540U/C541U provides two basic power saving modes, the idle mode and the power down
mode.
– Idle mode
In the idle mode the main oscillator of the C540U/C541U continues to run, but the CPU is
gated off from the clock signal. However, the interrupt system, the SSC (C541U only), the
USB module, and the timers with the exception of the watchdog timer (C541U only) are further
provided with the clock. The CPU status is preserved in its entirety : the stack pointer, program
counter, program status word, accumulator, and all other registers maintain their data during
idle mode. The idle mode can be terminated by activating any enabled interrupt. or by a
hardware reset.
– Power down mode
In the power down mode, the RC osciillator and the on-chip oscillator which operates with the
XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The power down mode
can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity
on the USB bus. Using reset to leave power down mode puts the microcontroller with its SFRs
into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the
state of the SFRs, which has been frozen when power down mode is entered.
In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC
is restored to its normal operating level, before the power down mode is terminated. Table 8 gives
a general overview of the entry and exit procedures of the power saving modes.
Table 8
Power Saving Modes Overview
Mode
Entering
2-Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Power Down Mode
ORL PCON, #02H
ORL PCON, #40H
Semiconductor Group
Hardware Reset
Short low pulse at
pin P3.2/INT0 or
activity on the USB
bus
37
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
1997-10-01
C540U
C541U
OTP Memory Operation
The C540U/C541U contains a 8k byte one-time programmable (OTP) program memory (C540U :
4k byte). With the C540U/C541U fast programming cycles are achieved (1 byte in 100 µsec). Also
several levels of OTP memory protection can be selected.
For programming of the device, the C540U/C541U must be put into the programming mode. This
typically is done not in-system but in a special programming hardware. In the programming mode
the C540U/C541U operates as a slave device similar as an EPROM standalone memory device
and must be controlled with address/data information, control lines, and an external 11.5V
programming voltage. Figure 20 shows the pins of the C504-2E which are required for controlling
of the OTP programming mode.
V CC
A0 - A7 /
A8 - A12
V SS
Port 2
Port 0
D0 - D7
PALE
EA / V PP
PMSEL0
PMSEL1
C540U
C541U
PROG
PRD
RESET
PSEN
XTAL1
PSEL
XTAL2
MCS03386
Figure 20
Programming Mode Configuration
Semiconductor Group
38
1997-10-01
C540U
C541U
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D0
D1
D2
D3
Pin Configuration in Programming Mode
6 5 4 3 2 1 44 43 42 41 40
N.C.
V CC
V SS
RESET
PMSEL0
N.C:
PMSEL1
PSEL
PRD
PALE
GND
7
8
9
10
11
12
13
14
15
16
17
C540U
C541U
Programming
Mode
39
38
37
36
35
34
33
32
31
30
29
D4
D5
D6
D7
EA / V PP
N.C.
PROG
PSEN
A7
A6
A5
A0 / A8
A1 / A9
A2 / A10
A3 / A11
A4 / A12
GND
GND
XTAL2
XTAL1
V SS
V CC
18 19 20 21 22 23 24 25 26 27 28
MCP03387
Figure 21
P-LCC-44 Pin Configuration of the C540U/C541U in Programming Mode (Top View)
Semiconductor Group
39
1997-10-01
C540U
C541U
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
V CC
V SS
RESET
PMSEL0
N.C.
N.C.
PMSEL1
PSEL
PRD
PALE
GND
GND
GND
XTAL2
XTAL1
V SS
V CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
C540U
C541U
Programming
Mode
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
N.C.
P1.5 / SLS
D0
D1
D2
D3
D4
D5
D6
D7
EA / V PP
N.C.
N.C.
PROG
PSEN
N.C.
N.C.
A7
A6
A5
A4 / A12
A3 / A11
A2 / A10
A1 / A9
A0 / A8
N.C.
MCP03388
Figure 22
P-SDIP-52 Pin Configuration of the C540U/C541U in Programming Mode (Top View)
Semiconductor Group
40
1997-10-01
C540U
C541U
The following table 9 contains the functional description of all C517A-2E pins which are required for
OTP memory programming.
Table 9
Pin Definitions and Functions in Programming Mode
Symbol
Pin Numbers
I/O*) Function
P-LCC-44 P-SDIP-52
RESET
10
12
I
Reset
This input must be at static “1“ (active) level during the
whole programming mode.
PMSEL0
PMSEL1
11
13
13
16
I
I
Programming mode selection pins
These pins are used to select the different access
modes in programming mode. PMSEL1,0 must satisfy
a setup time to the rising edge of PALE. When the
logic level of PMSEL1,0 is changed, PALE must be at
low level.
PMSEL PMSEL Access Mode
1
0
0
0
Reserved
0
1
Read version bytes
1
0
Program/read lock bits
1
1
Program/read OTP memory byte
PSEL
14
17
I
Basic programming mode select
This input is used for the basic programming mode
selection and must be switched according figure 1023.
PRD
15
18
I
Programming mode read strobe
This input is used for read access control for OTP
memory read, version byte read, and lock bit read
operations.
PALE
16
19
I
Programming mode address latch enable
PALE is used to latch the high address lines. The high
address lines must satisfy a setup and hold time to/
from the falling edge of PALE. PALE must be at low
level whenever the logic level of PMSEL1,0 is
changed.
XTAL2
20
23
O
XTAL2
Output of the inverting oscillator amplifier.
*) I = Input
O = Output
Semiconductor Group
41
1997-10-01
C540U
C541U
Table 9
Pin Definitions and Functions in Programming Mode (cont’d)
Symbol
Pin Numbers
I/O*) Function
P-LCC-44 P-SDIP-52
XTAL1
21
24
I
XTAL1
Input to the oscillator amplifier.
A0/A8 A7
24 - 31
28 - 35
I
Address lines
P2.0-7 are used as multiplexed address input lines
A0-A7 and A8-A12. A8-A12 must be latched with
PALE. Address A12 is requred only for the C541U.
PSEN
32
38
I
Program store enable
This input must be at static “0“ level during the whole
programming mode.
PROG
33
39
I
Programming mode write strobe
This input is used in programming mode as a write
strobe for OTP memory program and lock bit write
operations During basic programming mode selection
a low level must be applied to PROG.
EA/VPP
35
42
I
External Access / Programming voltage
This pin must be at 11.5 V (VPP) voltage level during
programming of an OTP memory byte or lock bit.
During an OTP memory read operation this pin must
be at high level (VIH). This pin is also used for basic
programming mode selection. At basic programming
mode selection a low level must be applied to EA/VPP.
D0 - 7
43 - 38
50 - 43
I/O
Data lines 0-7
During programming mode, data bytes are read or
written from or to the C540U/C541U via the
bidirectional D0-7 lines which are located at port 0.
VSS
9, 22
11, 25
–
Circuit ground potential
must be applied to these pins in programming mode.
VCC
8, 23
10, 26
–
Power supply terminal
must be applied to these pins in programming mode.
N.C.
1, 12,,
34, 44
1 - 9, 14,
15, 27, 36,
37, 40, 41,
52
–
Not Connected
These pins should not be connected in programming
mode.
GND
17 - 19
20 - 22
I
Ground pins
In programming mode these pins must be connected
to VIL level.
*) I = Input
O = Output
Semiconductor Group
42
1997-10-01
C540U
C541U
Basic Programming Mode Selection
The basic programming mode selection scheme is shown in figure 23.
5V
V CC
Clock
(XTAL1 / XTAL2)
Stable
RESET
"1"
PSEN
"0"
PMSEL1,0
PROG
0,1
"0"
PRD
"1"
PSEL
PALE
"0"
V PP
EA / V PP
0V
V IH1
Ready for Access
Mode Selection
During this Period Signals
are not actively driven
MCT03389
Figure 23
Basic Programming Mode Selection
Semiconductor Group
43
1997-10-01
C540U
C541U
Table 10
Access Modes Selection
Access Mode
EA/
VPP
Program OTP memory byte
VPP
Read OTP memory byte
VIH
Program OTP lock bits
VPP
Read OTP lock bits
VIH
H
Read OTP version byte
VIH
H
PROG
PRD
PMSEL
Address
(Port 2)
Data
(Port 0)
1
0
H
H
H
A0-7
A8-15
D0-7
H
H
L
–
D1,D0 see
table 11
L
H
Byte addr.
of sign. byte
D0-7
H
Lock Bits Programming / Read
The C540U/C541U has two programmable lock bits which, when programmed according tabie 11,
provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can
also be read.
Table 11
Lock Bit Protection Types
Lock Bits at D1,D0
D1
D0
Protection Protection Type
Level
1
1
Level 0
The OTP lock feature is disabled. During normal operation of
the C540U/C541U, the state of the EA pin is not latched on
reset.
1
0
Level 1
During normal operation of the C540U/C541U, MOVC
instructions executed from external program memory are
disabled from fetching code bytes from internal memory. EA is
sampled and latched on reset. An OTP memory read operation
is only possible using the OTP verification mode for protection
level 1. Further programming of the OTP memory is disabled
(reprogramming security).
0
1
Level 2
Same as level 1, but also OTP memory read operation using
OTP verification mode is disabled.
0
0
Level 3
Same as level 2; but additionally external code execution by
setting EA=low during normal operation of the C540U/C541U
is no more possible.
External code execution, which is initiated by an internal
program (e.g. by an internal jump instruction above the ROM
boundary), is still possible.
Semiconductor Group
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1997-10-01
C540U
C541U
Absolute Maximum Ratings
Ambient temperature under bias (TA) .........................................................
Storage temperature (Tstg) ..........................................................................
Voltage on VCC pins with respect to ground (VSS) .......................................
Voltage on any pin with respect to ground (VSS) .........................................
Input current on any pin during overload condition.....................................
Absolute sum of all input currents during overload condition .....................
Power dissipation........................................................................................
0 to 70 °C
– 65 °C to 150 °C
– 0.5 V to 6.5 V
– 0.5 V to VCC +0.5 V
– 10 mA to 10 mA
I 100 mA I
TBD
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
45
1997-10-01
C540U
C541U
DC Characteristics
TA = 0 to 70 °C
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
Parameter
Symbol
Limit Values
min.
max.
Unit
Test Condition
Input low voltage (except EA,
RESET)
VIL
– 0.5
0.2 VCC –
0.1
V
–
Input low voltage (EA)
VIL1
– 0.5
0.2 VCC –
0.3
V
–
Input low voltage (RESET)
VIL2
– 0.5
0.2 VCC +
0.1
V
–
0.2 VCC +
0.9
VCC + 0.5
V
–
Input high voltage (except XTAL1, VIH
RESET)
Input high voltage to XTAL1
VIH1
0.7 VCC
VCC + 0.5
V
–
Input high voltage to RESET
VIH2
0.6 VCC
VCC + 0.5
V
–
Output low voltage
Ports 1, 2, 3
P1.0, P1.1, P3.0
VOL
–
–
0.45
0.45
V
V
IOL = 1.6 mA 1)
IOL = 10 mA 1)
VOL1
–
0.45
V
IOL = 3.2 mA 1)
2.4
0.9 VCC
–
–
V
IOH = – 80 µA,
IOH = – 10 µA
2.4
0.9 VCC
–
–
V
IOH = – 800 µA
IOH = – 80 µA 2)
Logic 0 input current (ports 1, 2, 3) IIL
– 10
– 50
µA
VIN = 0.45 V
Logical 1-to-0 transition current
(ports 1, 2, 3)
ITL
– 65
– 650
µA
VIN = 2 V
Input leakage current (port 0, EA)
ILI
–
±1
µA
0.45 < VIN < VCC
Pin capacitance
CIO
–
10
pF
fc = 1 MHz,
TA = 25 °C 7)
Overload current
IOV
–
±5
mA
Programming voltage
VPP
10.9
12.1
V
Output low voltage (port 0, ALE,
PSEN)
Output high voltage (ports 1, 2, 3) VOH
Output high voltage (port 0 in
external bus mode, ALE, PSEN)
VOH2
6) 7)
11.5 V ± 5%
Notes see next page
Semiconductor Group
46
1997-10-01
C540U
C541U
Power Supply Current
Parameter
Symbol
Limit Values
typ. 8)
max. 9)
Unit Test Condition
Active mode
12 MHz
ICC
15
TBD
mA
4)
Idle mode
12 MHz
ICC
TBD
TBD
mA
5)
IPD
TBD
50
µA
VCC = 2…5.5 V 3)
Power-down mode
Notes :
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the
0.9 VCC specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = Port 0 = VCC ; XTAL2 = N.C.; XTAL1 = VSS ; RESET = VSS; all other pins are disconnected.
the USB transceiver is switched off;
4) ICC (active mode) is measured with:
XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = RESET = Port 0 = Port 1 = VCC ; all other pins are disconnected.
ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA).
5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = RESET = Vss ; Port 0 = VCC ; all other pins are disconnected;
6) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.
7) Not 100% tested, guaranteed by design characterization.
8) The typical ICC values are periodically measured at TA = +25 ˚C but not 100% tested.
9) The maximum ICC values are measured under worst case conditions (TA = 0 ˚C and VCC = 5.5 V)
Semiconductor Group
47
1997-10-01
C540U
C541U
AC Characteristics
TA = 0 to 70 °C
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
10-MHz clock
Duty Cycle
0.4 to 0.6
Unit
Variable Clock
1/CLP = 2 MHz to
12 MHz **)
min.
max.
min.
max.
ALE pulse width
tLHLL
43
–
CLP - 40
–
ns
Address setup to ALE
tAVLL
13
–
TCLHmin -20 –
ns
Address hold after ALE
tLLAX
13
–
TCLHmin -20 –
ns
ALE to valid instruction in
tLLIV
–
80
–
ns
ALE to PSEN
tLLPL
13
–
TCLLmin -20 –
ns
PSEN pulse width
tPLPH
86
–
CLP+
–
TCLHmin -30
ns
PSEN to valid instruction in
tPLIV
–
51
–
CLP+
ns
TCLHmin- 65
Input instruction hold after PSEN
tPXIX
0
–
0
–
Input instruction float after PSEN
tPXIZ *)
–
23
–
TCLLmin -10 ns
Address valid after PSEN
tPXAV
28
–
TCLLmin - 5
–
Address to valid instruction in
tAVIV
–
140
–
2 CLP +
ns
TCLHmin -60
Address float to PSEN
tAZPL
0
0
–
*)
2 CLP - 87
ns
ns
ns
*)
Interfacing the C540U/C541U to devices with float times up to 28 ns is permissible. This limited bus contention
will not cause any damage to port 0 drivers.
**)
For correct function of the USB module the C540U/C541U must operate with 12 MHz external clock. The
microcontroller (except the USB module) operates down to 2 MHz.
Semiconductor Group
48
1997-10-01
C540U
C541U
AC Characteristics (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
10-MHz
clock
Duty Cycle
0.4 to 0.6
Unit
Variable Clock
1/CLP= 2 MHz to 12 MHz
min.
max.
min.
max.
RD pulse width
tRLRH
180
–
3 CLP - 70
–
ns
WR pulse width
tWLWH
180
–
3 CLP - 70
–
ns
Address hold after ALE
tLLAX2
56
–
CLP - 27
–
ns
RD to valid data in
tRLDV
–
110
–
2 CLP+
TCLHmin - 90
ns
Data hold after RD
tRHDX
0
0
–
ns
Data float after RD
tRHDZ
–
63
–
CLP - 20
ns
ALE to valid data in
tLLDV
–
200
–
4 CLP - 133
ns
Address to valid data in
tAVDV
–
211
–
4 CLP +
TCLHmin -155
ns
ALE to WR or RD
tLLWL
66
166
CLP +
TCLLmin - 50
CLP+
TCLLmin+ 50
ns
Address valid to WR
tAVWL
70
–
2 CLP - 97
–
ns
WR or RD high to ALE high
tWHLH
8
58
TCLHmin - 25
TCLHmin + 25
ns
Data valid to WR transition
tQVWX
8
–
TCLLmin - 25
–
ns
Data setup before WR
tQVWH
163
–
3 CLP +
–
TCLLmin - 120
ns
Data hold after WR
tWHQX
8
–
TCLHmin - 25
–
ns
Address float after RD
tRLAZ
–
0
–
0
ns
Semiconductor Group
49
1997-10-01
C540U
C541U
AC Characteristics (cont’d)
External Clock Drive Characteristics
Parameter
Symbol
CPU Clock = 12 MHz
Duty cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 2 to 12 MHz
min.
max.
min.
max.
Unit
Oscillator period
CLP
83.3
83.3
83.3
500
ns
High time
TCLH
33
–
33
CLP-TCLL
ns
Low time
TCLL
33
–
33
CLP-TCLH
ns
Rise time
tR
–
12
–
12
ns
Fall time
tF
–
12
–
12
ns
Oscillator duty cycle
DC
0.4
0.6
33 / CLP
1 - 33 / CLP
–
Clock cycle
TCL
33
50
CLP * DCmin
CLP * DCmax ns
SSC Interface Characteristics
Parameter
Symbol
Limit Values
min.
max.
Unit
Clock Cycle Time : Master Mode
Slave Mode
tSCLK
tSCLK
667
667
–
–
ns
ns
Clock high time
tSCH
300
–
ns
Clock low time
tSCL
300
–
ns
Data output delay
tD
–
100
ns
Data output hold
tHO
0
–
ns
Data input setup
tS
100
–
ns
Data input hold
tHI
50
–
ns
TC bit set delay
tDTC
–
8 CLP
ns
SLS low to first SCLK clock edge
tSC
2 tCLCL
–
ns
tCLCL
–
ns
Last SCLK clock edge to SLS high tCS
SLS low to STO active
tTS
0
100
ns
SLS high to STO tristate
tST
–
100
ns
Data output delay (already
defined)
tD
–
100
ns
Semiconductor Group
50
1997-10-01
C540U
C541U
t LHLL
ALE
t AVLL
t PLPH
t LLPL
t
LLIV
t PLIV
PSEN
t AZPL
t PXAV
t LLAX
t PXIZ
t PXIX
Port 0
A0 - A7
Instr.IN
A0 - A7
t AVIV
Port 2
A8 - A15
A8 - A15
MCT00096
Figure 24
Program Memory Read Cycle
Semiconductor Group
51
1997-10-01
C540U
C541U
t WHLH
ALE
PSEN
t LLDV
t LLWL
t RLRH
RD
t RLDV
t AVLL
t RHDZ
t LLAX2
t RLAZ
Port 0
t RHDX
A0 - A7 from
Ri or DPL
Data IN
A0 - A7
from PCL
Instr.
IN
t AVWL
t AVDV
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00097
Figure 25
Data Memory Read Cycle
Semiconductor Group
52
1997-10-01
C540U
C541U
t WHLH
ALE
PSEN
t LLWL
t WLWH
WR
t QVWX
t AVLL
t WHQX
t LLAX2
Port 0
A0 - A7 from
Ri or DPL
t QVWH
A0 - A7
from PCL
Data OUT
Instr.IN
t AVWL
Port 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MCT00098
Figure 26
Data Memory Write Cycle
tR
TCL H
tF
0.7 V CC
XTAL1
0.2 V CC - 0.1
TCL L
CLP
MCT03310
Figure 27
External Clock Drive on XTAL1
Semiconductor Group
53
1997-10-01
C540U
C541U
t SCLK
t SCL
t SCH
~
~
SCLK
t HD
~
~
tD
STO
LSB
~
~
MSB
t HI
~
~
tS
SRI
LSB
~
~
MSB
t DTC
~
~
TC
MCT02417
Notes :
Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other
cases accordingly.
In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge
of SLS (if transmitter is enabled).
In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written
into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Figure 28
SSC Master Mode Timing
Semiconductor Group
54
1997-10-01
C540U
C541U
t SCLK
t SCH
t SCL
SCLK (CPOL = 1)
SCLK (CPOL = 0)
t SC
t CS
SLS
t ST
t TS
STO (CPHA = 0)
tD
DOUT 7
tD
DOUT 0
tD
STO (CPHA = 1)
tD
tD
DOUT 7
DOUT 1
DOUT 0
MCT03390
Figure 29
SSC Slave Mode Timing
Semiconductor Group
55
1997-10-01
C540U
C541U
AC Characteristics of Programming Mode
VCC = 5 V ± 10 %; VPP = 11.5 V ± 5 %; TA = 25 ˚C ± 10 ˚C
Parameter
Symbol
Limit Values
min.
max.
Unit
ALE pulse width
tPAW
35
–
PMSEL setup to ALE rising edge
tPMS
10
–
Address setup to ALE, PROG, or PRD falling tPAS
edge
10
–
ns
Address hold after ALE, PROG, or PRD
falling edge
tPAH
10
–
ns
Address, data setup to PROG or PRD
tPCS
100
–
ns
Address, data hold after PROG or PRD
tPCH
0
–
ns
PMSEL setup to PROG or PRD
tPMS
10
–
ns
PMSEL hold after PROG or PRD
tPMH
10
–
ns
PROG pulse width
tPWW
100
–
µs
PRD pulse width
tPRW
100
–
ns
Address to valid data out
tPAD
–
75
ns
PRD to valid data out
tPRD
–
20
ns
Data hold after PRD
tPDH
0
–
ns
Data float after PRD
tPDF
–
20
ns
PROG high between two consecutive PROG tPWH1
low pulses
1
–
µs
PRD high between two consecutive PRD low tPWH2
pulses
100
tCLKP
83.3
XTAL clock period
Semiconductor Group
56
ns
ns
500
ns
1997-10-01
C540U
C541U
t PAW
PALE
t PMS
H, H
PMSEL1,0
t PAS
Port 2
t PAH
A8-A13
A0-A7
D0-D7
Port 0
PROG
t PWH
t PCS
t PWW
t PCH
MCT03369
Figure 30
Programming Code Byte - Write Cycle Timing
Semiconductor Group
57
1997-10-01
C540U
C541U
t PAW
PALE
t PMS
H, H
PMSEL1,0
t PAS
Port 2
t PAH
A8-13
A0-7
t PAD
t PDH
D0-7
Port 0
t PRD
t PDF
PRD
t PWH
t PCS
t PRW
Notes: PROG must be high during a programming read cycle.
t PCH
MCT03392
Figure 31
Verify Code Byte - Read Cycle Timing
Semiconductor Group
58
1997-10-01
C540U
C541U
PMSEL1,0
H, L
H, L
Port 0
D0, D1
D0, D1
t PCH
t PCS
t PMS
t PMH
PROG
t PDH
t PMS t PRD
t PWW
t PDF
t PRW
t PMH
PRD
Note: PALE should be low during a lock bit read / write cycle.
MCT03393
Figure 32
Lock Bit Access Timing
L, H
PMSEL1,0
e. g. FD H
Port 2
t PCH
D0-7
Port 0
t PCS
t PDH
t PDF
t PRD
t PMS
t PRW
PRD
t PMH
Note: PROG must be high during a programming read cycle.
MCT03394
Figure 33
Version Byte Read Timing
Semiconductor Group
59
1997-10-01
C540U
C541U
OTP Verification Characteristics
OTP Verification Mode for Protection Level 1
Parameter
Symbol
Limit Values
Unit
min.
typ
max.
ALE pulse width
tAWD
–
2 tCLCL
–
ns
ALE period
tACY
–
12 tCLCL
–
ns
Data valid after ALE
tDVA
–
–
4 tCLCL
ns
Data stable after ALE
tDSA
8 tCLCL
–
–
ns
P3.5 setup to ALE low
tAS
–
tCLCL
–
ns
Oscillator frequency
1/tCLCL
4
–
6
MHz
t ACY
t AWD
ALE
t DSA
t DVA
Port 0
Data Valid
t AS
P3.5
MCT02613
Figure 34
OTP Verification Mode for Protection Level 1
Semiconductor Group
60
1997-10-01
C540U
C541U
USB Transceiver Characteristics
VCC = 4.0V to 5.5V (5V +10%, -20%); VSS = 0 V
TA = 0 to 70 °C
Parameter
Limit Values
Symbol
min.
max.
Unit
Test Condition
1)
Output impedance (high state)
RDH
28
43
Ω
Output impedance (low state)
RDL
28
51
Ω
Input leakage current
II
–
±5
µA
VIN = VSS or VCC
Tristate output off-state current
I OZ
–
± 10
µA
VOUT = VSS or VCC 1)
Crossover point
VCR
1.3
2.0
V
2)
Notes :
1) This value includes an external resistor of 30Ω ± 1% (see “Load for D+/D-“ diagram for testing details)
2) The crossover point is in the range of 1.3V to 2.0V for the high speed mode with a 50pF capacitance. In the
low-speed mode with a 100pF or greater capacitance, the crossover point is in the range of 1.3V to 2.0V.
Parameter
Symbol
Limit Values
min.
max.
Unit
High speed mode rise time
tFR
4
20
ns
High speed mode fall time
tFF
4
20
ns
Low speed mode rise time
tLR
75
300
ns
Low speed mode fall time
tLF
75
300
ns
Semiconductor Group
61
1997-10-01
C540U
C541U
VCC -0.5 V
0.2 VCC+0.9
Test Points
0.2 VCC -0.1
0.45 V
MCT00039
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
Figure 35
AC Testing: Input, Output Waveforms
VOH -0.1 V
VLoad +0.1 V
Timing Reference
Points
VLoad
VLoad -0.1 V
VOL +0.1 V
MCT00038
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 36
AC Testing : Float Waveforms
2.8 V
30 k Ω
Test Point
1.5 k Ω *)
S1
D.U.T
15 k Ω
CL
C L = 50 pF, full speed
C L = 50 pF, low speed (min. timing)
C L = 350 pF, low speed (max. timing)
*) 1.5 kΩ on D- (low speed) or D+ (full speed) only
Test
S1
D- / LS
D+ / LS
D- / FS
D+ / FS
Close
Open
Open
Close
MCS03425
Figure 37
Load for D+/DSemiconductor Group
62
1997-10-01
C540U
C541U
Crystal Oscillator Mode
Driving from External Source
C
N.C.
XTAL2
2 - 12
MHz
External Oscillator
Signal
XTAL1
XTAL2
XTAL1
C
Crystal Mode: C = 20 pF 10 pF
(Incl. Stray Capacitance)
MCS03426
Figure 38
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
63
1997-10-01
C540U
C541U
GPL05102
Plastic Package, P-LCC-44-1 (SMD)
(Plastic Leaded Chip Carrier Package)
Figure 39
P-LCC-44-1 Package Outline
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
Semiconductor Group
64
Dimensions in mm
1997-10-01
C540U
C541U
GPD05262
Plastic Package, P-SDIP-52-1
(Plastic Shrink Dual In-Line Package)
Figure 40
P-SDIP-52-1 Package Outline
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
Dimensions in mm
Semiconductor Group
65
1997-10-01