AN526 PIC16C5X / PIC16CXXX Math Utility Routines Author: Amar Palacherla Microchip Technology Inc. PLEASE NOTE: This application note uses the old Microchip Math Routine format. It is intended for reference purposes only and is being provided for those of you still implementing Binary Coded Decimal(BCD) routines. For any new designs, please refer to application notes contained in Microchip’s Embedded Control Handbook Volume II - Math Library. INTRODUCTION This application note provides some utility math routines for Microchip’s PIC16C5X and PIC16CXXX series of 8-bit microcontrollers. The following math outlines are provided: • • • • • • • • • • 8x8 unsigned multiply 16x16 double precision multiply Fixed Point Division (Table 3) 16x16 double precision addition 16x16 double precision subtraction BCD (Binary Coded Decimal) to binary conversion routines Binary to BCD conversion routines BCD addition BCD subtraction Square root These are written in native assembly language and the listing files are provided. They are also available on a disk (MS-DOS). All the routines provided can be called as subroutines. Most of the routines have two different versions: one optimized for speed and the other optimized for code size. The calling sequence of each routine is explained at the beginning of each listing file. SINGLE PRECISION UNSIGNED MULTIPLICATION (8x8) This routine computes the product of two 8-bit unsigned numbers and produces a 16-bit result. Two routines are provided: one routine is optimized for speed (by writing a straight line code) and the other routine has been written to reduce the code size (a looped code). The listing of these routines are given in Appendices A and B. The performance specs for the routines are shown in Table 1. TABLE 1: PERFORMANCE SPECS Spec Program Memory Instruction Cycles Speed Efficient 35 37 Code Efficient 16 71 FIGURE 1: Flowchart for Unsigned 8x8 Multiply 8x8 Multiply Count = 8 H_Byte = L_Byte = 0 W ← Multiplicand Clear Carry Bit Rotate Right Multiplier Thru Carry Carry = 1? H_Byte = H_Byte + W Rotate Right H_Byte Rotate Right L_Byte Count = Count - 1 Carry = 0? Return MS-DOS is a registered trademark of Microsoft Corporation. 1997 Microchip Technology Inc. DS00526E-page 1 AN526 DOUBLE PRECISION MULTIPLY This routine computes the product of two 16-bit numbers and produces a 32-bit result. Both signed and unsigned arithmetic are supported. Two routines are provided: one routine is optimized for speed (by writing a straight line code) the other routine has been written to reduce code size (a looped code). The listing of these routines are given in Appendices C and D. The performance specs for routines are shown in Table 2. TABLE 2: PERFORMANCE SPECS Spec Program Memory Instruction Cycles Speed Efficient 240 233 Code Efficient 33 333 The code in Appendices C and D has been setup for unsigned arithmetic and the performance specs in the table above is for unsigned arithmetic. If signed arithmetic is desired, edit the line with “SIGNED equ FALSE” to “SIGNED equ TRUE” then re-assemble the code. In case of signed multiply, both operands are assumed to be 16-bit 2’s complement numbers. Conditional assembly is supported by MPASM. If you have an older version, please contact the Microchip Technology sales office nearest you. DOUBLE PRECISION DIVISION Fixed Point Divide Routines Fixed point division is fundamentally a conditional shift and subtract operation, resulting in a quotient and a remainder, with standard methods related to simple binary long division by hand calculation. Typically, a processor with n-bit operands uses a fixed accumulator of 2n bits containing the dividend. In standard restoring division, the dividend is left shifted by one bit and the divisor is subtracted from the high half of the accumulator, referred to as the partial remainder. If the result is positive, the divisor was less than or equal to the partial remainder and the corresponding quotient bit in the LSb of the accumulator is set to one. If the result is negative, the divisor was greater than the partial remainder and the dividend is restored by adding back the divisor to the high half of the accumulator and setting the LSb to zero. This process is repeated for each of the n bits in the divisor, resulting in an n-bit quotient in the low half of the accumulator and the n-bit remainder in the high half, and requiring n subtractions and on average n/2 additions [1]. Nonrestoring division, requiring a total of at most n+1 subtractions and additions, offers potential for speed improvement by allowing a negative partial remainder during the calculation with a final addition of the divisor if the final remainder is negative. After the first left shift DS00526E-page 2 of the dividend, the divisor is subtracted and the corresponding quotient bit as well as the next add or subtract operation is determined by the carry bit [1]. Unfortunately, no simple method exists for performing two’s complement binary division, thereby requiring negate operations during a preprocessing phase. It is important to note that with the dividend initially loaded into the accumulator, an overflow of the final quotient will result if the high half of the dividend is greater than or equal to the divisor [1], indicating that the n-bit range of the quotient will be exceeded. Because of the inherent byte structure of the PICmicro™ family of microcontrollers, a more creative and efficient implementation of the above algorithms is possible. In what follows, partial remainder is initialized at zero and is separated from the dividend, thereby avoiding any alignment logic overhead and yielding a quotient with the same number of bits as the dividend and a remainder with the same number as the divisor. Furthermore, routines are named in format FXDxxyyz, where xx is the number of bits in the dividend, yy is the number of bits in the divisor, and z indicates a signed or unsigned routine. Macros are used for core sections of each routine, thereby permitting simple switching between restoring and nonrestoring methods. The signed macros are exclusively a variation of the nonrestoring method, taking advantage of the zero MSb of the arguments after the preprocessing negation. Both restoring and nonrestoring macros are included for the unsigned case, with selection based on best worst case or best average performance as desired. For example, the unsigned macros exhibit the following performance data: # of Cycles (TCY) restore nonrestore max. 32/16 16/16 16/8 561 240 193 ave. 481 208 173 max. 481 240 190 ave. 466 233 183 This demonstrates that while the nonrestoring algorithm is preferred for the 32/16 case, the restoring method is preferred for the 16/16 case, with the choice for the 16/8 case a function of user requirements. These optimization complications are a result of trade-offs between the number of instructions required for the restore operations verses the added logic requirements. Finally, additional routines with tacit MSb equal to zero in each argument are included, yielding significant speed improvement. These routines can also be called in the signed case when the arguments are known to be positive for a small benefit. 1997 Microchip Technology Inc. AN526 Routines References It is useful to note that the additional routines FXD3115U, FXD1515U, and FXD1507U can be called in a signed divide application in the special case where AARG > 0 and BARG > 0, thereby offering some improvement in performance. 1. Data RAM Requirements 2. 3. Cavanagh, J.J.F., “Digital Computer Arithmetic,” McGraw-Hill,1984. Hwang, K., “Computer Arithmetic,” John Wiley & Sons, 1979. Scott, N.R., “Computer Number Systems & Arithmetic,” Prentice Hall, 1985. The following contiguous data RAM locations are used by the fixed point divide routines: ACC+B0 ACC+B1 ACC+B2 ACC+B3 ACC+B4 ACC+B5 SIGN BARG+B0 BARG+B1 TEMP+B0 TEMP+B1 = = = = = = AARG+B0 AARG+B1 AARG+B2 AARG+B3 REM+B0 REM+B1 AARG and ACC remainder sign in MSb BARG temporary storage where Bx = x. TABLE 3: Fixed Point Divide Routines Routine Cycles FXD3216S 414 32-bit/16-bit -> 32.16 signed fixed point divide FXD3216U 485 32-bit/16-bit -> 32.16 unsigned fixed point divide FXD3215U 390 32-bit/15-bit -> 32.15 unsigned fixed point divide FXD3115U 383 31-bit/15-bit -> 31.15 unsigned fixed point divide FXD1616S 214 16-bit/16-bit -> 16.16 signed fixed point divide FXD1616U 244 16-bit/16-bit -> 16.16 unsigned fixed point divide FXD1615U 197 16-bit/15-bit -> 16.15 unsigned fixed point divide FXD1515U 191 15-bit/15-bit -> 15.15 unsigned fixed point divide FXD1608S 146 16-bit/08-bit -> 16.08 signed fixed point divide FXD1608U 196 16-bit/08-bit -> 16.08 unsigned fixed point divide FXD1607U 130 16-bit/07-bit -> 16.07 unsigned fixed point divide FXD1507U 125 15-bit/07-bit -> 15.07 unsigned fixed point divide 1997 Microchip Technology Inc. Function DS00526E-page 3 AN526 TABLE 4: PIC16CXXX Fixed Point Divide Performance Data Routine Max. Cycles Min. Cycles Program Memory Data Memory 16 / 8 Signed 146 135 146 5 16 / 8 Unsigned 196 156 195 4 16 / 7 Unsigned 130 130 129 4 15 / 7 Unsigned 125 125 124 4 16 / 16 Unsigned 214 187 241 7 16 / 16 Unsigned 244 180 243 6 16 / 15 Unsigned 197 182 216 6 16 / 15 Unsigned 191 177 218 6 32 / 16 Unsigned 414 363 476 9 32 / 16 Unsigned 485 459 608 9 32 / 15 Unsigned 390 359 451 8 31 / 15 Unsigned 383 353 442 8 DOUBLE PRECISION ADDITION & SUBTRACTION This routine adds or subtracts two 16-bit numbers and produces a 16-bit result. This routine is used by other double precision routines. The listing of these routines is given in Appendix E. The performance specs for the routines are shown below: TABLE 5: PERFORMANCE SPECS Spec Program Memory This routine converts a five digit BCD number to a 16-bit binary number. The listing of this routine is given in Appendix F. The performance spec for the routine is shown below: TABLE 6: PERFORMANCE SPECS Spec Program Memory Instruction Cycles BCD to Binary 30 121 Instruction Cycles Addition 7 8 Subtraction 14 17 DS00526E-page 4 BCD TO BINARY CONVERSION 1997 Microchip Technology Inc. AN526 BINARY TO BCD CONVERSION BCD ADDITION & SUBTRACTION Two routines are provided: one routine converts a 16-bit binary number to a five-digit BCD number and the other routine converts an 8-bit binary number to a two-digit BCD number. The listing of these routines are given in Appendices G and H. The performance specs for the routines are shown below: These two routines perform a two-digit unsigned BCD addition and subtraction. The results are the sum (or difference) in one file register and with a overflow carry-bit in another file register. The performance specs for the routines are shown below: TABLE 8: PERFORMANCE SPECS TABLE 7: PERFORMANCE SPECS Spec Program Memory Spec Instruction Cycles Binary (8-Bit) to BCD 10 81 (Worst Case) Binary (16-Bit) to BCD 30 719 Count = 16 R0 = 0, R1 = 0, R2 = 0 Binary to BCD Conversion In: BCD #In R0, R1, R2 Out: Binary #In S0, S1 BCD MSD LSD Shift S0, S1 Left into R0, R1, R2 (One Bit) Carry = 0 ? MSD R0, R1, R2 29 23 (Worst Case) BCD Subtraction 31 21 (Worst Case) FIGURE 3: Flowchart for BCD Addition Unsigned BCD Addition LSD Perform Binary Addition S0, S1 R0 = MSD R2 = LSD S0 = High Order Byte S1 = Low Order Byte Y BCD Addition The listing files for the above two routines are given in Appendices J and K. The flow charts for BCD addition and BCD subtraction are given in Figure 3 and Figure 4, respectively. FIGURE 2: Flowchart for Binary to BCD Conversion Binary to BCD Program Memory Instruction Cycles Return N Adjust BCD DC = 1? No LSD > 9? Adjust R2 Adjust BCD Yes Yes No Add 6 to LSD Adjust R1 Adjust BCD Yes CY = 1? Adjust R0 No FSR = 2 Digit BCD # Adjust BCD LSD +3>7 Y LSD = LSD + 3 MSD > 9? No N Yes Add 6 to LSD RETURN MSD +3>7 Y MSD = MSD + 3 N Return 1997 Microchip Technology Inc. DS00526E-page 5 AN526 FIGURE 4: Flowchart for BCD Subtraction U BCD SUB Do 2’s Complement Binary Addition DC = 0 ? N Y SQUARE ROOT Often in many applications one needs to find the square root of a number. Of many numerical methods to find the square root of a number, the Newton-Raphson method is very attractive because of its fast convergence rate. In this method the square root of a number, “N”, is obtained from the approximate solution of: f(Y) = Y2 – N = 0 The function “f(Y)” can be expanded about Y0 using first order Taylor polynomial expansion as: Equation 1: f(Y) = f (Y0) + (Y –Y0) f’(Y0) + (Y –Y0) 2f” (Y0) / 2 ! + .... If X is a root of f(Y), then f(X) = 0: LSD > 9 ? Y N f(X) = f(Y0) + (x – Y0) f’ (Y0) + (X - Y0) 2f” (Y0) / 2 ! + ... = 0 Subtract 6 from LSD Equation 2: f(Y0) + (X – Y0) f’ (Y0) [i.e., X = Y0 – f(Y0) / f’ (Y0)] Thus, X is a better approximation for Y0. From this, the sequence {Xn} can be generated: Y CY = 0 ? If Y0 is an approximate root of f(Y), then higher order terms are negligible. Therefore: Equation 3: Xn = Xn – 1 – f(Xn – 1) / f’ (Xn – 1), n ≥ 1 From equation 1 and equation 3 we get, N Equation 4: Xn = 0.5* {Xn – 1 + N/Xn – 1} MSD > 9 ? N Return DS00526E-page 6 The initial approximate root of N is taken to be N/2. If the approximate range of N is known a priori, then the total number of iterations may be cut down by starting with a better approximate root than N/2. Y Subtract 6 from MSD This program, as listed in Appendix K, computes the square root of a 16-bit number. This routine uses double precision math routines (division and addition) as described in the previous pages of this application note. The divide routines are integrated into the source listing. For fixed point divide routines, see Appendices L - O. 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX A: MPASM 01.40 Released LOC OBJECT CODE VALUE 00000009 00000010 00000012 00000013 00000014 00000001 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0072 0073 0C08 0034 0209 0403 0330 0603 01F2 0332 MULT8X8S.ASM 1-16-1997 12:54:42 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00001 00002 00224 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 1997 Microchip Technology Inc. LIST P = 16C54, n = 66 ; ;******************************************************************* ; 8x8 Software Multiplier ; ( Code Efficient : Looped Code ) ;******************************************************************* ; ; The 16 bit result is stored in 2 bytes ; ; Before calling the subroutine “ mpy “, the multiplier should ; be loaded in location “ mulplr “, and the multiplicand in ; “ mulcnd “ . The 16 bit result is stored in locations ; H_byte & L_byte. ; ; Performance : ; Program Memory : 15 locations ; # of cycles : 71 ; Scratch RAM : 0 locations ; ; ; Program: MULT8x8S.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ; This routine is optimized for code efficiency (looped code) ; For time efficiency code refer to “mult8x8F.asm”(straight line code) ;******************************************************************* ; mulcnd equ 09 ; 8 bit multiplicand mulplr equ 10 ; 8 bit multiplier H_byte equ 12 ; High byte of the 16 bit result L_byte equ 13 ; Low byte of the 16 bit result count equ 14 ; loop counter ; ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST Same equ 1 ; ; ***************************** Begin Multiplier Routine mpy_S clrf H_byte clrf L_byte movlw 8 movwf count movf mulcnd,W bcf STATUS,C ; Clear the carry bit in the status Reg. loop rrf mulplr, F btfsc STATUS,C addwf H_byte,Same rrf H_byte,Same DS00526E-page 7 AN526 000A 0333 000B 02F4 000C 0A06 00052 rrf L_byte,Same 00053 decfsz count, F 00054 goto loop 00055 ; 000D 0800 00056 retlw 0 00057 ; 00058 ;******************************************************************** 00059 ; Test Program 00060 ;********************************************************************* 000E 0CFF 00061 main movlw 0FF 000F 0030 00062 movwf mulplr ; multiplier (in mulplr) = 0FF 0010 0CFF 00063 movlw 0FF ; multiplicand(W Reg ) = 0FF 0011 0029 00064 movwf mulcnd 00065 ; 0012 0900 00066 call mpy_S ; The result 0FF*0FF = FE01 is in locations 00067 ; ; H_byte & L_byte 00068 ; 0013 0A13 00069 self goto self 00070 ; 01FF 00071 org 01FF 01FF 0A0E 00072 goto main 00073 ; 00074 END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXX------------ ---------------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00526E-page 8 0 0 reported, 0 reported, 21 491 0 suppressed 0 suppressed 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX B: MPASM 01.40 Released LOC OBJECT CODE VALUE 00000009 00000010 00000012 00000013 00000001 0000 0072 0001 0073 MULT8X8F.ASM 1-16-1997 12:54:10 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00001 00002 00224 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 1997 Microchip Technology Inc. LIST P = 16C54, n = 66 ; ;******************************************************************* ; 8x8 Software Multiplier ; ( Fast Version : Straight Line Code ) ;******************************************************************* ; ; The 16 bit result is stored in 2 bytes ; ; Before calling the subroutine “ mpy “, the multiplier should ; be loaded in location “ mulplr “, and the multiplicand in ; “ mulcnd “ . The 16 bit result is stored in locations ; H_byte & L_byte. ; ; Performance : ; Program Memory : 35 locations ; # of cycles : 37 ; Scratch RAM : 0 locations ; ; ; Program: MULT8x8F.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ; This routine is optimized for speed efficiency (straight line code) ; For code efficiency, refer to “mult8x8S.asm” (looped code) ;******************************************************************* ; mulcnd equ 09 ; 8 bit multiplicand mulplr equ 10 ; 8 bit multiplier H_byte equ 12 ; High byte of the 16 bit result L_byte equ 13 ; Low byte of the 16 bit result ; ; include “p16c5x.inc” LIST ; P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST Same ; ;**** ; mult equ 1 Define a macro for adding & right shifting MACRO btfsc addwf rrf rrf ENDM bit mulplr,bit H_byte,Same H_byte,Same L_byte,Same ** ; Begin macro ; End of macro ; ; ***************************** Begin Multiplier Routine mpy_F clrf H_byte clrf L_byte DS00526E-page 9 AN526 0002 0209 0003 0403 0004 0005 0006 0007 0610 01F2 0332 0333 0008 0009 000A 000B 0630 01F2 0332 0333 000C 000D 000E 000F 0650 01F2 0332 0333 0010 0011 0012 0013 0670 01F2 0332 0333 0014 0015 0016 0017 0690 01F2 0332 0333 0018 0019 001A 001B 06B0 01F2 0332 0333 001C 001D 001E 001F 06D0 01F2 0332 0333 0020 0021 0022 0023 06F0 01F2 0332 0333 0024 0800 0025 0026 0027 0028 0CFF 0030 0CFF 0029 0029 0900 002A 0A2A 01FF 01FF 0A25 00052 00053 00054 M M M M 00055 M M M M 00056 M M M M 00057 M M M M 00058 M M M M 00059 M M M M 00060 M M M M 00061 M M M M 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 movf bcf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mult btfsc addwf rrf rrf mulcnd,W ; move the multiplicand to W reg. STATUS,C ; Clear the carry bit in the status Reg. 0 mulplr,0 H_byte,Same H_byte,Same L_byte,Same 1 mulplr,1 H_byte,Same H_byte,Same L_byte,Same 2 mulplr,2 H_byte,Same H_byte,Same L_byte,Same 3 mulplr,3 H_byte,Same H_byte,Same L_byte,Same 4 mulplr,4 H_byte,Same H_byte,Same L_byte,Same 5 mulplr,5 H_byte,Same H_byte,Same L_byte,Same 6 mulplr,6 H_byte,Same H_byte,Same L_byte,Same 7 mulplr,7 H_byte,Same H_byte,Same L_byte,Same ; retlw 0 ; ;******************************************************************** ; Test Program ;********************************************************************* main movlw 0FF movwf mulplr ; multiplier (in mulplr) = 0FF movlw 0FF movwf mulcnd ; multiplicand(in mulcnd) = 0FF ; call mpy_F ; The result 0FF*0FF = FE01 is in locations ; ; H_byte & L_byte ; self goto self ; org 01FF goto main ; END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXX----- ---------------- DS00526E-page 10 1997 Microchip Technology Inc. AN526 01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 44 468 0 suppressed 0 suppressed DS00526E-page 11 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX C:DOUBLE PRECISION MULTIPLICATION LISTING (LOOPED) MPASM 01.40 Released LOC OBJECT CODE VALUE 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 0000001F 000001FF 00000001 DS00526E-page 12 DBL_MPYS.ASM 1-16-1997 12:53:00 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00001 00002 00224 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************* ; Double Precision Multiplication ; ; ( Optimized for Code Size : Looped Code ) ; ;*******************************************************************; ; Multiplication: ACCb(16 bits)*ACCa(16 bits) -> ACCb,ACCc (32 bits) ; (a) Load the 1st operand in location ACCaLO & ACCaHI (16 bits) ; (b) Load the 2nd operand in location ACCbLO & ACCbHI (16 bits) ; (c) CALL D_mpy ; (d) The 32 bit result is in location (ACCbHI,ACCbLO,ACCcHI,ACCcLO) ; ; Performance : ; Program Memory : 033 ; Clock Cycles : 333 ; ; Note : The above timing is the worst case timing, when the ; register ACCb = FFFF. The speed may be improved if ; the register ACCb contains a number ( out of the two ; numbers ) with less number of 1s. ; The performance specs are for Unsigned arithmetic (i.e, ; with “SIGNED equ FALSE“). ; ; The performance specs are for Unsigned arithmetic (i.e, ; with “SIGNED equ FALSE“). ; ; ; Program: DBL_MPYS.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; ACCaLO equ 0x10 ACCaHI equ 0x11 ACCbLO equ 0x12 ACCbHI equ 0x13 ACCcLO equ 0x14 ACCcHI equ 0x15 ACCdLO equ 0x16 ACCdHI equ 0x17 temp equ 0x18 sign equ 0x19 Flags equ 0x1F ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST PIC54 TRUE equ equ 1FFH 1 ; Define Reset Vector 1997 Microchip Technology Inc. AN526 00000000 00000007 0000 00000001 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 041F 0210 01F2 0603 02B3 0603 051F 0211 01F3 061F 0503 0800 000C lsb’s) 000C 0935 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 0926 0337 0336 0603 0900 0333 0332 0335 0334 02F8 0A0E 07F9 0800 0274 02B4 0643 00F5 0275 0643 0272 02B2 0643 00F3 0273 0800 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 1997 Microchip Technology Inc. FALSE MSB equ equ 0 7 org 0 ;******************************************************************* SIGNED equ TRUE ; Set This To ‘TRUE’ if the routines ; ; for Multiplication & Division needs ; ; to be assembled as Signed Integer ; ; Routines. If ‘FALSE’ the above two ; ; routines ( D_mpy & D_div ) use ; ; unsigned arithmetic. ;******************************************************************* ; Double Precision Addition ( ACCb + ACCa -> ACCb ) ; D_add bcf Flags,C ;Clear temp Carry bit movf ACCaLO,W ; Addition ( ACCb + ACCa -> ACCb ) addwf ACCbLO, F ;add lsb btfsc STATUS,C ;add in carry incf ACCbHI, F btfsc STATUS,C bsf Flags,C movf ACCaHI,W addwf ACCbHI, F ;add msb btfsc Flags,C bsf STATUS,C retlw 0 ;******************************************************************* ; Double Precision Multiply ( 16x16 -> 32 ) ; ( ACCb*ACCa -> ACCb,ACCc ) : 32 bit output with high word ; in ACCb ( ACCbHI,ACCbLO ) and low word in ACCc ( ACCcHI,ACCcLO ). ; D_mpyS ;results in ACCb(16 msb’s) and ACCc(16 ; IF SIGNED CALL S_SIGN ENDIF ; call rrf rrf btfsc call rrf rrf rrf rrf decfsz goto mloop setup ACCdHI, F ACCdLO, F STATUS,C D_add ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F temp, F mloop ;rotate d right ;need to add? ;loop until all bits checked ; IF neg_B SIGNED btfss sign,MSB retlw 0 comf ACCcLO, F incf ACCcLO, F btfsc STATUS,Z decf ACCcHI, F comf ACCcHI, F btfsc STATUS,Z comf ACCbLO, F incf ACCbLO, F btfsc STATUS,Z decf ACCbHI, F comf ACCbHI, F retlw 0 ; negate ACCa ( -ACCa -> ACCa ) ; negate ACCb ELSE DS00526E-page 13 AN526 0026 0027 0028 0029 002A 002B 002C 002D 002E 0C10 0038 0213 0037 0212 0036 0073 0072 0800 002F 0030 0031 0032 0033 0034 0270 02B0 0643 00F1 0271 0800 0035 0036 0037 0038 0039 0211 0193 0039 07F3 0A3F 003A 003B 003C 003D 003E 0272 02B2 0643 00F3 0273 003F 07F1 0040 0800 0041 0A2F 0042 0043 0044 0045 0C01 0031 0CFF 0030 0046 0047 0048 0049 0C7F 0033 0CFF 0032 004A 090C 004B 0A4B DS00526E-page 14 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 retlw ENDIF 0 ; ;******************************************************************* ; setup movlw .16 ; for 16 shifts movwf temp movf ACCbHI,W ; move ACCb to ACCd movwf ACCdHI movf ACCbLO,W movwf ACCdLO clrf ACCbHI clrf ACCbLO retlw 0 ; ;******************************************************************* ; neg_A comf ACCaLO, F ; negate ACCa ( -ACCa -> ACCa ) incf ACCaLO, F btfsc STATUS,Z decf ACCaHI, F comf ACCaHI, F retlw 0 ; ;******************************************************************* ; Assemble this section only if Signed Arithmetic Needed ; IF SIGNED ; S_SIGN movf ACCaHI,W xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB ; if MSB set go & negate ACCb goto chek_A ; comf ACCbLO, F ; negate ACCb incf ACCbLO, F btfsc STATUS,Z decf ACCbHI, F comf ACCbHI, F ; chek_A btfss ACCaHI,MSB ; if MSB set go & negate ACCa retlw 0 goto neg_A ; ENDIF ; ;******************************************************************* ; Test Program ;******************************************************************* ; Load constant values to ACCa & ACCb for testing ; main movlw 1 movwf ACCaHI movlw 0FF ; loads ACCa = 01FF movwf ACCaLO ; movlw 0x7F movwf ACCbHI movlw 0xFF ; loads ACCb = 7FFF movwf ACCbLO ; call D_mpyS ; Here (ACCb,ACCc) = 00FF 7E01 ; self goto self ; 1997 Microchip Technology Inc. AN526 01FF 01FF 0A42 00183 00184 00185 org goto END MEMORY USAGE MAP (‘X’ = Used, PIC54 main ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 0040 : XXXXXXXXXXXX---- ---------------- ---------------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 77 435 0 suppressed 0 suppressed DS00526E-page 15 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX D:DOUBLE PRECISION MULTIPLICATION LISTINGS (FAST) MPASM 01.40 Released LOC OBJECT CODE VALUE DBL_MPYF.ASM 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 000001FF 00000001 00000000 0000 DS00526E-page 16 1-16-1997 12:52:26 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00001 00002 00224 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************* ; Double Precision Multiplication ; ; ( Optimized for Speed : straight Line Code ) ; ;*******************************************************************; ;Multiplication : ACCb(16 bits) * ACCa(16 bits) -> ACCb,ACCc (32 bits) ; (a) Load the 1st operand in location ACCaLO & ACCaHI (16 bits) ; (b) Load the 2nd operand in location ACCbLO & ACCbHI (16 bits) ; (c) CALL D_mpy ; (d) The 32 bit result is in location (ACCbHI,ACCbLO,ACCcHI,ACCcLO) ; ; Performance : ; Program Memory : 240 ; Clock Cycles : 233 ; ; Note : The above timing is the worst case timing, when the ; register ACCb = FFFF. The speed may be improved if ; the register ACCb contains a number (out of the two ; numbers) with less number of 1s. ; ; The performance specs are for Unsigned arithmetic (i.e, ; with “SIGNED equ FALSE“). ; ; Program: DBL_MPYF.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; ACCaLO equ 10 ACCaHI equ 11 ACCbLO equ 12 ACCbHI equ 13 ACCcLO equ 14 ACCcHI equ 15 ACCdLO equ 16 ACCdHI equ 17 temp equ 18 sign equ 19 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST PIC54 TRUE FALSE equ equ equ 1FFH 1 0 ; Define Reset Vector org 0 ;******************************************************************* 1997 Microchip Technology Inc. AN526 00000000 0000 0000 09E2 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 0337 0336 0703 0A0B 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 000F 0337 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 M M M M M M M M M M M M M M M M M 00097 M M M SIGNED equ FALSE ; Set This To ‘TRUE’ if the routines ; ; for Multiplication & Division needs ; ; to be assembled as Signed Integer ; ; Routines. If ‘FALSE’ the above two ; ; routines ( D_mpy & D_div ) use ; ; unsigned arithmetic. ;******************************************************************* ; multiplication macro ; mulMac MACRO LOCAL NO_ADD ; rrf ACCdHI, F ;rotate d right rrf ACCdLO, F btfss STATUS,C ; need to add? goto NO_ADD ; no addition necessary movf ACCaLO,W ; Addition ( ACCb + ACCa -> ACCb ) addwf ACCbLO, F ;add lsb btfsc STATUS,C ; add in carry incf ACCbHI, F movf ACCaHI,W addwf ACCbHI, F ;add msb NO_ADD rrf ACCbHI, F rrf ACCbLO, F rrf ACCcHI, F rrf ACCcLO, F ; ENDM ; ;*******************************************************************; ; Double Precision Multiply ( 16x16 -> 32 ) ; ( ACCb*ACCa -> ACCb,ACCc ) : 32 bit output with high word ; in ACCb ( ACCbHI,ACCbLO ) and low word in ACCc ( ACCcHI,ACCcLO ). ; D_mpyF ;results in ACCb(16 msb’s) and ACCc(16 lsb’s) ; IF SIGNED CALL S_SIGN ENDIF ; call setup ; ; use the mulMac macro 16 times ; mulMac LOCAL NO_ADD ; rrf ACCdHI, F ;rotate d right rrf ACCdLO, F btfss STATUS,C ; need to add? goto NO_ADD ; no addition necessary movf ACCaLO,W ; Addition ( ACCb + ACCa -> ACCb ) addwf ACCbLO, F ; add lsb btfsc STATUS,C ; add in carry incf ACCbHI, F movf ACCaHI,W addwf ACCbHI, F ; add msb NO_ADD rrf ACCbHI, F rrf ACCbLO, F rrf ACCcHI, F rrf ACCcLO, F ; mulMac LOCAL NO_ADD ; rrf ACCdHI, F ; rotate d right 1997 Microchip Technology Inc. DS00526E-page 17 AN526 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 0336 0703 0A19 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 001D 001E 001F 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 0337 0336 0703 0A27 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0337 0336 0703 0A35 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 0039 003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0337 0336 0703 0A43 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 DS00526E-page 18 M M M M M M M M M M M M M M 00098 M M M M M M M M M M M M M M M M M 00099 M M M M M M M M M M M M M M M M M 00100 M M M M M M M M M M M M M M M NO_ADD rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ; need to add? ; no addition necessary ; Addition ( ACCb + ACCa -> ACCb ) ;add lsb ; add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb 1997 Microchip Technology Inc. AN526 0046 0334 0000 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0337 0336 0703 0A51 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0337 0336 0703 0A5F 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0337 0336 0703 0A6D 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 0071 0072 0073 0074 0075 0076 0077 0337 0336 0703 0A7B 0210 01F2 0603 M M 00101 M M M M M M M M M M M M M M M M M 00102 M M M M M M M M M M M M M M M M M 00103 M M M M M M M M M M M M M M M M M 00104 M M M M M M M M M rrf ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ; ; NO_ADD ;rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; 1997 Microchip Technology Inc. ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry DS00526E-page 19 AN526 0078 0079 007A 007B 007C 007D 007E 02B3 0211 01F3 0333 0332 0335 0334 0000 007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C 0337 0336 0703 0A89 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 0337 0336 0703 0A97 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 0337 0336 0703 0AA5 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 00A9 0337 DS00526E-page 20 M M M M M M M M 00105 M M M M M M M M M M M M M M M M M 00106 M M M M M M M M M M M M M M M M M 00107 M M M M M M M M M M M M M M M M M 00108 M M M NO_ADD incf movf addwf rrf rrf rrf rrf ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf ACCdHI, F ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; ; rotate d right 1997 Microchip Technology Inc. AN526 00AA 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 0336 0703 0AB3 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 00C1 00C2 00C3 00C4 0337 0336 0703 0AC1 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 0337 0336 0703 0ACF 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 0334 0000 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 0337 0336 0703 0ADD 0210 01F2 0603 02B3 0211 01F3 0333 0332 0335 M M M M M M M M M M M M M M 00109 M M M M M M M M M M M M M M M M M 00110 M M M M M M M M M M M M M M M M M 00111 M M M M M M M M M M M M M M M NO_ADD rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ACCcLO, F mulMac LOCAL NO_ADD rrf rrf btfss goto movf addwf btfsc incf movf addwf rrf rrf rrf ACCdHI, F ACCdLO, F STATUS,C NO_ADD ACCaLO,W ACCbLO, F STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F ACCbHI, F ACCbLO, F ACCcHI, F ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb ; ; NO_ADD 1997 Microchip Technology Inc. ; rotate d right ; ; ; ; ; need to add? no addition necessary Addition ( ACCb + ACCa -> ACCb ) add lsb add in carry ; add msb DS00526E-page 21 AN526 00E0 0334 00E1 0800 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 0C10 0038 0213 0037 0212 0036 0073 0072 0800 00EB 00EC 00ED 00EE 00EF 00F0 0270 02B0 0643 00F1 0271 0800 DS00526E-page 22 M M 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 rrf ACCcLO, F ; ; IF neg_B SIGNED btfss sign,MSB retlw 0 comf ACCcLO incf ACCcLO btfsc STATUS,Z decf ACCcHI comf ACCcHI btfsc STATUS,Z comf ACCbLO incf ACCbLO btfsc STATUS,Z decf ACCbHI comf ACCbHI retlw 0 ; negate ACCa ( -ACCa -> ACCa ) ; negate ACCb ELSE retlw ENDIF 0 ; ;******************************************************************* ; setup movlw .16 ; for 16 shifts movwf temp movf ACCbHI,W ;move ACCb to ACCd movwf ACCdHI movf ACCbLO,W movwf ACCdLO clrf ACCbHI clrf ACCbLO retlw 0 ; ;******************************************************************* ; neg_A comf ACCaLO, F ; negate ACCa ( -ACCa -> ACCa ) incf ACCaLO, F btfsc STATUS,Z decf ACCaHI, F comf ACCaHI, F retlw 0 ; ;******************************************************************* ; Assemble this section only if Signed Arithmetic Needed ; IF SIGNED ; S_SIGN movf ACCaHI,W xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB ; if MSB set go & negate ACCb goto chek_A ; comf ACCbLO ; negate ACCb incf ACCbLO btfsc STATUS,Z decf ACCbHI comf ACCbHI ; chek_A btfss ACCaHI,MSB ; if MSB set go & negate ACCa retlw 0 goto neg_A ; ENDIF ; 1997 Microchip Technology Inc. AN526 00176 00177 00178 00179 00180 00F1 0C01 00181 00F2 0031 00182 00F3 0CFF 00183 00F4 0030 00184 00185 00F5 0C7F 00186 00F6 0033 00187 00F7 0CFF 00188 00F8 0032 00189 00F9 0800 00190 00191 00FA 0000 00192 00193 00FB 09F1 00194 00FC 0900 00195 00196 00FD 0AFD 00197 00198 01FF 00199 01FF 0AFA 00200 00201 MEMORY USAGE MAP (‘X’ 0000 0040 0080 00C0 01C0 : : : : : ;******************************************************************* ; Test Program ;******************************************************************* ; Load constant values to ACCa & ACCb for testing ; loadAB movlw 1 movwf ACCaHI movlw 0FF ; loads ACCa = 01FF movwf ACCaLO ; movlw 07F movwf ACCbHI movlw 0FF ; loads ACCb = 7FFF movwf ACCbLO retlw 0 ; main nop ; call loadAB ;result of multiplying ACCb*ACCa->(ACCb,ACCc) call D_mpyF ; Here (ACCb,ACCc) = 00FF 7E01 ; self goto self ; org PIC54 goto main END = Used, ‘-’ = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXX----------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 255 257 0 suppressed 0 suppressed DS00526E-page 23 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX E:DOUBLE PRECISION ADDITION AND SUBTRACTION LISTING MPASM 01.40 Released LOC OBJECT CODE VALUE 00000010 00000011 00000012 00000013 000001FF 0000 0000 0908 0001 0210 0002 01F2 DS00526E-page 24 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00001 00002 00224 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 DBL_ADD.ASM 1-16-1997 12:50:38 PAGE 1 LINE SOURCE TEXT LIST P = 16C54, n = 66 ; ;******************************************************************* ; Double Precision Addition & Subtraction ; ;*******************************************************************; ; Addition : ACCb(16 bits) + ACCa(16 bits) -> ACCb(16 bits) ; (a) Load the 1st operand in location ACCaLO & ACCaHI ( 16 bits ) ; (b) Load the 2nd operand in location ACCbLO & ACCbHI ( 16 bits ) ; (c) CALL D_add ; (d) The result is in location ACCbLO & ACCbHI ( 16 bits ) ; ; Performance : ; Program Memory : 07 ; Clock Cycles : 08 ;*******************************************************************; ; Subtraction : ACCb(16 bits) - ACCa(16 bits) -> ACCb(16 bits) ; (a) Load the 1st operand in location ACCaLO & ACCaHI ( 16 bits ) ; (b) Load the 2nd operand in location ACCbLO & ACCbHI ( 16 bits ) ; (c) CALL D_sub ; (d) The result is in location ACCbLO & ACCbHI ( 16 bits ) ; ; Performance : ; Program Memory : 14 ; Clock Cycles : 17 ; ; ; Program: DBL_ADD.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; ACCaLO equ 10 ACCaHI equ 11 ACCbLO equ 12 ACCbHI equ 13 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST PIC54 equ 1FFH ; Define Reset Vector org 0 ;******************************************************************* ; Double Precision Subtraction ( ACCb - ACCa -> ACCb ) ; D_sub call neg_A ; At first negate ACCa; Then add ; ;******************************************************************* ; Double Precision Addition ( ACCb + ACCa -> ACCb ) ; D_add movf ACCaLO,W addwf ACCbLO, F ; add lsb 1997 Microchip Technology Inc. AN526 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 0603 02B3 0211 01F3 0800 0270 02B0 0643 00F1 0271 0800 000E 000F 0010 0011 0C01 0031 0CFF 0030 0012 0013 0014 0015 0016 0C7F 0033 0CFF 0032 0800 0017 0000 0018 090E 0019 0901 001A 090E 001B 0900 001C 0A1C 01FF 01FF 0A17 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 STATUS,C ACCbHI, F ACCaHI,W ACCbHI, F 0 ; add in carry comf incf btfsc decf comf retlw ACCaLO, F ACCaLO, F STATUS,Z ACCaHI, F ACCaHI, F 0 ; negate ACCa ( -ACCa -> ACCa ) ; ; neg_A btfsc incf movf addwf retlw ; add msb ; ;******************************************************************* ; Test Program ;******************************************************************* ; Load constant values to ACCa & ACCb for testing ; loadAB movlw 1 movwf ACCaHI movlw 0FF ; loads ACCa = 01FF movwf ACCaLO ; movlw 07F movwf ACCbHI movlw 0FF ; loads ACCb = 7FFF movwf ACCbLO retlw 0 ; main nop ; call loadAB ; result of adding ACCb+ACCa->ACCb call D_add ; Here Accb = 81FE ; call loadAB ; result of subtracting ACCb - ACCa->ACCb call D_sub ; Here Accb = 7E00 ; self goto self ; org PIC54 goto main END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXX--- ---------------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 30 482 0 suppressed 0 suppressed DS00526E-page 25 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX F:BCD TO BINARY CONVERSION LISTING MPASM 01.40 Released LOC OBJECT CODE VALUE 00000010 00000011 00000012 00000013 00000014 00000015 00000016 0000 0001 0002 0003 0004 0005 0006 0007 0008 0E0F 01F1 0603 02B0 0403 0351 0036 0350 0035 DS00526E-page 26 BCD2BIN.ASM 1-16-1997 12:49:30 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00001 00002 00224 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;********************************************************************** ; BCD To Binary Conversion ; ; This routine converts a 5 digit BCD number to a 16 bit binary ; number. ; The input 5 digit BCD numbers are asumed to be in locations ; R0, R1 & R2 with R0 containing the MSD in its right most nibble. ; ; The 16 bit binary number is output in registers H_byte & L_byte ; ( high byte & low byte repectively ). ; ; The method used for conversion is : ; input number X = abcde ( the 5 digit BCD number ) ; X = abcde = 10[10[10[10a+b]+c]+d]+e ; ; Performance : ; Program Memory : 30 ; Clock Cycles : 121 ; ; ; Program: BCD2BIN.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; H_byte equ 10 L_byte equ 11 R0 equ 12 ; RAM Assignments R1 equ 13 R2 equ 14 ; H_temp equ 15 ; temporary register L_temp equ 16 ; temporary register ; ; INCLUDE “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST ; ; mpy10b andlw 0F addwf L_byte, F btfsc STATUS,C incf H_byte, F mpy10a bcf STATUS,C ; multiply by 2 rlf L_byte,W movwf L_temp rlf H_byte,W ; (H_temp,L_temp) = 2*N movwf H_temp ; 1997 Microchip Technology Inc. AN526 0009 000A 000B 000C 000D 000E 000F 0010 0011 0403 0371 0370 0403 0371 0370 0403 0371 0370 00052 bcf STATUS,C ; multiply by 2 00053 rlf L_byte, F 00054 rlf H_byte, F 00055 bcf STATUS,C ; multiply by 2 00056 rlf L_byte, F 00057 rlf H_byte, F 00058 bcf STATUS,C ; multiply by 2 00059 rlf L_byte, F 00060 rlf H_byte, F ; (H_byte,L_byte) = 8*N 00061 ; 0012 0216 00062 movf L_temp,W 0013 01F1 00063 addwf L_byte, F 0014 0603 00064 btfsc STATUS,C 0015 02B0 00065 incf H_byte, F 0016 0215 00066 movf H_temp,W 0017 01F0 00067 addwf H_byte, F 0018 0800 00068 retlw 0 ; (H_byte,L_byte) = 10*N 00069 ; 00070 ; 0019 0070 00071 BCDtoB clrf H_byte 001A 0212 00072 movf R0,W 001B 0E0F 00073 andlw 0F 001C 0031 00074 movwf L_byte 001D 0904 00075 call mpy10a ; result = 10a+b 00076 ; 001E 0393 00077 swapf R1,W 001F 0900 00078 call mpy10b ; result = 10[10a+b] 00079 ; 0020 0213 00080 movf R1,W 0021 0900 00081 call mpy10b ; result = 10[10[10a+b]+c] 00082 ; 0022 0394 00083 swapf R2,W 0023 0900 00084 call mpy10b ; result = 10[10[10[10a+b]+c]+d] 00085 ; 0024 0214 00086 movf R2,W 0025 0E0F 00087 andlw 0F 0026 01F1 00088 addwf L_byte, F 0027 0603 00089 btfsc STATUS,C 0028 02B0 00090 incf H_byte, F ; result = 10[10[10[10a+b]+c]+d]+e 0029 0800 00091 retlw 0 ; BCD to binary conversion done 00092 ; 00093 ; 00094 ;******************************************************************** 00095 ; Test Program 00096 ;********************************************************************* 002A 0C06 00097 main movlw 06 002B 0032 00098 movwf R0 ; Set R0 = 06 002C 0C55 00099 movlw 55 002D 0033 00100 movwf R1 ; Set R1 = 55 002E 0C35 00101 movlw 35 002F 0034 00102 movwf R2 ; Set R2 = 35 ( R0, R1, R2 = 6,55,35 ) 00103 ; 0030 0919 00104 call BCDtoB ; After conversion H_Byte = FF & L_Byte = FF 00105 ; 0031 0A31 00106 self goto self 00107 ; 01FF 00108 org 1FF 01FF 0A2A 00109 goto main 00110 ; 00111 END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XX-------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. 1997 Microchip Technology Inc. DS00526E-page 27 AN526 Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00526E-page 28 0 0 reported, 0 reported, 51 461 0 suppressed 0 suppressed 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX G:BINARY (8-BIT) TO BCD CONVERSION MPASM 01.40 Released LOC OBJECT CODE VALUE BIN8BCD.ASM 1-16-1997 12:50:05 PAGE 1 LINE SOURCE TEXT 00001 LIST P = 16C54, n = 66 00002 ; 00003 ;******************************************************************** 00004 ; Binary To BCD Conversion Routine 00005 ; 00006 ; This routine converts the 8 bit binary number in the W Register 00007 ; to a 2 digit BCD number. 00008 ; The least significant digit is returned in location LSD and 00009 ; the most significant digit is returned in location MSD. 00010 ; 00011 ; Performance : 00012 ; Program Memory : 10 00013 ; Clock Cycles : 81 (worst case when W = 63 Hex ) 00014 ; ( i.e max Decimal number 99 ) 00015 ; 00016 ; Program: BIN8BCD.ASM 00017 ; Revision Date: 00018 ; 1-13-97 Compatibility with MPASMWIN 1.40 00019 ; 00020 ;******************************************************************* 00021 ; 00000010 00022 LSD equ 10 00000011 00023 MSD equ 11 00024 ; 00025 INCLUDE “p16c5x.inc” 00001 LIST 00002 ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. 00224 LIST 00026 ; 0000 0071 00027 BinBCD clrf MSD 0001 0030 00028 movwf LSD 0002 0C0A 00029 gtenth movlw .10 0003 0090 00030 subwf LSD,W 0004 0703 00031 BTFSS STATUS,C 0005 0A09 00032 goto over 0006 0030 00033 movwf LSD 0007 02B1 00034 incf MSD, F 0008 0A02 00035 goto gtenth 0009 0800 00036 over retlw 0 00037 ;******************************************************************* 00038 ; 000A 0C63 00039 main movlw 63 ; W reg = 63 Hex 000B 0900 00040 call BinBCD ; after conversion, MSD = 9 & LSD = 9 000C 0A0C 00041 self goto self ; ( 63 Hex = 99 Decimal ) 00042 ; 01FF 00043 org 1FF 01FF 0A0A 00044 goto main 00045 ; 00046 END 0000 : XXXXXXXXXXXXX--- ---------------- ---------------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. 1997 Microchip Technology Inc. DS00526E-page 29 AN526 Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00526E-page 30 0 0 reported, 0 reported, 14 498 0 suppressed 0 suppressed 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX H:BINARY (16-BIT) TO BCD LISTING MPASM 01.40 Released LOC OBJECT CODE VALUE B16TOBCD.ASM 00000016 00000017 00000010 00000011 00000012 00000013 00000014 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 0403 0C10 0036 0072 0073 0074 0371 0370 0374 0373 0372 000B 02F6 000C 0A0E 000D 0800 1-16-1997 12:48:00 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00001 00002 00224 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************** ; Binary To BCD Conversion Routine ; This routine converts a 16 Bit binary Number to a 5 Digit ; BCD Number. This routine is useful since PIC16C55 & PIC16C57 ; have two 8 bit ports and one 4 bit port ( total of 5 BCD digits) ; ; The 16 bit binary number is input in locations H_byte and ; L_byte with the high byte in H_byte. ; The 5 digit BCD number is returned in R0, R1 and R2 with R0 ; containing the MSD in its right most nibble. ; ; Performance : ; Program Memory : 35 ; Clock Cycles : 885 ; ; ; Program: B16TOBCD.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; count equ 16 temp equ 17 ; H_byte equ 10 L_byte equ 11 R0 equ 12 ; RAM Assignments R1 equ 13 R2 equ 14 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST ; B2_BCD bcf STATUS,0 ; clear the carry bit movlw .16 movwf count clrf R0 clrf R1 clrf R2 loop16 rlf L_byte, F rlf H_byte, F rlf R2, F rlf R1, F rlf R0, F ; decfsz count, F goto adjDEC RETLW 0 ; 1997 Microchip Technology Inc. DS00526E-page 31 AN526 000E 0C14 000F 0024 0010 0918 0011 0C13 0012 0024 0013 0918 0014 0C12 0015 0024 0016 0918 0017 0A06 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 0026 0C03 01C0 0037 0677 0020 0C30 01C0 0037 06F7 0020 0800 0CFF 0030 0031 0900 0027 0A27 01FF 01FF 0A23 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 adjDEC movlw movwf call R2 FSR adjBCD movlw movwf call R1 FSR adjBCD movlw movwf call R0 FSR adjBCD goto loop16 movlw addwf movwf btfsc movwf movlw addwf movwf btfsc movwf RETLW 3 0,W temp temp,3 0 30 0,W temp temp,7 0 0 ; ; ; ; adjBCD ; test if result > 7 ; test if result > 7 ; save as MSD ; ;******************************************************************** ; Test Program ;********************************************************************* main movlw 0FF movwf H_byte movwf L_byte ; The 16 bit binary number = FFFF call B2_BCD ; After conversion the Decimal Number ; ; in R0,R1,R2 = 06,55,35 ; self goto self ; org 1FF goto main ; END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXX-------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00526E-page 32 0 0 reported, 0 reported, 41 471 0 suppressed 0 suppressed 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX I:UNSIGNED BCD SUBTRACTION LISTING MPASM 01.40 Released LOC OBJECT CODE VALUE BCD_SUB.ASM 00000008 00000008 00000009 00000009 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0208 00A9 0068 0368 0723 0A0C 0769 0A0E 0649 0A0C 0729 0A0E 0C06 00A9 0708 0A17 0068 07E9 0800 06C9 0A17 07A9 1-16-1997 12:49:00 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00001 00002 00224 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************* Unsigned BCD Subtraction *************** ; ; This routine performs a 2 Digit Unsigned BCD Subtraction. ; It is assumed that the two BCD numbers to be subtracted are in ; locations Num_1 & Num_2. The result is the difference of Num_1 & Num_2 ; ( Num_2 - Num_1) and is stored in location Num_2 and the overflow carry ; is returned in location Num_1. ; ; Performance : ; Program Memory : 31 ; Clock Cycles : 21 ( worst case ) ; ; ; Program: BCD_SUB.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;******************************************************************* ; Num_1 equ 8 ; Overflow flow carry overwrites Num_1 result equ 8 ; Num_2 equ 9 ; Num_2 - Num_1 overwrites Num_2 O_flow equ 9 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST ; BCDSub movf Num_1,W subwf Num_2, F clrf Num_1 rlf Num_1, F btfss STATUS,DC goto adjst1 btfss Num_2,3 ; Adjust LSD of Result goto Over_1 btfsc Num_2,2 goto adjst1 ; Adjust LSD of Result btfss Num_2,1 goto Over_1 ; No : Go for MSD adjst1 movlw 6 subwf Num_2, F Over_1 btfss Num_1,0 ; CY = 0 ? goto adjst2 ; Yes, adjust MSD of result clrf Num_1 btfss Num_2,7 ; No, test for MSD >9 RETLW 0 btfsc Num_2,6 goto adjst2 btfss Num_2,5 1997 Microchip Technology Inc. DS00526E-page 33 AN526 0016 0017 0018 0019 001A 001B 001C 001D 001E 0800 0C60 00A9 0068 0703 0800 0C01 0028 0800 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 001F 0C23 00065 0020 0028 00066 0021 0C99 00067 0022 0029 00068 0023 0900 00069 00070 00071 0024 0C99 00072 0025 0028 00073 0026 0C00 00074 0027 0029 00075 00076 0028 0900 00077 00078 00079 00080 0029 0A29 00081 00082 01FF 00083 01FF 0A1F 00084 00085 00086 MEMORY USAGE MAP (‘X’ adjst2 RETLW movlw subwf clrf btfss RETLW movlw movwf RETLW 0 60 Num_2, F Num_1 STATUS,C 0 1 Num_1 0 ; add 6 to MSD ; test if underflow Over ; ;******************************************************************** ; Test Program ;********************************************************************* main movlw 23 movwf Num_1 ; Set Num_1 = 23 movlw 99 movwf Num_2 ; Set Num_2 = 99 call BCDSub ; After subtraction, Num_2 = 76 ( 99-23 ) ; ; and Num_1 = 0 ( indicates positive result ) ; movlw 99 movwf Num_1 ; Set Num_1 = 99 movlw 0 movwf Num_2 ; Set Num_2 = 0 ; call BCDSub ; After subtraction, Num_2 = 1 ; ; and Num_1 = 1 ( indicates negative result ) ; ; -1 <- ( -99 ) ; self goto self ; org 1FF goto main ; END = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXX------ ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : DS00526E-page 34 0 0 reported, 0 reported, 43 469 0 suppressed 0 suppressed 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX J:SQUARE ROOT METHOD MPASM 01.40 Released LOC OBJECT CODE VALUE SQRT.ASM 000001FF 00000001 1-16-1997 12:55:13 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00001 00002 00224 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************* ; ; Square Root By Newton Raphson Method ; ; This routine computes the square root of a 16 bit number(with ; low byte in NumLo & high byte in NumHi ). After loading NumLo & ; NumHi with the desired number whose square root is to be computed, ; branch to location Sqrt ( by “GOTO Sqrt” ). “ CALL Sqrt” cannot ; be issued because the Sqrt function makes calls to Math routines ; and the stack is completely used up. ; The result = sqrt(NumHi,NumLo) is returned in location SqrtLo. ; The total number of iterations is set to ten. If more iterations ; are desired, change “LupCnt equ .10” to the desired value. Also, ; the initial guess value of the square root is given set as ; input/2 ( in subroutine “init” ). The user may modify this scheme ; if a better initial approximation value is known. A good initial ; guess will help the algorithm converge at a faster rate and thus ; less number of iterations required. ; Two utility math routines are used by this program : D_divS ; and D_add. These two routines are listed as seperate routines ; under double precision Division and double precision addtion ; respectively. ; ; Note : If square root of an 8 bit number is desired, it is probably ; better to have a table look scheme rather than using numerical ; methods. ; ; ; ; Performance : ; Program Memory : 27 (excluding Math Routines ; D_divS & D_add ) ; Clock Cycles : 3600 ( approximately ) ; ; ; Program: SQRT.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ; To assemble this program, two routines, namely “D_add” & ; “D_divS” must be included into this program. These two routines ; are listed as separate programs in files “DBL_ADD.ASM” & ; “DBL_DIVS.ASM” respectively. ; ;******************************************************************* include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver.n 3.30 Microchip Technology, Inc. LIST PIC54 TRUE 1997 Microchip Technology Inc. equ equ 1FFH 1 ; Define Reset Vector DS00526E-page 35 AN526 00000000 0000 0000000A 00000010 00000011 00000013 00000014 00000014 00000015 00000016 00000017 00000018 00000019 00000010 00000011 0000001D 0000001E 0000001F 0000 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0C0A 003F 021E 0031 021D 0030 0403 0331 0330 0800 000A 000B 000C 000D 000E 000F 0403 0314 0031 0313 0030 0800 0010 0011 0012 0013 0014 0015 0016 0210 01F3 0603 02B4 0211 01F4 0800 00000000 DS00526E-page 36 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 FALSE ; LupCnt ; ACCaLO ACCaHI ACCbLO ACCbHI ACCcLO ACCcHI ACCdLO ACCdHI temp sign ; SqrtLo SqrtHi ; NumLo NumHi count ; ; init ; div2 equ 0 org 0 equ .10 equ equ equ equ equ equ equ equ equ equ 10 11 13 14 14 15 16 17 18 19 equ equ ACCaLO ACCaHI equ equ equ 1D 1E 1F movlw movwf movf movwf movf movwf bcf rrf rrf retlw LupCnt count NumHi,W SqrtHi NumLo,W SqrtLo STATUS,C SqrtHi, F SqrtLo, F 0 bcf rrf movwf rrf movwf retlw STATUS,C ACCbHI,W SqrtHi ACCbLO,W SqrtLo 0 ; Number of iterations ; set initial guess root = NUM/2 ; ;******************************************************************* ; Double Precision Addition ( ACCb + ACCa -> ACCb ) ; D_add movf ACCaLO,W addwf ACCbLO, F ;add lsb btfsc STATUS,C ;add in carry incf ACCbHI, F movf ACCaHI,W addwf ACCbHI, F ;add msb retlw 0 ; ;******************************************************************* SIGNED equ FALSE ; Set This To ‘TRUE’ if the routines ; ; for Multiplication & Division needs ; ; to be assembled as Signed Integer ; ; Routines. If ‘FALSE’ the above two ; ; routines ( D_mpy & D_div ) use ; ; unsigned arithmetic. ;******************************************************************* ; Double Precision Divide ( 16/16 -> 16 ) ; ; ( ACCb/ACCa -> ACCb with remainder in ACCc ) : 16 bit output 1997 Microchip Technology Inc. AN526 0017 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0933 0075 0074 0403 0376 0377 0374 0375 0211 0095 0743 0A25 0210 0094 0703 0A2E 0210 00B4 0703 00F5 0211 00B5 0503 0373 0374 02F8 0A1A 0032 0800 0033 0034 0035 0036 0037 0038 0039 003A 003B 0C10 0038 0214 0037 0213 0036 0074 0073 0800 003C 0270 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 ; with Quotiont in ACCb (ACCbHI,ACCbLO) and Remainder in ; ACCc (ACCcHI,ACCcLO). ; NOTE: Before calling this routine, the user should make sure that ; the Numerator(ACCb) is greater than Denominator(ACCa). If ; the case is not true, the user should scale either Numerator ; or Denominator or both such that Numerator is greater than ; the Denominator. ; ; D_divS ; IF SIGNED CALL S_SIGN ENDIF ; call setup clrf ACCcHI clrf ACCcLO dloop bcf STATUS,C rlf ACCdLO, F rlf ACCdHI, F rlf ACCcLO, F rlf ACCcHI, F movf ACCaHI,W subwf ACCcHI,W ; check if a>c btfss STATUS,Z goto nochk movf ACCaLO,W subwf ACCcLO,W ; if msb equal then check lsb nochk btfss STATUS,C ; carry set if c>a goto nogo movf ACCaLO,W ; c-a into c subwf ACCcLO, F btfss STATUS,C decf ACCcHI, F movf ACCaHI,W subwf ACCcHI, F bsf STATUS,C ; shift a 1 into b (result) nogo rlf ACCbLO, F rlf ACCbHI, F decfsz temp, F ; loop untill all bits checked goto dloop ; IF SIGNED btfss sign,MSB ; check sign if negative retlw 0 goto neg_B ; negate ACCa ( -ACCa -> ACCa ) ELSE retlw 0 ENDIF ; ;******************************************************************* ; setup movlw .16 ; for 16 shifts movwf temp movf ACCbHI,W ; move ACCb to ACCd movwf ACCdHI movf ACCbLO,W movwf ACCdLO clrf ACCbHI clrf ACCbLO retlw 0 ; ;******************************************************************* ; neg_A comf ACCaLO, F ; negate ACCa ( -ACCa -> ACCa ) 1997 Microchip Technology Inc. DS00526E-page 37 AN526 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 02B0 0643 00F1 0271 0800 0900 021D 0033 021E 0034 0047 0917 0048 0910 0049 004A 004B 004C 090A 02FF 0A43 0A52 004D 004E 004F 0050 0CF3 003E 0CF6 003D 0051 0A42 0052 0000 0053 0A53 01FF 01FF 0A4D DS00526E-page 38 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 incf btfsc decf comf retlw ACCaLO, F STATUS,Z ACCaHI, F ACCaHI, F 0 ; ;******************************************************************* ; Assemble this section only if Signed Arithmetic Needed ; IF SIGNED ; S_SIGN movf ACCaHI,W xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB ; if MSB set go & negate ACCb goto chek_A ; comf ACCbLO ; negate ACCb incf ACCbLO btfsc STATUS,Z decf ACCbHI comf ACCbHI ; chek_A btfss ACCaHI,MSB ; if MSB set go & negate ACCa retlw 0 goto neg_A ; ENDIF ; ; Sqrt call init sloop movf NumLo,W movwf ACCbLO movf NumHi,W movwf ACCbHI ; call D_divS ; double precision division call D_add ; double precision addition ; ; the above 2 routines are listed ; ; as seperate routines call div2 decfsz count, F goto sloop goto over ; all iterations done ; ; branch back to desired location ; ;************************************************************* ; Test Program ;************************************************************* ; main movlw 0F3 movwf NumHi movlw 0F6 ; Set input test number = 62454 movwf NumLo ; = F3F6h ; goto Sqrt ; cannot use CALL : Math routines ; ; use up all the stack. over nop ; all iterations done ; self goto self ; result = 00F9h = 249 ; ; exact sqrt(62454) = 249.9 ; org PIC54 goto main ; END 1997 Microchip Technology Inc. AN526 MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 0040 : XXXXXXXXXXXXXXXX XXXX------------ ---------------- ---------------01C0 : ---------------- ---------------- ---------------- ---------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : 0 Warnings : Messages : 0 reported, 0 reported, 1997 Microchip Technology Inc. 85 427 0 suppressed 0 suppressed DS00526E-page 39 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX K:DOUBLE PRECISION DIVISION LISTING (LOOPED) MPASM 01.40 Released LOC OBJECT CODE VALUE DBL_DIVF.ASM 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 000001FF 00000001 00000000 0000 00000000 DS00526E-page 40 1-16-1997 12:51:16 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00001 00002 00224 00044 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************* ; Double Precision Division ; ; ( Optimized for Speed : straight Line Code ) ; ;*******************************************************************; ; Division : ACCb(16 bits)/ACCa(16 bits)-> ACCb(16 bits) with ; Remainder in ACCc (16 bits) ; (a) Load the Denominator in location ACCaHI & ACCaLO ( 16 bits ) ; (b) Load the Numerator in location ACCbHI & ACCbLO ( 16 bits ) ; (c) CALL D_div ; (d) The 16 bit result is in location ACCbHI & ACCbLO ; (e) The 16 bit Remainder is in locations ACCcHI & ACCcLO ; ; Performance : ; Program Memory : 370 ; Clock Cycles : 263 ; ; NOTE : ; The performance specs are for Unsigned arithmetic (i.e, ; with “SIGNED equ FALSE“). ; ; ; Program: DBL_DIVF.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; ACCaLO equ 10 ACCaHI equ 11 ACCbLO equ 12 ACCbHI equ 13 ACCcLO equ 14 ACCcHI equ 15 ACCdLO equ 16 ACCdHI equ 17 temp equ 18 sign equ 19 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST PIC54 TRUE FALSE equ equ equ 1FFH 1 0 ; Define Reset Vector org 0 ;******************************************************************* SIGNED equ FALSE ; Set This To ‘TRUE’ if the routines 1997 Microchip Technology Inc. AN526 0000 0001 0002 0003 0004 0005 0006 0007 0008 0C10 0038 0213 0037 0212 0036 0073 0072 0800 0009 000A 000B 000C 0270 02B0 0643 00F1 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 ; ; for Multiplication & Division needs ; ; to be assembled as Signed Integer ; ; Routines. If ‘FALSE’ the above two ; ; routines ( D_mpy & D_div ) use ; ; unsigned arithmetic. ;*******************************************************************; ; division macro ; divMac MACRO LOCAL NOCHK LOCAL NOGO ; bcf STATUS,C rlf ACCdLO, F rlf ACCdHI, F rlf ACCcLO, F rlf ACCcHI, F movf ACCaHI,W subwf ACCcHI,W ; check if a>c btfss STATUS,Z goto NOCHK movf ACCaLO,W subwf ACCcLO,W ; if msb equal then check lsb NOCHK btfss STATUS,C ; carry set if c>a goto NOGO movf ACCaLO,W ; c-a into c subwf ACCcLO, F btfss STATUS,C decf ACCcHI, F movf ACCaHI,W subwf ACCcHI, F bsf STATUS,C ; shift a 1 into b (result) NOGO rlf ACCbLO, F rlf ACCbHI, F ; ENDM ; ;******************************************************************* ; Double Precision Divide ( 16/16 -> 16 ) ; ; ( ACCb/ACCa -> ACCb with remainder in ACCc ) : 16 bit output ; with Quotiont in ACCb (ACCbHI,ACCbLO) and Remainder in ACCc ; (ACCcHI,ACCcLO). ; NOTE: Before calling this routine, the user should make sure that ; the Numerator(ACCb) is greater than Denominator(ACCa). If ; the case is not true, the user should scale either Numerator ; or Denominator or both such that Numerator is greater than ; the Denominator. ; ; setup movlw .16 ; for 16 shifts movwf temp movf ACCbHI,W ; move ACCb to ACCd movwf ACCdHI movf ACCbLO,W movwf ACCdLO clrf ACCbHI clrf ACCbLO retlw 0 ; ;******************************************************************* ; neg_A comf ACCaLO, F ; negate ACCa ( -ACCa -> ACCa ) incf ACCaLO, F btfsc STATUS,Z decf ACCaHI, F 1997 Microchip Technology Inc. DS00526E-page 41 AN526 000D 0271 000E 0800 000F 000F 0900 0010 0075 0011 0074 0000 0000 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 0026 0027 0403 0376 0377 0374 0375 0211 0095 0743 0A1D 0210 0094 0703 0A26 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0403 0376 0377 0374 0375 0211 0095 0743 0A33 0210 0094 0703 0A3C 0210 00B4 0703 00F5 DS00526E-page 42 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 M M M M M M M M M M M M M M M M M M M M M M M M M M 00137 M M M M M M M M M M M M M M M M M M M M comf retlw ACCaHI, F 0 ; ;******************************************************************* ; D_divF ; IF SIGNED CALL S_SIGN ENDIF ; call setup clrf ACCcHI clrf ACCcLO ; ; use the mulMac macro 16 times ; divMac LOCAL NOCHK LOCAL NOGO ; bcf STATUS,C rlf ACCdLO, F rlf ACCdHI, F rlf ACCcLO, F rlf ACCcHI, F movf ACCaHI,W subwf ACCcHI,W btfss STATUS,Z goto NOCHK movf ACCaLO,W subwf ACCcLO,W NOCHK btfss STATUS,C goto NOGO movf ACCaLO,W subwf ACCcLO, F btfss STATUS,C decf ACCcHI, F movf ACCaHI,W subwf ACCcHI, F bsf STATUS,C NOGO rlf ACCbLO, F rlf ACCbHI, F ; divMac LOCAL NOCHK LOCAL NOGO ; bcf STATUS,C rlf ACCdLO, F rlf ACCdHI, F rlf ACCcLO, F rlf ACCcHI, F movf ACCaHI,W subwf ACCcHI,W btfss STATUS,Z goto NOCHK movf ACCaLO,W subwf ACCcLO,W NOCHK btfss STATUS,C goto NOGO movf ACCaLO,W subwf ACCcLO, F btfss STATUS,C decf ACCcHI, F ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c 1997 Microchip Technology Inc. AN526 0039 003A 003B 003C 003D 0211 00B5 0503 0372 0373 0000 0000 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0403 0376 0377 0374 0375 0211 0095 0743 0A49 0210 0094 0703 0A52 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0054 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 0403 0376 0377 0374 0375 0211 0095 0743 0A5F 0210 0094 0703 0A68 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 006A 0403 006B 0376 M M M M M M 00138 M M M M M M M M M M M M M M M M M M M M M M M M M M 00139 M M M M M M M M M M M M M M M M M M M M M M M M M M 00140 M M M M M NOGO movf subwf bsf rlf rlf ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf STATUS,C ACCdLO, F ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; 1997 Microchip Technology Inc. DS00526E-page 43 AN526 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 007A 007B 007C 007D 007E 007F 0377 0374 0375 0211 0095 0743 0A75 0210 0094 0703 0A7E 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0403 0376 0377 0374 0375 0211 0095 0743 0A8B 0210 0094 0703 0A94 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 0403 0376 0377 0374 0375 0211 0095 0743 0AA1 0210 0094 0703 0AAA 0210 DS00526E-page 44 M M M M M M M M M M M M M M M M M M M M M 00141 M M M M M M M M M M M M M M M M M M M M M M M M M M 00142 M M M M M M M M M M M M M M M M M NOCHK NOGO rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ;c-a into c ; shift a 1 into b (result) ; ; NOCHK ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c 1997 Microchip Technology Inc. AN526 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 00AC 00AD 00AE 00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF 00C0 00C1 0403 0376 0377 0374 0375 0211 0095 0743 0AB7 0210 0094 0703 0AC0 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 0403 0376 0377 0374 0375 0211 0095 0743 0ACD 0210 0094 0703 0AD6 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 M M M M M M M M M 00143 M M M M M M M M M M M M M M M M M M M M M M M M M M 00144 M M M M M M M M M M M M M M M M M M M M M M M M M M 00145 M M NOGO subwf btfss decf movf subwf bsf rlf rlf ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; 1997 Microchip Technology Inc. DS00526E-page 45 AN526 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED 0403 0376 0377 0374 0375 0211 0095 0743 0AE3 0210 0094 0703 0AEC 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 00EE 00EF 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF 0100 0101 0102 0103 0403 0376 0377 0374 0375 0211 0095 0743 0AF9 0210 0094 0703 0B02 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0104 0105 0106 0107 0108 0109 010A 010B 010C 010D 010E 0403 0376 0377 0374 0375 0211 0095 0743 0B0F 0210 0094 DS00526E-page 46 M M M M M M M M M M M M M M M M M M M M M M M M 00146 M M M M M M M M M M M M M M M M M M M M M M M M M M 00147 M M M M M M M M M M M M M M ; NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; ; check if a>c ; if msb equal then check lsb 1997 Microchip Technology Inc. AN526 010F 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 0703 0B18 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 011A 011B 011C 011D 011E 011F 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0403 0376 0377 0374 0375 0211 0095 0743 0B25 0210 0094 0703 0B2E 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 013A 013B 013C 013D 013E 013F 0140 0141 0142 0143 0144 0145 0403 0376 0377 0374 0375 0211 0095 0743 0B3B 0210 0094 0703 0B44 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 M M M M M M M M M M M M 00148 M M M M M M M M M M M M M M M M M M M M M M M M M M 00149 M M M M M M M M M M M M M M M M M M M M M M M M M M NOCHK NOGO btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; 1997 Microchip Technology Inc. DS00526E-page 47 AN526 0000 0000 0146 0147 0148 0149 014A 014B 014C 014D 014E 014F 0150 0151 0152 0153 0154 0155 0156 0157 0158 0159 015A 015B 0403 0376 0377 0374 0375 0211 0095 0743 0B51 0210 0094 0703 0B5A 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0000 0000 015C 015D 015E 015F 0160 0161 0162 0163 0164 0165 0166 0167 0168 0169 016A 016B 016C 016D 016E 016F 0170 0171 0403 0376 0377 0374 0375 0211 0095 0743 0B67 0210 0094 0703 0B70 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 0172 0800 DS00526E-page 48 00150 M M M M M M M M M M M M M M M M M M M M M M M M M M 00151 M M M M M M M M M M M M M M M M M M M M M M M M M M 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F divMac LOCAL LOCAL NOCHK NOGO bcf rlf rlf rlf rlf movf subwf btfss goto movf subwf btfss goto movf subwf btfss decf movf subwf bsf rlf rlf STATUS,C ACCdLO, F ACCdHI, F ACCcLO, F ACCcHI, F ACCaHI,W ACCcHI,W STATUS,Z NOCHK ACCaLO,W ACCcLO,W STATUS,C NOGO ACCaLO,W ACCcLO, F STATUS,C ACCcHI, F ACCaHI,W ACCcHI, F STATUS,C ACCbLO, F ACCbHI, F ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; NOCHK NOGO ; check if a>c ; if msb equal then check lsb ; carry set if c>a ; c-a into c ; shift a 1 into b (result) ; ; IF SIGNED btfss sign,MSB retlw 0 goto neg_B ; check sign if negative ; negate ACCa (-ACCa -> ACCa) ELSE retlw ENDIF 0 ; ;******************************************************************* ; Assemble this section only if Signed Arithmetic Needed ; 1997 Microchip Technology Inc. AN526 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 0173 0C01 00189 0174 0031 00190 0175 0CFF 00191 0176 0030 00192 00193 0177 0C7F 00194 0178 0033 00195 0179 0CFF 00196 017A 0032 00197 00198 017B 090F 00199 00200 017C 0B7C 00201 00202 01FF 00203 01FF 0B73 00204 00205 MEMORY USAGE MAP (‘X’ 0000 0040 0080 00C0 0100 0140 01C0 : : : : : : : IF SIGNED ; S_SIGN movf ACCaHI,W xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB ; if MSB set go & negate ACCb goto chek_A ; comf ACCbLO ; negate ACCb incf ACCbLO btfsc STATUS,Z decf ACCbHI comf ACCbHI ; chek_A btfss ACCaHI,MSB ; if MSB set go & negate ACCa retlw 0 goto neg_A ; ENDIF ; ;******************************************************************* ; Test Program ;******************************************************************* ; Load constant values to ACCa & ACCb for testing ; main movlw 1 movwf ACCaHI movlw 0FF ; loads ACCa = 01FF movwf ACCaLO ; movlw 07F movwf ACCbHI movlw 0FF ; loads ACCb = 7FFF movwf ACCbLO self ; call D_divF goto self ; remainder in ACCc. Here ACCb = 0040 & ; ACCc=003F org PIC54 goto main END = Used, ‘-’ = Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX ---------------- XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXX-----------------X All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 382 130 0 suppressed 0 suppressed DS00526E-page 49 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX L:DOUBLE PRECISION DIVISION LISTING (FAST) MPASM 01.40 Released LOC OBJECT CODE VALUE 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018 00000019 000001FF 00000001 00000000 0000 00000000 DS00526E-page 50 DBL_DIVS.ASM 1-16-1997 12:51:51 PAGE 1 LINE SOURCE TEXT 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00001 00002 00224 00044 00045 00046 00047 00048 00049 00050 00051 LIST P = 16C54, n = 66 ; ;******************************************************************* ; Double Precision Division ; ; ( Optimized for Code Size : Looped Code ) ; ;*******************************************************************; ; Division : ACCb(16 bits) / ACCa(16 bits) -> ACCb(16 bits) with ; Remainder in ACCc (16 bits) ; (a) Load the Denominator in location ACCaHI & ACCaLO ( 16 bits ) ; (b) Load the Numerator in location ACCbHI & ACCbLO ( 16 bits ) ; (c) CALL D_div ; (d) The 16 bit result is in location ACCbHI & ACCbLO ; (e) The 16 bit Remainder is in locations ACCcHI & ACCcLO ; ; Performance : ; Program Memory : 037 ; Clock Cycles : 310 ; ; NOTE : ; The performance specs are for Unsigned arithmetic ; ( i.e,with “SIGNED equ FALSE “). ; ; ; Program: DBL_DIVS.ASM ; Revision Date: ; 1-13-97 Compatibility with MPASMWIN 1.40 ; ;*******************************************************************; ; ACCaLO equ 10 ACCaHI equ 11 ACCbLO equ 12 ACCbHI equ 13 ACCcLO equ 14 ACCcHI equ 15 ACCdLO equ 16 ACCdHI equ 17 temp equ 18 sign equ 19 ; include “p16c5x.inc” LIST ;P16C5X.INC Standard Header File, Ver. 3.30 Microchip Technology, Inc. LIST PIC54 TRUE FALSE equ equ equ 1FFH 1 0 ; Define Reset Vector org 0 ;******************************************************************* SIGNED equ FALSE ; Set This To ‘TRUE’ if the routines 1997 Microchip Technology Inc. AN526 0000 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 091C 0075 0074 0403 0376 0377 0374 0375 0211 0095 0743 0A0E 0210 0094 0703 0A17 0210 00B4 0703 00F5 0211 00B5 0503 0372 0373 02F8 0A03 001B 0800 001C 001D 001E 001F 0C10 0038 0213 0037 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 1997 Microchip Technology Inc. ; ; for Multiplication & Division needs ; ; to be assembled as Signed Integer ; ; Routines. If ‘FALSE’ the above two ; ; routines ( D_mpy & D_div ) use ; ; unsigned arithmetic. ;******************************************************************* ; Double Precision Divide ( 16/16 -> 16 ) ; ; (ACCb/ACCa -> ACCb with remainder in ACCc) : 16 bit output ; with Quotiont in ACCb (ACCbHI,ACCbLO) and Remainder in ACCc ; (ACCcHI,ACCcLO). ; NOTE: Before calling this routine, the user should make sure that ; the Numerator(ACCb) is greater than Denominator(ACCa). If ; the case is not true, the user should scale either Numerator ; or Denominator or both such that Numerator is greater than ; the Denominator. ; ; D_divS ; IF SIGNED CALL S_SIGN ENDIF ; call setup clrf ACCcHI clrf ACCcLO dloop bcf STATUS,C rlf ACCdLO, F rlf ACCdHI, F rlf ACCcLO, F rlf ACCcHI, F movf ACCaHI,W subwf ACCcHI,W ; check if a>c btfss STATUS,Z goto nochk movf ACCaLO,W subwf ACCcLO,W ; if msb equal then check lsb nochk btfss STATUS,C ; carry set if c>a goto nogo movf ACCaLO,W ; c-a into c subwf ACCcLO, F btfss STATUS,C decf ACCcHI, F movf ACCaHI,W subwf ACCcHI, F bsf STATUS,C ; shift a 1 into b (result) nogo rlf ACCbLO, F rlf ACCbHI, F decfsz temp, F ; loop untill all bits checked goto dloop ; IF SIGNED btfss sign,MSB ; check sign if negative retlw 0 goto neg_B ; negate ACCa ( -ACCa -> ACCa ) ELSE retlw 0 ENDIF ; ;******************************************************************* ; setup movlw .16 ; for 16 shifts movwf temp movf ACCbHI,W ; move ACCb to ACCd movwf ACCdHI DS00526E-page 51 AN526 0020 0021 0022 0023 0024 0212 0036 0073 0072 0800 0025 0026 0027 0028 0029 002A 0270 02B0 0643 00F1 0271 0800 002B 002C 002D 002E 0C01 0031 0CFF 0030 002F 0030 0031 0032 0C7F 0033 0CFF 0032 0033 0900 ACCc=003F 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 movf movwf clrf clrf retlw ACCbLO,W ACCdLO ACCbHI ACCbLO 0 ; ;******************************************************************* ; neg_A comf ACCaLO, F ; negate ACCa ( -ACCa -> ACCa ) incf ACCaLO, F btfsc STATUS,Z decf ACCaHI, F comf ACCaHI, F retlw 0 ; ;******************************************************************* ; Assemble this section only if Signed Arithmetic Needed ; IF SIGNED ; S_SIGN movf ACCaHI,W xorwf ACCbHI,W movwf sign btfss ACCbHI,MSB ; if MSB set go & negate ACCb goto chek_A ; comf ACCbLO ; negate ACCb incf ACCbLO btfsc STATUS,Z decf ACCbHI comf ACCbHI ; chek_A btfss ACCaHI,MSB ; if MSB set go & negate ACCa retlw 0 goto neg_A ; ENDIF ; ;******************************************************************* ; Test Program ;******************************************************************* ; Load constant values to ACCa & ACCb for testing ; main movlw 1 movwf ACCaHI movlw 0FF ; loads ACCa = 01FF movwf ACCaLO ; movlw 07F movwf ACCbHI movlw 0FF ; loads ACCb = 7FFF movwf ACCbLO ; call D_divS ; remainder in ACCc. Here ACCb =0040 & 00172 ; 00173 self goto self 00174 ; 01FF 00175 org PIC54 01FF 0A2B 00176 goto main 00177 END MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused) 0034 0A34 0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXX----------01C0 : ---------------- ---------------- ---------------- ---------------X DS00526E-page 52 1997 Microchip Technology Inc. AN526 All other memory blocks unused. Program Memory Words Used: Program Memory Words Free: Errors : Warnings : Messages : 0 0 reported, 0 reported, 1997 Microchip Technology Inc. 54 458 0 suppressed 0 suppressed DS00526E-page 53 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX M: LIST ; P16C5X.INC NOLIST ; ; ; ; Microchip Technology, Inc. This header file defines configurations, registers, and other useful bits of information for the 16C5X microcontrollers. These names are taken to match the data sheets as closely as possible. The microcontrollers included in this file are: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Standard Header File, Version 3.30 16C52 16C54 16CR54 16C54A 16CR54A 16C55 16C56 16C57 16CR57A 16CR57B 16C58A 16CR58A There is one group of symbols that is valid for all microcontrollers. Each microcontroller in this family also has its own section of special symbols. Note that the processor must be selected before this file is included. The processor may be selected the following ways: ; ; ; ; ; 1. Command line switch: C:\ MPASM MYFILE.ASM /P16C54A 2. LIST directive in the source file LIST P=16C54A 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;3.30 07/16/96 Aligned processors with MPASM v1.40 ;3.2004/09/96 Added 16C54B, 16CR56B, 16C58B ;3.10 12/14/95 Added 16C52 ;3.01 11/29/95 Removed 16CR55 ;3.00 10/16/95 Added new processors for MPASM v1.30 ;2.04 07/26/95 Reformatted for readability ;2.03 06/21/95 Removed leading spaces ;========================================================================== ; ; Generic Definitions ; ;========================================================================== W F EQU EQU H’0000’ H’0001’ ;----- Register Files ----------------------------------------------------- DS00526E-page 54 1997 Microchip Technology Inc. AN526 INDF TMR0 PCL STATUS FSR PORTA PORTB EQU EQU EQU EQU EQU EQU EQU H’0000’ H’0001’ H’0002’ H’0003’ H’0004’ H’0005’ H’0006’ ;----- STATUS Bits -------------------------------------------------------PA2 PA1 PA0 NOT_TO NOT_PD Z DC C EQU EQU EQU EQU EQU EQU EQU EQU H’0007’ H’0006’ H’0005’ H’0004’ H’0003’ H’0002’ H’0001’ H’0000’ ;----- OPTION Bits -------------------------------------------------------T0CS T0SE PSA PS2 PS1 PS0 EQU EQU EQU EQU EQU EQU H’0005’ H’0004’ H’0003’ H’0002’ H’0001’ H’0000’ ;========================================================================== ; ; Processor-dependent Definitions ; ;========================================================================== IFDEF __16C52 __MAXRAM H’01F’ #define __CONFIG_2 ENDIF ;-------------------------------------------------------------------------IFDEF __16C54 __MAXRAM H’01F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16CR54 __MAXRAM H’01F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16C54A __MAXRAM H’01F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16CR54A __MAXRAM H’01F’ #define __CONFIG_1 ENDIF 1997 Microchip Technology Inc. DS00526E-page 55 AN526 ;-------------------------------------------------------------------------IFDEF __16C55 ; Register Files PORTC EQU H’0007’ __MAXRAM H’01F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16C56 __MAXRAM H’01F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16C57 ; Register Files PORTC EQU H’0007’ __MAXRAM H’07F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16CR57A ; Register Files PORTC EQU H’0007’ __MAXRAM H’07F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16CR57B ; Register Files PORTC EQU H’0007’ __MAXRAM H’07F’ #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------IFDEF __16C58A __MAXRAM H’07F’ #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------IFDEF __16CR58A __MAXRAM H’07F’ #define __CONFIG_1 ENDIF ;========================================================================== ; ; Configuration Bits ; ;========================================================================== IFDEF __CONFIG_0 _CP_ON DS00526E-page 56 EQU H’0FF7’ 1997 Microchip Technology Inc. AN526 _CP_OFF _WDT_ON _WDT_OFF _LP_OSC _XT_OSC _HS_OSC _RC_OSC EQU EQU EQU EQU EQU EQU EQU #undefine __CONFIG_0 ENDIF H’0FFF’ H’0FFF’ H’0FFB’ H’0FFC’ H’0FFD’ H’0FFE’ H’0FFF’ IFDEF __CONFIG_1 _CP_ON _CP_OFF _WDT_ON _WDT_OFF _LP_OSC _XT_OSC _HS_OSC _RC_OSC EQU EQU EQU EQU EQU EQU EQU EQU #undefine __CONFIG_1 ENDIF H’0007’ H’0FFF’ H’0FFF’ H’0FFB’ H’0FFC’ H’0FFD’ H’0FFE’ H’0FFF’ IFDEF __CONFIG_2 _CP_ON _CP_OFF _XT_OSC _RC_OSC EQU EQU EQU EQU #undefine __CONFIG_2 ENDIF H’0FF7’ H’0FFF’ H’0FFD’ H’0FFF’ LIST 1997 Microchip Technology Inc. DS00526E-page 57 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX N:INCLUDE FILE FOR FIXED POINT ROUTINE processor16C71 ; define assembler constants B0 B1 B2 B3 B4 B5 equ equ equ equ equ equ MSB LSB equ 7 equ 0 W equ 0 ; 0 1 2 3 4 5 define special function registers cblock 0x00; page 0 registers INDF,RTCC,PCL,STATUS,FSR,TRISA,TRISB,ZZZZ, ADCON0,ADRES,PCLATH,INTCON endc cblock 0x00; page 1 registers INDF,OPTION,PCL,STATUS,FSR,PORTA,PORTB,ZZZZ, ADCON1,ADRES,PCLATH,INTCON endc ; define beginning of general purpose RAM RAMSTART RAMSTOP equ equ 0x0C 0x2F ; define commonly used bits ; STATUS bit definitions #define_C STATUS,0 #define_DC STATUS,1 #define_Z STATUS,2 #define_PD STATUS,3 #define_TO STATUS,4 #define_RP0 STATUS,5 #define_PA0 STATUS,5 #define_RP1 STATUS,6 #define_PA1 STATUS,6 #define_IRP STATUS,7 #define_PA2 STATUS,7 DS00526E-page 58 1997 Microchip Technology Inc. AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX O: ; 16/8 PIC16 FIXED POINT DIVIDE ROUTINES ; Input: ; Output: quotient AARG/BARG followed by remainder in REM ; All timings are worst case cycle counts ; ; ; ; It is useful to note that the additional routine FXD1507U can be called in a signed divide application in the special case where AARG > 0 and BARG > 0, thereby offering some improvement in performance. ; VERSION 1.5 fixed point arguments in AARG and BARG Routine Clocks Function ; FXD1608S 188 16 bit/8 bit -> 16.08 signed fixed point divide ; FXD1608U 294 16 bit/8 bit -> 16.08 unsigned fixed point divide ; FXD1607U 174 16 bit/7 bit -> 16.07 unsigned fixed point divide ; FXD1507U 166 15 bit/7 bit -> 15.07 unsigned fixed point divide ; ; The above timings are based on the looped macros. If space permits, approximately 41-50 clocks can be saved by using the unrolled macros. list r=dec,x=on,t=off,p=16C71 include <PIC16.INC> ;********************************************************************************************** ;********************************************************************************************** ; Define divide register variables ACC equ 0x0D ; most significant byte of contiguous 4 byte accumulator SIGN equ 0x13 ; save location for sign in MSB TEMP equ 0x19 ; temporary storage ; Define binary operation arguments AARG equ 0x0D ; most significant byte of argument A BARG equ 0x16 ; most significant byte of argument B REM equ 0x11 ; most significant byte of remainder LOOPCOUNT equ 0x14 ; loop counter ; ; ; ( AARG+B0, AARG+B1 ) and ( ACC+B0, ACC+B1) reference the same storage locations, and similarly for ( REM+B0, REM+B1 ) and ( ACC+B4, ACC+B5 ) Note: ;********************************************************************************************** ;********************************************************************************************** ; 16/08 BIT Division Macros 1997 Microchip Technology Inc. DS00526E-page 59 AN526 SDIV1608L ; macro Max Timing: ; Min Timing: ; PM: 42 LOOPS1608A LOOPS1608B 3+5+2+5*11+10+10+6*11+10+2 = 163 clks 3+5+2+5*11+10+10+6*11+10+2 = 163 clks DM: 5 MOVF SUBWF RLF BARG+B0,W REM+B0 ACC+B0 RLF RLF MOVF ADDWF RLF ACC+B0,W REM+B0 BARG+B0,W REM+B0 ACC+B0 MOVLW MOVWF 6 LOOPCOUNT RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPS1608A RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPS1608B BTFSS ADDWF ACC+B1,LSB REM+B0 endm UDIV1608L macro DS00526E-page 60 1997 Microchip Technology Inc. AN526 ; Max Timing: 2+7*12+11+3+7*24+23 = 291 clks ; Min Timing: 2+7*11+10+3+7*17+16 = 227 clks ; PM: 39 LOOPU1608A UOK68A LOOPU1608B UOK68B DM: 7 MOVLW MOVWF 8 LOOPCOUNT RLF RLF MOVF SUBWF ACC+B0,W REM+B0 BARG+B0,W REM+B0 BTFSC GOTO ADDWF BCF RLF _C UOK68A REM+B0 _C ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU1608A CLRF TEMP MOVLW MOVWF 8 LOOPCOUNT RLF RLF RLF MOVF SUBWF CLRF CLRW BTFSS INCFSZ SUBWF ACC+B1,W REM+B0 TEMP BARG+B0,W REM+B0 ACC+B5 BTFSC GOTO MOVF ADDWF CLRF CLRW BTFSC INCFSZ ADDWF _C UOK68B BARG+B0,W REM+B0 ACC+B5 BCF RLF _C ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPU1608B _C ACC+B5,W TEMP _C ACC+B5,W TEMP endm UDIV1607L macro ; Max Timing: 7+6*11+10+10+6*11+10+2 = 171 clks ; Min Timing: 7+6*11+10+10+6*11+10+2 = 171 clks ; PM: 39 DM: 5 RLF RLF 1997 Microchip Technology Inc. ACC+B0,W REM+B0 DS00526E-page 61 AN526 LOOPU1607A LOOPU1607B MOVF SUBWF RLF BARG+B0,W REM+B0 ACC+B0 MOVLW MOVWF 7 LOOPCOUNT RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU1607A RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPU1607B BTFSS ADDWF ACC+B1,LSB REM+B0 endm UDIV1507L macro ; Max Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks ; Min Timing: 3+5+2+5*11+10+10+6*11+10+2 = 163 clks ; PM: 42 DS00526E-page 62 DM: 5 MOVF SUBWF RLF BARG+B0,W REM+B0 ACC+B0 RLF RLF MOVF ADDWF RLF ACC+B0,W REM+B0 BARG+B0,W REM+B0 ACC+B0 1997 Microchip Technology Inc. AN526 LOOPU1507A LOOPU1507B MOVLW MOVWF 6 LOOPCOUNT RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU1507A RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPU1507B BTFSS ADDWF ACC+B1,LSB REM+B0 endm SDIV1608 macro ; Max Timing: 3+5+14*8+2 = 122 clks ; Min Timing: 3+5+14*8+2 = 122 clks ; PM: 122 DM: 4 variable i MOVF SUBWF RLF BARG+B0,W REM+B0 ACC+B0 RLF RLF MOVF ADDWF RLF ACC+B0,W REM+B0 BARG+B0,W REM+B0 ACC+B0 1997 Microchip Technology Inc. DS00526E-page 63 AN526 i = 2 while i < 8 RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 i=i+1 endw RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 i = 9 while i < 16 RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 i=i+1 endw BTFSS ADDWF ACC+B1,LSB REM+B0 endm UDIV1608 macro ; restore = 9/21 clks, nonrestore = 8/14 clks ; Max Timing: 8*9+1+8*21 = 241 clks ; Min Timing: 8*8+1+8*14 = 177 clks ; PM: 241 DM: 6 variable i i = 0 while i < 8 RLF DS00526E-page 64 ACC+B0,W 1997 Microchip Technology Inc. AN526 UOK68#v(i) RLF MOVF SUBWF REM+B0 BARG+B0,W REM+B0 BTFSC GOTO ADDWF BCF RLF _C UOK68#v(i) REM+B0 _C ACC+B0 i=i+1 endw CLRF TEMP i = 8 while i < 16 UOK68#v(i) RLF RLF RLF MOVF SUBWF CLRF CLRW BTFSS INCFSZ SUBWF ACC+B1,W REM+B0 TEMP BARG+B0,W REM+B0 ACC+B5 BTFSC GOTO MOVF ADDWF CLRF CLRW BTFSC INCFSZ ADDWF _C UOK68#v(i) BARG+B0,W REM+B0 ACC+B5 BCF RLF _C ACC+B1 _C ACC+B5,W TEMP _C ACC+B5,W TEMP i=i+1 endw endm UDIV1607 macro ; Max Timing: 5+15*8+2 = 127 clks ; Min Timing: 5+15*8+2 = 127 clks ; PM: 127 DM: 4 variable i RLF RLF MOVF SUBWF RLF ACC+B0,W REM+B0 BARG+B0,W REM+B0 ACC+B0 i = 1 1997 Microchip Technology Inc. DS00526E-page 65 AN526 while i < 8 RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 i=i+1 endw RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 i = 9 while i < 16 RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 i=i+1 endw BTFSS ADDWF ACC+B1,LSB REM+B0 endm UDIV1507 macro ; Max Timing: 3+5+14*8+2 = 122 clks ; Min Timing: 3+5+14*8+2 = 122 clks ; PM: 122 DM: 4 variable i DS00526E-page 66 MOVF SUBWF RLF BARG+B0,W REM+B0 ACC+B0 RLF RLF MOVF ADDWF RLF ACC+B0,W REM+B0 BARG+B0,W REM+B0 ACC+B0 1997 Microchip Technology Inc. AN526 i = 2 while i < 8 RLF RLF MOVF ACC+B0,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B0 i=i+1 endw RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B0,LSB REM+B0 ACC+B0,LSB REM+B0 ACC+B1 i = 9 while i < 16 RLF RLF MOVF ACC+B1,W REM+B0 BARG+B0,W BTFSC SUBWF BTFSS ADDWF RLF ACC+B1,LSB REM+B0 ACC+B1,LSB REM+B0 ACC+B1 i=i+1 endw BTFSS ADDWF ACC+B1,LSB REM+B0 endm ;********************************************************************************************** ;********************************************************************************************** ; 16/8 Bit Signed Fixed Point Divide 16/8 -> 16.08 ; ; Input: 16 bit signed fixed point dividend in AARG+B0, AARG+B1 8 bit signed fixed point divisor in BARG+B0 ; Use: CALL ; ; Output: 16 bit signed fixed point quotient in AARG+B0, AARG+B1 8 bit signed fixed point remainder in REM+B0 ; Result: AARG, REM ; Max Timing: FXD1608S <— AARG / BARG 10+163+3 = 176 clks 1997 Microchip Technology Inc. A > 0, B > 0 DS00526E-page 67 AN526 ; ; ; 11+163+11 = 185 clks 14+163+11 = 188 clks 15+163+3 = 181 clks ; ; ; ; Min Timing: ; PM: 15+42+10 = 67 FXD1608S CA1608S C1608S 10+163+3 = 176 clks A > 0, B > 0 11+163+11 = 185 clks 14+163+11 = 188 clks 15+163+3 = 181 clks A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 DM: 6 MOVF XORWF MOVWF AARG+B0,W BARG+B0,W SIGN BTFSS GOTO BARG+B0,MSB CA1608S COMF INCF BARG+B0 BARG+B0 BTFSS GOTO AARG+B0,MSB C1608S COMF INCF BTFSC DECF COMF AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 CLRF REM+B0 ; if MSB set go & negate BARG ; if MSB set go & negate ACCa SDIV1608L BTFSS RETLW SIGN,MSB 0x00 COMF INCF BTFSC DECF COMF AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 COMF INCF REM+B0 REM+B0 RETLW 0x00 ; negate (ACCc,ACCd) ;********************************************************************************************** ;********************************************************************************************** ; 16/8 Bit Unsigned Fixed Point Divide 16/8 -> 16.08 ; ; Input: 16 bit unsigned fixed point dividend in AARG+B0, AARG+B1 16 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 16 bit unsigned fixed point quotient in AARG+B0, AARG+B1 16 bit unsigned fixed point remainder in REM+B0 ; Result: AARG, REM ; Max Timing: 1+291+2 = 294 clks ; Min Timing: 1+227+2 = 230 clks DS00526E-page 68 FXD1608U <— AARG / BARG 1997 Microchip Technology Inc. AN526 ; PM: 1+39+1 = 41 FXD1608U DM: 7 CLRF REM+B0 UDIV1608L RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; 16/7 Bit Unsigned Fixed Point Divide 16/7 -> 16.07 ; ; Input: 16 bit unsigned fixed point dividend in AARG+B0, AARG+B1 7 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 16 bit unsigned fixed point quotient in AARG+B0, AARG+B1 7 bit unsigned fixed point remainder in REM+B0 ; Result: AARG, REM ; Max Timing: 1+171+2 = 174 clks ; Min Timing: 1+171+2 = 174 clks ; PM: 1+39+1 = 41 FXD1607U FXD1607U <— AARG / BARG DM: 5 CLRF REM+B0 UDIV1607L RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; 15/7 Bit Unsigned Fixed Point Divide 15/7 -> 15.07 ; ; Input: 15 bit unsigned fixed point dividend in AARG+B0, AARG+B1 7 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 15 bit unsigned fixed point quotient in AARG+B0, AARG+B1 7 bit unsigned fixed point remainder in REM+B0 ; Result: AARG, REM ; Max Timing: 1+163+2 = 166 clks ; Min Timing: 1+163+2 = 166 clks ; PM: 1+42+1 = 44 FXD1507U FXD1507U CLRF <— AARG / BARG DM: 5 REM+B0 UDIV1507L RETLW 0x00 END ;********************************************************************************************** ;********************************************************************************************** 1997 Microchip Technology Inc. DS00526E-page 69 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX P:16/16 FIXED POINT DIVIDE ROUTINES ; 16/16 PIC16 FIXED POINT DIVIDE ROUTINES VERSION 1.5 ; Input: ; Output: quotient AARG/BARG followed by remainder in REM ; All timings are worst case cycle counts ; ; ; ; It is useful to note that the additional routine FXD1515U can be called in a signed divide application in the special case where AARG > 0 and BARG > 0, thereby offering some improvement in performance. ; fixed point arguments in AARG and BARG Routine Clocks Function ; FXD1616S 319 16 bit/16 bit -> 16.16 signed fixed point divide ; FXD1616U 373 16 bit/16 bit -> 16.16 unsigned fixed point divide ; FXD1515U 294 15 bit/15 bit -> 15.15 unsigned fixed point divide ; ; The above timings are based on the looped macros. If space permits, approximately 65-69 clocks can be saved by using the unrolled macros. list r=dec,x=on,t=off,p=16C71 include <PIC16.INC> ;********************************************************************************************** ;********************************************************************************************** ; Define divide register variables ACC equ 0x0D ; most significant byte of contiguous 4 byte accumulator SIGN equ 0x13 ; save location for sign in MSB TEMP equ 0x19 ; temporary storage ; Define binary operation arguments AARG equ 0x0D ; most significant byte of argument A BARG equ 0x16 ; most significant byte of argument B REM equ 0x11 ; most significant byte of remainder LOOPCOUNT equ 0x14 ; loop counter ; ; ; ( AARG+B0, AARG+B1 ) and ( ACC+B0, ACC+B1) reference the same storage locations, and similarly for ( REM+B0, REM+B1 ) and ( ACC+B4, ACC+B5 ) Note: ;********************************************************************************************** ;********************************************************************************************** ; 16/16 Bit Division Macros DS00526E-page 70 1997 Microchip Technology Inc. AN526 SDIV1616L macro ; Max Timing: 13+14*18+17+8 = 290 clks ; Min Timing: 13+14*16+15+3 = 255 clks ; PM: 42 DM: 7 RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B1 ACC+B0 MOVLW MOVWF 15 LOOPCOUNT RLF RLF RLF MOVF ACC+B0,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B1,LSB SADD66L SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66LL SADD66L ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66LL RLF RLF ACC+B1 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPS1616 BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B1,LSB SOK66L BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 LOOPS1616 SOK66L endm UDIV1616L ; macro restore = 23 clks, 1997 Microchip Technology Inc. nonrestore = 17 clks DS00526E-page 71 AN526 ; Max Timing: 2+15*23+22 = 369 clks ; Min Timing: 2+15*17+16 = 273 clks ; PM: 24 LOOPU1616 UOK66LL DM: 7 MOVLW MOVWF 16 LOOPCOUNT RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF _C UOK66LL BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 BCF _C RLF RLF ACC+B1 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU1616 endm UDIV1515L macro ; Max Timing: 13+14*18+17+8 = 290 clks ; Min Timing: 13+14*17+16+3 = 270 clks ; PM: 42 LOOPU1515 DS00526E-page 72 DM: 7 RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF RLF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B1 ACC+B0 MOVLW MOVWF 15 LOOPCOUNT RLF RLF RLF MOVF ACC+B0,W REM+B1 REM+B0 BARG+B1,W 1997 Microchip Technology Inc. AN526 BTFSS GOTO ACC+B1,LSB UADD55L SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55LL UADD55L ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55LL RLF RLF ACC+B1 ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU1515 BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B1,LSB UOK55L BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55L endm SDIV1616 macro ; Max Timing: 7+10+6*14+14+7*14+8 = 221 clks ; Min Timing: 7+10+6*13+13+7*13+3 = 202 clks ; PM: 7+10+6*18+18+7*18+8 = 277 DM: 6 variable i MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 RLF RLF RLF MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RLF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 i = 2 while i < 8 1997 Microchip Technology Inc. DS00526E-page 73 AN526 RLF RLF RLF MOVF ACC+B0,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B0,LSB SADD66#v(i) SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66#v(i) SADD66#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66#v(i) RLF ACC+B0 i=i+1 endw RLF RLF RLF MOVF ACC+B1,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B0,LSB SADD668 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK668 SADD668 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK668 RLF ACC+B1 i = 9 while i < 16 DS00526E-page 74 RLF RLF RLF MOVF ACC+B1,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B1,LSB SADD66#v(i) SUBWF MOVF BTFSS REM+B1 BARG+B0,W _C 1997 Microchip Technology Inc. AN526 INCFSZ SUBWF GOTO BARG+B0,W REM+B0 SOK66#v(i) SADD66#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66#v(i) RLF ACC+B1 i=i+1 endw BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B1,LSB SOK66 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK66 endm UDIV1616 macro ; restore = 20 clks, ; Max Timing: 16*20 = 320 clks ; Min Timing: 16*14 = 224 clks ; PM: 16*20 = 320 variable nonrestore = 14 clks DM: 6 i i = 0 while i < 16 UOK66#v(i) RLF RLF RLF MOVF SUBWF MOVF BTFSS INCFSZ SUBWF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 BTFSC GOTO MOVF ADDWF MOVF BTFSC INCFSZ ADDWF _C UOK66#v(i) BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 BCF _C RLF ACC+B1 1997 Microchip Technology Inc. DS00526E-page 75 AN526 RLF ACC+B0 i=i+1 endw endm UDIV1515 macro ; Max Timing: 7+10+6*14+14+7*14+8 = 221 clks ; Min Timing: 7+10+6*13+13+7*13+3 = 202 clks ; PM: 7+10+6*18+18+7*18+8 = 277 DM: 6 variable i MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 RLF RLF RLF MOVF ADDWF MOVF BTFSC INCFSZ ADDWF RLF ACC+B0,W REM+B1 REM+B0 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 i = 2 while i < 8 RLF RLF RLF MOVF ACC+B0,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B0,LSB UADD55#v(i) SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55#v(i) UADD55#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55#v(i) RLF ACC+B0 i=i+1 DS00526E-page 76 1997 Microchip Technology Inc. AN526 endw RLF RLF RLF MOVF ACC+B1,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B0,LSB UADD558 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK558 UADD558 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK558 RLF ACC+B1 i = 9 while i < 16 RLF RLF RLF MOVF ACC+B1,W REM+B1 REM+B0 BARG+B1,W BTFSS GOTO ACC+B1,LSB UADD55#v(i) SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55#v(i) UADD55#v(i) ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55#v(i) RLF ACC+B1 i=i+1 endw BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B1,LSB UOK55 BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK55 1997 Microchip Technology Inc. DS00526E-page 77 AN526 endm ;********************************************************************************************** ;********************************************************************************************** ; 16/16 Bit Signed Fixed Point Divide 16/16 -> 16.16 ; ; Input: 16 bit fixed point dividend in AARG+B0, AARG+B1 16 bit fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 16 bit fixed point quotient in AARG+B0, AARG+B1 16 bit fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; ; ; ; Max Timing: ; ; ; ; Min Timing: ; PM: 19+42+13 = 74 FXD1616S CA1616S C1616S FXD1616S <— AARG / BARG 11+290+3 = 304 clks A > 0, B > 0 15+290+14 = 319 clks 15+290+14 = 319 clks 19+290+3 = 312 clks A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 11+255+3 = 269 clks A > 0, B > 0 15+255+14 = 284 clks 15+255+14 = 284 clks 19+255+3 = 277 clks A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 DM: 8 MOVF XORWF MOVWF BTFSS GOTO AARG+B0,W BARG+B0,W SIGN BARG+B0,MSB CA1616S COMF INCF BTFSC DECF COMF BARG+B1 BARG+B1 _Z BARG+B0 BARG+B0 BTFSS GOTO AARG+B0,MSB C1616S COMF INCF BTFSC DECF COMF AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 CLRF CLRF REM+B0 REM+B1 ; if MSB set go & negate BARG ; if MSB set go & negate ACCa SDIV1616L DS00526E-page 78 BTFSS RETLW SIGN,MSB 0x00 COMF INCF BTFSC DECF COMF AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 COMF REM+B1 ; negate (ACCc,ACCd) 1997 Microchip Technology Inc. AN526 INCF BTFSC DECF COMF REM+B1 _Z REM+B0 REM+B0 RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; 16/16 Bit Unsigned Fixed Point Divide 16/16 -> 16.16 ; ; Input: 16 bit unsigned fixed point dividend in AARG+B0, AARG+B1 16 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 16 bit unsigned fixed point quotient in AARG+B0, AARG+B1 16 bit unsigned fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; Max Timing: 2+369+2 = 373 clks ; Min Timing: 2+273+2 = 277 clks ; PM: 2+24+1 = 27 FXD1616U FXD1616U <— AARG / BARG DM: 7 CLRF CLRF REM+B0 REM+B1 UDIV1616L RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; 15/15 Bit Unsigned Fixed Point Divide 15/15 -> 15.15 ; ; Input: 15 bit unsigned fixed point dividend in AARG+B0, AARG+B1 15 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 15 bit unsigned fixed point quotient in AARG+B0, AARG+B1 15 bit unsigned fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; Max Timing: 2+290+2 = 294 clks ; Min Timing: 2+270+2 = 274 clks ; PM: 2+42+1 = 45 FXD1515U FXD1515U CLRF CLRF <— AARG / BARG DM: 7 REM+B0 REM+B1 UDIV1515L RETLW 0x00 END ;********************************************************************************************** ;********************************************************************************************** 1997 Microchip Technology Inc. DS00526E-page 79 AN526 Please check the Microchip BBS for the latest version of the source code. Microchip’s Worldwide Web Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership not required). APPENDIX Q:32/16 FIXED POINT DIVIDE ROUTINES ; 32/16 PIC16 FIXED POINT DIVIDE ROUTINES VERSION 1.5 ; Input: ; Output: quotient AARG/BARG followed by remainder in REM ; All timings are worst case cycle counts ; ; ; ; It is useful to note that the additional routine FXD3115U can be called in a signed divide application in the special case where AARG > 0 and BARG > 0, thereby offering some improvement in performance. ; fixed point arguments in AARG and BARG Routine Clocks Function ; FXD3216S 578 32 bit/16 bit -> 32.16 signed fixed point divide ; FXD3216U 702 32 bit/16 bit -> 32.16 unsigned fixed point divide ; FXD3115U 541 31 bit/15 bit -> 31.15 unsigned fixed point divide list r=dec,x=on,t=off,p=16C71 include <PIC16.INC> ;********************************************************************************************** ;********************************************************************************************** ; Define divide register variables ACC equ 0x0D ; most significant byte of contiguous 4 byte accumulator SIGN equ 0x13 ; save location for sign in MSB TEMP equ 0x19 ; temporary storage ; Define binary operation arguments AARG equ 0x0D ; most significant byte of argument A BARG equ 0x16 ; most significant byte of argument B REM equ 0x11 ; most significant byte of remainder LOOPCOUNT equ 0x14 ; loop counter ; ; ; ( AARG+B0, AARG+B1 ) and ( ACC+B0, ACC+B1) reference the same storage locations, and similarly for ( REM+B0, REM+B1 ) and ( ACC+B4, ACC+B5 ) Note: ;********************************************************************************************** ;********************************************************************************************** ; 32/16 Bit Division Macros SDIV3216L ; macro Max Timing: DS00526E-page 80 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks 1997 Microchip Technology Inc. AN526 ; Min Timing: ; PM: 157 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks DM: 9 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B0,W REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB SADD26LA SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LA SADD26LA ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LA RLF ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPS3216A RLF RLF RLF MOVF BTFSS GOTO ACC+B1,W REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB SADD26L8 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L8 SADD26L8 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L8 RLF ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF ACC+B1,W LOOPS3216A LOOPS3216B 1997 Microchip Technology Inc. DS00526E-page 81 AN526 RLF RLF MOVF BTFSS GOTO REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB SADD26LB SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LB SADD26LB ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LB RLF ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPS3216B RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB SADD26L16 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L16 SADD26L16 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L16 RLF ACC+B2 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB SADD26LC SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LC ADDWF MOVF BTFSC REM+B1 BARG+B0,W _C LOOPS3216C SADD26LC DS00526E-page 82 1997 Microchip Technology Inc. AN526 INCFSZ ADDWF BARG+B0,W REM+B0 RLF ACC+B2 DECFSZ GOTO LOOPCOUNT LOOPS3216C RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB SADD26L24 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L24 SADD26L24 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26L24 RLF ACC+B3 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B3,LSB SADD26LD SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LD SADD26LD ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LD RLF ACC+B3 DECFSZ GOTO LOOPCOUNT LOOPS3216D BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B3,LSB SOK26L BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SOK26LC LOOPS3216D 1997 Microchip Technology Inc. DS00526E-page 83 AN526 SOK26L endm UDIV3216L macro ; Max Timing: 15+6*22+21+21+6*22+21+21+6*22+21+21+6*22+21+8 = 698 clks ; Min Timing: 15+6*21+20+20+6*21+20+20+6*21+20+20+6*21+20+3 = 662 clks ; PM: 233 LOOPU3216A UADD26LA UOK26LA DS00526E-page 84 DM: 11 CLRF TEMP MOVF SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF RLF BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B0,W REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB UADD26LA SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN RLF ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU3216A RLF ACC+B1,W _C SIGN,W TEMP ACC+B0 _C SIGN,W TEMP UOK26LA _C SIGN,W TEMP 1997 Microchip Technology Inc. AN526 UADD26L8 UOK26L8 LOOPU3216B UADD26LB UOK26LB RLF RLF MOVF BTFSS GOTO REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB UADD26L8 SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN RLF ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B1,W REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB UADD26LB SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN RLF ACC+B1 1997 Microchip Technology Inc. _C SIGN,W TEMP UOK26L8 _C SIGN,W TEMP _C SIGN,W TEMP UOK26LB _C SIGN,W TEMP DS00526E-page 85 AN526 UADD26L16 UOK26L16 LOOPU3216C UADD26LC DS00526E-page 86 DECFSZ GOTO LOOPCOUNT LOOPU3216B RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB UADD26L16 SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN RLF ACC+B2 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB UADD26LC SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN _C SIGN,W TEMP UOK26L16 _C SIGN,W TEMP _C SIGN,W TEMP UOK26LC _C SIGN,W 1997 Microchip Technology Inc. AN526 UOK26LC UADD26L24 UOK26L24 LOOPU3216D UADD26LD ADDWF TEMP RLF ACC+B2 DECFSZ GOTO LOOPCOUNT LOOPU3216C RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB UADD26L24 SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF CLRF CLRW BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN RLF ACC+B3 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B3,LSB UADD26LD SUBWF MOVF BTFSS INCFSZ SUBWF CLRF CLRW BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 SIGN ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 1997 Microchip Technology Inc. _C SIGN,W TEMP UOK26L24 _C SIGN,W TEMP _C SIGN,W TEMP UOK26LD DS00526E-page 87 AN526 UOK26LD CLRF CLRW BTFSC INCFSZ ADDWF SIGN RLF ACC+B3 DECFSZ GOTO LOOPCOUNT LOOPU3216D BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B3,LSB UOK26L BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 _C SIGN,W TEMP UOK26L endm UDIV3115L macro ; Max Timing: 9+6*17+16+16+6*17+16+16+6*17+16+16+6*17+16+8 = 537 clks ; Min Timing: 9+6*16+15+15+6*16+15+15+6*16+15+15+6*16+15+3 = 501 clks ; PM: 157 DM: 9 MOVF SUBWF MOVF BTFSS INCFSZ SUBWF RLF BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 ACC+B0 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B0,W REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB UADD15LA SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LA UADD15LA ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LA RLF ACC+B0 DECFSZ GOTO LOOPCOUNT LOOPU3115A LOOPU3115A DS00526E-page 88 1997 Microchip Technology Inc. AN526 RLF RLF RLF MOVF BTFSS GOTO ACC+B1,W REM+B1 REM+B0 BARG+B1,W ACC+B0,LSB UADD15L8 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L8 UADD15L8 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L8 RLF ACC+B1 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B1,W REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB UADD15LB SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LB UADD15LB ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LB RLF ACC+B1 DECFSZ GOTO LOOPCOUNT LOOPU3115B RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B1,LSB UADD15L16 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L16 ADDWF REM+B1 LOOPU3115B UADD15L16 1997 Microchip Technology Inc. DS00526E-page 89 AN526 MOVF BTFSC INCFSZ ADDWF BARG+B0,W _C BARG+B0,W REM+B0 RLF ACC+B2 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B2,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB UADD15LC SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LC UADD15LC ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LC RLF ACC+B2 DECFSZ GOTO LOOPCOUNT LOOPU3115C RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B2,LSB UADD15L24 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L24 UADD15L24 ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L24 RLF ACC+B3 MOVLW MOVWF 7 LOOPCOUNT RLF RLF RLF MOVF BTFSS GOTO ACC+B3,W REM+B1 REM+B0 BARG+B1,W ACC+B3,LSB UADD15LD UOK15L16 LOOPU3115C LOOPU3115D DS00526E-page 90 1997 Microchip Technology Inc. AN526 SUBWF MOVF BTFSS INCFSZ SUBWF GOTO REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LD UADD15LD ADDWF MOVF BTFSC INCFSZ ADDWF REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15LD RLF ACC+B3 DECFSZ GOTO LOOPCOUNT LOOPU3115D BTFSC GOTO MOVF ADDWF MOVF BTFSC INCF ADDWF ACC+B3,LSB UOK15L BARG+B1,W REM+B1 BARG+B0,W _C BARG+B0,W REM+B0 UOK15L endm ;********************************************************************************************** ;********************************************************************************************** ; 32/16 Bit Signed Fixed Point Divide 32/16 -> 32.16 ; ; Input: 32 bit fixed point dividend in AARG+B0, AARG+B1,AARG+B2,AARG+B3 16 bit fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 32 bit fixed point quotient in AARG+B0, AARG+B1,AARG+B2,AARG+B3 16 bit fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; ; ; ; Max Timing: ; ; ; ; Min Timing: ; PM: 25+157+19 = 201 FXD3216S FXD3216S <— AARG / BARG 11+537+3 = 551 clks A > 0, B > 0 15+537+20 = 572 clks 21+537+20 = 578 clks 25+537+3 = 565 clks A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 11+501+3 = 515 clks A > 0, B > 0 15+501+20 = 536 clks 21+501+20 = 542 clks 25+501+3 = 529 clks A > 0, B < 0 A < 0, B > 0 A < 0, B < 0 DM: 10 MOVF XORWF MOVWF BTFSS GOTO AARG+B0,W BARG+B0,W SIGN BARG+B0,MSB CA3216S COMF INCF BARG+B1 BARG+B1 1997 Microchip Technology Inc. ; if MSB set go & negate BARG DS00526E-page 91 AN526 CA3216S C3216S BTFSC DECF COMF _Z BARG+B0 BARG+B0 BTFSS GOTO AARG+B0,MSB C3216S COMF INCF BTFSC DECF COMF BTFSC DECF COMF BTFSC DECF COMF AARG+B3 AARG+B3 _Z AARG+B2 AARG+B2 _Z AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 CLRF CLRF REM+B0 REM+B1 ; if MSB set go & negate ACCa SDIV3216L BTFSS RETLW SIGN,MSB 0x00 COMF INCF BTFSC DECF COMF BTFSC DECF COMF BTFSC DECF COMF AARG+B3 AARG+B3 _Z AARG+B2 AARG+B2 _Z AARG+B1 AARG+B1 _Z AARG+B0 AARG+B0 COMF INCF BTFSC DECF COMF REM+B1 REM+B1 _Z REM+B0 REM+B0 RETLW 0x00 ; negate (ACCc,ACCd) ;********************************************************************************************** ;********************************************************************************************** ; 32/16 Bit Unsigned Fixed Point Divide 32/16 -> 32.16 ; ; Input: 32 bit unsigned fixed point dividend in AARG+B0, AARG+B1,AARG+B2,AARG+B3 16 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 32 bit unsigned fixed point quotient in AARG+B0, AARG+B1,AARG+B2,AARG+B3 16 bit unsigned fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; Max Timing: 2+698+2 = 702 clks ; Max Timing: 2+662+2 = 666 clks DS00526E-page 92 FXD3216U <— AARG / BARG 1997 Microchip Technology Inc. AN526 ; PM: 2+233+1 = 236 FXD3216U DM: 11 CLRF CLRF REM+B0 REM+B1 UDIV3216L RETLW 0x00 ;********************************************************************************************** ;********************************************************************************************** ; 31/15 Bit Unsigned Fixed Point Divide 31/15 -> 31.15 ; ; Input: 31 bit unsigned fixed point dividend in AARG+B0, AARG+B1,AARG+B2,AARG+B3 15 bit unsigned fixed point divisor in BARG+B0, BARG+B1 ; Use: CALL ; ; Output: 31 bit unsigned fixed point quotient in AARG+B0, AARG+B1,AARG+B2,AARG+B3 15 bit unsigned fixed point remainder in REM+B0, REM+B1 ; Result: AARG, REM ; Max Timing: 2+537+2 = 541 clks ; Min Timing: 2+501+2 = 505 clks ; PM: 2+157+1 = 160 FXD3115U FXD3115U CLRF CLRF <— AARG / BARG DM: 9 REM+B0 REM+B1 UDIV3115L RETLW 0x00 END ;********************************************************************************************** ;********************************************************************************************** 1997 Microchip Technology Inc. DS00526E-page 93 Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. 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