Freescale Semiconductor Technical Data MM908E624 Internal Rev 4.0, 12/2004 Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers 908E624 TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN The 908E624 is an integrated single-package solution that includes a high-performance HC08 microcontroller with a SMARTMOSTM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI) (only internal), and an internal clock generator module. The analog control die provides three high-side outputs with diagnostic functions, voltage regulator, watchdog, operational amplifier, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive high-current motors applications using relays (e.g., window lifts, fans, and sun roofs). Features • High-Performance M68HC908EY16 Core • 16 K Bytes of On-Chip Flash Memory • 512 Bytes of RAM • Internal Clock Generator Module • Two 16-Bit, 2-Channel Timers • 10-Bit Analog-to-Digital Converter (ADC) • LIN Physical Layer Interface • Low Dropout Voltage Regulator • Three High-Side Outputs • Two Wake-Up Inputs • 16 Microcontroller I/Os DW SUFFIX 98ASA99294D 54-TERMINAL SOICW ORDERING INFORMATION Device Temperature Range (TA) Package MM908E624ACDWB/R -40°C to 85°C 54 SOICW VBAT VSUP1 LIN Interface +5.0 V VSUP2 LIN VREFH VDDA EVDD VCC VDD VREFL VSSA EVSS AGND GND HS3 L1 L2 HS1 RxD PTE1/RxD RSTB RSTB_A IRQB IRQB_A M HS2 +E PTD0/TACH0 PWMin Microcontroller Ports PTA0−4 PTB1;3−7 PTC2−4 PTD1/TACH1 To Microcontroller A/D Channel OUT -E WDCONF Figure 1. 908E624 Simplified Application Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2004. All rights reserved. VSS VDD VSSA VREFL VDDA VREFH IRQ RST OSC1 OSC2 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6/TBCH0 PTB7/AD7/TBCH1 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTA5/SPSCK PTA6/SS Security Module Power-On Reset Module POWER 10 Bit Analog-to-Digital Converter Module Single External IRQ Module 24 Internal System Integration Module Internal Clock Generator Module User Flash Vector Space, 36 Bytes PTE1/RXD MCU Die PTA5/SPSCK PTC1/MOSI PTC0/MISO PTA6/SS PTE0/TXD SPSCK MOSI MISO SS TXD VSUP1 SPI & Mode Control Reset Control Module Window Watchdog LIN Physical Layer Analog Die RXD Figure 2. 908E624 Simplified Internal Block PTE0/TxD PTE1/RxD PTD0/TACH0 PTD1/TACH1 PTC0/MISO PTC1/MOSI PTC2/MCLK PTC3/OSC2 PTC4/OSC1 BEMF Module Prescaler Module Arbiter Module Periodic Wakeup Timebase Module Configuration Register Module Serial Pheripheral Interface Module Computer Operating Properly Module Enhanced Serial Communication Interface Module 2-channel Timer Interface Module B 2-channel Timer Interface Module A 5-Bit Keyboard Interrupt Module Single Breakpoint Break Module PWMIN PWMIN Amplifier Wake Up Input 2 Wake Up Input 1 High Side Driver & Diagnostic High Side Driver & Diagnostic High Side Driver & Diagnostic Voltage Regulator VSUP2 FLSVPP PTD1/TACH1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 FLASH programming (burn in) ROM, 1024 Bytes Monitor ROM, 310 Bytes User RAM, 512 Bytes User Flash, 15,872 Bytes Control and Status Register, 64 Bytes ALU PORT A 2 CPU Registers VDDA PTA1/KBD1 EVDD PORT B PTA0/KBD0 EVSS Internal Bus VSSA DDRC VREFL DDRA RST DDRB PTD0/TACH0 PORT C LIN DDRD PWMIN PORT D VSUP1 DDRE VSUP2 VSUP2 VSUP2 GND PORT E WDCONF M68HC08 CPU OUT -E +E VCC L2 L1 HS3 HS2 HS1 VDD Internal Block Diagram INTERNAL BLOCK DIAGRAM AGND RST_A IRQ_A IRQ VREFH 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor Terminal Connections TERMINAL CONNECTIONS PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 54 2 53 3 52 4 51 5 50 6 49 7 48 8 47 9 46 10 45 11 44 12 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 33 23 32 24 31 25 30 26 29 27 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 Figure 3. Terminal Connections Table 1. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17. Die Terminal Terminal Name Formal Name Definition MCU 1 2 6 7 8 11 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 Port B I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 3 4 5 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK Port C I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. MCU 9 IRQ External Interrupt Input MCU 10 RST External Reset MCU 12 13 PTD0/TACH0 PTD1/TACH1 Port D I/Os These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. — 14, 15, 16, 20, 21, 22, 32, 41 NC No Connect Not connected. MCU 42 PTE1/RXD Port E I/O This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Terminal Connections Table 1. Terminal Definitions (continued) A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 17. Die Terminal Terminal Name Formal Name Definition MCU 43 48 VREFL VREFH ADC References These terminals are the reference voltage terminals for the analog-todigital converter (ADC). MCU 44 47 VSSA VDDA ADC Supply Terminals These terminals are the power supply terminals for the analog-to-digital converter. MCU 45 46 EVSS EVDD MCU Power Supply Terminals MCU 49 50 52 53 54 PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 Port A I/Os MCU 51 FLSVPP Test Terminal Analog 17 PWMIN Direct High-Side Control Input Analog 18 RST_A Internal Reset Output Analog 19 IRQ_A Internal Interrupt Output This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. Analog 23 24 L1 L2 Wake-Up Inputs These terminals are the wake-up inputs of the analog chip. Analog 25 26 27 HS3 HS2 HS1 High-Side Output These output terminals are low RDS(ON) high-side switches. Analog 31 28 VSUP1 VSUP2 Power Supply Terminals Analog 29 LIN LIN Bus Analog 30 34 GND AGND Power Ground Terminals Analog 33 VDD Voltage Regulator Output Analog 35 VCC Amplifier Power Supply This terminal is the single +5.0 V power supply for the operational amplifier. Analog 36 OUT Amplifier Output This terminal is the output of the operational amplifier. Analog 37 38 -E +E Amplifier Inputs These terminals are the amplifier inverted and non-inverted inputs. Analog 39 WDCONF Watchdog Configuration Terminal This input terminal is for configuration of the watchdog period and allows the disabling of the watchdog. Analog 40 RXD LIN Transceiver Output These terminals are the ground and power supply terminals, respectively. The MCU operates from a single-power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For test purposes only. Do not connect in the application. This terminal allows the enabling and PWM control of the high-side HS1 and HS2 terminals. This terminal is the reset output terminal of the analog die. These terminals are device power supply terminals. This terminal represents the single-wire bus transmitter and receiver. These terminals are device power ground connections. The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This terminal is the output of LIN transceiver. 908E624 4 Analog Integrated Circuit Device Data Freescale Semiconductor Maximum Ratings MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit Analog Chip Supply Voltage under Normal Operation (Steady-State) VSUP(SS) -0.3 to 27 Analog Chip Supply Voltage under Transient Conditions VSUP(PK) -0.3 to 40 VDD -0.3 to 5.5 VIN(ANALOG) -0.3 to VDD +0.3 VIN(MCU) VSS -0.3 to VDD +0.3 All Terminals except VDD, VSS, PTA0:PTA6, PTC0:PTC1 IPIN(1) ±15 PTA0:PTA6, PTC0:PTC1 Terminals IPIN(2) ±25 Maximum Microcontroller VSS Output Current IMVSS 100 mA Maximum Microcontroller VDD Input Current IMVDD 100 mA V +E-E I +E-E -0.3 to 7.0 ±20 VOUT mA -0.3 to VCC +0.3 V ±20 mA Electrical Ratings Supply Voltage MCU Chip Supply Voltage V V Input Terminal Voltage Analog Chip Microcontroller Chip Maximum Microcontroller Current per Terminal mA Current Sense Amplifier Maximum Input Voltage, +E, -E Terminals Maximum Input Current, +E, -E Terminals Maximum Output Voltage, OUT Terminal Maximum Output Current, OUT Terminal IOUT LIN Supply Voltage V Normal Operation (Steady-State) VBUS(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) VBUS(PK) -150 to 100 V L1 and L2 Terminal Voltage Normal Operation with a 33 kΩ resistor (Steady-State) VWAKE(SS) -18 to 40 Transient Input Voltage (per ISO7637 Specification) and with External Components (Figure 4, page 15) VWAKE(PK) -100 to 100 VESD1 ±2000 VESD2 ±100 VESD3 ±500 ESD Voltage Human Body Model (1) Machine Model (2) Charge Device Model (3) V V Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 2. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 Ω). 3. ESD3 testing is performed in accordance with Charge Device Model, Robotic (CZAP = 4.0 pF). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Maximum Ratings Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device. Rating Symbol Value Unit TA -40 to 85 °C TJ(ANALOG) -40 to 150 °C TJ(MCU) -40 to 125 °C TSTG -40 to 150 °C TSOLDER 245 °C RθJA 36 °C/ W Thermal Ratings Operating Ambient Temperature Operating Junction Temperature (4) Analog MCU Storage Temperature Peak Package Reflow Temperature During Solder Mounting (5) Thermal Resistance, Junction to Ambient (6) , (7) Notes 4. Die temperature of analog and MCU is linked via the package. High temperature on analog die can lead to a high MCU temperature. 5. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. All power outputs ON and dissipating equal power. 7. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7. 908E624 6 Analog Integrated Circuit Device Data Freescale Semiconductor Static Electrical Characteristics STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP 5.5 — 18 V VSUPOP — — 27 V Supply Voltage Range Nominal Operating Voltage Functional Operating Voltage (8) Supply Current Range Normal Mode (9) VSUP = 13.5 V, Analog Chip in Normal Mode, MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled Stop Mode (9), (10) VSUP = 13.5 V Sleep Mode (9), (10) IRUN mA — 20 — — 60 75 µA — 35 45 µA 0.4 V ISTOP ISLEEP VSUP = 13.5 V Digital Interface Ratings (Analog Die) Output Terminal RST_A Low-State Output Voltage (IOUT = -1.5 mA) VOL — — High-State Output Current (VOUT > 3.5 V) IOH — 250 — µA IOL_MAX -1.5 — -8.0 mA Low-State Output Voltage (IOUT = -1.5 mA) VOL — — 0.4 High-State Output Voltage (IOUT = 250 µA) VOH 3.85 — — VOL VOH CIN — — 0.4 3.85 — — V — 4.0 — pF — — 1.5 V Pulldown Current Limitation V Output Terminal IRQ_A Output Terminal RXD Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 250 µA) Capacitance (11) V Input Terminal PWMIN Input Logic Low Voltage Input Logic High Voltage Input Current Capacitance (11) Terminal TXD, SS –Pullup Current VIL VIH IIN CIN IPULLUP 3.5 — — V -10 — 10 µA — 4.0 — pF — 40 — µA Notes 8. Device is fully functional. All functions are operating. Overtemperature may occur. 9. Total current (IVSUP1 + IVSUP2) measured at GND terminal. 10. Stop and Sleep mode current will increase if VSUP exceeds 15 V. 11. This parameter is guaranteed by process monitoring but is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit V LVRON 3.6 4.0 4.4 Threshold V LVI 5.7 6.0 6.6 Hysteresis V LVI_HYS — 1.0 — Threshold V HVI 18 19.25 20.5 V Hysteresis V HVI_HYS — 220 — mV 4.75 5.0 5.25 50 110 200 System Resets and Interrupts V Low-Voltage Reset (LVR) Threshold V Low-Voltage Interrupt (LVI) High-Voltage Interrupt (HVI) Voltage Regulator (12) Normal Mode Output Voltage Normal Mode Output Current Limitation (13) Dropout Voltage (14) V V DDRUN 2.0 mA < IDD < 50 mA, 5.5 V < VSUP < 27 V IDDRUN V V DDDROP IDD = 50 mA mA — 0.1 0.2 Stop Mode Output Voltage (15) V DDSTOP 4.75 5.0 5.25 V Stop Mode Regulator Current Limitation IDDSTOP 4.0 8.0 14 mA mV Line Regulation Normal Mode, 5.5 V < VSUP < 27 V, IDD = 10 mA LR RUN — 20 150 Stop Mode, 5.5 V < VSUP < 27 V, IDD = 2.0 mA LR STOP — 10 100 Normal Mode, 1.0 mA < IDD < 50 mA, VSUP = 18 V LD RUN — 40 150 Stop Mode, 1.0 mA < IDD < 5 mA, VSUP = 18 V LD STOP — 40 150 Overtemperature Pre-Warning (Junction) (16) T PRE 120 135 160 Thermal Shutdown Temperature (Junction) (16) T SD 155 170 Load Regulation Temperature Threshold Difference TSD -TPRE Notes 12. 13. 14. 15. 16. mV °C °C ∆ TSD-TPRE °C 20 30 45 Specification with external capacitor 1.0 µF< C < 10 µF and 200 mΩ ≤ ESR ≤ 1.0 Ω. Capacitor value up to 47 µF can be used. Total VDD regulator current. A 5.0 mA current for operational amplifier is included. Digital output supplied from VDD. Measured when voltage has dropped 100 mV below its nominal value. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage specification. This parameter is guaranteed by process monitoring but not production tested 908E624 8 Analog Integrated Circuit Device Data Freescale Semiconductor Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit REXT 10 — 100 kΩ -15 — 15 Window Watchdog Configuration Terminal (WDCONF) External Resistor Range Watchdog Period Accuracy with External Resistor (Excluding Resistor Accuracy) (17) WDCACC % LIN Physical Layer LIN Transceiver Output Level V Recessive State, TXD HIGH, IOUT = 1.0 µA V LIN_REC VSUP -1 — — Dominant State, TXD LOW, 500 Ω External Pullup Resistor V LIN_DOM — — 1.4 Normal Mode Pullup Resistor to VSUP R PU 20 30 60 kΩ Stop, Sleep Mode Pullup Current Source IPU — 2.0 — µA IOV-CUR 50 75 150 mA IOV-DELAY — 10 — µs Output Current Shutdown Threshold Output Current Shutdown Delay Leakage Current to GND µA IBUS VSUP Disconnected, VBUS at 18 V — 1.0 10 Recessive State, VSUP 8.0 V to 18 V, VBUS 8.0 V to 18 V, VBUS ≥ VSUP GND Disconnected, VGND = VSUP, VBUS at -18 V 0 3.0 20 -1.0 — 1.0 LIN Receiver VSUP Receiver Threshold Dominant V BUS_DOM — — 0.4 Receiver Threshold Recessive V BUS_REC 0.6 — — Receiver Threshold Center V BUS_CNT 0.475 0.5 0.525 Receiver Threshold Hysteresis V BUS_HYS — — 0.175 Notes 17. Watchdog timing period calculation formula: PWD = 0.991 * REXT +0.648 (REXT in kΩ and PWD in ms). 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit High-Side Outputs HS1 and HS2 Ω RDS(ON) Switch On Resistance TJ = 25°C, ILOAD = 150 mA, VSUP > 9.0 V — 2.0 2.5 TJ = 125°C, ILOAD = 150 mA, VSUP > 9.0 V — — 4.5 TJ = 125°C, ILOAD = 120 mA, 5.5 V < VSUP > 9.0 V — 3.0 — ILIM 300 — 600 mA THSSD 155 — 190 °C ILEAK — — 10 µA TJ = 25°C, ILOAD = 50 m A, VSUP > 9.0 V — — 7.0 TJ = 125°C, ILOAD = 50 mA, VSUP > 9.0 V — — 10 TJ = 125°C, ILOAD = 30 mA, 5.5 V < VSUP > 9.0 V — — 14 ILIM 60 100 200 mA Overtemperature Shutdown (18), (19) THSSD 155 — 190 °C Leakage Current ILEAK — — 10 µA -6.0 — — Output Current Limit Overtemperature Shutdown (18), (19) Leakage Current High-Side Output HS3 Switch On Resistance Output Current Limitation Output Clamp Voltage Ω RDS(ON) V VCL IOUT = -100 mA Notes 18. This parameter is guaranteed by process monitoring but it is not production tested 19. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI. 908E624 10 Analog Integrated Circuit Device Data Freescale Semiconductor Static Electrical Characteristics Table 3. Static Electrical Characteristics (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VIMC -0.1 — VCC +0.1 V Sense Current Amplifier Rail to Rail Input Voltage V Output Voltage Range Output Current ±1.0 mA VOUT1 0.1 — VCC -0.1 Output Current ±5.0 mA VOUT2 0.3 — VCC -0.3 Input Bias Current IB — — 250 nA Input Offset Current IO -100 — 100 nA Input Offset Voltage VIO -25 — 25 mV Supply Voltage Rejection Ratio (20) SVR 60 — — dB (20) CMR 70 — — dB GBP 1.0 — — MHz SR 0.5 — — V/µs PHMO 40 — — ° OLG — 85 — dB 5.5 V < VSUP < 6.0 V 2.0 2.5 3.0 6.0 V < VSUP < 18 V 2.5 3.0 3.5 18 V < VSUP < 27 V 2.7 3.2 3.7 Common Mode Rejection Ratio Gain Bandwidth (20) Slew Rate Phase Margin (for Gain = 1, Load 100 pF/ /5.0 kΩ (20) Open Loop Gain L1 and L2 Inputs Negative Switching Threshold Positive Switching Threshold VTHN V V VTHP 5.5 V < VSUP < 6.0 V 2.7 3.3 3.8 6.0 V < VSUP < 18 V 3.0 4.0 4.5 18 V < VSUP < 27 V 3.5 4.2 4.7 0.5 — 1.3 Hysteresis Input Current V VHYST 5.5 V < VSUP < 27 V µA IIN -0.2 V < VIN < 40 V -10 — 10 Notes 20. This parameter is guaranteed by process monitoring but is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 11 Dynamic Electrical Characteristics DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Dominant Propagation Delay TXD to LIN t DOM-MIN — — 50 µs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 50 µs Recessive Propagation Delay TXD to LIN t REC-MIN — — 50 µs Recessive Propagation Delay TXD to LIN t REC-MAX — — 50 µs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX dt1 -10.44 — — µs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN dt2 — — 11 µs Dominant Propagation Delay TXD to LIN t DOM-MIN — — 100 µs Dominant Propagation Delay TXD to LIN t DOM-MAX — — 100 µs Recessive Propagation Delay TXD to LIN t REC-MIN — — 100 µs Recessive Propagation Delay TXD to LIN t REC-MAX — — 100 µs Propagation Delay Symmetry: t DOM-MIN - t REC-MAX dt1s -22 — — µs Propagation Delay Symmetry: t DOM-MAX - t REC-MIN dt2s — — 23 µs SRFAST — 15 — V/µs Receiver Dominant Propagation Delay (24) t RL — 3.5 6.0 µs Receiver Recessive Propagation Delay (24) t RH — 3.5 6.0 µs t R-SYM -2.0 — 2.0 µs t PROPWL 35 80 µs t WAKE — — µs LIN Physical Layer Driver Characteristics for Normal Slew Rate (21), (22) Driver Characteristics for Slow Slew Rate (21), (23) Driver Characteristics for Fast Slew Rate LIN High Slew Rate (Programming Mode) Receiver Characteristics and Wake-Up Timings Receiver Propagation Delay Symmetry Bus Wake-Up Deglitcher Bus Wake-Up Event Reported (25) 20 Notes 21. VSUP from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. 22. See Figure 6, page 15. 23. See Figure 7, page 16. 24. Measured between LIN signal threshold VIL or VIH and 50% of RXD signal. 25. t WAKE is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 16. In Sleep mode the VDD rise time is strongly dependent upon the decoupling capacitor at VDD terminal. 908E624 12 Analog Integrated Circuit Device Data Freescale Semiconductor Dynamic Electrical Characteristics Table 4. Dynamic Electrical Characteristics (continued) All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit f SPIOP 0.25 — 4.0 MHz t WUF 8.0 20 38 µs SPI Interface Timing SPI Operating Recommended Frequency L1 AND L2 INPUTS Wake-Up Filter Time (26) Window Watchdog Configuration Terminal (WDCONF) PWD Watchdog Period ms External Resistor REXT = 10 kΩ (1%) — 10.558 External Resistor REXT = 100 kΩ (1%) — 99.748 — Without External Resistor REXT (WDCONF Terminal Open) 97 150 205 — State Machine Timing Reset Low-Level Duration after VDD High t RST 0.65 1.0 1.35 ms Interrupt Low-Level Duration t INT 7.0 10 13 µs NR TOUT 97 150 205 ms t S-HSON — 3.0 10 µs t S-HSOFF — 3.0 10 µs Delay Between Normal Request and Normal Mode After W/D Trigger Command (29) t S-NR2N 6.0 35 70 µs Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode (VDD On and Reset High) t W-SSB 15 40 80 Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI Command t W-SPI 90 — N/A t S-1STSPI 30 — N/A µs t 2SSB 15 — — µs Normal Request Mode Timeout Delay Between SPI Command and HS1/HS2/HS3 Turn On (27) , (28) Delay Between SPI Command and HS1/HS2/HS3 Turn Off (27) , (28) Delay Between Interrupt Pulse and First SPI Command Accepted Minimum Time Between Two Rising Edges on SS Notes 26. 27. 28. 29. µs µs This parameter is guaranteed by process monitoring but is not production tested. Delay between turn-on or turn-off command and high-side on or high-side off, excluding rise or fall time due to external load. Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation. This parameter is guaranteed by process monitoring but it is not production tested. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Microcontroller Parametrics MICROCONTROLLER PARAMETRICS Table 5. Microcontroller For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet. Module Description Core High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Timer Two 16-Bit Timers with 2 Channels (TIM A and TIM B) Flash 16 K Bytes RAM 512 Bytes ADC 10-Bit Analog-to-Digital Converter SPI SPI Module ESCI Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment ICG Internal Clock Generation Module 908E624 14 Analog Integrated Circuit Device Data Freescale Semiconductor Timing Diagrams TIMING DIAGRAMS Transient Pulse Generator LIN, L1, and L2 10 kΩ 10k 1.0 nF 1nF Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b. Figure 4. Test Circuit for Transient Test Pulses VSUP R0 TXD LIN RXD C0 R0 R0 andand C0 C0 Combinations: combinations: • 1.0- 1k kΩOhm and and 1.0 nF 1nF • 600 Ω and nF6.8nF - 660 Ohm6.8 and • 500 Ω and nF10nF - 500 Ohm10and Figure 5. Test Circuit for LIN Timing Measurements TXD t REC-MAX Trec-max VLIN_REC Vrec Tdom-min t DOM-MIN 58.1% Vsup 58.1% VSUP 74.4% Vsup 74.4% VSUP 40% 40%Vsup VSUP LIN 60% Vsup 60% VSUP 42.2% Vsup 42.4% VSUP 28.4% 28.4%Vsup VSUP tTdom-max DOM-MAX Trec-min t REC-MIN RXD t RL TrL t RH TrH Figure 6. LIN Timing Measurements for Normal Slew Rate 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Timing Diagrams TXD t REC-MAX Trec-max VLIN_REC Vrec Tdom-min t DOM-MIN 58.1% Vsup 61.6% VSUP 74.4% Vsup 77.8% VSUP 40% 40%Vsup VSUP LIN 60% Vsup 60% VSUP 42.2% Vsup 38.9% VSUP 28.4% 25.1%Vsup VSUP tTdom-max DOM-MAX Trec-min t REC-MIN RXD t RH t RL TrH TrL Figure 7. LIN Timing Measurements for Slow Slew Rate Vrec VLIN_REC LIN 0.4VSUP 0.4 V SUP Dominant Level Dominant level VDD tTpropWL PROPWL tTwake WAKE Figure 8. Wake-Up Sleep Mode Timing VLIN_REC Vrec LIN 0.4VSUP 0.4 VSUP Dominant Level Dominant level IRQ_A tTpropWL PROPWL tTwake WAKE Figure 9. Wake-Up Stop Mode Timing 908E624 16 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Introduction FUNCTIONAL DESCRIPTION INTRODUCTION The 908E624 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E624 is well suited to perform relay control in applications like window lift, sunroof, etc., via a three-wire LIN bus. The device combines an HC908EY16 MCU core with flash memory together with a SmartMOS IC chip. The SmartMOS IC chip combines power and control in one chip. Power switches are provided on the SmartMOS IC configured as high-side outputs. Other ports are also provided, which include an operational amplifier port and two wake-up terminals. An internal voltage regulator provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables this device to be compatible with three-wire bus systems, where one wire is used for communication, one for battery, and one for ground. FUNCTIONAL TERMINAL DESCRIPTION See Figure 1, 908E624 Simplified Application Diagram, page 1, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. PORT A I/O TERMINALS PORT D I/O TERMINALS PTD1/TACH1 and PTD0/TACH0/BEMF are specialfunction, bidirectional I/O port terminals that can also be programmed to be timer terminals. For details refer to the 68HC908EY16 datasheet. PORT E I/O TERMINAL These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/ SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet. PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally. For details refer to the 68HC908EY16 datasheet. PORT B I/O TERMINALS EXTERNAL INTERRUPT TERMINAL (IRQ) These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. The PTB0/AD0 and PTB2/AD2 terminals are not accessible in this device. For details refer to the 68HC908EY16 datasheet. The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet. PORT C I/O TERMINALS These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet. EXTERNAL RESET TERMINAL (RST) A logic [0] on the RST terminal forces the MCU to a known startup state. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. Important To ensure proper operation, do not add any external pullup resistor. For details refer to the 68HC908EY16 datasheet. MCU POWER SUPPLY TERMINALS (EVDD AND EVSS) EVDD and EVSS are the power supply and ground terminals, respectively. The MCU operates from a singlepower supply. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 17 Functional Description Functional Terminal Description Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet. ADC SUPPLY TERMINALS (VDDA AND VSSA) INTERRUPT TERMINAL (IRQ_A) IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal must be connected to the IRQ terminal of the MCU. WINDOW WATCHDOG CONFIGURATION TERMINAL (WDCONF) VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet. This terminal is the configuration terminal for the internal watchdog. A resistor is connected to this terminal. The resistor value defines the watchdog period. If the terminal is open, the watchdog period is fixed to its default value. The watchdog can be disabled (e.g., for flash programming or software debugging) by connecting this terminal to GND. ADC REFERENCE TERMINALS (VREFL AND VREFH) This VSUP1 power supply terminal supplies the voltage regulator, the internal logic, and LIN transceiver. This VSUP2 power supply terminal is the positive supply for the high-side switches. VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSSA via separate traces. For details refer to the 68HC908EY16 datasheet. POWER SUPPLY TERMINALS (VSUP1 AND VSUP2) POWER GROUND TERMINAL (GND) This terminal is the device ground connection. HIGH-SIDE OUTPUT TERMINALS (HS1 AND HS2) This terminal is for test purposes only. Do not connect in the application. These terminals are high-side switch outputs to drive loads such as relays or lamps. Each switch is protected with overtemperature and current limit (overcurrent). The output has an internal clamp circuitry for inductive load. The HS1 and HS2 outputs are controlled by SPI and have a direct enabled input (PWMIN) for PWM capability. PWMIN TERMINAL HIGH-SIDE OUTPUT TERMINAL (HS3) TEST TERMINAL (FLSVPP) This terminal is the direct PWM input for high-side outputs 1 and 2 (HS1 and HS2). If no PWM control is required, PWMIN must be connected to VDD to enable the HS1 and HS2 outputs. LIN TRANSCEIVER OUTPUT TERMINAL (RXD) This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller’s Enhanced Serial Communications Interface (ESCI) module (RXD terminal). RESET TERMINAL (RST_A) RST_A is the reset output terminal of the analog die and must be connected to the RST terminal of the MCU. Important To ensure proper operation, do not add any external pullup resistor. This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. The switch is protected with overtemperature and current limit (overcurrent). The output is controlled only by SPI. LIN BUS TERMINAL (LIN) The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification. WAKE-UP TERMINALS (L1 AND L2) These terminals are high-voltage capable inputs used to sense external switches and to wake up the device from Sleep or Stop mode. During Normal mode the state of these terminals can be read through SPI. 908E624 18 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Functional Terminal Description SENSE AMPLIFIER TERMINALS (E+, E-, OUT, VCC) These are the terminals of the single-supply sense amplifier. • The E+ and E- input terminals are the non-inverting and inverting inputs of the amplifier, respectively. • The OUT terminal is the output terminal of the current sense amplifier. • The VCC terminal is the +5.0 V single-supply connection. +5.0 V VOLTAGE REGULATOR OUTPUT TERMINAL (VDD) intended to supply the embedded microcontroller. The terminal is protected against shorts to GND with an integrated current limit (temperature shutdown could occur). Important The VDD, EVDD, VDDA, and VREFH terminals must be connected together. VOLTAGE REGULATOR AND SENSE AMPLIFIER GROUND TERMINAL (AGND) The AGND terminal is the ground terminal of the voltage regulator and the Sense Amplifier. Important GND, AGND, VSS, EVSS, VSSA, and VREFL terminals must be connected together. The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Functional Description Functional Device Operation FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES 908E624 ANALOG DIE MODES OF OPERATION Wake-up from Stop mode is initiated by a wake-up interrupt. Wakeup from Sleep mode is done by a reset and the voltage regulator is turned back on. The 908E624 offers three operating modes: Normal (Run), Stop, and Sleep. In Normal mode the device is active and is operating under normal application conditions. The Stop and Sleep modes are low-power modes with wake-up capabilities. In Stop mode the voltage regulator still supplies the MCU with VDD (limited current capability) and in Sleep mode the voltage regulator is turned off (VDD = 0 V). The selection of the different modes is controlled by the MODE1:2 bits in the SPI Control register. Figure 10 describes how transitions are done between the different operating modes and Table 6, page 21, gives an overview of the operating mode. Normal Request Timeout Expired (NR ) TOUT Normal Request timeout expired (NR ) TOUT VVDD Low DD Low VDD High and Normal Request VVDDLow Low DD VVDD LOW (>NR TOUT) Expired DD Low (>NRTOUT) expired and and VSUVLVF =0 =0 Wake-Up (Reset) Wake-Up (Reset) Sleep Command SLEEP Command Sleep Sleep STOPCommand Command Normal WD Failed WD failed Wake-Up Interrupt Wake-Up Interrupt Reset Reset Delay (t Delay VDD High and Reset RST) expired RST) (tExpired WD Disabled WD disabled Power Up WDtrigger Trigger WD Power Down Stop VDD VDD Low Low Legend WD: Watchdog Notes: WD Disabled: Watchdog disabled (WDCONF terminal connected to GND) WD - meansisWatchdog WD Trigger: Watchdog triggered by SPI command means or Watchdog disabled (WDCONF terminal connected to GND) WD Failed:WD No disabled watchdog- trigger trigger occurs in closed window WD trigger – means Watchdog is triggered by SPI command Stop Command: Stop command sent via SPI WD failed – means no Watchdog trigger or trigger occurs in closed window Sleep Command: Sleep command sent via SPI STOP Command - means STOP command sent via SPI Wake-Up: L1 or L2 state change or LIN bus wake-up or SS rising edge SLEEP Command - means SLEEP command send via SPI Wake-Up - means L1 or L2 state change or LIN bus wake up or SS rising edge Figure 10. Operating Modes and Transitions 908E624 20 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Functional Device Operation Table 6. Operating Modes Overview Device Mode Voltage Regulator Wake-Up Capabilities Output Watchdog Function HS1, HS2, and HS3 LIN Interface Sense Amplifier Reset VDD ON N/A LOW Disabled Disabled Recessive only Not active Normal Request VDD ON N/A HIGH 150 ms time out if WD enabled Enabled Transmit and receive Not active Normal (Run) VDD ON N/A HIGH Window WD if enabled Enabled Transmit and receive Active Stop VDD ON with limited current capability LIN wake-up, L1, L2 state change, SS rising edge HIGH Disabled Disabled Recessive state with wake-up capability Not active Sleep VDD OFF LIN wake-up L1, L2 state change LOW Disabled Disabled Recessive state with wake-up capability Not active RST_A INTERRUPTS In Normal (Run) mode the 908E624 has four different interrupt sources. An interrupt pulse on the IRQ_A terminal is generated to report a fault to the MCU. All interrupts are not maskable and cannot be disabled. After an Interrupt the INTSRC bit in the SPI Status register is set, indicating the source of the event. This interrupt source information is only transferred once, and the INTSRC bit is cleared automatically. Low-Voltage Interrupt Low-voltage interrupt (LVI) is related to external supply voltage VSUP1. If this voltage falls below the LVI threshold, it will set the LVF bit in the SPI Status register and an interrupt will be initiated. The LVF bit remains set as long as the Lowvoltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled. High-Voltage Interrupt High-voltage interrupt (HVI) is related to external supply voltage VSUP1. If this voltage rises above the HVI threshold, it will set the HVF bit in the SPI Status register and an interrupt will be initiated. The HVF bit remains set as long as the high-voltage condition is present. During Sleep and Stop mode the low-voltage interrupt circuitry is disabled. After a wake-up interrupt, the INTSRC bit in the Serial Peripheral Interface (SPI) Status register is set, indicating the source of the event. This wake-up source information is only transferred once, and the INTSRC bit is cleared automatically. Figure 11, page 22, describes the Stop/Wake-Up procedure. VOLTAGE REGULATOR TEMPERATURE PREWARNING (VDDT) Voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold, it will set the VDDT bit in the SPI Status register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop mode the voltage regulator temperature prewarning circuitry is disabled. HIGH-SIDE SWITCH THERMAL SHUTDOWN (HSST) The high-side switch thermal shutdown HSST is generated if one of the high-side switches HS1:HS3 is above the HSST threshold, it will shutdown the corresponding Highside switch, set the HSST flag in the SPI Status register and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop mode the high-side switch thermal shutdown circuitry is disabled. Wake-Up Interrupts In Stop mode the IRQ_A terminal reports wake-up events on the L1, L2, or the LIN bus to the MCU. All wake-up interrupts are not maskable and cannot be disabled. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Functional Description Functional Device Operation ANALOG DIE INPUTS/OUTPUTS MCU Power Die These are two high-side switches used to drive loads such as relays or lamps. They are protected with overtemperature and current limit (overcurrent) and include an active internal clamp circuitry for inductive load drive. Control is done using the SPI Control register. PWM capability is offered through the PWMIN input terminal. The high-side switch is turned on if both the HSxON bit in the SPI Control register is set and the PWMIN input is HIGH (refer to Figure 12, page 23). In order to have HS1 on, the PWMIN must be HIGH and bit HS1ON must be set. The same applies to the HS2 output. If no PWM control is required, PWMIN must be connected to the VDD terminal. From Reset initialize operate SPI: 2x STOP Command Switch to VREG low current mode Current Limit (Overcurrent) Protection These high-side switches feature current limit to protect them against overcurrent and short circuit conditions. Overtemperature Protection STOP Wake Up on LIN or L1, L2? IRQ interrupt ? High-Side Output Terminals HS1 and HS2 Assert IRQ If an overtemperature condition occurs on any of the three high-side switches, the faulty switch is turned off and latched off until the HS1 (or HS2 or HS3) bit is set to “1” in the SPI Control register. The failure is reported by the HSST bit in the SPI Control register. Sleep and Stop Mode In Sleep and Stop modes the high-sides are disabled. SPI: reason for interrupt Switch to VREG high current mode operate High-Side Output HS3 This high-side switch can be used to drive small lamps, Hall-effect sensors, or switch pullup resistors. Control is done using the SPI Control register. No direct PWM control is possible on this terminal (refer to Figure 13, page 23). Current Limit (Overcurrent) Protection Figure 11. Stop Mode/Wake-Up Procedure This high-side feature switch feature current limit to protect it against overcurrent and short circuit conditions. Overtemperature Protection If an overtemperature condition occurs on any of the three high-side switches, the faulty switch is turned off and latched off until the HS3 (or HS1 or HS2) bit is set to “1” in the SPI Control register. The failure is reported by the HSST bit in the SPI Control register. Sleep and Stop Mode In Sleep and Stop mode the high-side is disabled. 908E624 22 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Functional Device Operation . PWMIN VSUP2 MODE1:2 HSxON Control On/Off High-Side Driver Status Charge Pump, Current Limit Protection, Overtemperature Protection HSx Figure 12. High-Side HS1 and HS2 Circuitry . MODE1:2 VSUP2 HS3ON Control On/Off High-Side Driver Status Charge Pump, Current Limit Protection, Overtemperature Protection HS3 Figure 13. High-Side HS3 Circuitry WINDOW WATCHDOG The window watchdog is configurable using an external resistor at the WDCONF terminal. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 26). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A terminal and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window. Window closed no watchdog clear allowed Window open for watchdog clear WD timing x 50% WD timing x 50% WD period (PWD) WD timing selected by resistor on WDCONF terminal. Figure 14. Window Watchdog Operation 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Functional Description Functional Device Operation Watchdog Configuration Stop Mode If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: During Stop mode the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. PWD [ms] = 0.991 * REXT [kΩ] + 0.648 Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. VOLTAGE REGULATOR FACTORY TRIMMING AND CALIBRATION The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” (0xFF) state: • 0xFD80:0xFDDF Trim and Calibration Values • 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Current Limit (Overcurrent) Protection The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. Overtemperature Protection The voltage regulator also features an overtemperature protection having an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 datasheet. 908E624 24 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Functional Device Operation LOGIC COMMANDS AND REGISTERS 908E624 SPI INTERFACE AND CONFIGURATION The interface consists of four terminals (see Figure 15): • SS —Slave Select • MOSI—Master-Out Slave-In • MISO—Master-In Slave-Out • SPSCK—Serial Clock A complete data transfer via the SPI consists of 1 byte. The master sends 8 bits of control information and the slave replies with 8 bits of status data. The serial peripheral interface creates the communication link between the microcontroller and the analog die of the 908E624. SS Register write data MOSI D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Register read data MISO D7 D6 D5 D4 D3 SPSCK Read data latch Rising edge of SPSCK Change MISO/MOSI Output Write data latch Falling edge of SPSCK Sample MISO/MOSI Input Figure 15. SPI Protocol During the inactive phase of the SS (High), the new data transfer is prepared. The falling edge of the SS indicates the start of a new data transfer and puts the MISO in the low-impedance state and latches the analog status data (Register read data). With the rising edge of the SPI clock, SPSCK the data is moved to MISO/MOSI terminals. With the falling edge of the SPI clock SPSCK the data is sampled by the Receiver. The data transfer is only valid if exactly 8 sample clock edges are present in the active (low) phase of SS. The rising edge of the slave select SS indicates the end of the transfer and latches the write data (MOSI) into the register The SS high forces MISO to the high impedance state. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 25 Functional Description Functional Device Operation SPI REGISTER OVERVIEW Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition. . Table 7. SPI Register Overview Bit Read/Write Information D7 D6 D5 D4 D3 D2 D1 D0 Write LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 Read INTSRC (30) LINWU or LINFAIL HVF LVF or BATFAIL (31) VDDT HSST L2 L1 Write Reset Value 0 0 0 0 0 0 — — Write Reset Condition POR, RESET POR, RESET POR POR, RESET POR, RESET POR, RESET — — Notes 30. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source. 31. The first SPI read after reset returns the BATFAIL flag state on bit D4. SPI Control Register (Write) HS3ON:HS1ON—High-Side H3:HS1 Enable Bit Table 8 shows the SPI Control register bits by name. Table 8. Control Bits Function (Write Operation) D7 D6 D5 D4 D3 D2 D1 D0 LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1 This bit enables the HSx. Reset clears the HSx bit. • 1 = HSx switched on (refer to Note below). • 0 = HSx switched off. Note If no PWM on HS1 and HS2 is required, the PWMIN terminal must be connected to the VDD terminal. MODE2:1—Mode Section Bits LINSL2:1—LIN Baud Rate and Low-Power Mode Selection Bits These bits select the LIN slew rate and requested lowpower mode in accordance with Table 9. Reset clears the LINSL2:1 bits. Table 9. LIN Baud Rate and Low-Power Mode Selection Bits The MODE2:1 bits control the operating modes and the watchdog in accordance with Table 10. Table 10. Mode Selection Bits MODE2 MODE1 Description 0 0 Sleep Mode (32) 0 1 Stop Mode (32) LINSL2 LINSL1 Description 0 0 Baud Rate up to 20 kbps (normal) 1 0 Watchdog Clear (33) 0 1 Baud Rate up to 10 kbps (slow) 1 1 Run (Normal) Mode 1 0 Fast Program Download Baud Rate up to 100 kbps 1 1 Low-Power Mode (Sleep or Stop) Request LIN-PU—LIN Pullup Enable Bit This bit controls the LIN pullup resistor during Sleep and Stop modes. • 1 = Pullup disconnected in Sleep and Stop modes. • 0 = Pullup connected in Sleep and Stop modes. Notes 32. To enter Sleep and Stop mode, a special sequence of SPI commands is implemented. 33. The device stays in Run (Normal) mode. To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep/Stop commands require two SPI transmissions. 908E624 26 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Description Functional Device Operation Sleep Mode Sequence LINWU/LINFAIL—LIN Status Flag Bit The Sleep command, as shown in Table 11, has to be sent twice. Table 11. Sleep Command Bits LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON 1 1 x x x x MODE 2 MODE 1 0 0 x = Don’t care. Stop Mode Sequence The Stop command, as shown in Table 12, has to be sent twice. Table 12. Stop Command Bits LINSL2 LINSL1 LIN-PU 1 1 x HS3O N HS2O N HS1O N x x x MODE2 MODE1 0 1 x = Don’t care. SPI Status Register (Read) Table 13 shows the SPI Status register bits by name. This bit indicates a LIN wake-up condition. • 1 = LIN bus wake-up occurred or LIN overcurrent/ overtemperature occurred. • 0 = No LIN bus wake-up occurred. HVF —High-Voltage Flag Bit This flag is set on an overvoltage (VSUP1) condition. • 1 = High-voltage condition has occurred. • 0 = no High-voltage condition. LVF/BATFAIL—Low-Voltage Flag Bit This flag is set on an undervoltage (VSUP1) condition. • 1 = Low-voltage condition has occurred. • 0 = No low-voltage condition. VDDT—Voltage Regulator Status Flag Bit This flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. • 1 = Voltage regulator overtemperature condition, prewarning. • 0 = No overtemperature detected. HSST—High-Side Status Flag Bit Table 13. Control Bits Function (Read Operation) D7 D6 D5 D4 D3 D2 D1 D0 INTSRC LINWU or LINFAIL HVF LVF or BATFAIL VDDT HSST L2 L1 This flag is set on overtemperature conditions on one of the high-side outputs. • 1 = HSx off due to overtemperature. • 0 = No overtemperature. L2:L1— Wake-Up Inputs L1, L2 Status Flag Bit INTSCR —Register Content Flags or Interrupt Source This bit indicates if the register contents reflect the flags or an interrupt/wake-up interrupt source. • 1 = D6:D0 reflects the interrupt or wake-up source. • 0 = No interrupt occurred. Other SPI bits report real time status. These flags reflect the status of the L2 and L1 input terminals and indicate the wake-up source. • 1 = L2:L1 input high or wake-up by L2:L1 (first register read after wake-up indicated with INTSRC = 1). • 0 = L2:L1 input low. 908E624 Analog Integrated Circuit Device Data Freescale Semiconductor 27 Package Dimensions PACKAGE DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below. 10.3 5 7.6 7.4 9 C 1 2.65 2.35 B 52X 54 0.65 PIN 1 INDEX 4 9 B 27 18.0 17.8 CL B 28 A 5.15 54X 2X 27 TIPS 0.3 SEATING PLANE 0.10 A A B C (0.29) A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. BASE METAL R0.08 MIN 0.30 0.25 (0.25) 0 ° MIN 0.25 0.29 0.13 GAUGE PLANE 0.38 0.22 6 A 0.13 M PLATING A B C 8 SECTION A-A ROTATED 90 ° CLOCKWISE DWB SUFFIX 54-TERMINAL SOIC WIDE BODY CASE 1365-01 PLASTIC PACKAGE ISSUE O 98ASA99294D ISSUE O 8° 0° 0.9 0.5 SECTION B-B DATE 09/19/01 908E624 28 Analog Integrated Circuit Device Data Freescale Semiconductor MM908E624DWTAD Rev 2.0, 12/2004 Freescale Semiconductor Technical Data Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers 54-TERMINAL SOICW Introduction This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. TJ1 TJ2 RθJA11 RθJA12 RθJA21 RθJA22 = . P1 P2 The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 1. Thermal Performance Comparison 1 = Power Chip, 2 = Logic Chip (°C/W) Thermal Resistance 908E624DW m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 RθJAmn 40 31 36 RθJBmn 25 16 21 RθJAmn 57 47 52 RθJCmn 21 12 16 © Freescale Semiconductor, Inc., 2004. All rights reserved. DW SUFFIX 98ASA99294D 54-TERMINAL SOICW Note For package dimensions, refer to the 908E624 device datasheet. A PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3 IRQ RST PTB1/AD1 PTD0/TACH0 PTD1/TACH1 NC NC NC PWMIN RST_A IRQ_A NC NC NC L1 L2 HS3 HS2 HS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD NC RXD WDCONF +E -E OUT VCC AGND VDD NC VSUP1 GND LIN VSUP2 908E624 Terminal Connections 54-Terminal SOICW 0.65 mm Pitch 17.9 mm x 7.5 mm Body Figure 1. Thermal Test Board Device on Thermal Test Board Material: Outline: Area A: Ambient Conditions: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 2. Thermal Resistance Performance Terminal Resistance RθJAmn Area A (mm2) 1 = Power Chip, 2 = Logic Chip (°C/W) m = 1, n=1 m = 1, n = 2 m = 2, n = 1 m = 2, n=2 0 58 48 53 300 56 46 51 600 54 45 50 RθJAmn is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed. 908E624DW 32 Analog Integrated Circuit Device Data Freescale Semiconductor 70 Thermal Resistance (°CW) 60 50 40 30 x 20 10 RθJA11 RθJA22 RθJA12 = RθJA21 0 0 300 600 Heat Spreading Area A (mm2) Figure 2. Device on Thermal Test Board RθJA 100 Thermal Resistance (°CW) 10 x RθJA11 RθJA22 RθJA12 = RθJA21 1 0.1 1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 time[s] Time (s) Figure 3. Transient Thermal Resistance (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2) 908E624DW Analog Integrated Circuit Device Data Freescale Semiconductor 33 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] MM908E624 Rev. 4.0 12/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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