INFINEON TLE7209

7 A H-Bridge for DC-Motor Applications
1
Overview
1.1
Features
TLE 7209-2R
• Operating supply voltage 5 V to 28 V
• Typical RDSon = 150 mΩ for each output transistor
(at 25 °C)
• Continuous DC load current 5 A (TC < 100 °C)
• Output current limitation at typ. 6.6 A ± 1.1 A
• Short circuit shut-down for output currents over 8 A
• Logic- inputs TTL/CMOS-compatible
• Output switching frequency up to 30 kHz
• Rise and fall times optimized for 0.5-2 kHz
• Over-temperature protection
• Short circuit protection
• Undervoltage disable function
• Diagnostic by SPI or Status-Flag (configurable)
• Enable and Disable inputs
• PG-DSO-20-37, -65 power package
• Green Product (RoHS compliant)
Functional Description
The TLE 7209-2R is an intelligent full H-Bridge, designed for the control of DC and
stepper motors in safety critical applications and under extreme environmental
conditions.
The H-Bridge is protected against over-temperature and short circuits and has an under
voltage lockout for all the supply voltages “VS” (main DC power supply). All malfunctions
cause the output stages to go tristate.
The device is configurable by the DMS pin. When grounded, the device gives diagnostic
information via a simple error flag. When supplied with VCC = 5 V, the device works in
SPI mode. In this mode, detailed failure diagnosis is available via the serial interface.
Type
Package
TLE 7209-2R
PG-DSO-20-37, -65
Data Sheet
1
Rev. 1.5, 2010-11-05
TLE 7209-2R
Overview
1.2
Pin Configuration
GND
SCK/SF
IN1
V S CP
VS
OUT1
OUT1
SDO
SDI
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
IN2
DIS
CSN
VS
OUT2
OUT2
EN
DMS
GND
Metal slug is
connected to GND
pins internally
Figure 1
Table 1
Pinout TLE 7209-2R
Pin Definitions and Functions
Pin. No.
Symbol
Function
1
GND
Ground
2
SCK/SF
SPI-Clock/Status-flag
3
IN1
Input 1
4
5, 16
VSCP
VS
Supply voltage; connect pins externally
6, 7
OUT1
Output 1; connect pins externally
8
SDO
Serial data out
9
SDI
Serial data in
10
GND
Ground
11
GND
Ground
Data Sheet
Supply voltage for internal charge pump
2
Rev. 1.5, 2010-11-05
TLE 7209-2R
Overview
Table 1
Pin Definitions and Functions (cont’d)
Pin. No.
Symbol
Function
12
DMS
Diagnostic-Mode selection
(+ Supply voltage for SPI-Interface)
13
EN
Enable
14, 15
OUT2
Output 2; connect pins externally
17
CSN
Chip Select (low active)
18
DIS
Disable
19
IN2
Input 2
20
GND
Ground
Data Sheet
3
Rev. 1.5, 2010-11-05
TLE 7209-2R
Overview
1.3
Block Diagram
DMS
Bias
V SCP
VS
Charge
Pump
FaultDetect
EN
DIS
Driver
CSN
SDI
SDO
SCK/SF
IN1
IN2
SPI
8 Bit
Logic
and
Latch
OUT 1
&
GateControl
OUT 2
Direct
Input
Under
Voltage
Over
Temperature
GND
Figure 2
Data Sheet
Block Diagram TLE 7209-2R
4
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2
Circuit Description
2.1
Control Inputs
The bridge is controlled by the Inputs IN1, IN2, DIS and EN as shown in Table 2. The
outputs OUT1 and OUT2 are set to High or Low by the parallel inputs IN1 and IN2,
respectively. In addition, the outputs can be disabled (set to tristate) by the Disable and
Enable inputs DIS and EN.
Inputs IN1, IN2 and DIS have an internal pull-up. Input EN has an internal pull-down.
Table 2
Functional Truth Table
Pos.
DIS EN
IN1 IN2 OUT1
OUT2 SF1) SPI2)
DIA_REG
1. Forward
L
H
H
L
H
L
H
2. Reverse
L
H
L
H
L
H
H
3. Free-wheeling low
L
H
L
L
L
L
H
4. Free-wheeling high
L
H
H
H
H
H
H
5. Disable
H
X
X
X
Z
Z
L
6. Enable
X
L
X
X
Z
Z
L
7. IN1 disconnected
L
H
Z
X
H
X
H
8. IN2 disconnected
L
H
X
Z
X
H
H
9. DIS disconnected
Z
X
X
X
Z
Z
L
10. EN disconnected
X
Z
X
X
Z
Z
L
11. Current limit. active
L
H
X
X
Z
Z
H
12. Under Voltage
X
X
X
X
Z
Z
L
13. Over-temperature
X
X
X
X
Z
Z
L
14. Over-current
X
X
X
X
Z
Z
L
1)
If Mode “Status-Flag” is selected (see Chapter 2.4)
2)
If Mode “SPI-Diagnosis” is selected (see Chapter 2.4)
Data Sheet
5
see
Chapter 2.4.2
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.2
Power Stages
Four n-channel power-DMOS transistors build up the output H-bridge. Integrated circuits
protect the outputs against over current and over-temperature if there is a short-circuit to
ground, to the supply voltage or across the load. Positive and negative voltage spikes,
which occur when switching inductive loads, are limited by integrated freewheeling
diodes. To drive the gates of the high-side DMOS, an internal charge pump is integrated
to generate a voltage higher than the supply voltage.
2.2.1
Chopper Current Limitation
To limit the output current at low power loss, a chopper current limitation is integrated as
shown in Figure 3. The current is measured by sense cells integrated in the low-side
switches. When the current limit IL has been exceeded for a time tb, all output stages are
switched off for a fixed time ta.
Blanking time tb
IOUT
Current limit IL
Switch-off time ta
time
Figure 3
Data Sheet
Chopper current limitation
6
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.2.2
Temperature-depending Current Reduction
For TILR < Tj < TSD the current limit
IL = 2.5 A ± 1.1 A as shown in Figure 4
decreases
from
IL = 6.6 A ± 1.1 A
to
A
6.6A
range of overtemperature shut-down
tolerance of temperature
dependent current
reduction
IL
2.5A
Tj
Figure 4
2.3
TILR
TSD
°C
Temperature dependent current reduction
Protection
The TLE 7209-2R is protected against short circuits, overload and invalid supply voltage
by the following measures:
2.3.1
Short circuit to Ground
The high-side switches are protected against a short of the output to ground by an over
current shut-down. If a high-side switch is turned on and the current rises above the short
circuit detection current IOUK all output transistors are turned off after a typical filter time
of 2 μs, and the error bit “Short Circuit to Ground on output 1 (2)”, SCG1 (SCG2) is stored
in the internal status register.
2.3.2
Short circuit to VS
Due to the chopper current regulation, the low-side switches are already protected
against a short to the supply voltage. To be able to distinguish a short circuit from normal
current limit operation, the current limitation is deactivated for the blanking time tb after
the current has exceeded the current limit threshold IL. If the short circuit detection
current IOUK is reached within this blanking time, a short circuit is detected (see
Figure 5). All output transistors are turned OFF and the according error bit “Short Circuit
to Battery on output 1 (2)”, SCB1 (SCB2) is set.
Data Sheet
7
Rev. 1.5, 2010-11-05
TLE 7209-2R
IN
IN
Circuit Description
IOUK
IOUK
tb
ta
tb
tb
IL
IOUT
IOUT
IL
time
Figure 5
2.3.3
time
Short to Vs detection. Left: normal operation. Right: short circuit is
detected
Short circuit across the load
If short circuit messages from high- and low-side switch occur simultaneously within a
delay time of typically 2μs, the error bit “Short Circuit Over Load”, SCOL is set.
2.3.4
Over-Temperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip
temperature may rise above the thermal shut-down temperature TSD. In that case, all
output transistors are shut-down and the error-bit “Over-Temperature”, OT is set.
2.3.5
Under-Voltage shut-down
If the supply-voltage at the VS pins falls below the under-voltage detection threshold, the
outputs are set to tristate and the error-bit “Under-Voltage at VS“ is set.
2.4
Diagnosis
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag
Diagnosis. The choice of the Diagnosis-Mode is selected by the voltage-level on Pin 12
(DMS Diagnosis Mode Selection):
• DMS = GND, Status-Flag Mode
• DMS = VCC, SPI-Diagnosis Mode
For the connection of Pins SDI, SDO, CSN and SCK/SF see Figure 14 and Figure 15.
Data Sheet
8
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.4.1
Status-Flag (SF) Mode (DMS = GND)
2.4.1.1
SF output
In SF-mode, pin 2 is used as an open-drain output status-flag. The pin has to be pulled
to the logic supply voltage with a pull-up resistor, 47 kOhm recommended.
In case of any failure that leads to a shut-down of the outputs, the status-flag is set (e.g.
SF pin pulled to low). These failures are:
–
–
–
–
–
Under Voltage on VS
Short circuit of OUT1 or OUT2 against VS or GND
Short circuit between OUT1 and OUT2
Over-current
Over-temperature
SF is also pulled low when the outputs are disabled by EN or DIS.
2.4.1.2
Fault storage and reset
– In case of under-Voltage, the failure is not latched. As soon as VS falls below the
under-Voltage detection threshold, the output stage switches in tristate and the statusflag is set from high level to low-level. If the voltage has risen above the specified value
again, the output stage switches on again and the status-flag is reset to high-level.
The Under Voltage failure is shown at the SF pin for VS in the voltage range below the
detection threshold (typical 4.2V) down to 2.5V.
– In the SF-mode, all internal circuitry is supplied by the voltage on VS. For that reason,
a loss of VS supply voltage leads to a reset of all stored information (Power-ONReset). This Power-ON-Reset occurs as soon as under-Voltage is detected on VS
– In case of short circuit, over-current or over-temperature, the fault will be stored.
The output stage remains in tristate and the status-flag at low-level until the error is
reset by one of the following conditions: H -> L on DIS, L -> H on EN or Power-ON
Reset.
2.4.2
SPI-Mode (DMS = 5V)
2.4.2.1
SPI-Interface
The serial SPI interface establishes a communication link between TLE 7209-2R and the
systems microcontroller. The TLE 7209-2R always operates in slave mode whereas the
controller provides the master function. The maximum baud rate is 2 MBaud (200pF on
SDO).
By applying an active slave select signal at CSN the TLE 7209-2R is selected by the SPI
master. SDI is the data input (Slave In), SDO the data output (Slave Out). Via SCK
(Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave
select signal (High) the data output SDO goes into tristate.
Data Sheet
9
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
The first two bits of an instruction may be used to establish an extended deviceaddressing. This gives the opportunity to operate up to 4 Slave-devices sharing one
common CSN signal from the Master-Unit (see Figure 7)
S P I p o w e rs u p p ly
DMS
CSN
S P I - C o n t r o l:
SCK
SDI
SDO
- > s t a t e m a c h in e
- > c lo c k c o u n t e r
- > in s t r u c t io n r e c o g n it io n
s h if t - r e g is t e r
8
D IA _ R E G
R eset
8
D ia g n o s t ic s
D IS
OR
DMS
U n d e rv o lt a g e
EN
Figure 6
2.4.2.2
SPI block-diagram
Characteristics of the SPI Interface
1. When DMS is > 3.5V, the SPI is active, independently of the state of EN or DIS. During
active reset conditions (DMS < 3.5V) the SPI is driven into its default state. When reset
becomes inactive, the state machine enters into a wait-state for the next instruction.
2. If the slave select signal at CSN is inactive (high), the state machine is forced to enter
the wait-state, i.e. the state machine waits for the following instruction.
3. During active (low) state of the select signal CSN the falling edge of the serial clock
signal SCK will be used to latch the input data at SDI. Output data at SDO are driven
with the rising edge of SCK (see timing diagram Figure 13)
4. Chip-address:
In order to establish the option of extended addressing the uppermost two bits of the
instruction-byte (i.e the first two SDI-bits of a Frame) are reserved to send a chipaddress. To avoid a bus conflict the output SDO must stay high impedance during the
addressing phase of a frame (i.e. until the address-bits are recognized as valid chipaddress). If the chip-address does not match, the data at SDI will be ignored and SDO
remains high impedance for the complete frame. See also Figure 7
5. Verification byte:
Simultaneously to the receipt of an SPI instruction TLE 7209-2R transmits a
verification byte via the output SDO to the controller. Refer to Figure 8. This byte
indicates normal or abnormal operation of the SPI. It contains an initial bit pattern and
a flag indicating an error occurred during the previous access.
Data Sheet
10
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
6. Because only read access is used in the TLE 7209-2R, the SDI data-bits (2nd byte)
are not used
7. Invalid instruction/access:
An instruction is invalid if an unused instruction code is detected (see tables with SPI
instructions). In case an unused instruction code occurred, the data byte “ffhex” (no
error) will be transmitted after having sent the verification byte. This transmission
takes place within the same SPI-frame that contained the unused instruction byte. In
addition any transmission is invalid if the number of SPI clock pulses (falling edge)
counted during active CSN differs from exactly 16 clock pulses. If an invalid instruction
is detected, bit TRANS_F in the following verification byte (next SPI transmission) is
set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the
microcontroller.
8. Transfer error bit TRANS_F:
The bit TRANS_F indicates an error during the previous transfer. An error is
considered to have occurred when an invalid command was sent, the number of SPI
clock pulses (falling edge) counted during active CSN was less than or greater than
16 clock pulses, or SPI clock (SCK) was logical high during falling edge of CSN.
Data Sheet
11
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
SDO remains tristated
after CSN active
Address sent by
master is "00"
Correct addres is recognized,
data transmitted to SDO
CSN
SCK
6
7
SDI
7
5
6
Z
SDO
4
2
3
1
7
0
5
6
4
2
3
0
1
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SDO remains tristated
after CSN active
Address sent by master
is differnt from "00"
Correct addres is not recognized, SDO
remains tristated and SDI data are ignored
CSN
SCK
SDI
SDO
Figure 7
Data Sheet
6
7
7
5
6
4
5
2
3
4
3
1
2
7
0
1
0
5
6
7
6
4
5
2
3
4
3
0
1
2
1
0
Z
Bus-arbitration by chip-address
12
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.4.2.3
SPI-Communication
The 16 input bits consist of the SPI-instruction byte and a second, unused byte. The 16
output bits consist of the verification-byte and the data-byte (see also Figure 8). The
definition of these bytes is given in the subsequent sections.
CSN
SCK
6
7
5
4
3
2
SDI
MSB
SPI Instruction
SDO
MSB
Verification byte
Figure 8
2.4.2.4
1
7
0
6
5
4
2
3
LSB
not used
LSB MSB
data-byte
1
0
LSB
SPI communication
SPI instruction
The uppermost 2 bit of the instruction byte contain the chip-address. The chip-address
of the TLE 7209-2R is 00. During read-access, the output data according to the register
requested in the instruction byte are applied to SDO within the same SPI frame. That
means, the output data corresponding to an instruction byte sent during one SPI frame
are transmitted to SDO during the same SPI frame.
Table 3
SPI Instruction Format
MSB
7
6
0
0
Table 4
5
4
3
2
1
0
INSTR4
INSTR3
INSTR2
INSTR1
INSTR0
INSW
SPI instruction Description
Bit
Name
Description
7,6
CPAD1,0
Chip Address (has to be ‘0’, ‘0’)
5-1
INSTR (4-0)
SPI instruction (encoding)
0
INSW
Even parity
Data Sheet
13
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
Table 5
SPI Instruction-Bytes Encoding
SPI Instruction
Encoding
Description
bit 7,6
bit 5-1
CPAD1,0 INSTR(4-0)
Bit 0
INSW
RD_IDENT
00
00000
0
read identifier
RD_VERSION
00
00001
1
read version
00
00100
1
read DIA_REG
–
RD_DIA
00
all others
x
unused, TRANS_F is set to high,
ff_hex is sent as data bit
–
all others
xxxxx
x
invalid address, SDO remains
tristate during entire SPI frame
2.4.2.5
Verification Byte
Table 6
Verification Byte Format
MSB
7
6
5
4
3
2
1
0
Z
Z
1
0
1
0
1
TRANS_F
Table 7
Verification Byte Description
Bit
Name
Description
0
TRANS_F
Bit = 1: error detected during previous transfer
Bit = 0: previous transfer was recognized as valid
1
Fixed to High
2
Fixed to Low
3
Fixed to High
4
Fixed to Low
5
Fixed to High
6
send as high impedance
7
send as high impedance
The default value after power-up at DMS of the TRANS_F bit is L (previous transfer valid)
Data Sheet
14
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.4.2.6
Data-byte: Diagnostics/Encoding of Failures
(Register DIA_REG, SPI Instruction RD_DIA)
)
Table 8
DIA_REG Format
MSB
7
6
5
4
3
2
1
0
EN/DIS
OT
CurrRed
CurrLim
DIA21
DIA20
DIA11
DIA10
Table 9
DIA_REG Description
Default value after reset is FFhex. Access by controller is read only
Bit
Name
Description
0
DIA 10
Diagnosis-Bit1 of OUT1
see below
1
DIA 11
Diagnosis-Bit2 of OUT1
see below
2
DIA 20
Diagnosis-Bit1 of OUT2
see below
3
DIA 21
Diagnosis-Bit2 of OUT2
see below
4
CurrLim
is set to „0“ in case of current limitation.
latched
5
CurrRed is set to „0“ in case of temperature dependent
current limitation
latched
6
OT
is set to „0“ in case of over-temperature
latched
7
EN/DIS
is set to „0“ in case of EN = L or DIS = H
not latched
EN
DIS
DIA_REG_7
H
L
1
L
L
0
H
H
0
L
H
0
Data Sheet
latch
behavior
15
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
Table 10
Encoding of the Diagnostic Bits of OUT1 and OUT2
DIA21 DIA20 DIA11 DIA10 Description
latch
behavior
1
1
0
0
Short circuit over load (SCOL)
latched
-
-
0
1
Short circuit to battery on OUT1 (SCB1) latched
-
-
1
0
Short circuit to ground on OUT1 (SCG1) latched
-
-
1
1
No error detected on OUT1
-
0
0
1
1
Open load (OL)
latched
0
1
-
-
Short circuit to battery on OUT2 (SCB2) latched
1
0
-
-
Short circuit to ground on OUT2 (SCG2) latched
1
1
-
-
No error detected on OUT2
-
0
0
0
0
Under Voltage on Pin Vs
not latched
Failure Encoding in case of multiple faults
If multiple faults are stored in the failure register, the faults that are encoded in the DIAxx
bits can not be displayed simultaneously due to the encoding scheme that is used. In this
case, errors are encoded according to the following priority list.
– Priority 1: Under Voltage (please note that after removal of Under Voltage, the original
error will be restored, see below)
– Priority 2: Short circuit across the load
– Priority 3: all other short circuits
– Priority 4: open load
If a failure of higher priority is detected, the failures of lower priority are no longer visible
in the encoded SPI message.
Fault storage and reset of the Diagnosis Register DIA_REG
Register DIA_REG is reset upon the following conditions:
– With the rising edge of the CSN-Signal after the SPI-instruction RD_DIA. This reset
only takes place if the correct number of 16 SCK pulses has been counted.
– When the voltage on DMS exceeds the threshold for detecting SPI-Mode (after Under
Voltage condition). Under Voltage on Vs (typ. < 5,0V) sets Bit 0.... Bit 3 of DIA_REG
to 0000. If Vs rises above the Under Voltage level, Bits of DIA_REG are restored
(when DMS > 3.5V).
– A rising edge on EN while DIS=0 or a falling edge on DIS while EN=1 re-activates the
output power-stages, and resets the DIA_REG register.
Data Sheet
16
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.4.2.7
Data-byte: Device Identifier and Version
(SPI instructions RD_IDENT and RD_VERSION)
The IC‘s identifier (device ID) and version number are used for production test purposes
and features plug & play functionality depending on the systems software release. The
two numbers are read-only accessible via the SPI instructions RD_IDENT and
RD_VERSION as described in Section 2.4.2.4.
The device ID is defined to allow identification of different IC-Types by software and is
fixed for the TLE 7209-2R.
The Version number may be utilized to distinguish different states of hardware and is
updated with each redesign of the TLE 7209-2R. The contents is divided into an upper
4 bit field reserved to define revisions (SWR) corresponding to specific software releases
and a lower 4 bit field utilized to identify the actual mask set revision (MSR).
Both (SWR and MSR) will start with 0000b and are increased by 1 every time an
according modification of the hardware is introduced.
Reading the IC Identifier (SPI Instruction: RD_IDENT):
Table 11
Device Identifier Format
MSB
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Table 12
Device Identifier Description
Bit
Name
Description
7...0
device-ID(7...0)
ID-No.: 10100010
Reading the IC version number (SPI Instruction: RD_VERSION):
Table 13
IC version number Format
MSB
7
6
5
4
3
2
1
0
SWR3
SWR2
SWR1
SWR0
MSR3
MSR2
MSR1
MSR0
Table 14
Bit
IC version number Description
Name
Description
7...4
SWR(3...0)
This register is set to 0
3...0
MSR(3...0)
Version corresponding to Mask set
Data Sheet
17
Rev. 1.5, 2010-11-05
TLE 7209-2R
Circuit Description
2.4.2.8
Open-Load Diagnosis
Open-load diagnostic in OFF-state is only possible in the SPI-mode (DMS = 5 V) if the
device is Disabled (EN = L or DIS = H). The detection mechanism is depicted in
Figure 9. The according diagnostic information can be read out via the SPI diagnostic
register. The resulting overall diagnostic truth-table is shown as Table 15
VS
VS
DMS
1.5mA
+
AND
DIS
OR
OUT1 OUT2
EN
1V
+
to diagnostic
register
1V
1mA
1
Figure 9
Functional block diagram of open-load detection
Table 15
Diagnosis Truth Table for open load detection
AND
Output stage inactive, EN = low or DIS = high, DMS > 4.5 V
OUT1 OUT2
Load available
H
Open Load
H
H
L
OL detected
SC -> GND on OUT1 and Open Load L
L
OL not detected – double Fault
SC -> GND on OUT2 and Open Load H
L
OL detected
SC -> VS on OUT1 and Open Load
H
L
OL detected
SC -> VS on OUT2 and Open Load
H
H
OL not detected – double Fault
Data Sheet
18
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Pos.
Parameter
Sym- Limit Values Unit Test Conditions
bol
min. max.
3.1.1
Junction temperature Tj
-40
+150
°C
–
–
+175
°C
dynamic: t < 1 s
Storage temperature Ts
-55
+125
°C
–
3.1.3
Ambient temperature Ta
-40
+125
°C
–
3.1.4
Supply voltage
-1
40
V
static destruction proof
-2
40
V
dynamic destruction proof
t < 0.5 s
(single pulse, Tj < 85 °C)
In status-flag-mode, SF
pull-up R ≥ 10 kΩ
3.1.2
VS
3.1.5
Voltage at logic
inputs
IN1, IN2, DIS, EN,
SDI, SCK/SF
V
-0.5
18
V
3.1.6
Voltage at logic input V
CSN
-0.5
40
V
3.1.7
Voltage at logic input VDMS -0.5
DMS
18
V
–
3.1.8
Voltage at logic
output SDO
V
–
3.1.9
Voltage at VsCP
VCP
VDMS V
+0.5
VS + V
3.1.10 ESD voltage human
3.1.11 body model (MIL
STD 883D / ANSI
EOS\ESD S5.1)
-0.5
VS -
0.5
-
0.5
VESD –
VESD-- –
OUT
–
4kV all pins
–
8kV only pins 6, 7, 14 and 15
(outputs)
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Data Sheet
19
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.2
Pos.
Operating Range
Symbol
min.
max.
Supply Voltage
VS
5
28
3.2.2
DMS Supply Voltage
VDMS
3.5
5.5
V
Device in SPI-mode
3.2.3
PWM frequency
f
–
30
kHz
May be limited to lower values
in the application due to
switching losses or duty cycle
requirements
3.2.4
Junction Temperature
TJ
-40
150
°C
3.2.1
Parameter
Limit Values
Unit
Remark
V
Note: In the operating range, the circuit functionality as described in the circuit
description is fulfilled.
3.3
Thermal Resistance
3.3.1
Junction-case
RthJC
–
1.5
K/W
specified by design
3.3.2
Junction-ambient
RthJA
–
50
K/W
minimal footprint
3.4
Electrical Characteristics
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
V
Switch off threshold
min.
typ.
max.
VUV OFF
3.4
4.2
5
VUV ON
3.6
4.4
5.2
VUV HY
100
–
1000
mV
Hysteresis
IUB
–
–
30
mA
f = 20 kHz, IOUT = 0 A
–
–
20
mA
f = 0 Hz, IOUT = 0 A
Power Supply
3.4.1
3.4.2
Under voltage at VS
Supply current
Data Sheet
20
Switch on threshold
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.4
Electrical Characteristics (cont’d)
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Conditions
Logic Inputs IN1, IN2, DIS, EN
3.4.3
Input “high”
VIH
2
–
–
V
–
3.4.4
Input “low”
VIL
–
–
1
V
–
3.4.5
Input hysteresis
VIHY
0.1
–
0.6
V
–
3.4.6
pull-up current
IN1, IN2, DIS
IIL
-200
-125
–
μA
U≤1V
3.4.7
pull-down current EN
IIH
–
–
100
μA
U≥2V
Power Outputs OUT1, OUT2
3.4.8
Switch on resistance
–
–
–
300
mΩ
ROUT-UB, ROUT-GND
VS > 5 V, IOUT = 3 A
3.4.9
Switch-off current
|IL|
5.5
6.6
7.7
A
-40 °C < Tj < TILR
1.4
2.5
3.6
A
Tj = TSD; specified by
design
3.4.10
Switch-off time
ta
8
16
26
μs
Vs=13.2 V, L=2.2 mH,
R=0.23 Ω
3.4.11
Blanking time
tb
8
13
19
μs
Vs=13.2 V, L=2.2 mH,
R=0.23 Ω
3.4.12
Switch-off Tracking
ta/tb
1.0
–
–
–
Vs=13.2 V, L=2.2 mH,
R=0.23 Ω
3.4.13
Short circuit detection
current
|IOUK|
8
–
18
A
–
3.4.14
Current Tracking
|IOUK||IL|
2
3.5
–
A
specified by design
3.4.15
Reactivation time after
internal shut-down
t
–
–
200
μs
Over-current- or overtemperature shutdown to reactivation
of the output stage
Note: Reactivation time is not subject to production test; specified by design
Data Sheet
21
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.4
Electrical Characteristics (cont’d)
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
Unit
Test Conditions
min.
typ.
max.
3.4.16
Leakage current
–
–
–
200
μA
Output stage
switched off
3.4.17
Free-wheel diode
forward voltage
UD
–
–
2
V
IOUT = 3 A
3.4.18
Free-wheel diode
reverse recovery time
trr
–
–
100
ns
Reverse recovery
time is not subject to
production test;
specified by design
20
μA
VSF = 5 V
Output Status-flag, Open Drain Output DMS < 0.8 V
3.4.19
Output “high”
(SF not set)
ISF
3.4.20
Output “low”
(SF set)
ISF
3.4.21
Output ON-delay
3.4.22
–
–
300
–
–
μA
VSF = 1 V
100
–
–
μA
VSF = 0.5 V
tdon
–
–
6
μs
IN1 --> OUT1 resp.
IN2 --> OUT2, IOUT =
3A
Output OFF-delay
tdoff
–
–
6
μs
IN1 --> OUT1 resp.
IN2 --> OUT2, IOUT =
3A
3.4.23
Output switching time
tr, tf
–
–
5
μs
OUT1H --> OUT1L,
OUT2H --> OUT2L,
IOUT = 3 A
OUT1L --> OUT1H,
OUT2L --> OUT2H
3.4.24
Disable delay time
tddis
–
–
2
μs
DIS --> OUTn,
EN --> OUTn
3.4.25
Power on delay time
–
–
–
1
ms
VS = on --> output
3.4.26
Delay time for fault
detection
tdf
1.0
2
–
μs
specified by design
3.4.27
Minimum pulse width
tden
–
1.6
2.2
μs
EN/DIS-->Reset
DIA_REG
Timing
stage active; no load
Data Sheet
22
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.4
Electrical Characteristics (cont’d)
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Conditions
Input SCK, SPI Clock Input
3.4.28
Low Level
USCKL
–
–
1
V
–
3.4.29
High Level
USCKH
2
–
–
V
–
3.4.30
Hysteresis
ΔUSCK
0.1
–
0.4
V
–
3.4.31
Input Capacity
CSCK
–
–
20
pF
–
3.4.32
Input Current
-ISCK
–
20
50
μA
Pull-up current source
connected to VCC
Input CSN, Chip Select Signal
3.4.33
Low Level
UCSNL
–
–
1
V
TLE 7209-2R is
selected
3.4.34
High Level
UCSNH
2
–
–
V
–
3.4.35
Hysteresis
ΔUCSN
0.1
–
0.4
V
–
3.4.36
Input Capacity
CCSN
–
–
20
pF
–
3.4.37
Input Current
-ICSN
–
20
50
μA
Pull up current source
connected to VCC
Input SDI, SPI Data Input
3.4.38
Low Level
USDIL
–
–
1
V
–
3.4.39
High Level
USDIH
2
–
–
V
–
3.4.40
Hysteresis
ΔUSDI
0.1
–
0.4
V
–
3.4.41
Input Capacity
CSDI
–
–
20
pF
–
3.4.42
Input Current
-ISDI
–
20
50
μA
Pull up current source
connected to VCC
Data Sheet
23
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.4
Electrical Characteristics (cont’d)
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
min.
typ.
max.
–
Unit
Test Conditions
Output SDO
Tristate Output of the TLE 7209-2R (SPI output);
3.4.43
Low Level
VSDOL
–
0.4
V
ISDO = 2 mA
3.4.44
High Level
VSDOH
VDMS –
–
V
ISDO = -2 mA
- 0.75
3.4.45
Capacity
CSDO
–
–
30
pF
Capacity of the pin in
tristate
3.4.46
Leakage Current
ISDO
-10
–
10
μA
In tristate
Note: All in- and output pin capacities are not subject to production test; specified by design
Input DMS
Supply-Input for the SPI-Interface and Selection Pin for SPI- or SF-Mode
3.4.47
3.4.48
Input Voltage
Input Current
VDMS
3.5
–
–
V
VDMS
–
–
0.8
V
Status-Flag-Mode
IDMS
–
–
10
mA
SPI-Mode
VOUT1
0.8
–
2.0
V
VOUT2
0.8
–
2.0
V
DMS > 4.5 V, EN <
0.8 V or DIS > 4.5 V;
no load
-IOUT1
1000
1500
2000
μA
VOUT1=0 V,
IOUT2
700
SPI-Mode
Open-Load Diagnosis
3.4.49
3.4.50
3.4.51
Diagnostic Threshold
Pull-up Current
Pull-down Current
DMS > 4.5 V, EN <
0.8 V or DIS > 4.5 V;
no load
1000
1400
μA
VOUT2=5 V,
DMS > 4.5 V, EN <
0.8 V or DIS > 4.5 V;
no load
3.4.52
Tracking Diag. C
–
1.2
1.5
1.7
–
IOUT1/IOUT2
3.4.53
Delay Time
tD
30
–
100
ms
–
Note: Open Load is detected if VOUT1 > 2 V AND VOUT2 < 0.8 V (refer to fig. 9).
Data Sheet
24
Rev. 1.5, 2010-11-05
TLE 7209-2R
Electrical Characteristics
3.4
Electrical Characteristics (cont’d)
5V < VS < 28V; – 40 °C < Tj < 150 °C; unless otherwise specified
Pos.
Parameter
Symbol
Limit Values
min.
typ.
max.
200
–
–
Unit
Test Conditions
ns
referred to master
SPI Timing (see Figure 13)
3.4.54
Cycle-Time (1)
tcyc (1)
3.4.55
Enable Lead Time
tlead (2)
100
–
–
ns
referred to master
3.4.56
Enable Lag Time
tlag (3)
150
–
–
ns
referred to master
3.4.57
Data Valid
tv (4)
–
–
–
–
40
150
ns
ns
CL = 40 pF
CL = 200 pF
referred to TLE 72092R
3.4.58
Data Setup Time
tsu (5)
3.4.59
Data Hold Time
th (6)
20
–
–
ns
referred to master
3.4.60
Disable Time
tdis (7)
–
–
100
ns
referred to TLE 72092R; specified by
design
50
–
–
ns
referred to master
3.4.61
Transfer Delay
tdt (8)
150
–
–
ns
referred to master
3.4.62
Select time
tCSN (9)
50
–
–
ns
referred to master
3.4.63
Access time
tacc (10)
8.35
–
–
μs
referred to master
3.4.64
Clock inactive before
chip select becomes
valid
(11)
200
–
–
ns
–
3.4.65
Clock inactive after
chip select becomes
invalid
(12)
200
–
–
ns
–
Temperature Thresholds
3.4.66
Start of current limit
reduction
TILR
150
165
–
°C
3.4.67
Thermal Shut-down
TSD
175
–
–
°C
Note: Temperature thresholds are not subject to production test; specified by design
Data Sheet
25
Rev. 1.5, 2010-11-05
TLE 7209-2R
Timing Diagrams
4
Timing Diagrams
V
5
INx
50%
50%
0
80%
OUTx
20%
tdon
Figure 10
tdoff
Output Delay Time--Depicted for Low-Side FETs
V
5
DIS / EN
50%
0
Z
OUTx
20%
tddis
Figure 11
Data Sheet
Disable Delay Time
26
Rev. 1.5, 2010-11-05
TLE 7209-2R
Timing Diagrams
tRISE
tFALL
80%
80%
OUTx
20%
Figure 12
20%
Output Switching Time
10
9
CSN
11
2
3
1
SCK
8
12
4
SDO
tristate
5
SDI
7
Bit (n-3)
Bit (n-4)...1
Bit 0; LSB
6
MSB IN
Bit (n-2) Bit (n-3)
Bit (n-4)...1
LSB IN
n = 16
Figure 13
Data Sheet
SPI-timing
27
Rev. 1.5, 2010-11-05
TLE 7209-2R
Application
Application
Vs <
40V
5
100µF 100nF
VSCP
VS
DMS
100nF
V-Reg
Vcc
IN1
IN2
DIS
CSN
µC
OUT 1
M
SDI
SDO
OUT 2
SCK/SF
from Watchdog or
fail-safe Controller
EN
GND
Application Example with SPI-Interface
Vs <
40V
Figure 14
100µF 100nF
VSCP
VS
DMS
Vcc
V-Reg
IN1
IN2
DIS
µC
47k
CSN
OUT 1
M
SDI
SDO
OUT 2
SCK/SF
from Watchdog or
fail-safe Controller
EN
GND
Figure 15
Data Sheet
Application Example with Status-Flag
28
Rev. 1.5, 2010-11-05
TLE 7209-2R
Application
Reverse polarity protection via main relay
ignition
switch
Vs < 40V
main
relay
VS
100µF
TLE 7209-2R
100nF
battery
Figure 16
Data Sheet
Application Examples for Over-Voltage- and Reverse-Voltage
Protection
29
Rev. 1.5, 2010-11-05
TLE 7209-2R
Package Outlines
6
Package Outlines
+0.07
-0.02
5˚ ±3˚
0.25
6.3
0.1
Heatslug
(Mold)
0.95 ±0.15
+0.13
0.25 M A 20x
14.2 ±0.3
20
11
11
1
10
10
0.25 B
20
5.9 ±0.1
(Metal)
0.4
15.74 ±0.1
(Heatslug)
3.2 ±0.1
(Metal)
1.27
B
2.8
1.3
1.2 -0.3
11 ±0.15 1)
3.5 MAX.
0 +0.1
3.25 ±0.1
PG-DSO-20-37, -65
(Plastic Dual Small Outline Package)
Index Marking
15.9 ±0.15 1)
(Mold)
1)
13.7 -0.2
1
Heatslug
(Metal)
A
Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
1 x 45˚
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products
and to be compliant with government regulations the device is available as a green
product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable
for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Dimensions in mm
Data Sheet
Rev. 1.5, 2010-11-05
30
TLE 7209-2R
Package Outlines
7
Revision History
Rev.
Date
Changes
1.3
2005-01-11
non RoHS compliant version of the TLE7209-2R
1.4
2007-04-05
RoHS compliant version of the TLE7209-2R
RoHS Logo and references added
Package changed to PG-DSO-20-37
Pos. 3.1.7, VDMS max. changed from 13V to 18V
1.5
2010-11-05
Data Sheet
Package name updated
31
Rev. 1.5, 2010-11-05
Edition 2010-11-05
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions
or characteristics. With respect to any examples or hints given herein, any typical values stated
herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the
nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on
the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the
express written approval of Infineon Technologies, if a failure of such components can reasonably
be expected to cause the failure of that life-support device or system or to affect the safety or
effectiveness of that device or system. Life support devices or systems are intended to be implanted
in the human body or to support and/or maintain and sustain and/or protect human life. If they fail,
it is reasonable to assume that the health of the user or other persons may be endangered.