DK-DEV-5AGXB3N/ES Dev Kit Schematic

8
7
6
5
4
NOTES:
E
1. Project Drawing Numbers:
Raw PCB
Gerber Files
PCB Design Files
Assembly Drawing
Fab Drawing
Schematic Drawing
PCB Film
Bill of Materials
Schematic Design Files
Functional Specification
PCB Layout Guidelines
Assembly Rework
3
REV
DATE
PAGES
A
B
12/14/2011
5/16/2012
All
Many
2
Initial Released Rev A
1. Separated VCC into 2 power rails (VCC and VCCP) including decoupling caps.
2. A5_VCCIO_FMC power pin correction
3. Added FM_A26 to MAX II device
4. Corrected FPGA 2 config bus
5. hardwired CLKIN50 to enabled on power up
6. Constrain MSEL pins to known states for both FPGAs
7. Tie FPGA pin N6 to GND
8. Mini-USB pin 5 coonected to board GND
9. Correct reverse power diode pin connections
10. Add CLOCK_SDA and CLOCK_SCL to FPGA1
11. Removed FPGA2 and MAXII devices from JTAG chain
12. Removed unused PCIe JTAG circuit
13. Added x2 clock buffer for eye measurement via Bullseye cables
14. C2C_DIN_P/N9 pin swapped
15. Reduced C2C to x29 and added C2C clock inputs
16. PCIE_PERSTn moved to pin N9
17. MAX3378 decoupling added
18. Moved DDR3*_CKE to discrete 4.7K pulldown
19. Moved DDR3*_RESET to discrete 51 Ohm to 1.5V
20. Moved SMA AC-coupling from TX pins to RX pins
21. Removed backplane interface
100-0320804-B1
110-0320804-B1
120-0320804-B1
130-0320804-B1
140-0320804-B1
150-0320804-B1
160-0320804-B1
170-0320804-B1
180-0320804-B1
210-0320804-B1
220-0320804-B1
320-0320804-B1
2. 1699 Parts, 87 Library Parts, 1962 Nets, 9866 Pins
Arria V GX FPGA Development Kit Board
D
C
B
1
DESCRIPTION
PAGE
E
DESCRIPTION
PAGE
DESCRIPTION
1
Title, Notes, Block Diagram, Rev. History
30
HSMC Port A & Port B
2
FPGA 1 Package Top
31
FMC
3
FPGA 2 Package Top
32
Ethernet PHY & RJ-45
4
PCI Express Edge Connector
33
On-Board USB Blaster II
5
Arria V GX 1 Bank 3
34
User I/O (FPGA 1)
6
Arria V GX 1 Bank 4
35
User I/O (FPGA 2)
7
Arria V GX 1 Bank 7
36
Arria V GX 1 Power
8
Arria V GX 1 Bank 8
37
Arria V GX 2 Power
9
Arria V GX 1 Transceiver Banks
38
Power 1 - DC Input, 12V, 3.3V
10
Clocks (Part 1 of 2)
39
Power 2 - 1.1V (VCCINT)
11
Clocks (Part 2 of 2)
40
Power 3 - 2.5V, 1.2V, 1.5V, 1.8V
12
Arria V GX 1 Clocks
41
Power 4 - 3.3V
13
Arria V GX 2 Clocks
42
Power 5 - Linear Regulator
14
Arria V GX Configuration
43
Power 6 - Power & Temp Monitor
15
JTAG
44
Decoupling (FPGA 1)
16
Arria V GX 2 Bank 3
45
Decoupling (FPGA 2)
17
Arria V GX 2 Bank 4
46
Arria V GX Power (GND/NC)
18
Arria V GX 2 Bank 7
19
Arria V GX 2 Bank 8
20
Arria V GX 2 Transceiver Banks
21
DDR3A - Part 1 of 2
22
DDR3A - Part 2 of 2
23
QDRII+ SRAM
24
DDR3B -x32
25
DDR3C -x32
26
Flash
27
5M2210 System Controller
28
SFP+ Interface
29
SDI TX Cable Driver & SMB
A
D
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
C
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
1
of
1
46
8
7
6
5
4
3
2
1
FPGA 1 Package Top View
BANK 8A
BANK 7A
BANK 7B
BANK 8B
VCCIO = 2.5V
BANK 7C
DDR3, Embedded USB Blaster II
BANK 8D
BANK 7D
E
VCCIO = 1.5V
BANK 8C
Chip-to-Chip (LVDS)
E
LCD, USER IO
D
D
XCVR BANK QL2 (GT option only)
SFP+ x1
Bullseye SMA (10G)
XCVR BANK QR2 (GT option only)
HSMC Port x4 (Total XCVR x8)
Bullseye SMAs (6G) x2
Bullseye SMA (10G)
C
C
XCVR BANKS: QL0, QL1
XCVR BANKS QR0, QR1
HSMC Port A x4
Chip-to-Chip x8
PCI Express x8
SFP+ x1
SMA (6G)
B
B
A
BANK 4A
BANK 4B
VCCIO = 2.5V
BANK 4C
BANK 4D
HSMA,
SFP+ control,
User IO
Ethernet, PCIe,
SFP+ control
BANK 3A
BANK 3B
VCCIO = 1.8V
BANK 3C
QDRII+, FM
BANK 3D
FLASH, FM bus
Title
Size
B
Date:
8
7
6
5
4
3
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
2
of
1
46
8
7
6
5
4
3
2
1
FPGA 2 Package Top View
BANK 8A
BANK 7A
BANK 7B
BANK 7C
BANK 8B
VCCIO = 2.5V
DDR3 x32 (2 Individual Interfaces)
BANK 8D
BANK 7D
E
VCCIO = 1.5V
BANK 8C
Chip-to-Chip (LVDS)
E
D
D
XCVR BANK QL2 (GT option only)
Bullseye SMA (10G)
XCVR BANK QR2 (GT option only)
FMC x6 (Total FMC x10)
C
C
XCVR BANKS: QL0, QL1
XCVR BANKS QR0, QR1
Chip-to-Chip x8
HSMC Port B x4
SDI
FMC x4
Bullseye SMA (6G)
SMA (10G)
B
B
BANK 4A
A
BANK 4B
BANK 4C
BANK 3A
VCCIO = 2.5V
BANK 3B
FMC
BANK 3C
BANK 4D
BANK 3D
VCCIO = 2.5V
Title
HSMC Port B
SDI
USER I/O
Size
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
3
of
1
46
8
7
6
5
4
3
2
1
PCI Express Edge Connector
E
E
12V_PCIE
12V_PCIE
3.3V_PCIE
Link Width DIP Switch
J30
D
6
6
PCIE_SMBCLK
PCIE_SMBDAT
6
PCIE_WAKEn
R60
R59
DNI 3.3V_PCIE_AUX
DNI PCIE_WAKEn_R
PCIE_PRSNT2n_x1
C
9
9
PCIE_RX_P1
PCIE_RX_N1
9
9
PCIE_RX_P2
PCIE_RX_N2
9
9
PCIE_RX_P3
PCIE_RX_N3
B
9
9
PCIE_RX_P4
PCIE_RX_N4
9
9
PCIE_RX_P5
PCIE_RX_N5
9
9
PCIE_RX_P6
PCIE_RX_N6
9
9
PCIE_RX_P7
PCIE_RX_N7
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
PCIE_PRSNT2n_x8
PRSNT1_N
+12V
+12V
GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
+3_3V
+3_3V
PERST_N
RSVD1
GND
X1
GND
REFCLK+
PET0P
REFCLKPET0N
GND
GND
PER0P
PRSNT2_N_X1
PER0N
GND
GND
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
PCIE_PRSNT2n_x4
SW7
+12V
+12V
+12V
GND
SMCLK
SMDAT
GND
+3_3V
JTAG_TRSTN
+3_3VAUX
WAKE_N
KEY
B12
B13
B14
B15
B16
B17
B18
PCIE_RX_P0
PCIE_RX_N0
9
9
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
PET1P
X4
PET1N
GND
GND
PET2P
PET2N
GND
GND
PET3P
PET3N
GND
RSVD3
PRSNT2_N_X4
GND
RSVD2
GND
PER1P
PER1N
GND
GND
PER2P
PER2N
GND
GND
PER3P
PER3N
GND
RSVD4
PET4P
X8
PET4N
GND
GND
PET5P
PET5N
GND
GND
PET6P
PET6N
GND
GND
PET7P
PET7N
GND
PRSNT2_N_X8
GND
RSVD5
GND
PER4P
PER4N
GND
GND
PER5P
PER5N
GND
GND
PER6P
PER6N
GND
GND
PER7P
PER7N
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
PCIE_PRSNT1n
1
2
3
4
8
7
6
5
OPEN
3.3V_PCIE
PCIE_PRSNT2n_x1
PCIE_PRSNT2n_x4
PCIE_PRSNT2n_x8
TDA04H0SB1
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
PCIE_PERSTn
14
PCIE_REFCLK_P
PCIE_REFCLK_N
9
9
PCIE_TX_CP0
PCIE_TX_CN0
0.1uF
0.1uF
C976
C975
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_CP1
PCIE_TX_CN1
0.1uF
0.1uF
C974
C973
PCIE_TX_P1
PCIE_TX_N1
9
9
PCIE_TX_CP2
PCIE_TX_CN2
0.1uF
0.1uF
C972
C971
PCIE_TX_P2
PCIE_TX_N2
9
9
PCIE_TX_CP3
PCIE_TX_CN3
0.1uF
0.1uF
C970
C969
PCIE_TX_P3
PCIE_TX_N3
9
9
PCIE_TX_CP4
PCIE_TX_CN4
0.1uF
0.1uF
C968
C967
PCIE_TX_P4
PCIE_TX_N4
9
9
PCIE_TX_CP5
PCIE_TX_CN5
0.1uF
0.1uF
C966
C965
PCIE_TX_P5
PCIE_TX_N5
9
9
PCIE_TX_CP6
PCIE_TX_CN6
0.1uF
0.1uF
C964
C963
PCIE_TX_P6
PCIE_TX_N6
9
9
PCIE_TX_CP7
PCIE_TX_CN7
0.1uF
0.1uF
C962
C961
PCIE_TX_P7
PCIE_TX_N7
D
9
9
C
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
B
9
9
PCIE_Slot
B1
12V_PCIE
C85
0.1uF
A
3.3V_PCIE
C979
0.1uF
C980
0.1uF
C84
0.1uF
C86
0.1uF
C978
0.1uF
C87
0.1uF
C977
0.1uF
PCI BRACKET
Title
Size
B
Date:
8
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
4
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 1, Bank 3
E
E
VCCIO = 1.8V
U16B
VCCIO =1.8V
U16A
Arria V GX Bank 3
Arria V GX Bank 3
Bank 3C
D
C
FM_A10
FM_A25
FM_A26
AP33
AL32
AK31
FM_A3
FM_A11
FM_A12
FM_A14
FM_A13
FM_A15
FM_A8
FM_A16
AP32
AM31
AP31
AT31
AR31
AE29
AH30
AG30
FM_A0
FM_A7
AW32
AW33
FLASH_RDYBSYn
FLASH_WEn
FLASH_CLK
MAX_CLK
MAX_CSn
AK32
AN32
AL31
AN31
AD29
QDRII_A1
QDRII_A3
QDRII_A2
QDRII_A5
QDRII_D0
QDRII_D2
QDRII_D1
QDRII_D3
QDRII_D5
QDRII_D4
AC29
AG28
AF28
AL29
AE28
AB28
AB27
AM28
AD27
AC27
QDRII_A7
QDRII_A6
AJ28
AH28
QDRII_A0
QDRII_A4
QDRII_A8
QDRII_A9
AB29
AK29
AD28
AP28
Bank 3A
DQ1B/DIFFIO_TX_B1p
DQ1B/DIFFIO_TX_B3p
DQ1B
RZQ_0/DIFFIO_TX_B1n
DQ2B/DIFFIO_TX_B8p
DQ2B/DIFFIO_TX_B10p
DQ2B/DIFFIO_TX_B12p
DQ2B/DIFFIO_RX_B13p
DQ2B/DIFFIO_RX_B13n
DQ2B/DIFFIO_TX_B14p
DQ2B/DIFFIO_RX_B15p
DQ2B/DIFFIO_RX_B15n
DQ3B/DIFFIO_TX_B16p
DQ3B/DIFFIO_RX_B17p
DQ3B/DIFFIO_RX_B17n
DQ3B/DIFFIO_TX_B18p
DQ3B/DIFFIO_TX_B20p
DQ3B/DIFFIO_RX_B21p
DQ3B/DIFFIO_RX_B21n
DQ3B/DIFFIO_TX_B22p
DQ3B/DIFFIO_RX_B23p
DQ3B/DIFFIO_RX_B23n
DQS2B/DIFFIO_RX_B11p
DQSn2B/DIFFIO_RX_B11n
DQS3B/DIFFIO_RX_B19p
DQSn3B/DIFFIO_RX_B19n
DIFFIO_TX_B3n
DIFFIO_TX_B8n
DIFFIO_TX_B10n
DIFFIO_TX_B12n
DIFFIO_TX_B14n
DIFFIO_TX_B16n
DIFFIO_TX_B18n
DIFFIO_TX_B20n
DIFFIO_TX_B22n
DQ4B/DIFFIO_TX_B24p
DQ4B/DIFFIO_RX_B25p
DQ4B/DIFFIO_RX_B25n
DQ4B/DIFFIO_TX_B26p
DQ4B/DIFFIO_TX_B28p
DQ4B/DIFFIO_RX_B29p
DQ4B/DIFFIO_RX_B29n
DQ4B
DQ4B/DIFFIO_RX_B30p
DQ4B/DIFFIO_RX_B30n
DQS4B/DIFFIO_RX_B27p
DQSn4B/DIFFIO_RX_B27n
DIFFIO_TX_B24n
DIFFIO_TX_B26n
DIFFIO_TX_B28n
DIFFIO_TX_B31n
Bank 3B
DQ5B/DIFFIO_TX_B31p
DQ5B/DIFFIO_RX_B32p
DQ5B/DIFFIO_RX_B32n
DQ5B/DIFFIO_TX_B33p
DQ5B/DIFFIO_TX_B35p
DQ5B/DIFFIO_RX_B36p
DQ5B/DIFFIO_RX_B36n
DQ5B/DIFFIO_TX_B37p
DQ5B/DIFFIO_RX_B38p
DQ5B/DIFFIO_RX_B38n
DQS5B/DIFFIO_RX_B34p
DQSn5B/DIFFIO_RX_B34n
DIFFIO_TX_B33n
DIFFIO_TX_B35n
DIFFIO_TX_B37n
AN33
RZQIN_1_8V
AV31
AW31
AW30
AL30
AV30
AU29
AT29
AP30
AP29
AN29
FM_A17
FM_A19
FM_A18
FM_A2
FM_A20
FM_A22
FM_A21
FM_A23
MAX_WEn
FM_A24
AT30
AR30
FM_A1
FM_A9
AU31
AK30
AU30
AN30
MAX_OEn
FLASH_ADVn
FLASH_CEn
FLASH_OEn
AR28
AV28
AU28
AK27
AR27
AU27
AT27
AN27
AW27
AV27
QDRII_D6
QDRII_D8
QDRII_D7
QDRII_BWSn0
QDRII_D11
QDRII_D13
QDRII_D12
QDRII_D14
QDRII_D16
QDRII_D15
AW28
AW29
QDRII_D10
QDRII_D9
AJ27
AP27
AM27
QDRII_A10
QDRII_A11
QDRII_A12
R350
100, 1%
5AGXB3H4F40
Version = 1.86 Pin-out
QDRII_D17
QDRII_D18
QDRII_BWSn1
QDRII_D19
QDRII_D20
QDRII_D22
QDRII_D21
QDRII_D23
QDRII_D25
QDRII_D24
AH27
AC25
AB25
AF27
AD25
AH26
AG26
AE26
AH25
AG25
QDRII_K_P
QDRII_K_N
AF25
AE25
QDRII_D26
QDRII_D27
QDRII_BWSn2
QDRII_D28
QDRII_D31
QDRII_D33
QDRII_D32
QDRII_D34
QDRII_BWSn3
QDRII_D35
AP26
AN25
AM25
AK25
AT25
AW26
AW25
AL26
AV24
AV25
QDRII_D30
QDRII_D29
AU26
AT26
QDRII_Q12
QDRII_Q14
QDRII_Q13
QDRII_Q15
QDRII_Q18
QDRII_Q20
QDRII_Q19
QDRII_Q21
QDRII_Q23
QDRII_Q22
AP23
AE23
AD22
AL23
AW22
AW21
AV21
AH23
AF22
AE22
QDRII_Q17
QDRII_Q16
AU22
AT22
FM_D10
FM_D15
FM_D5
FM_D6
FM_D7
FM_D14
AN23
AK23
AV22
AG23
AN22
AK22
DQ6B/DIFFIO_TX_B39p
DQ6B/DIFFIO_RX_B40p
DQ6B/DIFFIO_RX_B40n
DQ6B/DIFFIO_TX_B41p
DQ6B/DIFFIO_TX_B43p
DQ6B/DIFFIO_RX_B44p
DQ6B/DIFFIO_RX_B44n
DQ6B/DIFFIO_TX_B45p
DQ6B/DIFFIO_RX_B46p
DQ6B/DIFFIO_RX_B46n
DQS6B/DIFFIO_RX_B42p
DQSn6B/DIFFIO_RX_B42n
DQ7B/DIFFIO_TX_B47p
DQ7B/DIFFIO_RX_B48p
DQ7B/DIFFIO_RX_B48n
DQ7B/DIFFIO_TX_B49p
DQ7B/DIFFIO_TX_B51p
DQ7B/DIFFIO_RX_B52p
DQ7B/DIFFIO_RX_B52n
DQ7B
DQ7B/DIFFIO_RX_B53p
DQ7B/DIFFIO_RX_B53n
DQ8B/DIFFIO_TX_B54p
DQ8B/DIFFIO_RX_B55p
DQ8B/DIFFIO_RX_B55n
DQ8B/DIFFIO_TX_B56p
DQ8B/DIFFIO_TX_B58p
DQ8B/DIFFIO_RX_B59p
DQ8B/DIFFIO_RX_B59n
DQ8B/DIFFIO_TX_B60p
DQ8B/DIFFIO_RX_B61p
DQ8B/DIFFIO_RX_B61n
DQS8B/DIFFIO_RX_B57p
DQSn8B/DIFFIO_RX_B57n
DIFFIO_TX_B39n
DIFFIO_TX_B41n
DIFFIO_TX_B43n
DIFFIO_TX_B45n
DIFFIO_TX_B47n
DIFFIO_TX_B49n
DIFFIO_TX_B51n
DIFFIO_TX_B54n
DIFFIO_TX_B56n
DIFFIO_TX_B58n
DIFFIO_TX_B60n
DQS7B/DIFFIO_RX_B50p
DQSn7B/DIFFIO_RX_B50n
Bank 3D
DQ9B/DIFFIO_TX_B62p
DQ10B/DIFFIO_TX_B70p
DQ9B/DIFFIO_RX_B63p
DQ10B/DIFFIO_RX_B71p
DQ9B/DIFFIO_RX_B63n
DQ10B/DIFFIO_RX_B71n
DQ9B/DIFFIO_TX_B64p
DQ10B/DIFFIO_TX_B72p
DQ9B/DIFFIO_TX_B66p
DQ10B/DIFFIO_TX_B74p
DQ9B/DIFFIO_RX_B67p
DQ10B/DIFFIO_RX_B75p
DQ9B/DIFFIO_RX_B67n
DQ10B/DIFFIO_RX_B75n
DQ9B/DIFFIO_TX_B68p
DQ10B
DQ9B/DIFFIO_RX_B69p
DQ9B/DIFFIO_RX_B69n
DQS10B/DIFFIO_RX_B73p
DQSn10B/DIFFIO_RX_B73n
DQS9B/DIFFIO_RX_B65p
DQSn9B/DIFFIO_RX_B65n
DQ11B/DIFFIO_TX_B77p
DQ11B/DIFFIO_TX_B81p
DIFFIO_TX_B62n
DQ11B/DIFFIO_TX_B83p
DIFFIO_TX_B64n
DIFFIO_TX_B66n
DIFFIO_TX_B74n
DIFFIO_TX_B68n
DIFFIO_TX_B77n
DIFFIO_TX_B70n
DIFFIO_TX_B81n
DIFFIO_TX_B72n
DIFFIO_TX_B83n
AD24
AU24
AT24
AL24
AH24
AW24
AW23
AP24
AU23
AT23
QDRII_Q0
QDRII_Q2
QDRII_Q1
QDRII_Q3
QDRII_Q6
QDRII_Q8
QDRII_Q7
QDRII_Q9
QDRII_Q11
QDRII_Q10
AF24
AE24
QDRII_Q5
QDRII_Q4
AG27
AE27
AC24
AD26
AN26
AJ25
AR25
AD23
AK24
AG24
AN24
QDRII_A13
QDRII_A14
QDRII_A15
QDRII_A16
QDRII_A17
QDRII_A18
QDRII_RPSn
QDRII_C_P
QDRII_WPSn
QDRII_C_N
QDRII_DOFFn
AP22
AW20
AW19
AL22
AH22
AU20
AT20
AK21
QDRII_Q24
QDRII_Q26
QDRII_Q25
FM_D12
QDRII_Q27
QDRII_Q29
QDRII_Q28
QDRII_Q30
AT21
AR21
QDRII_CQ_P
QDRII_CQ_N
AN21
AP20
AH20
QDRII_Q33
FM_D4
FM_D1
AG22
AM21
AN20
AG20
FM_D2
FM_D11
FM_D3
FM_D13
QDRII+ INTERFACE
QDRII_A[20:0]
12,23
QDRII_D[35:0]
23
QDRII_Q[35:0]
12,23
D
QDRII_CQ_P
QDRII_CQ_N
QDRII_K_P
QDRII_K_N
QDRII_BWSn0
QDRII_BWSn1
QDRII_BWSn2
QDRII_BWSn3
QDRII_WPSn
QDRII_RPSn
23
23
23
23
23
23
23
23
23
23
QDRII_C_P
QDRII_C_N
QDRII_DOFFn
23
23
23
FLASH INTERFACE
FM_D[15:0]
12,26,27
FM_A[26:0]
QDRII+ QVLD = QDRII C_P
QDRII+ ODT = QDRII C_N
C
12,26,27
FLASH_OEn
FLASH_CLK
FLASH_WEn
FLASH_RDYBSYn
FLASH_CEn
FLASH_ADVn
26,27
26,27
26,27
26,27
26,27
26,27
MAX II CONTROL
MAX_OEn
MAX_CSn
MAX_WEn
MAX_CLK
27
27
27
27
5AGXB3H4F40
B
B
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
5
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 1, Bank 4
HSMC PORT A INTERFACE
HSMA_D[3:0]
30
HSMA_CLK_OUT_P[2:1]
E
VCCIO = 2.5V
U16C
VCCIO = 2.5V
U16D
HSMA_CLK_OUT_P[2:1]
Bank 4C
AM9
AW8
AW7
AV6
AK10
AU8
AU7
AP9
AR9
AT8
HSMA_RX_D_P7
HSMA_RX_D_N7
AW5
AW6
D
C
HSMA_TX_D_P15
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMA_TX_D_P4
HSMA_TX_D_P12
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMA_TX_D_P6
HSMA_RX_D_P11
HSMA_RX_D_N11
AR13
AE13
AE14
AU12
AM13
AW11
AW10
AP12
AJ13
AH13
HSMA_RX_D_P0
HSMA_RX_D_N0
AW12
AV12
HSMA_TX_D_P16
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMA_TX_D_P3
HSMA_TX_D_P11
HSMA_RX_D_P14
HSMA_RX_D_N14
USER1_LED_G3
HSMA_RX_D_P4
HSMA_RX_D_N4
AJ12
AG13
AF13
AV10
AL12
AD13
AC13
AP11
AW9
AV9
HSMA_RX_D_P5
HSMA_RX_D_N5
AU11
AT11
Bank 4A
RZQ_1/DQ22B/DIFFIO_TX_B167p
DQ20B/DIFFIO_TX_B146p
DQ20B/DIFFIO_RX_B147p
DQ21B
DQ20B/DIFFIO_RX_B147n
DQ20B/DIFFIO_TX_B148p
DQ22B/DIFFIO_TX_B163p
DQ20B/DIFFIO_TX_B150p
DQ22B/DIFFIO_TX_B165p
DQ20B/DIFFIO_RX_B151p
DQ20B/DIFFIO_RX_B151n
DIFFIO_TX_B146n
DQ20B/DIFFIO_TX_B152p
DIFFIO_TX_B148n
DQ20B/DIFFIO_RX_B153p
DIFFIO_TX_B150n
DQ20B/DIFFIO_RX_B153n
DIFFIO_TX_B152n
DIFFIO_TX_B163n
DQS20B/DIFFIO_RX_B149p
DIFFIO_TX_B165n
DQSn20B/DIFFIO_RX_B149n
DIFFIO_TX_B167n
Bank 4B
DQ17B/DIFFIO_TX_B123p
DQ17B/DIFFIO_RX_B124p
DQ17B/DIFFIO_RX_B124n
DQ17B/DIFFIO_TX_B125p
DQ17B/DIFFIO_TX_B127p
DQ17B/DIFFIO_RX_B128p
DQ17B/DIFFIO_RX_B128n
DQ17B/DIFFIO_TX_B129p
DQ17B/DIFFIO_RX_B130p
DQ17B/DIFFIO_RX_B130n
DQ19B/DIFFIO_TX_B138p
DQ19B/DIFFIO_RX_B139p
DQ19B/DIFFIO_RX_B139n
DQ19B/DIFFIO_TX_B140p
DQ19B/DIFFIO_TX_B142p
DQ19B/DIFFIO_RX_B143p
DQ19B/DIFFIO_RX_B143n
DQ19B/DIFFIO_TX_B144p
DQ19B/DIFFIO_RX_B145p
DQ19B/DIFFIO_RX_B145n
DQS17B/DIFFIO_RX_B126p
DQSn17B/DIFFIO_RX_B126n
DQ18B/DIFFIO_TX_B131p
DQ18B/DIFFIO_RX_B132p
DQ18B/DIFFIO_RX_B132n
DQ18B/DIFFIO_TX_B133p
DQ18B/DIFFIO_TX_B135p
DQ18B/DIFFIO_RX_B136p
DQ18B/DIFFIO_RX_B136n
DQ18B
DQ18B/DIFFIO_RX_B137p
DQ18B/DIFFIO_RX_B137n
DQS18B/DIFFIO_RX_B134p
DQSn18B/DIFFIO_RX_B134n
E
6,12,30
Arria V GX Bank 4
Arria V GX Bank 4
HSMA_TX_D_P7
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMA_TX_D_P0
HSMA_TX_D_P9
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMA_TX_D_P5
HSMA_RX_D_P6
HSMA_RX_D_N6
6,12,30
HSMA_CLK_OUT_N[2:1]
DQS19B/DIFFIO_RX_B141p
DQSn19B/DIFFIO_RX_B141n
DIFFIO_TX_B123n
DIFFIO_TX_B125n
DIFFIO_TX_B127n
DIFFIO_TX_B129n
DIFFIO_TX_B131n
DIFFIO_TX_B133n
DIFFIO_TX_B135n
DIFFIO_TX_B138n
DIFFIO_TX_B140n
DIFFIO_TX_B142n
DIFFIO_TX_B144n
AP7
AH8
AU6
AL8
HSMA_TX_D_P1
HSMA_TX_D_P8
AL9
AV7
AK9
AN9
AT6
AK8
AN7
HSMA_TX_D_N7
HSMA_TX_D_N0
HSMA_TX_D_N9
HSMA_TX_D_N5
HSMA_TX_D_N1
HSMA_TX_D_N8
SFP_TX_RS12
AD11
AG12
AF12
AU9
AE12
AR10
AP10
AL11
AM10
AL10
HSMA_TX_D_P14
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMA_TX_D_P2
HSMA_TX_D_P13
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMA_TX_D_P10
HSMA_RX_D_P10
HSMA_RX_D_N10
AH11
AG11
HSMA_RX_D_P12
HSMA_RX_D_N12
AP13
AT12
AL13
AN12
AH12
AU10
AK12
AC12
AT9
AD12
AK11
HSMA_TX_D_N15
HSMA_TX_D_N4
HSMA_TX_D_N12
HSMA_TX_D_N6
HSMA_TX_D_N16
HSMA_TX_D_N3
HSMA_TX_D_N11
HSMA_TX_D_N14
HSMA_TX_D_N2
HSMA_TX_D_N13
HSMA_TX_D_N10
SFP_SDA2
HSMA_PRSNTn
MAX_CTL2
SFP_SCL2
USER1_LED_R0
HSMA_D3
HSMA_D2
USER1_LED_R7
HSMA_SCL
HSMA_RX_LED
AP15
AW15
AW14
AD16
AL15
AW13
AV13
AH15
AU15
AT15
HSMA_D1
HSMA_D0
AH16
AG16
SFP_TX_DIS1
SFP_SDA1
USER1_LED_G7
AN15
AC16
AK15
DQS15B/DIFFIO_RX_B111p
DQSn15B/DIFFIO_RX_B111n
DQ16B/DIFFIO_TX_B115p
DQ16B/DIFFIO_RX_B116p
DQ16B/DIFFIO_RX_B116n
DQ16B/DIFFIO_TX_B117p
DQ16B/DIFFIO_TX_B119p
DQ16B/DIFFIO_RX_B120p
DQ16B/DIFFIO_RX_B120n
DQ16B/DIFFIO_TX_B121p
DQ16B/DIFFIO_RX_B122p
DQ16B/DIFFIO_RX_B122n
DQS16B/DIFFIO_RX_B118p
DQSn16B/DIFFIO_RX_B118n
DIFFIO_TX_B108n
DIFFIO_TX_B110n
DIFFIO_TX_B112n
DIFFIO_TX_B115n
DIFFIO_TX_B117n
DIFFIO_TX_B119n
DIFFIO_TX_B121n
AF15
AE16
USER1_LED_G6
USER1_LED_G5
AC15
AT13
AK14
AG14
USER1_LED_R1
HSMA_CLK_OUT_N1
USER1_LED_R5
USER1_LED_R6
MAX_BEn3
ENET_TX_D2
ENET_TX_D3
ENET_TX_EN
ENET_MDC
ENET_TX_D0
ENET_TX_D1
ENET_TX_P
ENET_RX_D2
ENET_RX_DV
AW18
AH19
AG19
AP19
AJ18
AT19
AU18
AF19
AW16
AW17
ENET_RX_P
ENET_RX_N
AL19
AK19
ENET_MDIO
ENET_RX_D0
ENET_RX_D1
MAX_CTL1
PCIE_LED_X1
MAX_BEn0
MAX_BEn1
MAX_CTL0
SFP_OP_TX_FLT2
SFP_SCL1
AL17
AU17
AT17
AD19
AC18
AE18
AD18
AG18
AM18
AL18
HSMA_RX_D_P1
HSMA_RX_D_N1
AR18
AP18
DQ12B/DIFFIO_TX_B85p
DQ12B/DIFFIO_RX_B86p
DQ12B/DIFFIO_RX_B86n
DQ12B/DIFFIO_TX_B87p
DQ12B/DIFFIO_TX_B89p
DQ12B/DIFFIO_RX_B90p
DQ12B/DIFFIO_RX_B90n
DQ12B/DIFFIO_TX_B91p
DQ12B/DIFFIO_RX_B92p
DQ12B/DIFFIO_RX_B92n
DQ14B/DIFFIO_TX_B100p
DQ14B/DIFFIO_RX_B101p
DQ14B/DIFFIO_RX_B101n
DQ14B/DIFFIO_TX_B102p
DQ14B/DIFFIO_TX_B104p
DQ14B/DIFFIO_RX_B105p
DQ14B/DIFFIO_RX_B105n
DQ14B/DIFFIO_TX_B106p
DQ14B/DIFFIO_RX_B107p
DQ14B/DIFFIO_RX_B107n
DQS12B/DIFFIO_RX_B88p
DQSn12B/DIFFIO_RX_B88n
DQS14B/DIFFIO_RX_B103p
DQSn14B/DIFFIO_RX_B103n
DQ13B/DIFFIO_TX_B93p
DQ13B/DIFFIO_RX_B94p
DQ13B/DIFFIO_RX_B94n
DQ13B/DIFFIO_TX_B95p
DQ13B/DIFFIO_TX_B97p
DQ13B/DIFFIO_RX_B98p
DQ13B/DIFFIO_RX_B98n
DQ13B
DQ13B/DIFFIO_RX_B99p
DQ13B/DIFFIO_RX_B99n
DQS13B/DIFFIO_RX_B96p
DQSn13B/DIFFIO_RX_B96n
DIFFIO_TX_B85n
DIFFIO_TX_B87n
DIFFIO_TX_B89n
DIFFIO_TX_B91n
DIFFIO_TX_B93n
DIFFIO_TX_B95n
DIFFIO_TX_B97n
DIFFIO_TX_B100n
DIFFIO_TX_B102n
DIFFIO_TX_B104n
DIFFIO_TX_B106n
B
30
HSMA_TX_D_N[16:0]
30
HSMA_RX_D_P[16:0]
30
HSMA_RX_D_N[16:0]
30
HSMA_SDA
HSMA_SCL
HSMA_CLK_OUT0
HSMA_TX_LED
HSMA_RX_LED
HSMA_PRSNTn
30
30
30
34
34
27,30,34
D
ETHERNET INTERFACE
ENET_TX_D[3:0]
AH17
AP17
AN17
AT16
AK16
AP16
AN16
AM16
AF16
AE17
SFP_OP_RX_LOS2
AV16
AU16
FPGA1_CLOCK_SDA
FPGA1_CLOCK_SCL
AV18
AN19
AH18
AE19
AK17
AC19
AD17
AG17
AR16
AJ16
AL16
PCIE_SMBCLK
SFP_OP_RX_LOS1
ENET_RX_D3
ENET_TX_N
ENET_RESETn
32
ENET_RX_D[3:0]
ENET_LED_LINK1000
PCIE_LED_X8
SFP_MOD_ABS1
ENET_INTn
ENET_GTX_CLK
PCIE_SMBDAT
FLASH_ACCESSn
32
ENET_GTX_CLK
ENET_TX_EN
ENET_RX_P
ENET_RX_N
ENET_RX_DV
ENET_LED_LINK1000
ENET_INTn
ENET_RESETn
ENET_MDIO
ENET_MDC
ENET_TX_P
ENET_TX_N
32
32
32
32
32
32
32
32
32
32
32
32
C
PCIE INTERFACE
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
PCIE_WAKEn
PCIE_SMBCLK
PCIE_SMBDAT
FPGA2_PCIE_PERSTn
PCIE_LED_X4
SFP_OP_TX_FLT1
FPGA2_PCIE_PERSTn
SFP_MOD_ABS2
PCIE_WAKEn
34
34
34
4
4
4
14
MAX II CONTROL
Version = 1.86 Pin-out
R293
R292
6,12,30
HSMA_TX_D_P[16:0]
5AGXB3H4F40
FPGA1_CLOCK_SDA
FPGA1_CLOCK_SCL
6,12,30
HSMA_CLK_OUT_N[2:1]
USER1_LED_R2
USER1_LED_G4
HSMA_SDA
HSMA_CLK_OUT_P1
HSMA_CLK_OUT0
SFP_TX_RS02
SFP_TX_RS01
HSMA_TX_LED
SFP_TX_RS11
SFP_TX_DIS2
Bank 4D
5AGXB3H4F40
Version = 1.86 Pin-out
DQ15B/DIFFIO_TX_B108p
DQ15B/DIFFIO_RX_B109p
DQ15B/DIFFIO_RX_B109n
DQ15B/DIFFIO_TX_B110p
DQ15B/DIFFIO_TX_B112p
DQ15B/DIFFIO_RX_B113p
DQ15B/DIFFIO_RX_B113n
DQ15B
DQ15B/DIFFIO_RX_B114p
DQ15B/DIFFIO_RX_B114n
AD14
AU14
AT14
AU13
AL14
AP14
AN14
AH14
AE15
AD15
MAX_CTL[2:0]
DNICLOCK_SDA
DNICLOCK_SDA
SPF+ INTERFACE
SFP_TX_RS0[2:1]
SFP_TX_RS1[2:1]
SFP_OP_RX_LOS[2:1]
SFP_OP_TX_FLT[2:1]
SFP_TX_DIS[2:1]
SFP_MOD_ABS[2:1]
SFP_SCL[2:1]
27
MAX_BEn[3:0]
28
USER1_LED_R[7:0]
28
USER1_LED_G[7:0]
28
FLASH_ACCESSn
28
12,27
12,34
7,34
27
CLOCK_SDA
CLOCK_SCL
28
B
10,11,27
10,11,27
28
28
SFP_SDA[2:1]
28
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
6
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 1, Bank 7
E
E
VCCIO = 2.5V
VCCIO = 2.5V
U16E
U16F
Arria V GX Bank 7
Arria V GX Bank 7
Bank 7A
C2C_DOUT_P4
C2C_DOUT_P5
F7
C7
K7
D
C2C_DOUT_N4
C2C_DOUT_N5
C2C_DOUT_N0
C2C_DOUT_N1
C2C_DOUT_N2
C2C_DOUT_N3
G6
G7
D7
G9
L9
C9
J9
DQ1T/DIFFIO_TX_T4p
DQ1T/DIFFIO_TX_T6p
Bank 7C
RZQ_5/DQ1T/DIFFIO_TX_T2p
DQ3T/DIFFIO_RX_T16p
DQ3T/DIFFIO_RX_T16n
DQ3T/DIFFIO_TX_T17p
DQ3T/DIFFIO_RX_T18p
DQ3T/DIFFIO_RX_T18n
DQ3T/DIFFIO_TX_T19p
DQ3T/DIFFIO_TX_T21p
DQ3T/DIFFIO_RX_T22p
DQ3T/DIFFIO_RX_T22n
DQ3T/DIFFIO_TX_T23p
DQ2T
DIFFIO_TX_T2n
DIFFIO_TX_T4n
DIFFIO_TX_T6n
DIFFIO_TX_T17n
DIFFIO_TX_T19n
DIFFIO_TX_T21n
DIFFIO_TX_T23n
DQS3T/DIFFIO_RX_T20p
DQSn3T/DIFFIO_RX_T20n
F6
D9
E9
F9
C8
D8
K9
B9
A9
A8
H9
C2C_DIN_P22
C2C_DIN_N22
C2C_DOUT_P17
C2C_DIN_P23
C2C_DIN_N23
C2C_DOUT_P18
C2C_DOUT_P19
C2C_DIN_P25
C2C_DIN_N25
C2C_DOUT_P20
C2C_DIN_P0
C2C_DIN_N0
C2C_DOUT_P0
C2C_DIN_P1
C2C_DIN_N1
C2C_DOUT_P1
C2C_DOUT_P2
C2C_DIN_P3
C2C_DIN_N3
C2C_DOUT_P3
A7
B7
Bank 7B
C
C2C_DIN_P10
C2C_DIN_N10
C2C_DOUT_P6
C2C_DIN_P11
C2C_DIN_N11
C2C_DOUT_P7
C2C_DOUT_P8
C2C_DIN_P13
C2C_DIN_N13
C2C_DOUT_P9
E10
F10
N10
B10
C10
H10
R11
A11
A10
J11
C2C_DIN_P12
C2C_DIN_N12
P12
R12
C2C_DIN_P14
C2C_DIN_N14
USER1_LED_G2
C2C_DIN_P15
C2C_DIN_N15
C2C_DOUT_P10
C2C_DOUT_P11
C2C_DIN_P17
C2C_DIN_N17
C2C_DOUT_P12
M12
N12
F11
C11
D11
K12
F12
P13
R13
H12
C2C_DIN_P16
C2C_DIN_N16
D12
E12
DQ4T/DIFFIO_RX_T24p
DQ4T/DIFFIO_RX_T24n
DQ4T/DIFFIO_TX_T25p
DQ4T/DIFFIO_RX_T26p
DQ4T/DIFFIO_RX_T26n
DQ4T/DIFFIO_TX_T27p
DQ4T/DIFFIO_TX_T29p
DQ4T/DIFFIO_RX_T30p
DQ4T/DIFFIO_RX_T30n
DQ4T/DIFFIO_TX_T31p
DQS4T/DIFFIO_RX_T28p
DQSn4T/DIFFIO_RX_T28n
DQ5T/DIFFIO_RX_T32p
DQ5T/DIFFIO_RX_T32n
DQ5T
DQ5T/DIFFIO_RX_T33p
DQ5T/DIFFIO_RX_T33n
DQ5T/DIFFIO_TX_T34p
DQ5T/DIFFIO_TX_T36p
DQ5T/DIFFIO_RX_T37p
DQ5T/DIFFIO_RX_T37n
DQ5T/DIFFIO_TX_T38p
DQ6T/DIFFIO_RX_T39p
DQ6T/DIFFIO_RX_T39n
DQ6T/DIFFIO_TX_T40p
DQ6T/DIFFIO_RX_T41p
DQ6T/DIFFIO_RX_T41n
DQ6T/DIFFIO_TX_T42p
DQ6T/DIFFIO_TX_T44p
DQ6T/DIFFIO_RX_T45p
DQ6T/DIFFIO_RX_T45n
DQ6T/DIFFIO_TX_T46p
DQS6T/DIFFIO_RX_T43p
DQSn6T/DIFFIO_RX_T43n
DIFFIO_TX_T25n
DIFFIO_TX_T27n
DIFFIO_TX_T29n
DIFFIO_TX_T31n
DIFFIO_TX_T34n
DIFFIO_TX_T36n
DIFFIO_TX_T38n
DIFFIO_TX_T40n
DIFFIO_TX_T42n
DIFFIO_TX_T44n
DIFFIO_TX_T46n
B12
C12
M13
A13
A12
J13
A14
C14
D14
G13
C2C_DIN_P18
C2C_DIN_N18
C2C_DOUT_P13
C2C_DIN_P19
C2C_DIN_N19
C2C_DOUT_P14
C2C_DOUT_P15
C2C_DIN_P21
C2C_DIN_N21
C2C_DOUT_P16
D13
E13
C2C_DIN_P20
C2C_DIN_N20
M11
J10
T11
K11
L12
G12
J12
N13
K13
B13
H13
C2C_DOUT_N6
C2C_DOUT_N7
C2C_DOUT_N8
C2C_DOUT_N9
C2C_DOUT_N10
C2C_DOUT_N11
C2C_DOUT_N12
C2C_DOUT_N13
C2C_DOUT_N14
C2C_DOUT_N15
C2C_DOUT_N16
C2C_DIN_P24
C2C_DIN_N24
R15
T15
C2C_DOUT_N17
C2C_DOUT_N18
C2C_DOUT_N19
C2C_DOUT_N20
N14
M15
P15
K14
USER1_DIPSW1
USER1_DIPSW0
C2C_DOUT_P24
USER1_DIPSW3
USER1_DIPSW2
C2C_DOUT_P25
C2C_DOUT_P26
USER1_DIPSW7
USER1_DIPSW6
C2C_DOUT_P27
N18
P18
M17
B16
C16
J17
R17
C17
D17
K18
USER1_DIPSW5
USER1_DIPSW4
F17
G17
USER1_PB1
USER1_PB0
USER1_LED_G1
LCD1_CSn
USER1_PB2
C2C_FPGA2_CLKIN_P
C2C_DOUT_P28
C2C_DIN_P5
C2C_DIN_N5
LCD1_DATA7
R19
T19
R18
E18
F18
H18
B18
A17
A16
L19
C2C_DIN_P4
C2C_DIN_N4
N19
P19
DQ7T/DIFFIO_RX_T47p
DQ7T/DIFFIO_RX_T47n
DQ7T/DIFFIO_TX_T48p
DQ7T/DIFFIO_RX_T49p
DQ7T/DIFFIO_RX_T49n
DQ7T/DIFFIO_TX_T50p
DQ7T/DIFFIO_TX_T52p
DQ7T/DIFFIO_RX_T53p
DQ7T/DIFFIO_RX_T53n
DQ7T/DIFFIO_TX_T54p
DQ8T/DIFFIO_RX_T55p
DQ8T/DIFFIO_RX_T55n
DQ8T
DQ8T/DIFFIO_RX_T56p
DQ8T/DIFFIO_RX_T56n
DQ8T/DIFFIO_TX_T57p
DQ8T/DIFFIO_TX_T59p
DQ8T/DIFFIO_RX_T60p
DQ8T/DIFFIO_RX_T60n
DQ8T/DIFFIO_TX_T61p
DQS7T/DIFFIO_RX_T51p
DQSn7T/DIFFIO_RX_T51n
DQS8T/DIFFIO_RX_T58p
DQSn8T/DIFFIO_RX_T58n
DIFFIO_TX_T48n
DIFFIO_TX_T50n
DIFFIO_TX_T52n
DIFFIO_TX_T54n
DIFFIO_TX_T57n
DIFFIO_TX_T59n
DIFFIO_TX_T61n
P16
R16
C15
M16
N16
H15
A15
D16
E16
J16
C2C_DIN_P26
C2C_DIN_N26
USER1_LED_G0
C2C_DIN_P27
C2C_DIN_N27
C2C_DOUT_P21
C2C_DOUT_P22
C2C_DIN_P2
C2C_DIN_N2
C2C_DOUT_P23
USER I/O INTERFACES
USER1_LED_G[7:0]
DQS5T/DIFFIO_RX_T35p
DQSn5T/DIFFIO_RX_T35n
Version = 1.86 Pin-out
DQ9T/DIFFIO_RX_T62p
DQ9T/DIFFIO_RX_T62n
DQ9T/DIFFIO_TX_T63p
DQ9T/DIFFIO_RX_T64p
DQ9T/DIFFIO_RX_T64n
DQ9T/DIFFIO_TX_T65p
DQ9T/DIFFIO_TX_T67p
DQ9T/DIFFIO_RX_T68p
DQ9T/DIFFIO_RX_T68n
DQ9T/DIFFIO_TX_T69p
DQS9T/DIFFIO_RX_T66p
DQSn9T/DIFFIO_RX_T66n
DQ10T/DIFFIO_RX_T70p
DQ10T/DIFFIO_RX_T70n
DQ10T
DQ10T/DIFFIO_RX_T71p
DQ10T/DIFFIO_RX_T71n
DQ10T/DIFFIO_TX_T72p
DQ10T/DIFFIO_TX_T74p
DQ10T/DIFFIO_RX_T75p
DQ10T/DIFFIO_RX_T75n
DQ10T/DIFFIO_TX_T76p
DQS10T/DIFFIO_RX_T73p
DQSn10T/DIFFIO_RX_T73n
DQ11T/DIFFIO_RX_T77p
DQ11T/DIFFIO_RX_T77n
DQ11T/DIFFIO_TX_T78p
DQ11T/DIFFIO_RX_T79p
DQ11T/DIFFIO_RX_T79n
DQ11T/DIFFIO_TX_T80p
DQ11T/DIFFIO_TX_T82p
DQ11T/DIFFIO_RX_T83p
DQ11T/DIFFIO_RX_T83n
DQ11T/DIFFIO_TX_T84p
DQS11T/DIFFIO_RX_T81p
DQSn11T/DIFFIO_RX_T81n
DIFFIO_TX_T63n
DIFFIO_TX_T65n
DIFFIO_TX_T67n
DIFFIO_TX_T69n
DIFFIO_TX_T72n
DIFFIO_TX_T74n
DIFFIO_TX_T76n
DIFFIO_TX_T78n
DIFFIO_TX_T80n
DIFFIO_TX_T82n
DIFFIO_TX_T84n
6,34
USER1_PB[2:0]
34
USER1_DIPSW[7:0]
34
D
LCD INTERFACE
G16
H16
C2C_DIN_P28
C2C_DIN_N28
J15
B15
K16
C2C_DOUT_N21
C2C_DOUT_N22
C2C_DOUT_N23
F19
G19
J19
C19
D19
J20
R20
F20
G20
M20
C2C_DIN_P6
C2C_DIN_N6
LCD1_DATA5
C2C_DIN_P7
C2C_DIN_N7
LCD1_DATA3
LCD1_DATA1
C2C_DIN_P9
C2C_DIN_N9
LCD1_WEn
A18
A19
C2C_DIN_P8
C2C_DIN_N8
N17
K17
T17
L18
J18
C18
M19
K19
K20
T20
N20
C2C_DOUT_N24
C2C_DOUT_N25
C2C_DOUT_N26
C2C_DOUT_N27
C2C_FPGA2_CLKIN_N
C2C_DOUT_N28
LCD1_D_Cn
LCD1_DATA6
LCD1_DATA4
LCD1_DATA2
LCD1_DATA0
LCD1_DATA[7:0]
34
LCD1_CSn
LCD1_D_Cn
LCD1_WEn
Bank 7D
5AGXB3H4F40
B
R14
T14
M14
F14
G14
L15
N15
E15
F15
J14
34
34
34
CHIP-TO-CHIP INTERFACE
C2C_DIN_P[28:0]
18
C2C_DIN_N[28:0]
18
C2C_DOUT_P[28:0]
18
C
C2C_DOUT_N[28:0]
18
C2C_FPGA2_CLKIN_P
C2C_FPGA2_CLKIN_N
13
13
B
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
7
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 1, Bank 8
E
E
VCCIO = 1.5V
U16G
VCCIO = 1.5V
U16H
Arria V GX Bank 8
Bank 8A
D
DDR3A_DQS_P1
DDR3A_DQS_N1
DDR3A_CSn
DDR3A_RASn
DDR3A_RESETn
DDR3A_CASn
B30
C30
E31
B31
A30
A31
H31
C31
D31
C32
A33
B33
F31
A32
J31
D32
K32
DQ20T/DIFFIO_RX_T146p
DQ20T/DIFFIO_RX_T146n
DQ20T/DIFFIO_TX_T147p
DQ20T/DIFFIO_RX_T148p
DQ20T/DIFFIO_RX_T148n
DQ20T/DIFFIO_TX_T149p
DQ20T/DIFFIO_TX_T151p
DQ20T/DIFFIO_RX_T152p
DQ20T/DIFFIO_RX_T152n
DQ20T/DIFFIO_TX_T153p
DQ21T/DIFFIO_RX_T154p
DQ21T/DIFFIO_RX_T154n
DQ21T/DIFFIO_TX_T155p
DQ21T/DIFFIO_RX_T156p
DQ21T/DIFFIO_RX_T156n
DQ21T/DIFFIO_TX_T157p
DQ21T/DIFFIO_TX_T159p
DQ21T/DIFFIO_TX_T161p
DQS21T/DIFFIO_RX_T158p
DQSn21T/DIFFIO_RX_T158n
DQS20T/DIFFIO_RX_T150p
DQSn20T/DIFFIO_RX_T150n
DQ22T
DQ22T/DIFFIO_TX_T166p
DQ22T/DIFFIO_TX_T168p
DIFFIO_TX_T147n
DIFFIO_TX_T149n
DIFFIO_TX_T151n
DIFFIO_TX_T153n
DIFFIO_TX_T155n
DIFFIO_TX_T157n
DIFFIO_TX_T159n
DIFFIO_TX_T161n
DIFFIO_TX_T166n
F33
DDR3A_DQ48
DDR3A_DQ51
DDR3A_DQ54
DDR3A_DQ53
DDR3A_DM6
DDR3A_DQ49
DDR3A_DQ55
DDR3A_DQ50
DDR3A_DQ52
T26
T25
G25
N24
P24
R24
K24
D25
E25
P25
L33 DDR3A_DQS_P0
M33 DDR3A_DQS_N0
DDR3A_DQS_P6
DDR3A_DQS_N6
A25
B25
J33
F32
E33
DDR3A_A2
DDR3A_ODT
K34
M31
M34
G32
DDR3A_BA2
DDR3A_A13
DDR3A_A0
DDR3A_A5
DDR3A_DQ47
DDR3A_DQ41
DDR3A_DQ42
DDR3A_DQ46
DDR3A_DQ44
DDR3A_DM5
DDR3A_DQ40
DDR3A_DQ45
DDR3A_DQ43
C26
D26
K25
R26
T27
A26
J26
F26
G26
M25
N31
P31
J32
M32
N32
J34
L31
L34
RZQIN_1_5V
DDR3A_DQ1
DDR3A_DQ6
DDR3A_DQ7
DDR3A_DM0
DDR3A_DQ4
DDR3A_DQ5
DDR3A_DQ3
100, 1%
R349
Bank 8B
C
DDR3A_DQ26
DDR3A_DQ31
DDR3A_DM3
DDR3A_DQ25
DDR3A_DQ29
DDR3A_DQ27
DDR3A_DQ24
DDR3A_DQ30
DDR3A_DQ28
L28
M28
H28
C28
D28
F28
J29
M29
N29
F29
DDR3A_DQS_P3
DDR3A_DQS_N3
R29
T29
DDR3A_A10
DDR3A_A12
DDR3A_CKE
DDR3A_WEn
J28
G28
K29
G29
DQ18T/DIFFIO_RX_T131p
DQ18T/DIFFIO_RX_T131n
DQ18T/DIFFIO_TX_T132p
DQ18T/DIFFIO_RX_T133p
DQ18T/DIFFIO_RX_T133n
DQ18T/DIFFIO_TX_T134p
DQ18T/DIFFIO_TX_T136p
DQ18T/DIFFIO_RX_T137p
DQ18T/DIFFIO_RX_T137n
DQ18T/DIFFIO_TX_T138p
DQS18T/DIFFIO_RX_T135p
DQSn18T/DIFFIO_RX_T135n
DDR3A_DQ[71:0]
Bank 8C
RZQ_6/DIFFIO_TX_T168n
DDR3A_DQ10
DDR3A_DQ9
DDR3A_DQ13
DDR3A_DQ12
DDR3A_DQ8
DDR3A_DQ14
DDR3A_DQ11
DDR3A_DQ15
DDR3A_DM1
DDR3A x72 INTERFACE
Arria V GX Bank 8
DQ19T/DIFFIO_RX_T139p
DQ19T/DIFFIO_RX_T139n
DQ19T
DQ19T/DIFFIO_RX_T140p
DQ19T/DIFFIO_RX_T140n
DQ19T/DIFFIO_TX_T141p
DQ19T/DIFFIO_TX_T143p
DQ19T/DIFFIO_RX_T144p
DQ19T/DIFFIO_RX_T144n
DQ19T/DIFFIO_TX_T145p
DQS19T/DIFFIO_RX_T142p
DQSn19T/DIFFIO_RX_T142n
DIFFIO_TX_T132n
DIFFIO_TX_T134n
DIFFIO_TX_T136n
DIFFIO_TX_T138n
DIFFIO_TX_T141n
DIFFIO_TX_T143n
DIFFIO_TX_T145n
B28
C29
R30
A29
A28
L30
J30
D30
D29
F30
DDR3A_DQ23
DDR3A_DQ17
DDR3A_DQ18
DDR3A_DQ19
DDR3A_DQ21
DDR3A_DQ20
DDR3A_DQ22
DDR3A_DQ16
DDR3A_DM2
N30 DDR3A_DQS_P2
P30 DDR3A_DQS_N2
M30 DDR3A_A9
K30 DDR3A_A7
G30 DDR3A_BA0
5AGXB3H4F40
DDR3A_DQS_P5
DDR3A_DQS_N5
M26
N26
DDR3A_A11
DDR3A_A8
DDR3A_A6
M21
D21
R21
DDR3A_DQ69
DDR3A_DQ68
DDR3A_DQ71
DDR3A_DQ70
DDR3A_DQ65
DDR3A_DQ67
DDR3A_DM8
J22
E22
F22
A23
L22
N22
P22
R22
DDR3A_DQS_P8
DDR3A_DQS_N8
C23
D23
USB_DATA1
USB_DATA2
USB_DATA4
USB_DATA5
N21
E21
T21
A24
Version = 1.86. Pin-out
B
DQ15T/DIFFIO_RX_T108p
DQ15T/DIFFIO_RX_T108n
DQ15T/DIFFIO_TX_T109p
DQ15T/DIFFIO_RX_T110p
DQ15T/DIFFIO_RX_T110n
DQ15T/DIFFIO_TX_T111p
DQ15T/DIFFIO_TX_T113p
DQ15T/DIFFIO_RX_T114p
DQ15T/DIFFIO_RX_T114n
DQ15T/DIFFIO_TX_T115p
DQS15T/DIFFIO_RX_T112p
DQSn15T/DIFFIO_RX_T112n
DQ17T/DIFFIO_RX_T123p
DQ17T/DIFFIO_RX_T123n
DQ17T/DIFFIO_TX_T124p
DQ17T/DIFFIO_RX_T125p
DQ17T/DIFFIO_RX_T125n
DQ17T/DIFFIO_TX_T126p
DQ17T/DIFFIO_TX_T128p
DQ17T/DIFFIO_RX_T129p
DQ17T/DIFFIO_RX_T129n
DQ17T/DIFFIO_TX_T130p
DQS17T/DIFFIO_RX_T127p
DQSn17T/DIFFIO_RX_T127n
DQ16T/DIFFIO_RX_T116p
DQ16T/DIFFIO_RX_T116n
DQ16T
DQ16T/DIFFIO_RX_T117p
DQ16T/DIFFIO_RX_T117n
DQ16T/DIFFIO_TX_T118p
DQ16T/DIFFIO_TX_T120p
DQ16T/DIFFIO_RX_T121p
DQ16T/DIFFIO_RX_T121n
DQ16T/DIFFIO_TX_T122p
DQS16T/DIFFIO_RX_T119p
DQSn16T/DIFFIO_RX_T119n
Bank 8D
DQ12T/DIFFIO_TX_T86p
DQ12T/DIFFIO_TX_T88p
DQ12T/DIFFIO_TX_T92p
DQ13T
DQ13T/DIFFIO_RX_T94p
DQ13T/DIFFIO_RX_T94n
DQ13T/DIFFIO_TX_T95p
DQ13T/DIFFIO_TX_T97p
DQ13T/DIFFIO_RX_T98p
DQ13T/DIFFIO_RX_T98n
DQ13T/DIFFIO_TX_T99p
DQS13T/DIFFIO_RX_T96p
DQSn13T/DIFFIO_RX_T96n
DIFFIO_TX_T86n
DIFFIO_TX_T88n
DIFFIO_TX_T92n
DIFFIO_TX_T95n
DIFFIO_TX_T109n
DIFFIO_TX_T111n
DIFFIO_TX_T113n
DIFFIO_TX_T115n
DIFFIO_TX_T118n
DIFFIO_TX_T120n
DIFFIO_TX_T122n
DIFFIO_TX_T124n
DIFFIO_TX_T126n
DIFFIO_TX_T128n
DIFFIO_TX_T130n
DQ14T/DIFFIO_RX_T100p
DQ14T/DIFFIO_RX_T100n
DQ14T/DIFFIO_TX_T101p
DQ14T/DIFFIO_RX_T102p
DQ14T/DIFFIO_RX_T102n
DQ14T/DIFFIO_TX_T103p
DQ14T/DIFFIO_TX_T105p
DQ14T/DIFFIO_RX_T106p
DQ14T/DIFFIO_RX_T106n
DQ14T/DIFFIO_TX_T107p
DQS14T/DIFFIO_RX_T104p
DQSn14T/DIFFIO_RX_T104n
DIFFIO_TX_T97n
DIFFIO_TX_T99n
DIFFIO_TX_T101n
DIFFIO_TX_T103n
DIFFIO_TX_T105n
DIFFIO_TX_T107n
P27
R27
H27
B27
C27
E27
K27
M27
N27
N28
DDR3A_DQ32
DDR3A_DQ34
DDR3A_DQ37
DDR3A_DQ33
DDR3A_DQ35
DDR3A_DM4
DDR3A_DQ39
DDR3A_DQ36
DDR3A_DQ38
DDR3A_DQ56
DDR3A_DQ58
DDR3A_DQ61
DDR3A_DM7
DDR3A_DQ59
DDR3A_DQ63
DDR3A_DQ57
DDR3A_DQ60
DDR3A_DQ62
USB_EMPTY
D24
E24
DDR3A_DQS_P7
DDR3A_DQS_N7
M22
T22
T23
N23
K23
J24
USB_DATA6
USB_DATA7
USB_ADDR0
USB_ADDR1
USB_DATA3
USB_DATA0
21,22
DDR3A_DQS_N[8:0]
21,22
DDR3A_DM[8:0]
21,22
DDR3A_BA[2:0]
D
21,22
DDR3A_CSn
DDR3A_CASn
DDR3A_CKE
DDR3A_WEn
DDR3A_RASn
DDR3A_ODT
DDR3A_RESETn
DDR3A_A1
DDR3A_BA1
DDR3A_A4
USB_RESETn
USB_RDn
USB_OEn
USB_FULL
USB_WRn
USB_SDA
USB_SCL
DDR3A_A3
F23
G23
R23
B24
C24
M23
J23
F24
G24
H24
21,22
DDR3A_DQS_P[8:0]
R28 DDR3A_DQS_P4
T28 DDR3A_DQS_N4
H25
T24
L24
R25
A27
K26
N25
J27
F27
L27
P28
12,21,22
DDR3A_A[13:0]
21,22
21,22
21,22
21,22
21,22
21,22
21,22
USB INTERFACE
USB_DATA[7:0]
33
USB_ADDR[1:0]
33
USB_SDA
USB_SCL
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
USB_FULL
USB_EMPTY
33
33
33
33
33
33
33
33
C
B
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
8
of
1
46
8
7
6
5
4
3
2
1
Arria V GX Transceivers and Power (FPGA 1)
U16R
U16Q
Arria V GX Transceivers
Arria V GX Transceivers
Bank GXB_L0
E
AW37
AW36
AT39
AT38
AP39
AP38
AM39
AM38
AK39
AK38
AH39
AH38
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
4
4
4
4
4
4
4
4
10.0K
R361
PCIE_RX_P4
PCIE_RX_N4
4
4
4
4
10
10
PCIE_REFCLK_P
PCIE_REFCLK_N
REFCLK1_A_QL0_P
REFCLK1_A_QL0_N
AG32
AG33
AE31
AE32
4
4
4
4
4
4
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
SFP_RX_P1
SFP_RX_N1
SMA_A_RX_L11_P
SMA_A_RX_L11_N
AF39
AF38
AD39
AD38
AB39
AB38
Y39
Y38
V39
V38
T39
T38
R342
REFCLK3_A_QL1_P
REFCLK3_A_QL1_N
AC31
AC32
AA31
AA32
Bank GXB_R0
GXB_RX_L0p/GXB_REFCLK_L0p
GXB_RX_L0n/GXB_REFCLK_L0n
GXB_RX_L1p/GXB_REFCLK_L1p
GXB_RX_L1n/GXB_REFCLK_L1n
GXB_RX_L2p/GXB_REFCLK_L2p
GXB_RX_L2n/GXB_REFCLK_L2n
GXB_RX_L3p/GXB_REFCLK_L3p
GXB_RX_L3n/GXB_REFCLK_L3n
GXB_RX_L4p/GXB_REFCLK_L4p
GXB_RX_L4n/GXB_REFCLK_L4n
GXB_RX_L5p/GXB_REFCLK_L5p
GXB_RX_L5n/GXB_REFCLK_L5n
GXB_TX_L0p
GXB_TX_L0n
GXB_TX_L1p
GXB_TX_L1n
GXB_TX_L2p
GXB_TX_L2n
GXB_TX_L3p
GXB_TX_L3n
GXB_TX_L4p
GXB_TX_L4n
GXB_TX_L5p
GXB_TX_L5n
AU37
AU36
AR37
AR36
AN37
AN36
AL37
AL36
AJ37
AJ36
AG37
AG36
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
PCIE_TX_P4
PCIE_TX_N4
4
4
4
4
4
4
4
4
C2C_TXB_P0
C2C_TXB_N0
C2C_TXB_P1
C2C_TXB_N1
C2C_TXB_P2
C2C_TXB_N2
C2C_TXB_P3
C2C_TXB_N3
4
4
C2C_TXB_P4
C2C_TXB_N4
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C164 C2C_RXA_P0
C163 C2C_RXA_N0
C166 C2C_RXA_P1
C165 C2C_RXA_N1
C168 C2C_RXA_P2
C167 C2C_RXA_N2
C170 C2C_RXA_P3
C169 C2C_RXA_N3
HSMA_RX_P3
30
HSMA_RX_N3
30
C2C_RXA_P4
0.1uF
C172 C2C_RXA_N4
0.1uF
C171
REFCLK0_A_QR0_P
10
REFCLK0_A_QR0_N
10
REFCLK0Lp
REFCLK0Ln
REFCLK1Lp
REFCLK1Ln
10.0K
R263
AU1
AU2
AR1
AR2
AN1
AN2
AL1
AL2
AJ1
AJ2
AG1
AG2
AF8
AF7
AD9
AD8
GXB_RX_R0p/GXB_REFCLK_R0p
GXB_RX_R0n/GXB_REFCLK_R0n
GXB_RX_R1p/GXB_REFCLK_R1p
GXB_RX_R1n/GXB_REFCLK_R1n
GXB_RX_R2p/GXB_REFCLK_R2p
GXB_RX_R2n/GXB_REFCLK_R2n
GXB_RX_R3p/GXB_REFCLK_R3p
GXB_RX_R3n/GXB_REFCLK_R3n
GXB_RX_R4p/GXB_REFCLK_R4p
GXB_RX_R4n/GXB_REFCLK_R4n
GXB_RX_R5p/GXB_REFCLK_R5p
GXB_RX_R5n/GXB_REFCLK_R5n
10.0K
11
11
2.00K
R373
RREF_TL
B39
GXB_TX_L6p
GXB_TX_L6n
GXB_TX_L7p
GXB_TX_L7n
GXB_TX_L8p
GXB_TX_L8n
GXB_TX_L9p
GXB_TX_L9n
GXB_TX_L10p
GXB_TX_L10n
GXB_TX_L11p
GXB_TX_L11n
AE37
AE36
AC37
AC36
AA37
AA36
W37
W36
U37
U36
R37
R36
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
SFP_TX_P1
SFP_TX_N1
C2C_TXB_P5
C2C_TXB_N5
C2C_TXB_P6
C2C_TXB_N6
C2C_TXB_P7
C2C_TXB_N7
4
4
4
4
4
4
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
P39
P38
M39
M38
K39
K38
H39
H38
F39
F38
D39
D38
R374
SFP_RX_P2
SFP_RX_N2
SMA_A_RX_L15_P
SMA_A_RX_L15_N
B
10
10
10
10
REFCLK4_A_QL2_P
REFCLK4_A_QL2_N
REFCLK2_A_QL1_P
REFCLK2_A_QL1_N
W31
W32
U31
U32
C174 C2C_RXA_P5
C173 C2C_RXA_N5
C176 C2C_RXA_P6
C175 C2C_RXA_N6
C178 C2C_RXA_P7
C177 C2C_RXA_N7
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
30
30
30
30
30
30
SMA_A_TX_L11_P
SMA_A_TX_L11_N
10
10
REFCLK2Lp
REFCLK2Ln
REFCLK3Lp
REFCLK3Ln
10.0K
AE1
AE2
AC1
AC2
AA1
AA2
W1
W2
U1
U2
R1
R2
REFCLK2_A_QR1_P AB9
REFCLK2_A_QR1_N AB8
Y9
Y8
R262
2.00K
R233
RREF_BR
AW2
GXB_RX_R6p/GXB_REFCLK_R6p
GXB_RX_R6n/GXB_REFCLK_R6n
GXB_RX_R7p/GXB_REFCLK_R7p
GXB_RX_R7n/GXB_REFCLK_R7n
GXB_RX_R8p/GXB_REFCLK_R8p
GXB_RX_R8n/GXB_REFCLK_R8n
GXB_RX_R9p/GXB_REFCLK_R9p
GXB_RX_R9n/GXB_REFCLK_R9n
GXB_RX_R10p/GXB_REFCLK_R10p
GXB_RX_R10n/GXB_REFCLK_R10n
GXB_RX_R11p/GXB_REFCLK_R11p
GXB_RX_R11n/GXB_REFCLK_R11n
AD3
AD4
AB3
AB4
Y3
Y4
V3
V4
T3
T4
P3
P4
C2C_TXA_P5
C2C_TXA_N5
C2C_TXA_P6
C2C_TXA_N6
C2C_TXA_P7
C2C_TXA_N7
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
E
30
30
GXB_RX_L12p,GXB_REFCLK_L12p
GXB_RX_L12n,GXB_REFCLK_L12n
GXB_RX_L13p,GXB_REFCLK_L13p
GXB_RX_L13n,GXB_REFCLK_L13n
GXB_RX_L14p,GXB_REFCLK_L14p
GXB_RX_L14n,GXB_REFCLK_L14n
GXB_RX_L15p,GXB_REFCLK_L15p
GXB_RX_L15n,GXB_REFCLK_L15n
GXB_RX_L16p,GXB_REFCLK_L16p
GXB_RX_L16n,GXB_REFCLK_L16n
GXB_RX_L17p,GXB_REFCLK_L17p
GXB_RX_L17n,GXB_REFCLK_L17n
GXB_TX_R6p
GXB_TX_R6n
GXB_TX_R7p
GXB_TX_R7n
GXB_TX_R8p
GXB_TX_R8n
GXB_TX_R9p
GXB_TX_R9n
GXB_TX_R10p
GXB_TX_R10n
GXB_TX_R11p
GXB_TX_R11n
D
30
30
30
30
30
30
REFCLK2Rp
REFCLK2Rn
REFCLK3Rp
REFCLK3Rn
Reference Resistor
C
RREF_BR
RREF_TL
ONLY AVAILABLE IN GT DEVICES
Bank GXB_R2
ONLY AVAILABLE IN GT DEVICES
Bank GXB_L2
10.0K
C2C_TXA_P0
C2C_TXA_N0
C2C_TXA_P1
C2C_TXA_N1
C2C_TXA_P2
C2C_TXA_N2
C2C_TXA_P3
C2C_TXA_N3
HSMA_TX_P3
HSMA_TX_N3
C2C_TXA_P4
C2C_TXA_N4
Bank GXB_R1
GXB_RX_L6p/GXB_REFCLK_L6p
GXB_RX_L6n/GXB_REFCLK_L6n
GXB_RX_L7p/GXB_REFCLK_L7p
GXB_RX_L7n/GXB_REFCLK_L7n
GXB_RX_L8p/GXB_REFCLK_L8p
GXB_RX_L8n/GXB_REFCLK_L8n
GXB_RX_L9p/GXB_REFCLK_L9p
GXB_RX_L9n/GXB_REFCLK_L9n
GXB_RX_L10p/GXB_REFCLK_L10p
GXB_RX_L10n/GXB_REFCLK_L10n
GXB_RX_L11p/GXB_REFCLK_L11p
GXB_RX_L11n/GXB_REFCLK_L11n
Reference Resistor
C
AT3
AT4
AP3
AP4
AM3
AM4
AK3
AK4
AH3
AH4
AF3
AF4
REFCLK0Rp
REFCLK0Rn
REFCLK1Rp
REFCLK1Rn
Bank GXB_L1
D
GXB_TX_R0p
GXB_TX_R0n
GXB_TX_R1p
GXB_TX_R1n
GXB_TX_R2p
GXB_TX_R2n
GXB_TX_R3p
GXB_TX_R3n
GXB_TX_R4p
GXB_TX_R4n
GXB_TX_R5p
GXB_TX_R5n
GXB_TX_L12p
GXB_TX_L12n
GXB_TX_L13p
GXB_TX_L13n
GXB_TX_L14p
GXB_TX_L14n
GXB_TX_L15p
GXB_TX_L15n
GXB_TX_L16p
GXB_TX_L16n
GXB_TX_L17p
GXB_TX_L17n
N37
N36
L37
L36
J37
J36
G37
G36
E37
E36
C37
C36
SFP_TX_P2
SFP_TX_N2
SMA_A_TX_L15_P
SMA_A_TX_L15_N
N1
N2
L1
L2
J1
J2
G1
G2
E1
E2
C1
C2
R261
REFCLK4_A_QR2_P
REFCLK4_A_QR2_N
V9
V8
T9
T8
30
30
10.0K
10
10
REFCLK4Lp
REFCLK4Ln
REFCLK5Lp
REFCLK5Ln
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P6
HSMA_RX_N6
SMA_A_RX_R16_P
SMA_A_RX_R16_N
HSMA_RX_P7
HSMA_RX_N7
SMA_A_RX_R17_P
SMA_A_RX_R17_N
30
30
30
30
30
30
GXB_RX_R12p,GXB_REFCLK_R12p
GXB_RX_R12n,GXB_REFCLK_R12n
GXB_RX_R13p,GXB_REFCLK_R13p
GXB_RX_R13n,GXB_REFCLK_R13n
GXB_RX_R14p,GXB_REFCLK_R14p
GXB_RX_R14n,GXB_REFCLK_R14n
GXB_RX_R15p,GXB_REFCLK_R15p
GXB_RX_R15n,GXB_REFCLK_R15n
GXB_RX_R16p,GXB_REFCLK_R16p
GXB_RX_R16n,GXB_REFCLK_R16n
GXB_RX_R17p,GXB_REFCLK_R17p
GXB_RX_R17n,GXB_REFCLK_R17n
M3
M4
K3
K4
H3
H4
F3
F4
D3
D4
B3
B4
GXB_TX_R12p
GXB_TX_R12n
GXB_TX_R13p
GXB_TX_R13n
GXB_TX_R14p
GXB_TX_R14n
GXB_TX_R15p
GXB_TX_R15n
GXB_TX_R16p
GXB_TX_R16n
GXB_TX_R17p
GXB_TX_R17n
REFCLK4Rp
REFCLK4Rn
REFCLK5Rp
REFCLK5Rn
J21
30
30
30
30
30
30
30
30
B
CLOCK BUFFER BULLSEYE SMA INTERFACE
5AGXB3H4F40
SMA_A_RX_L11_P 0.1uF C80 SMA_A_6G_RX_P0 1
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P6
HSMA_TX_N6
SMA_A_TX_R16_P
SMA_A_TX_R16_N
HSMA_TX_P7
HSMA_TX_N7
SMA_A_TX_R17_P
SMA_A_TX_R17_N
BULLSEYE_SMA_CLKP
BULLSEYE_SMA_CLKN
Version = 1.86 Pin-out
11
11
5AGXB3H4F40
SMA_A_RX_L11_N 0.1uF
C81 SMA_A_6G_RX_N0 1
J22
2
3
4
5
Version = 1.86 Pin-out
SFP+ INTERFACE
CHIP-TO-CHIP XCVR INTERFACE
FPGA 2 BULLSEYE SMA INTERFACE
SFP_RX_P[2:1]
C2C_TXB_P[7:0]
SMA_B_TX_L15_P
SMA_B_TX_L15_N
SMA_B_TX_R6_P
SMA_B_TX_R6_N
20
20
20
20
SMA_B_RX_L15_P
SMA_B_RX_L15_N
SMA_B_RX_R6_P
SMA_B_RX_R6_N
20
20
20
20
2
3
4
5
SFP_RX_N[2:1]
J16
C960
C959
SMA_A_RX_R16_P
SMA_A_RX_R16_N
SMA_B_RX_L15_P
SMA_B_RX_L15_N
SMA_A_RX_R17_P
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C904
C903
C901
C902
C953
SMA_A_RX_R17_N
0.1uF
C954
SMA_A_10G_RX_P1
SMA_A_10G_RX_N1
BULLSEYE_SMA_CLKP
BULLSEYE_SMA_CLKN
SMA_A_10G_RX_P0
SMA_A_10G_RX_N0
SMA_B_10G_RX_P1
SMA_B_10G_RX_N1
SMA_A_6G_RX_P2
SMA_B_TX_R6_N
SMA_A_6G_RX_N2
1
2
3
4
22
21
16
15
11
10
7
1
2
3
4
22
21
16
15
11
10
7
12
13
9
8
18
17
20
19
5
6
14
12
13
9
8
18
17
20
19
5
6
14
SMA_A_TX_L15_P
SMA_A_TX_L15_N
SMA_A_TX_R17_P
SMA_A_TX_R17_N
SMA_A_TX_R16_P
SMA_A_TX_R16_N
SMA_B_TX_L15_P
SMA_B_TX_L15_N
SMA_B_6G_RX_N0 0.1uF
SMA_B_6G_RX_P0 0.1uF
SMA_B_TX_R6_P
SFP_TX_N[2:1]
1
SMA_A_TX_L11_P
SMA_A_TX_L11_N 1
28
28
C957
C958
SMA_B_RX_R6_N
SMA_B_RX_R6_P
20
C2C_TXB_N[7:0]
20
C2C_TXA_P[7:0]
20
C2C_TXA_N[7:0]
20
J20
J19
Title
Size
DNI
B
Date:
8
7
6
5
4
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
2
3
4
5
0.1uF
0.1uF
28
2
3
4
5
A
SMA_A_RX_L15_P
SMA_A_RX_L15_N
SFP_TX_P[2:1]
28
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
9
of
1
46
8
7
6
5
4
3
2
1
Clocks/Oscillators (1 of 2)
2.5V
2.5V
2.5V
7
CLOCK_SCL
11,27
8
3
OE
VCC
SDA
CLK+
SCL
CLK-
GND
NC
R425
9
5
2
4.7K
4
R45
100, 1%
2.5V
5
1
Si570 Programmable Oscillator
Use Clock Control GUI
(Default 100MHz)
I2C Address 00 HEX
SI570
R382
BUFFER_EN
4.7K
GL
R424
4.7K
PDn
1
8
21
6
7
100M_OSC_P
100M_OSC_N
J17
1 CLKIN_SMA_P
LTI-SASF546-P26-X1
3.3V
CLKIN_SMA_CP
CLKIN_SMA_CN
124
124
R54
R55
100, 1%
100, 1%
CLKIN_SMA_CP
CLKIN_SMA_CN
16
15
CLK_SEL
28
27,34
R411
R410
1 CLKIN_SMA_N
LTI-SASF546-P26-X1
J18
0.1uF
Q2p
Q2n
Gn
GL
Q3p
Q3n
PDn
Q4p
Q4n
CLK1p
CLK1n
CLK_SEL
0.1uF
C909
0.1uF
0.1uF
2.2uF
Q6p
Q6n
CLKINTOPA_P0
CLKINTOPA_N0
12
12
10
11
CLKINBOTA_P0
CLKINBOTA_N0
12
12
12
13
REFCLK1A_QL0_CP
REFCLK1A_QL0_CN
C881
0.1uF
C880
0.1uF
REFCLK1_A_QL0_P
REFCLK1_A_QL0_N
9
9
19
18
REFCLK1B_QL0_CP
REFCLK1B_QL0_CN
C926
REFCLK1_B_QL0_P
REFCLK1_B_QL0_N
20
20
24
23
CLKINTOPB_P0
CLKINTOPB_N0
13
13
26
25
CLKINBOTB_P0
CLKINBOTB_N0
13
13
C855
Y5
25.00MHz
2
5
4
3
2
4
5
6
C
CLOCK_SCL
12
CLOCK_SDA
19
CLKIN_P
CLKIN_N
CLKIN
I2C_LSB
FDBK_P
FDBK_N
INTR
SCL
CLK3B
CLK3A
SDA
CLK2B
CLK2A
CLK1B
CLK1A
CLK0B
CLK0A
DNI
B
4
DNI
C38
C407
C311
C402
C353
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
8
4.70K, 1%
1
4
5
6
BLM15AG221SN1
R249
CLOCK_SCL
12
CLOCK_SDA
19
SCL
CLOCK_SCL
12
CLOCK_SDA
19
CLKIN_P
CLKIN_N
CLKIN
I2C_LSB
FDBK_P
FDBK_N
SCL
7
24
11
15
16
20
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
CLKINTOPA_N1
CLKINTOPA_P1
13
14
REFCLK0_A_QR0_CN
REFCLK0_A_QR0_CP
C403
C404
0.1uF
0.1uF
REFCLK0_A_QR0_N
REFCLK0_A_QR0_P
9
9
17
18
REFCLK2_A_QR1_CN
REFCLK2_A_QR1_CP
C405
C406
0.1uF
0.1uF
REFCLK2_A_QR1_N
REFCLK2_A_QR1_P
9
9
21
22
REFCLK4_A_QR2_CN
REFCLK4_A_QR2_CP
C355
C354
0.1uF
0.1uF
REFCLK4_A_QR2_N
REFCLK4_A_QR2_P
SDA
9
9
CLK1B
CLK1A
CLK0B
CLK0A
C111
RSVD_GND
EPAD
DNI
LVDS
Y1
25.00MHz
2
4
U48: Si5338 Programmable Oscillator Use Clock Control GUI (Defaults
CLK0=125MHz, CLK1=100MHz, CLK2=625MHz, CLK3=125MHz)
I2C Address 71 HEX
C122
C55
2.5V_PLL1
C56
C711
C709
C777
C710
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
8
INTR
DNI
CLK3B
CLK3A
SDA
CLK2B
CLK2A
CLK1B
CLK1A
A
9
10
CLKINBOTA_N1
CLKINBOTA_P1
13
14
REFCLK2_A_QL1_CN
REFCLK2_A_QL1_CP
17
18
REFCLK3_A_BUF_N
REFCLK3_A_BUF_P
21
22
CLK0B
CLK0A
23
25
RSVD_GND
EPAD
Si5338A-CUSTOM
BLM15AG221SN1
CLOCK_SCL
12
CLOCK_SDA
19
C834
C835
0.1uF
0.1uF
REFCLK2_A_QL1_N
REFCLK2_A_QL1_P
REFCLK4_A_QL2_CN
REFCLK4_A_QL2_CP
C752
C751
0.1uF
0.1uF
REFCLK4_A_QL2_N
REFCLK4_A_QL2_P
C826
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
6
5
4
4.70K, 1%
C693
C744
0.1uF
0.1uF
REFCLK1_B_QR0_N
REFCLK1_B_QR0_P
20
20
17
18
REFCLK2_B_QR1_CN
REFCLK2_B_QR1_CP
C743
C766
0.1uF
0.1uF
REFCLK2_B_QR1_N
REFCLK2_B_QR1_P
20
20
21
22
REFCLK3_B_QR2_CN
REFCLK3_B_QR2_CP
C823
C824
0.1uF
0.1uF
REFCLK3_B_QR2_N
REFCLK3_B_QR2_P
20
20
13
13
LVDS
C
U52: Si5338 Programmable Oscillator Use Clock Control GUI (Defaults
CLK0=125MHz, CLK1=100MHz, CLK2=156.25MHz, CLK3=125MHz)
I2C Address 73 HEX
23
25
2.5V
CLKIN_P
CLKIN_N
CLKIN
I2C_LSB
FDBK_P
FDBK_N
SCL
7
24
11
15
16
20
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
C115
2.5V_PLL3
C131
C112
C99
C139
C104
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
8
INTR
CLK3B
CLK3A
SDA
L8
0.1uF
R158
BLM15AG221SN1
CLKINBOTB_N1
CLKINBOTB_P1
13
14
REFCLK0_B_QL0_CN
REFCLK0_B_QL0_CP
C132
C124
0.1uF
0.1uF
REFCLK0_B_QL0_N
REFCLK0_B_QL0_P
20
20
17
18
REFCLK2_B_QL1_CN
REFCLK2_B_QL1_CP
C123
C116
0.1uF
0.1uF
REFCLK2_B_QL1_N
REFCLK2_B_QL1_P
20
20
21
22
REFCLK4_B_QL2_CN
REFCLK4_B_QL2_CP
C114
C113
0.1uF
0.1uF
REFCLK4_B_QL2_N
REFCLK4_B_QL2_P
20
20
13
13
LVDS
23
25
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
3
B
4.70K, 1%
9
10
Size
B
Date:
7
BLM15AG221SN1
REFCLK1_B_QR0_CN
REFCLK1_B_QR0_CP
U34: Si5338 Programmable Oscillator Use Clock Control GUI (Defaults
CLK0=625MHz, CLK1=100MHz, CLK2=625MHz, CLK3=125MHz)
I2C Address 72 HEX
U53: Si5338 Programmable Oscillator Use Clock Control GUI (Defaults
CLK0=625 MHz, CLK1=156.25MHz, CLK2=125MHz, CLK3=125MHz)
I2C Address 70 HEX
0.1uF
R327
Si5338A-CUSTOM
LVDS
L12
13
14
RSVD_GND
EPAD
9
9
C822
CLKINTOPB_N1
CLKINTOPB_P1
CLK0B
CLK0A
11
11 TO CLK BUFFER (U25) NB6L11SMNG
C694
9
10
CLK1B
CLK1A
9
9
2.5V_PLL2
C856
C827
8
CLK2B
CLK2A
12
12
C825
Si5338A-CUSTOM
4
5
6
4.70K, 1%
7
24
11
15
16
20
U34
1
2
3
L13
R341
INTR
CLK3B
CLK3A
12
12
0.1uF
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
CLK2B
CLK2A
9
10
23
25
I2C_LSB
FDBK_P
FDBK_N
U53
4
5
6
8
0.1uF
CLKIN_P
CLKIN_N
CLKIN
L9
2.5V
1
2
3
1
C655
2.5V_PLL0
C39
Si5338A-CUSTOM
Y4
25.00MHz
2
3
C656
RSVD_GND
EPAD
7
24
11
15
16
20
3
DNI
DNI
1
2
3
1
C275
1
2
3
1
4
C868
2.5V
U52
U48
VDD1
VDD2
VDDO3
VDDO2
VDDO1
VDDO0
0.1uF
DNI
4
2.5V
Y2
25.00MHz
2
0.1uF
D
CLK_SEL = HIGH selects (CLK1p/n) Si570 input
CLK_SEL = LOW selects (CLK2p/n) SMA input
DNI
3
C276
E
3
4
C925
Q5p
Q5n
CLK2p
CLK2n
IDT5T9306
C923
Q1p
Q1n
C908
3
D
R422
R423
5
4
3
2
84.5
84.5
C924
VDD
VDD
VDD
GND
6,11,27
CLOCK_SDA
6
VDD
VDD
VDD
VDD
27
2
U56
0.1uF 10uF
X7
SI570_EN
14
17
20
27
C860 C928
2.5V
E
C927
29
Si570_EN
CLOCK_SDA
CLOCK_SCL
NC
4.70K, 1%
4.70K, 1%
4.70K, 1%
22
R42
R41
R40
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
10
of
1
46
8
7
6
5
4
3
2
1
Clocks/Oscillators (2 of 2)
2.5V
X1
E
1
CLK125A_EN
27
2
2.5V
6
C54
C53
0.1uF
10uF
U25
EN
OUT
NC
OUTn
VCC
4
CLKA_125_P
12
5
CLKA_125_N
12
5
13
14
15
16
3
GND
125.0MHz
11
12
9
10
REFCLK3_A_BUF_P
10
REFCLK3_A_BUF_N
10
VCC
VCC
VCC
VCC
VCC
D
VTD
VTD
D
X4
1
CLK125B_EN
27
2
2.5V
6
C40
EN
OUT
NC
OUTn
VCC
C43
4
CLKB_125_P
5
Q1
Q1
NC
GND
GND
EP_GND
1
2
REFCLK3_A_QL1_CP
REFCLK3_A_QL1_CN
3
4
BULLSEYE_SMA_CLKP
BULLSEYE_SMA_CLKN
C65
C73
0.1uF
0.1uF
REFCLK3_A_QL1_P
REFCLK3_A_QL1_N
E
9
9
9
9
6
7
8
17
NB6L11SMNG
13
CLKB_125_N
Q0
Q0
2.5V
13
C64
C74
C66
C67
C68
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
3
GND
125.0MHz
D
0.1uF
D
10uF
1.8V
C545
C544
0.1uF
10uF
1.8V
X6
1
EN
2
GND
1.8V
VCC
OUT
U51
4
2
3
3
50MHz
C
C644
C674
2.2uF
0.1uF
6
7
5
CLK50_EN
27
1.8V
R294
VDD
CLKIN
OE1
OE2
OE3
CLKOUT1
CLKOUT2
CLKOUT3
OE_OSC
GND
10K
8
9
10
CLKINA_50
CLKINB_50
CLKIN_MAX_50
12
13
27
4
C
1
SL18860DC
2.5V
Si571 Programmable Oscillator
Use Clock Control GUI
(Default 148.5MHz)
I2C Address 55 HEX
2.5V
R161
4.70K, 1%
C105 C117
0.1uF 10uF
X2
B
27
SI571_EN
2
6,10,27
CLOCK_SDA
7
10,27
CLOCK_SCL
8
3
OE
SDA
SCL
GND
VDD
CLK+
CLKVC
6
B
4
REFCLK0_B_QR0_CP
C107
5
REFCLK0_B_QR0_CN
C106
1
SI571_VCONTROL
0.1uF
REFCLK0_B_QR0_P
20
0.1uF REFCLK0_B_QR0_N
20
SI571
SDI_CLK148_UP
SDI_CLK148_DN
16
16
R138
R160
4.99K
4.99K
R139
From FPGA
C133
1.0nF
180K
C140
A
0.1uF
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
11
of
1
46
8
E
7
HSMA_CLK_IN_P1
HSMA_CLK_IN_P2
R244
R250
100, 1% HSMA_CLK_IN_N1
100, 1% HSMA_CLK_IN_N2
CLKINTOPA_P0
CLKINTOPA_P1
CLKINBOTA_P0
CLKINBOTA_P1
R304
R312
R305
R306
100, 1%
100, 1%
100, 1%
100, 1%
6
5
4
3
2
Arria V GX Clocks (FPGA 1)
CLOCKS
CLKINTOPA_P0
CLKINTOPA_N0
CLKINTOPA_P1
CLKINTOPA_N1
100, 1% CLKA_125_N
Bank 3A
AP34
AN34
AK34
AJ34
AM33
AL33
AU32
AT32
CLKA_125_P
CLKA_125_N
QDRII_A20
QDRII_A19
CLK0p/DQ1B/DIFFIO_RX_B2p
CLK0n/DQ1B/DIFFIO_RX_B2n
CLK1p/DQS1B/DIFFIO_RX_B4p
CLK1n/DQSn1B/DIFFIO_RX_B4n
CLK2p/DQ1B/DIFFIO_RX_B7p
CLK2n/DQ1B/DIFFIO_RX_B7n
CLK3p/DQ2B/DIFFIO_RX_B9p
CLK3n/DQ2B/DIFFIO_RX_B9n
10
10
10
10
CLKINA_50
CLKA_125_P
CLKA_125_N
Arria V GX Clocks
R351
10
10
10
10
CLKINBOTA_P0
CLKINBOTA_N0
CLKINBOTA_P1
CLKINBOTA_N1
CLKINTOPA_N0
CLKINTOPA_N1
CLKINBOTA_N0
CLKINBOTA_N1
U16I
CLKA_125_P
1
11
11
11
VCCIO = 1.8V
FPLL_BL_CLKOUT0/FPLL_BL_CLKOUTp/FPLL_BL_FB0/DQ1B/DIFFIO_TX_B5p
FPLL_BL_CLKOUT1/FPLL_BL_CLKOUTn/DIFFIO_TX_B5n
FPLL_BL_CLKOUT2/FPLL_BL_FBp/FPLL_BL_FB1/DQ1B/DIFFIO_RX_B6p
FPLL_BL_CLKOUT3/FPLL_BL_FBn/DQ1B/DIFFIO_RX_B6n
AM34
AL34
AK33
AJ33
FM_A4
FLASH_RESETn
FM_A6
FM_A5
CHIP-TO-CHIP INTERFACE
C2C_FPGA1_CLKIN_P
C2C_FPGA1_CLKIN_N
18
18
USB INTERFACE
USB_CLK
Bank 3D
AV19
AU19
AF21
AE21
AD20
AC21
AL20
AK20
QDRII_Q32
QDRII_Q31
CLKINA_50
QDRII_Q34
CLKINBOTA_P0
CLKINBOTA_N0
CLKINBOTA_P1
CLKINBOTA_N1
D
CLK4p/DQ10B/DIFFIO_RX_B76p
CLK4n/DQ10B/DIFFIO_RX_B76n
CLK5p/DQ11B/DIFFIO_RX_B78p
CLK5n/DQ11B/DIFFIO_RX_B78n
CLK6pDQ11B/DIFFIO_RX_B82p
CLK6nDQ11B/DIFFIO_RX_B82n
CLK7pDQ11B/DIFFIO_RX_B84p
CLK7nDQ11B/DIFFIO_RX_B84n
AR6
AP6
AW4
AV4
AT7
AR7
AK7
AJ7
ENET_RX_CLK
MAX_BEn2
C
C6
D6
A6
B6
E6
E7
H6
J6
C2C_FPGA1_CLKIN_P
C2C_FPGA1_CLKIN_N
USB_CLK
DDR3A_CLK_P
DDR3A_CLK_N
DDR3A_DQ2
DDR3A_DQ0
B
B22
C22
A22
A21
G21
H21
C20
D20
DDR3A_DQ64
DDR3A_DQ66
CLKINTOPA_P1
CLKINTOPA_N1
CLKINTOPA_P0
CLKINTOPA_N0
AC22
AD21
AH21
AG21
30
HSMA_CLK_IN_N[2:1]
30
6,30
HSMA_RX_D_N[16:0]
AM7
AL7
AP8
AN8
CLK12p/DQ1T/DIFFIO_RX_T1p
CLK12n/DQ1T/DIFFIO_RX_T1n
CLK13p/DQ1T/DIFFIO_RX_T3p
CLK13n/DQ1T/DIFFIO_RX_T3n
CLK14p/DQS1T/DIFFIO_RX_T5p
CLK14n/DQSn1T/DIFFIO_RX_T5n
CLK15p/DQ2T/DIFFIO_RX_T9p
CLK15n/DQ2T/DIFFIO_RX_T9n
F8
G8
J8
K8
FPLL_TR_CLKOUT2/FPLL_TR_FBp/FPLL_TR_FB1/DQ1T/DIFFIO_RX_T7p
FPLL_TR_CLKOUT3/FPLL_TR_FBn/DQ1T/DIFFIO_RX_T7n
FPLL_TR_CLKOUT0/FPLL_TR_CLKOUTp/FPLL_TR_FB0/DQ1T/DIFFIO_TX_T8p
FPLL_TR_CLKOUT1/FPLL_TR_CLKOUTn/DIFFIO_TX_T8n
6,30
HSMA_CLK_OUT_P[2:1]
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
USER1_LED_R4
USER1_LED_R3
6,30
HSMA_CLK_OUT_N[2:1]
6,30
HSMA_CLK_IN0
30
ETHERNET INTERFACE
ENET_RX_CLK
32
C
QDRII+ INTERFACE
QDRII_A[20:0]
5,23
QDRII_Q[35:0]
VCCIO = 1.5V
5,23
FLASH INTERFACE
CLK20p/DQ22T/DIFFIO_RX_T167p
CLK20n/DQ22T/DIFFIO_RX_T167n
CLK21p/DQS22T/DIFFIO_RX_T165p
FPLL_TL_CLKOUT2/FPLL_TL_FBp/FPLL_TL_FB1/DQ22T/DIFFIO_RX_T163p
CLK21n/DQSn22T/DIFFIO_RX_T165n
FPLL_TL_CLKOUT3/FPLL_TL_FBn/DQ22T/DIFFIO_RX_T163n
CLK22p/DQ22T/DIFFIO_RX_T162p FPLL_TL_CLKOUT0/FPLL_TL_CLKOUTp/FPLL_TL_FB0/DQ22T/DIFFIO_TX_T164p
CLK22n/DQ22T/DIFFIO_RX_T162n
FPLL_TL_CLKOUT1/FPLL_TL_CLKOUTn/DIFFIO_TX_T164n
CLK23p/DQ21T/DIFFIO_RX_T160p
CLK23n/DQ21T/DIFFIO_RX_T160n
Bank 8D VCCIO = 1.5V
CLK16p/DQ13T/DIFFIO_RX_T93p
CLK16n/DQ13T/DIFFIO_RX_T93n
CLK17p/DQ12T/DIFFIO_RX_T91p
CLK17n/DQ12T/DIFFIO_RX_T91n
CLK18p/DQ12T/DIFFIO_RX_T87p
CLK18n/DQ12T/DIFFIO_RX_T87n
CLK19p/DQ12T/DIFFIO_RX_T85p
CLK19n/DQ12T/DIFFIO_RX_T85n
HSMA_CLK_IN_P[2:1]
VCCIO = 2.5V
CLK8p/DQ22B/DIFFIO_RX_B168p
CLK8n/DQ22B/DIFFIO_RX_B168n FPLL_BR_CLKOUT0/FPLL_BR_CLKOUTp/FPLL_BR_FB0/DQ22B/DIFFIO_TX_B161p
CLK9p/DQ22B/DIFFIO_RX_B166p
FPLL_BR_CLKOUT1/FPLL_BR_CLKOUTn/DIFFIO_TX_B161n
CLK9n/DQ22B/DIFFIO_RX_B166n
FPLL_BR_CLKOUT2/FPLL_BR_FBp/FPLL_BR_FB1/DQ22B/DIFFIO_RX_B162p
CLK10p/DQS22B/DIFFIO_RX_B164p
FPLL_BR_CLKOUT3/FPLL_BR_FBn/DQ22B/DIFFIO_RX_B162n
CLK10n/DQSn22B/DIFFIO_RX_B164n
CLK11p/DQ21B/DIFFIO_RX_B160p
CLK11n/DQ21B/DIFFIO_RX_B160n
Bank 7A VCCIO = 2.5V
D
HSMC PORT A INTERFACE
FM_D0
FM_D9
FM_D8
QDRII_Q35
HSMA_RX_D_P[16:0]
Bank 8A
C34
D34
G34
H34
E34
F34
N34
N33
27,33
VCCIO = 1.8V
FPLL_BC_CLKOUT0/FPLL_BC_CLKOUTp/FPLL_BC_FB0/DQ11B/DIFFIO_TX_B79p
FPLL_BC_CLKOUT1/FPLL_BC_CLKOUTn/DIFFIO_TX_B79n
FPLL_BC_CLKOUT2/FPLL_BC_FBp/FPLL_BC_FB1/DQS11B/DIFFIO_RX_B80p
FPLL_BC_CLKOUT3/FPLL_BC_FBn/DQSn11B/DIFFIO_RX_B80n
Bank 4A
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN0
E
FM_A[26:0]
B34
A35
C33
D33
5,26,27
FM_D[15:0]
5,26,27
FLASH_RESETn
26,27
USER I/O INTERFACES
B
USER1_LED_R[7:0]
6,34
MAX_BEn[3:0]
FPLL_TC_CLKOUT2/FPLL_TC_FBp/FPLL_TC_FB1/DQS12T/DIFFIO_RX_T89p
FPLL_TC_CLKOUT3/FPLL_TC_FBn/DQSn12T/DIFFIO_RX_T89n
FPLL_TC_CLKOUT0/FPLL_TC_CLKOUTp/FPLL_TC_FB0/DQ12T/DIFFIO_TX_T90p
FPLL_TC_CLKOUT1/FPLL_TC_CLKOUTn/DIFFIO_TX_T90n
A20
B21
J21
K21
6,27
DDR3A INTERFACE
DDR3A_DQ[71:0]
8,21,22
DDR3A_DM[8:0]
5AGXB3H4F40
8,21,22
Version = 1.86 Pin-out
DDR3A_CLK_P
DDR3A_CLK_N
A
21,22
21,22
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
12
of
1
46
8
E
7
6
5
4
3
2
1
Arria V GX Clocks (FPGA 2)
CLKB_125_P
R275
100, 1% CLKB_125_N
HSMB_CLK_IN_P1
HSMB_CLK_IN_P2
R226
R240
100, 1% HSMB_CLK_IN_N1
100, 1% HSMB_CLK_IN_N2
CLOCKS
CLKINBOTB_P1
CLKINTOPB_P0
CLKINTOPB_P1
CLKINBOTB_P0
R159
R228
R326
R325
100, 1%
100, 1%
100, 1%
100, 1%
CLKINTOPB_P0
CLKINTOPB_N0
CLKINTOPB_P1
CLKINTOPB_N1
FMC_CLK_M2C_P0
FMC_CLK_M2C_P1
R289
R274
100, 1% FMC_CLK_M2C_N0
100, 1% FMC_CLK_M2C_N1
CLKINBOTB_N1
CLKINTOPB_N0
CLKINTOPB_N1
CLKINBOTB_N0
10
10
10
10
CLKINBOTB_P0
CLKINBOTB_N0
CLKINBOTB_P1
CLKINBOTB_N1
U13I
10
10
10
10
Arria V GX Clocks
Bank 3A
CLKINB_50
USER2_LED_R5
SDI_A_RX_EN
USER2_LED_R6
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
AP34
AN34
AK34
AJ34
AM33
AL33
AU32
AT32
FMC_CLK_M2C_P0
FMC_CLK_M2C_N0
FMC_CLK_M2C_P1
FMC_CLK_M2C_N1
CLKB_125_P
CLKB_125_N
CLKINBOTB_P1
CLKINBOTB_N1
AV19
AU19
AF21
AE21
AD20
AC21
AL20
AK20
CLK0p/DQ1B/DIFFIO_RX_B2p
CLK0n/DQ1B/DIFFIO_RX_B2n
CLK1p/DQS1B/DIFFIO_RX_B4p
CLK1n/DQSn1B/DIFFIO_RX_B4n
CLK2p/DQ1B/DIFFIO_RX_B7p
CLK2n/DQ1B/DIFFIO_RX_B7n
CLK3p/DQ2B/DIFFIO_RX_B9p
CLK3n/DQ2B/DIFFIO_RX_B9n
FPLL_BL_CLKOUT0/FPLL_BL_CLKOUTp/FPLL_BL_FB0/DQ1B/DIFFIO_TX_B5p
FPLL_BL_CLKOUT1/FPLL_BL_CLKOUTn/DIFFIO_TX_B5n
FPLL_BL_CLKOUT2/FPLL_BL_FBp/FPLL_BL_FB1/DQ1B/DIFFIO_RX_B6p
FPLL_BL_CLKOUT3/FPLL_BL_FBn/DQ1B/DIFFIO_RX_B6n
CLK4p/DQ10B/DIFFIO_RX_B76p
CLK4n/DQ10B/DIFFIO_RX_B76n
CLK5p/DQ11B/DIFFIO_RX_B78p
CLK5n/DQ11B/DIFFIO_RX_B78n
CLK6pDQ11B/DIFFIO_RX_B82p
CLK6nDQ11B/DIFFIO_RX_B82n
CLK7pDQ11B/DIFFIO_RX_B84p
CLK7nDQ11B/DIFFIO_RX_B84n
AR6
AP6
AW4
AV4
AT7
AR7
AK7
AJ7
CLKINBOTB_P0
CLKINBOTB_N0
C
C6
D6
A6
B6
E6
E7
H6
J6
USER2_PB1
USER2_PB0
C2C_FPGA2_CLKIN_P
C2C_FPGA2_CLKIN_N
USER2_DIPSW3
USER2_DIPSW2
CLKINTOPB_P1
CLKINTOPB_N1
C34
D34
G34
H34
E34
F34
N34
N33
B
B22
C22
A22
A21
G21
H21
C20
D20
DDR3C_DM1
DDR3C_DQ11
DDR3C_DQ6
DDR3C_DQ4
DDR3C_DQ5
DDR3C_DQ1
DDR3C_DQ7
DDR3C_DQ0
CHIP-TO-CHIP INTERFACE
7
7
HSMC PORT B INTERFACE
VCCIO = FMC VARIABLE
FPLL_BC_CLKOUT0/FPLL_BC_CLKOUTp/FPLL_BC_FB0/DQ11B/DIFFIO_TX_B79p
FPLL_BC_CLKOUT1/FPLL_BC_CLKOUTn/DIFFIO_TX_B79n
FPLL_BC_CLKOUT2/FPLL_BC_FBp/FPLL_BC_FB1/DQS11B/DIFFIO_RX_B80p
FPLL_BC_CLKOUT3/FPLL_BC_FBn/DQSn11B/DIFFIO_RX_B80n
AC22
AD21
AH21
AG21
FMC_LA_P22
FMC_LA_N22
AM7
AL7
AP8
AN8
CLK12p/DQ1T/DIFFIO_RX_T1p
CLK12n/DQ1T/DIFFIO_RX_T1n
CLK13p/DQ1T/DIFFIO_RX_T3p
CLK13n/DQ1T/DIFFIO_RX_T3n
CLK14p/DQS1T/DIFFIO_RX_T5p
CLK14n/DQSn1T/DIFFIO_RX_T5n
CLK15p/DQ2T/DIFFIO_RX_T9p
CLK15n/DQ2T/DIFFIO_RX_T9n
F8
G8
J8
K8
FPLL_TR_CLKOUT2/FPLL_TR_FBp/FPLL_TR_FB1/DQ1T/DIFFIO_RX_T7p
FPLL_TR_CLKOUT3/FPLL_TR_FBn/DQ1T/DIFFIO_RX_T7n
FPLL_TR_CLKOUT0/FPLL_TR_CLKOUTp/FPLL_TR_FB0/DQ1T/DIFFIO_TX_T8p
FPLL_TR_CLKOUT1/FPLL_TR_CLKOUTn/DIFFIO_TX_T8n
30
HSMB_CLK_OUT0
30
HSMB_CLK_OUT_P[2:1]
16,30
HSMB_CLK_OUT_N[2:1]
16,30
HSMB_CLK_IN0
FMC_HA_P9
FMC_HA_N9
30
USER I/O INTERFACES
USER2_DIPSW[7:0]
18,35,37
USER2_LED_R[7:0]
18,35,37
USER2_PB[2:0]
USER2_DIPSW5
USER2_DIPSW4
FMC_HA_P6
FMC_HA_N6
C
18,35
SDI INTERFACES
SDI_A_RX_EN
27,29
FMC INTERFACE
VCCIO = 1.5V
CLK20p/DQ22T/DIFFIO_RX_T167p
CLK20n/DQ22T/DIFFIO_RX_T167n
CLK21p/DQS22T/DIFFIO_RX_T165p
FPLL_TL_CLKOUT2/FPLL_TL_FBp/FPLL_TL_FB1/DQ22T/DIFFIO_RX_T163p
CLK21n/DQSn22T/DIFFIO_RX_T165n
FPLL_TL_CLKOUT3/FPLL_TL_FBn/DQ22T/DIFFIO_RX_T163n
CLK22p/DQ22T/DIFFIO_RX_T162p FPLL_TL_CLKOUT0/FPLL_TL_CLKOUTp/FPLL_TL_FB0/DQ22T/DIFFIO_TX_T164p
CLK22n/DQ22T/DIFFIO_RX_T162n
FPLL_TL_CLKOUT1/FPLL_TL_CLKOUTn/DIFFIO_TX_T164n
CLK23p/DQ21T/DIFFIO_RX_T160p
CLK23n/DQ21T/DIFFIO_RX_T160n
Bank 8D
VCCIO = 1.5V
FMC_LA_P[33:0]
16,17,31
FMC_LA_N[33:0]
B34
A35
C33
D33
16,17,31
FMC_HA_P[23:0]
16,17,18,31
FMC_HA_N[23:0]
16,17,18,31
B
FMC_CLK_M2C_P[1:0]
31
FMC_CLK_M2C_N[1:0]
CLK16p/DQ13T/DIFFIO_RX_T93p
CLK16n/DQ13T/DIFFIO_RX_T93n
CLK17p/DQ12T/DIFFIO_RX_T91p
CLK17n/DQ12T/DIFFIO_RX_T91n
CLK18p/DQ12T/DIFFIO_RX_T87p
CLK18n/DQ12T/DIFFIO_RX_T87n
CLK19p/DQ12T/DIFFIO_RX_T85p
CLK19n/DQ12T/DIFFIO_RX_T85n
D
30
HSMB_CLK_IN_N[2:1]
VCCIO = FMC VARIABLE
CLK8p/DQ22B/DIFFIO_RX_B168p
CLK8n/DQ22B/DIFFIO_RX_B168n FPLL_BR_CLKOUT0/FPLL_BR_CLKOUTp/FPLL_BR_FB0/DQ22B/DIFFIO_TX_B161p
CLK9p/DQ22B/DIFFIO_RX_B166p
FPLL_BR_CLKOUT1/FPLL_BR_CLKOUTn/DIFFIO_TX_B161n
CLK9n/DQ22B/DIFFIO_RX_B166n
FPLL_BR_CLKOUT2/FPLL_BR_FBp/FPLL_BR_FB1/DQ22B/DIFFIO_RX_B162p
CLK10p/DQS22B/DIFFIO_RX_B164p
FPLL_BR_CLKOUT3/FPLL_BR_FBn/DQ22B/DIFFIO_RX_B162n
CLK10n/DQSn22B/DIFFIO_RX_B164n
CLK11p/DQ21B/DIFFIO_RX_B160p
CLK11n/DQ21B/DIFFIO_RX_B160n
Bank 7A
VCCIO = 2.5V
Bank 8A
CLKINTOPB_P0
CLKINTOPB_N0
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
USER2_LED_R7
HSMB_CLK_OUT0
HSMB_CLK_IN_P[2:1]
Bank 4A
HSMB_CLK_IN0
AM34
AL34
AK33
AJ33
11
11
11
11,16
C2C_FPGA2_CLKIN_P
C2C_FPGA2_CLKIN_N
Bank 3D
D
CLKINB_50
CLKB_125_P
CLKB_125_N
SDI_CLK148_UP
VCCIO = 2.5V
E
FPLL_TC_CLKOUT2/FPLL_TC_FBp/FPLL_TC_FB1/DQS12T/DIFFIO_RX_T89p
FPLL_TC_CLKOUT3/FPLL_TC_FBn/DQSn12T/DIFFIO_RX_T89n
FPLL_TC_CLKOUT0/FPLL_TC_CLKOUTp/FPLL_TC_FB0/DQ12T/DIFFIO_TX_T90p
FPLL_TC_CLKOUT1/FPLL_TC_CLKOUTn/DIFFIO_TX_T90n
A20
B21
J21
K21
DDR3C_DQS_P0
DDR3C_DQS_N0
DDR3C_DQ3
31
DDR3C INTERFACE
DDR3C_DQ[31:0]
19,25
DDR3C_DQS_P[3:0]
19,25
DDR3C_DQS_N[3:0]
5AGXB3H4F40
Version = 1.86 Pin-out
19,25
DDR3C_DM[3:0]
A
19,25
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
13
of
1
46
8
7
6
5
4
3
2
1
Arria V GX Configuration
2.5V
10K
10K
10K
10K
K35
AW34
F35
A36
K6
L6
CPU1_RESETn
INIT_DONE1
FPGA1_CONFIG_D[15:0]
27
26,27
M7
FPGA1_CONFIG_D0
FPGA1_CONFIG_D1
FPGA1_CONFIG_D2
FPGA1_CONFIG_D3
FPGA1_CONFIG_D4
FPGA1_CONFIG_D5
FPGA1_CONFIG_D6
FPGA1_CONFIG_D7
FPGA1_CONFIG_D8
FPGA1_CONFIG_D9
FPGA1_CONFIG_D10
FPGA1_CONFIG_D11
FPGA1_CONFIG_D12
FPGA1_CONFIG_D13
FPGA1_CONFIG_D14
FPGA1_CONFIG_D15
DNI
1.00k FPGA1_CEn
D
2.5V
R191
R212
JTAG_FPGA1_TDO
R375
DNI
JTAG_BLASTER_TDO
Arria V GX Configuration
AN6
P9
27,34
(FPGA 1)
U16J
FPGA1_CONF_DONE
FPGA_DCLK
FPGA1_nSTATUS
FPGA1_nCONFIG
27
26,27
27
27
E
R141
R360
R348
R347
AV33
AU33
AR33
AU34
AR34
AF10
AE11
AH6
AJ6
AM6
AH10
AJ10
AK6
AL6
AH9
AJ9
M35
INSTALL THIS RESISTOR ONLY WHEN FPGA 1 IS NOT POPULATED.
CONF_DONE
DCLK
nSTATUS
nCONFIG
TCK
TMS
TDO
TDI
CLKUSR/DQ21B/DIFFIO_RX_B159p
CRC_ERROR/DQSn2T/DIFFIO_RX_T12n
DEV_OE/DQ2T/DIFFIO_RX_T10p
DEV_CLRn/DQ2T/DIFFIO_RX_T10n
INIT_DONE/DQ2T/DIFFIO_RX_T14p
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
DATA0/AS_DATA0/ASDO
DATA1/AS_DATA1
nCEO/DQ2T/DIFFIO_RX_T14n
DATA2/AS_DATA2
DATA3/AS_DATA3
PR_DONE/DQ2T/DIFFIO_TX_T13p
DATA4/nCSO
PR_REQUEST/DIFFIO_TX_T13n
DATA5/DQ21B/DIFFIO_RX_B155n
PR_READY/DIFFIO_TX_T15n
DATA6/DQ21B/DIFFIO_RX_B155pPR_ERROR/DQ2T/DIFFIO_TX_T15p
DATA7/DQSn21B/DIFFIO_RX_B157n
DATA8/DQS21B/DIFFIO_RX_B157p
CvP_CONFDONE/DQS2T/DIFFIO_RX_T12p
DATA9/DQ21B/DIFFIO_RX_B159n
DATA10/DIFFIO_TX_B154n
nPERSTL0/DIFFIO_TX_T11n
DATA11/DQ21B/DIFFIO_TX_B154pnPERSTL1/DQ2T/DIFFIO_TX_T11p
DATA12/DIFFIO_TX_B156n
DATA13/DQ21B/DIFFIO_TX_B156p
DATA14/DIFFIO_TX_B158n
DATA15/DQ21B/DIFFIO_TX_B158p
AV34
AM35
AT34
AT33
H35
A34
D35
A37
P34
E
JTAG_TCK
JTAG_TMS
JTAG_FPGA1_TDO
JTAG_BLASTER_TDO
14,15,27,30,31,33
14,15,27,33
15,33
FPGA1_MSEL0
FPGA1_MSEL1
FPGA1_MSEL2
FPGA1_MSEL3
FPGA1_MSEL4
A5A_VCCPD_PGM_IO_2.5V
R225
R50
DNI
DNI
R222
C75
R223
DNI
10K 10K 10K 10K
N7
FPGA1_CEOn
L7
M6
M10
L10
FPGA1_PR_DONE
FPGA1_PR_REQUEST
FPGA1_PR_READY
FPGA1_PR_ERROR
27
27
27
27
P10
FPGA1_CvP_CONFDONE
N9
M8
PCIE_PERSTn
FPGA1_MSEL0
R413
R414
2.5V
DNI
1.00k
FPGA1_MSEL3
R417
R396
2.5V
DNI
1.00k
27
D
4
2.5V
SW8
1
2
3
4
nCE
8
7
6
5
OPEN
R49
R224
FPGA_DCLK
FPGA1_MSEL1
FPGA1_MSEL2
R415
R416
1.00k
1.00k
FPGA1_MSEL4
R418
1.00k
5AGXB3H4F40
Version = 1.86 Pin-out
TDA04H0SB1
2.5V
27,35
27
CPU2_RESETn
K6
L6
INIT_DONE2
M7
B
2.5V
R202
R203
FPGA1_CONFIG_D0
FPGA1_CONFIG_D1
FPGA1_CONFIG_D2
FPGA1_CONFIG_D3
FPGA1_CONFIG_D4
FPGA1_CONFIG_D5
FPGA1_CONFIG_D6
FPGA1_CONFIG_D7
FPGA1_CONFIG_D8
FPGA1_CONFIG_D9
FPGA1_CONFIG_D10
FPGA1_CONFIG_D11
FPGA1_CONFIG_D12
FPGA1_CONFIG_D13
FPGA1_CONFIG_D14
FPGA1_CONFIG_D15
DNI
1.00k FPGA2_CEn
AV33
AU33
AR33
AU34
AR34
AF10
AE11
AH6
AJ6
AM6
AH10
AJ10
AK6
AL6
AH9
AJ9
M35
INSTALL THIS RESISTOR ONLY WHEN FPGA 2 IS NOT POPULATED.
TCK
TMS
TDO
TDI
CLKUSR/DQ21B/DIFFIO_RX_B159p
CRC_ERROR/DQSn2T/DIFFIO_RX_T12n
DEV_OE/DQ2T/DIFFIO_RX_T10p
DEV_CLRn/DQ2T/DIFFIO_RX_T10n
INIT_DONE/DQ2T/DIFFIO_RX_T14p
JTAG_FPGA1_TDO
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
DATA0/AS_DATA0/ASDO
DATA1/AS_DATA1
nCEO/DQ2T/DIFFIO_RX_T14n
DATA2/AS_DATA2
DATA3/AS_DATA3
PR_DONE/DQ2T/DIFFIO_TX_T13p
DATA4/nCSO
PR_REQUEST/DIFFIO_TX_T13n
DATA5/DQ21B/DIFFIO_RX_B155n
PR_READY/DIFFIO_TX_T15n
DATA6/DQ21B/DIFFIO_RX_B155pPR_ERROR/DQ2T/DIFFIO_TX_T15p
DATA7/DQSn21B/DIFFIO_RX_B157n
DATA8/DQS21B/DIFFIO_RX_B157p
CvP_CONFDONE/DQS2T/DIFFIO_RX_T12p
DATA9/DQ21B/DIFFIO_RX_B159n
DATA10/DIFFIO_TX_B154n
nPERSTL0/DIFFIO_TX_T11n
DATA11/DQ21B/DIFFIO_TX_B154pnPERSTL1/DQ2T/DIFFIO_TX_T11p
DATA12/DIFFIO_TX_B156n
DATA13/DQ21B/DIFFIO_TX_B156p
DATA14/DIFFIO_TX_B158n
DATA15/DQ21B/DIFFIO_TX_B158p
AV34
AM35
AT34
AT33
JTAG_TCK
JTAG_TMS
AVB_JTAG_TDO
JTAG_FPGA1_TDO
14,15,27,30,31,33
14,15,27,33
15,30
A5B_VCCPD_PGM_IO_2.5V
H35
A34
D35
A37
P34
FPGA2_MSEL0
FPGA2_MSEL1
FPGA2_MSEL2
FPGA2_MSEL3
FPGA2_MSEL4
27
27
27
27
27
27
27
FPGA2_CEn
FPGA2_MSEL0
FPGA2_MSEL1
FPGA2_MSEL2
FPGA2_MSEL3
FPGA2_MSEL4
FPGA2_CEOn
27
27
27
27
27
27
27
R367
AN6
P9
CONF_DONE
DCLK
nSTATUS
nCONFIG
DNI
R368
K35
AW34
F35
A36
R134
10K 10K 10K 10K
FPGA2_MSEL0
N7
FPGA2_CEOn
L7
M6
M10
L10
FPGA2_PR_DONE
FPGA2_PR_REQUEST
FPGA2_PR_READY
FPGA2_PR_ERROR
27
27
27
27
P10
FPGA2_CvP_CONFDONE
27
N9
M8
FPGA2_PCIE_PERSTn
FPGA2_MSEL3
R73
R72
2.5V
DNI
1.00k
R77
R76
2.5V
DNI
1.00k
6
C
B
2.5V
SW4
1
2
3
4
nCE
5AGXB3H4F40
OPEN
27
27
AVB_JTAG_TDO
Arria V GX Configuration
FPGA2_CONF_DONE
FPGA_DCLK
FPGA2_nSTATUS
FPGA2_nCONFIG
27
(FPGA 2)
U13J
R369
C
10K
10K
10K
10K
R370
R140
R190
R178
R179
FPGA1_CEn
FPGA1_MSEL0
FPGA1_MSEL1
FPGA1_MSEL2
FPGA1_MSEL3
FPGA1_MSEL4
FPGA1_CEOn
8
7
6
5
FPGA2_MSEL1
FPGA2_MSEL2
R74
R75
1.00k
1.00k
FPGA2_MSEL4
R78
1.00k
TDA04H0SB1
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
14
of
1
46
8
7
6
5
4
3
2
1
JTAG
TS5A23157 Switch Functions
When Pins 1 & 5 are:
LOW --> NC to/from COM = ON and NO to/from COM = OFF
HIGH --> NC to/from COM = OFF and NO to/from COM = ON
E
JTAG_TCK
USB Blaster Programming Header
(uses JTAG mode only)
R252
DNI
C330
Logic 0 = pin 10 <--> pin 9 (FMC Bypass)
Logic 1 = pin 10 <--> pin 2 (FMC Enable)
DNI
R253
1.00k
31
2.5V
J1
D
USB_DISABLEn
33
2.5V
R116
1.00k
2
4
6
8
10
1
3
5
7
9
JTAG_TCK
JTAG_BLASTER_TDI
JTAG_TMS
JTAG_BLASTER_TDO
FMC_JTAG_EN
1
FMC_JTAG_TDO
2
3
14,27,30,31,33
JTAG_TMS
4
14,27,33
R117
FMC_JTAG_EN
5
14,33
R119
1.00k
1.00k
R118
DNI
JTAG_BLASTER_TDI
27,33
Populate R118 if you would like to
Master the JTAG chain through
HSMC Port A, HSMC Port B or FMC.
30
2.5V
HSMB_JTAG_EN
1
HSMB_JTAG_TDO
2
3
OPEN
HSMA_JTAG_EN
HSMB_JTAG_EN
FMC_JTAG_EN
JTAG_TMS
4
HSMB_JTAG_EN
5
NC1
GND
V+
NO2
NC2
IN2
8
27
FMC_JTAG_TDI
2.5V
15,31
C120
0.1uF
2.5V
COM2
7
R123
6
FMC_JTAG_TMS
1.00k
D
31
IN1
10
COM1
NO1
NC1
GND
V+
NO2
NC2
IN2
9
8
FMC_JTAG_TDI
15,31
HSMB_JTAG_TDI
2.5V
C121
0.1uF
2.5V
7
6
COM2
R124
1.00k
HSMB_JTAG_TMS
30
R332
R333
R334
TS5A23157
Logic 0 = pin 10 <--> pin 9 (HSMA Bypass)
Logic 1 = pin 10 <--> pin 2 (HSMA Enable)
SW6
8
7
6
5
NO1
9
JTAG_EPM2210_TDI
C
JTAG Chain Control
1
2
3
4
10
COM1
U38
Logic 0 = pin 6 <--> pin 7 (HSMBBypass)
Logic 1 = pin 6 <--> pin 4 (HSMB Enable)
C
IN1
TS5A23157
Logic 0 = pin 10 <--> pin 9 (HSMB Bypass)
Logic 1 = pin 10 <--> pin 2 (HSMB Enable)
70246-1004
JTAG_BLASTER_TDO
U37
Logic 0 = pin 6 <--> pin 7 (FMC Bypass)
Logic 1 = pin 6 <--> pin 4 (FMC Enable)
2.5V
E
1.00k
1.00k
1.00k
30
U36
HSMA_JTAG_EN
1
HSMA_JTAG_TDO
2
IN1
10
COM1
NO1
NC1
GND
V+
NO2
NC2
9
HSMB_JTAG_TDI
30
AVB_JTAG_TDO
2.5V
14,30
TDA04H0SB1
ON = not-in-chain
OFF = in-chain
Logic 0 = pin 6 <--> pin 7 (HSMA Bypass)
Logic 1 = pin 6 <--> pin 4 (HSMA Enable)
3
JTAG_TMS
4
HSMA_JTAG_EN
5
IN2
8
C119
0.1uF
2.5V
COM2
7
R122
6
HSMA_JTAG_TMS
1.00k
30
TS5A23157
B
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
15
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 2, Bank 3
NOTE: HSMB, SDI AND FMC CAN ONLY BE USED AT THE SAME TIME WHEN A5_VCCIO_FMC = 2.5V
E
E
VCCIO = Varies(1.2V- 3.3V)
VCCIO = 2.5V
U13A
U13B
Arria V GX Bank 3
D
HSMB_TX_D_P16
HSMB_TX_D_P6
SDI_A_TX_EN
AP33
AL32
AK31
HSMB_TX_D_P15
HSMB_TX_D_P7
HSMB_TX_D_P14
HSMB_RX_D_P14
HSMB_RX_D_N14
HSMB_TX_D_P2
HSMB_RX_D_P6
HSMB_RX_D_N6
AP32
AM31
AP31
AT31
AR31
AE29
AH30
AG30
HSMB_RX_D_P13
HSMB_RX_D_N13
C
AW32
AW33
HSMB_TX_D_N6
HSMB_TX_D_N15
HSMB_TX_D_N7
HSMB_TX_D_N14
HSMB_TX_D_N2
AK32
AN32
AL31
AN31
AD29
HSMB_TX_D_P0
HSMB_RX_D_P5
HSMB_RX_D_N5
HSMB_TX_D_P4
HSMB_TX_D_P1
HSMB_RX_D_P3
HSMB_RX_D_N3
HSMB_TX_LED
HSMB_RX_D_P2
HSMB_RX_D_N2
AC29
AG28
AF28
AL29
AE28
AB28
AB27
AM28
AD27
AC27
HSMB_RX_D_P4
HSMB_RX_D_N4
AJ28
AH28
HSMB_TX_D_N0
HSMB_TX_D_N4
HSMB_TX_D_N1
HSMB_TX_D_N10
AB29
AK29
AD28
AP28
DQ1B/DIFFIO_TX_B1p
DQ1B/DIFFIO_TX_B3p
DQ1B
Arria V GX Bank 3
Bank 3A
DQ3B/DIFFIO_TX_B16p
DQ3B/DIFFIO_RX_B17p
DQ3B/DIFFIO_RX_B17n
DQ3B/DIFFIO_TX_B18p
DQ3B/DIFFIO_TX_B20p
DQ3B/DIFFIO_RX_B21p
DQ3B/DIFFIO_RX_B21n
DQ3B/DIFFIO_TX_B22p
DQ3B/DIFFIO_RX_B23p
DQ3B/DIFFIO_RX_B23n
DQS2B/DIFFIO_RX_B11p
DQSn2B/DIFFIO_RX_B11n
DQS3B/DIFFIO_RX_B19p
DQSn3B/DIFFIO_RX_B19n
DIFFIO_TX_B3n
DIFFIO_TX_B8n
DIFFIO_TX_B10n
DIFFIO_TX_B12n
DIFFIO_TX_B14n
DQ4B/DIFFIO_TX_B24p
DQ4B/DIFFIO_RX_B25p
DQ4B/DIFFIO_RX_B25n
DQ4B/DIFFIO_TX_B26p
DQ4B/DIFFIO_TX_B28p
DQ4B/DIFFIO_RX_B29p
DQ4B/DIFFIO_RX_B29n
DQ4B
DQ4B/DIFFIO_RX_B30p
DQ4B/DIFFIO_RX_B30n
DQS4B/DIFFIO_RX_B27p
DQSn4B/DIFFIO_RX_B27n
DIFFIO_TX_B16n
DIFFIO_TX_B18n
DIFFIO_TX_B20n
DIFFIO_TX_B22n
Bank 3B
DQ5B/DIFFIO_TX_B31p
DQ5B/DIFFIO_RX_B32p
DQ5B/DIFFIO_RX_B32n
DQ5B/DIFFIO_TX_B33p
DQ5B/DIFFIO_TX_B35p
DQ5B/DIFFIO_RX_B36p
DQ5B/DIFFIO_RX_B36n
DQ5B/DIFFIO_TX_B37p
DQ5B/DIFFIO_RX_B38p
DQ5B/DIFFIO_RX_B38n
DQS5B/DIFFIO_RX_B34p
DQSn5B/DIFFIO_RX_B34n
DIFFIO_TX_B33n
DIFFIO_TX_B35n
DIFFIO_TX_B37n
AN33
HSMB_TX_D_N16
AV31
AW31
AW30
AL30
AV30
AU29
AT29
AP30
AP29
AN29
HSMB_TX_D_P12
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_TX_D_P5
HSMB_TX_D_P11
HSMB_RX_D_P8
HSMB_RX_D_N8
HSMB_TX_D_P9
HSMB_RX_D_P7
HSMB_RX_D_N7
HSMB_SDA
AH27
AC25
AB25
AF27
AD25
AH26
AG26
AE26
AH25
AG25
HSMB_RX_D_P1
HSMB_RX_D_N1
AF25
AE25
FMC_LA_P31
HSMB_RX_D_P0
HSMB_RX_D_N0
FMC_LA_P30
FMC_LA_P33
HSMB_SCL
HSMB_RX_LED
HSMB_CLK_OUT_P2
AT30
AR30
HSMB_RX_D_P16
HSMB_RX_D_N16
FMC_LA_P29
AU31
AK30
AU30
AN30
HSMB_TX_D_N12
HSMB_TX_D_N5
HSMB_TX_D_N11
HSMB_TX_D_N9
FMC_LA_P24
FMC_HA_P17
HSMB_D1
HSMB_D0
AR28
AV28
AU28
AK27
AR27
AU27
AT27
AN27
AW27
AV27
HSMB_TX_D_P10
HSMB_RX_D_P15
HSMB_RX_D_N15
HSMB_TX_D_P3
HSMB_TX_D_P13
HSMB_RX_D_P11
HSMB_RX_D_N11
HSMB_TX_D_P8
HSMB_RX_D_P12
HSMB_RX_D_N12
HSMB_D3
HSMB_D2
AW28
AW29
HSMB_RX_D_P10
HSMB_RX_D_N10
AJ27
AP27
AM27
HSMB_TX_D_N3
HSMB_TX_D_N13
HSMB_TX_D_N8
AP26
AN25
AM25
AK25
AT25
AW26
AW25
AL26
AV24
AV25
AU26
AT26
AP23
FMC_HA_P21
FMC_CLK_BIDIR_P2 AE23
FMC_CLK_BIDIR_N2 AD22
AL23
FMC_LA_P25
AW22
FMC_LA_P19
AW21
FMC_CLK_DIR
AV21
AH23
FMC_LA_P27
AF22
AE22
FMC_CLK_BIDIR_P3
FMC_CLK_BIDIR_N3
AU22
AT22
FMC_HA_N21
FMC_LA_N25
FMC_LA_N19
FMC_LA_N27
FMC_HA_N22
FMC_LA_N26
AN23
AK23
AV22
AG23
AN22
AK22
5AGXB3H4F40
Version = 1.86 Pin-out
B
HSMC PORT B INTERFACE
HSMB_D[3:0]
Bank 3C
RZQ_0/DIFFIO_TX_B1n
DQ2B/DIFFIO_TX_B8p
DQ2B/DIFFIO_TX_B10p
DQ2B/DIFFIO_TX_B12p
DQ2B/DIFFIO_RX_B13p
DQ2B/DIFFIO_RX_B13n
DQ2B/DIFFIO_TX_B14p
DQ2B/DIFFIO_RX_B15p
DQ2B/DIFFIO_RX_B15n
DIFFIO_TX_B24n
DIFFIO_TX_B26n
DIFFIO_TX_B28n
DIFFIO_TX_B31n
Default =2.5V
DQ6B/DIFFIO_TX_B39p
DQ6B/DIFFIO_RX_B40p
DQ6B/DIFFIO_RX_B40n
DQ6B/DIFFIO_TX_B41p
DQ6B/DIFFIO_TX_B43p
DQ6B/DIFFIO_RX_B44p
DQ6B/DIFFIO_RX_B44n
DQ6B/DIFFIO_TX_B45p
DQ6B/DIFFIO_RX_B46p
DQ6B/DIFFIO_RX_B46n
DQS6B/DIFFIO_RX_B42p
DQSn6B/DIFFIO_RX_B42n
DQ7B/DIFFIO_TX_B47p
DQ7B/DIFFIO_RX_B48p
DQ7B/DIFFIO_RX_B48n
DQ7B/DIFFIO_TX_B49p
DQ7B/DIFFIO_TX_B51p
DQ7B/DIFFIO_RX_B52p
DQ7B/DIFFIO_RX_B52n
DQ7B
DQ7B/DIFFIO_RX_B53p
DQ7B/DIFFIO_RX_B53n
DQ8B/DIFFIO_TX_B54p
DQ8B/DIFFIO_RX_B55p
DQ8B/DIFFIO_RX_B55n
DQ8B/DIFFIO_TX_B56p
DQ8B/DIFFIO_TX_B58p
DQ8B/DIFFIO_RX_B59p
DQ8B/DIFFIO_RX_B59n
DQ8B/DIFFIO_TX_B60p
DQ8B/DIFFIO_RX_B61p
DQ8B/DIFFIO_RX_B61n
DQS8B/DIFFIO_RX_B57p
DQSn8B/DIFFIO_RX_B57n
DIFFIO_TX_B39n
DIFFIO_TX_B41n
DIFFIO_TX_B43n
DIFFIO_TX_B45n
DIFFIO_TX_B47n
DIFFIO_TX_B49n
DIFFIO_TX_B51n
DIFFIO_TX_B54n
DIFFIO_TX_B56n
DIFFIO_TX_B58n
DIFFIO_TX_B60n
DQS7B/DIFFIO_RX_B50p
DQSn7B/DIFFIO_RX_B50n
Bank 3D
DQ9B/DIFFIO_TX_B62p
DQ10B/DIFFIO_TX_B70p
DQ9B/DIFFIO_RX_B63p
DQ10B/DIFFIO_RX_B71p
DQ9B/DIFFIO_RX_B63n
DQ10B/DIFFIO_RX_B71n
DQ9B/DIFFIO_TX_B64p
DQ10B/DIFFIO_TX_B72p
DQ9B/DIFFIO_TX_B66p
DQ10B/DIFFIO_TX_B74p
DQ9B/DIFFIO_RX_B67p
DQ10B/DIFFIO_RX_B75p
DQ9B/DIFFIO_RX_B67n
DQ10B/DIFFIO_RX_B75n
DQ9B/DIFFIO_TX_B68p
DQ10B
DQ9B/DIFFIO_RX_B69p
DQ9B/DIFFIO_RX_B69n
DQS10B/DIFFIO_RX_B73p
DQSn10B/DIFFIO_RX_B73n
DQS9B/DIFFIO_RX_B65p
DQSn9B/DIFFIO_RX_B65n
DQ11B/DIFFIO_TX_B77p
DQ11B/DIFFIO_TX_B81p
DIFFIO_TX_B62n
DQ11B/DIFFIO_TX_B83p
DIFFIO_TX_B64n
DIFFIO_TX_B66n
DIFFIO_TX_B74n
DIFFIO_TX_B68n
DIFFIO_TX_B77n
DIFFIO_TX_B70n
DIFFIO_TX_B81n
DIFFIO_TX_B72n
DIFFIO_TX_B83n
AD24
AU24
AT24
AL24
AH24
AW24
AW23
AP24
AU23
AT23
FMC_LA_P32
30
HSMB_CLK_OUT_P[2:1]
HSMB_PRSNTn
FMC_LA_P16
FMC_LA_P28
13,30
HSMB_CLK_OUT_N[2:1]
13,30
D
HSMB_TX_D_P[16:0]
30
HSMB_TX_D_N[16:0]
FMC_HA_P23
SDI_CLK148_UP
SDI_CLK148_DN
30
HSMB_RX_D_P[16:0]
30
HSMB_RX_D_N[16:0]
AF24
AE24
30
HSMB_SDA
HSMB_PRSNTn
HSMB_TX_LED
HSMB_RX_LED
HSMB_SCL
AG27
AE27
AC24
AD26
AN26
AJ25
AR25
AD23
AK24
AG24
AN24
FMC_LA_N31
FMC_LA_N30
FMC_LA_N33
HSMB_CLK_OUT_N2
FMC_LA_N29
FMC_LA_N24
FMC_HA_N17
FMC_LA_N32
FMC_LA_N16
FMC_LA_N28
FMC_HA_N23
FMC_LA_P[33:0]
AP22
AW20
AW19
AL22
AH22
AU20
AT20
AK21
FMC_HA_P22
FMC_LA_N[33:0]
30
27,30,35
35
35
30
Si571 VCXO
SDI_CLK148_UP
SDI_CLK148_DN
11
11
C
FMC INTERFACE
13,17,31
13,17,31
FMC_HA_P[23:0]
FMC_LA_P26
FMC_LA_P21
13,17,18,31
FMC_HA_N[23:0]
13,17,18,31
FMC_CLK_BIDIR_P[3:2]
31
FMC_CLK_BIDIR_N[3:2]
AT21
AR21
31
FMC_CLK_DIR
AN21
AP20
AH20
FMC_HA_P20
FMC_HA_P18
FMC_HA_P15
AG22
AM21
AN20
AG20
FMC_LA_N21
FMC_HA_N20
FMC_HA_N18
FMC_HA_N15
31
SDI INTERFACES
B
SDI_A_TX_EN
27,29
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
16
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 2, Bank 4
NOTE: HSMB, SDI AND FMC CAN ONLY BE USED AT THE SAME TIME WHEN A5_VCCIO_FMC = 2.5V
E
VCCIO = Varies(1.2V- 3.3V)
VCCIO = Varies(1.2V- 3.3V)
Default =2.5V
U13C
Default =2.5V
U13D
Arria V GX Bank 4
FMC_LA_P6
FMC_LA_P10
FMC_HA_P4
D
FMC_LA_P8
AM9
AW8
AW7
AV6
AK10
AU8
AU7
AP9
AR9
AT8
AW5
AW6
C
FMC_HB_P14
FMC_HB_P5
FMC_HB_N5
FMC_HB_P19
FMC_HB_P21
FMC_HB_P3
FMC_HB_N3
FMC_HB_P16
FMC_HB_P0
FMC_HB_N0
AR13
AE13
AE14
AU12
AM13
AW11
AW10
AP12
AJ13
AH13
FMC_HB_P1
FMC_HB_N1
AW12
AV12
FMC_HB_P15
FMC_HB_P4
FMC_HB_N4
FMC_HB_P12
FMC_HB_P20
FMC_HB_P10
FMC_HB_N10
FMC_HB_P11
FMC_HB_N11
AJ12
AG13
AF13
AV10
AL12
AD13
AC13
AP11
AW9
AV9
FMC_HB_P2
FMC_HB_N2
AU11
AT11
Arria V GX Bank 4
Bank 4A
RZQ_1/DQ22B/DIFFIO_TX_B167p
DQ20B/DIFFIO_TX_B146p
DQ20B/DIFFIO_RX_B147p
DQ20B/DIFFIO_RX_B147n
DQ20B/DIFFIO_TX_B148p
DQ20B/DIFFIO_TX_B150p
DQ20B/DIFFIO_RX_B151p
DQ20B/DIFFIO_RX_B151n
DQ20B/DIFFIO_TX_B152p
DQ20B/DIFFIO_RX_B153p
DQ20B/DIFFIO_RX_B153n
DQ21B
DQ22B/DIFFIO_TX_B163p
DQ22B/DIFFIO_TX_B165p
DQS20B/DIFFIO_RX_B149p
DQSn20B/DIFFIO_RX_B149n
Bank 4B
DQ17B/DIFFIO_TX_B123p
DQ17B/DIFFIO_RX_B124p
DQ17B/DIFFIO_RX_B124n
DQ17B/DIFFIO_TX_B125p
DQ17B/DIFFIO_TX_B127p
DQ17B/DIFFIO_RX_B128p
DQ17B/DIFFIO_RX_B128n
DQ17B/DIFFIO_TX_B129p
DQ17B/DIFFIO_RX_B130p
DQ17B/DIFFIO_RX_B130n
DQS17B/DIFFIO_RX_B126p
DQSn17B/DIFFIO_RX_B126n
DQ18B/DIFFIO_TX_B131p
DQ18B/DIFFIO_RX_B132p
DQ18B/DIFFIO_RX_B132n
DQ18B/DIFFIO_TX_B133p
DQ18B/DIFFIO_TX_B135p
DQ18B/DIFFIO_RX_B136p
DQ18B/DIFFIO_RX_B136n
DQ18B
DQ18B/DIFFIO_RX_B137p
DQ18B/DIFFIO_RX_B137n
DQS18B/DIFFIO_RX_B134p
DQSn18B/DIFFIO_RX_B134n
DIFFIO_TX_B146n
DIFFIO_TX_B148n
DIFFIO_TX_B150n
DIFFIO_TX_B152n
DIFFIO_TX_B163n
DIFFIO_TX_B165n
DIFFIO_TX_B167n
DQ19B/DIFFIO_TX_B138p
DQ19B/DIFFIO_RX_B139p
DQ19B/DIFFIO_RX_B139n
DQ19B/DIFFIO_TX_B140p
DQ19B/DIFFIO_TX_B142p
DQ19B/DIFFIO_RX_B143p
DQ19B/DIFFIO_RX_B143n
DQ19B/DIFFIO_TX_B144p
DQ19B/DIFFIO_RX_B145p
DQ19B/DIFFIO_RX_B145n
DQS19B/DIFFIO_RX_B141p
DQSn19B/DIFFIO_RX_B141n
DIFFIO_TX_B123n
DIFFIO_TX_B125n
DIFFIO_TX_B127n
DIFFIO_TX_B129n
DIFFIO_TX_B131n
DIFFIO_TX_B133n
DIFFIO_TX_B135n
DIFFIO_TX_B138n
DIFFIO_TX_B140n
DIFFIO_TX_B142n
DIFFIO_TX_B144n
AP7
Bank 4C
FMC_LA_P5
AH8
AU6
AL8
FMC_LA_N7
FMC_LA_P4
AL9
AV7
AK9
AN9
AT6
AK8
AN7
FMC_LA_N6
FMC_LA_N10
FMC_HA_N4
FMC_LA_N8
FMC_LA_P7
FMC_LA_N4
FMC_LA_N5
AD11
AG12
AF12
AU9
AE12
AR10
AP10
AL11
AM10
AL10
FMC_HB_P17
FMC_HB_P6
FMC_HB_N6
FMC_HB_P13
FMC_HB_P18
FMC_HB_P8
FMC_HB_N8
FMC_HA_P5
FMC_HB_P9
FMC_HB_N9
AH11
AG11
FMC_HB_P7
FMC_HB_N7
AP13
AT12
AL13
AN12
AH12
AU10
AK12
AC12
AT9
AD12
AK11
FMC_HB_N14
FMC_HB_N19
FMC_HB_N21
FMC_HB_N16
FMC_HB_N15
FMC_HB_N12
FMC_HB_N20
FMC_HB_N17
FMC_HB_N13
FMC_HB_N18
FMC_HA_N5
FMC_LA_P2
FMC_LA_N2
AP15
AW15
AW14
AD16
AL15
AW13
AV13
AH15
AU15
AT15
FMC_HA_P0
FMC_HA_N0
AH16
AG16
FMC_LA_N17
FMC_LA_N18
FMC_LA_N11
AN15
AC16
AK15
FMC_LA_P23
AW18
AH19
AG19
AP19
AJ18
AT19
AU18
AF19
AW16
AW17
FMC_LA_P17
FMC_LA_P3
FMC_LA_N3
FMC_LA_P18
FMC_LA_P11
FMC_LA_P1
FMC_LA_N1
DQ15B/DIFFIO_TX_B108p
DQ15B/DIFFIO_RX_B109p
DQ15B/DIFFIO_RX_B109n
DQ15B/DIFFIO_TX_B110p
DQ15B/DIFFIO_TX_B112p
DQ15B/DIFFIO_RX_B113p
DQ15B/DIFFIO_RX_B113n
DQ15B
DQ15B/DIFFIO_RX_B114p
DQ15B/DIFFIO_RX_B114n
DQS15B/DIFFIO_RX_B111p
DQSn15B/DIFFIO_RX_B111n
AD14
AU14
AT14
AU13
AL14
AP14
AN14
AH14
AE15
AD15
DQ16B/DIFFIO_TX_B115p
DQ16B/DIFFIO_RX_B116p
DQ16B/DIFFIO_RX_B116n
DQ16B/DIFFIO_TX_B117p
DQ16B/DIFFIO_TX_B119p
DQ16B/DIFFIO_RX_B120p
DQ16B/DIFFIO_RX_B120n
DQ16B/DIFFIO_TX_B121p
DQ16B/DIFFIO_RX_B122p
DQ16B/DIFFIO_RX_B122n
FMC INTERFACE
FMC_LA_P[33:0]
FMC_LA_P14
FMC_LA_P13
DIFFIO_TX_B115n
DIFFIO_TX_B117n
DIFFIO_TX_B119n
DIFFIO_TX_B121n
13,16,31
FMC_LA_N[33:0]
13,16,31
FMC_HA_P[23:0]
FMC_HA_P7
13,16,18,31
FMC_HA_N[23:0]
31
FMC_HB_N[21:0]
AC15
AT13
AK14
AG14
FMC_HA_N14
FMC_LA_N14
FMC_LA_N13
FMC_HA_N7
AH17
AP17
AN17
AT16
AK16
AP16
AN16
AM16
AF16
AE17
FMC_LA_P9
FMC_HA_P3
FMC_HA_N3
FMC_LA_P20
FMC_LA_P12
FMC_LA_P0
FMC_LA_N0
FMC_LA_P15
FMC_HA_P1
FMC_HA_N1
AV16
AU16
FMC_HA_P2
FMC_HA_N2
AV18
AN19
AH18
AE19
AK17
AC19
AD17
AG17
AR16
AJ16
AL16
FMC_LA_N23
FMC_HA_N19
FMC_HA_N12
FMC_HA_N13
FMC_HA_N16
FMC_HA_N8
FMC_HA_N11
FMC_LA_N9
FMC_LA_N20
FMC_LA_N12
FMC_LA_N15
D
13,16,18,31
FMC_HB_P[21:0]
AF15
AE16
DQS16B/DIFFIO_RX_B118p
DQSn16B/DIFFIO_RX_B118n
DIFFIO_TX_B108n
DIFFIO_TX_B110n
DIFFIO_TX_B112n
FMC_HA_P14
31
Bank 4D
FMC_HA_P19
FMC_HA_P12
FMC_HA_P13
AL19
AK19
FMC_HA_P16
FMC_HA_P8
FMC_HA_P11
5AGXB3H4F40
AL17
AU17
AT17
AD19
AC18
AE18
AD18
AG18
AM18
AL18
Version = 1.86 Pin-out
B
E
AR18
AP18
DQ12B/DIFFIO_TX_B85p
DQ12B/DIFFIO_RX_B86p
DQ12B/DIFFIO_RX_B86n
DQ12B/DIFFIO_TX_B87p
DQ12B/DIFFIO_TX_B89p
DQ12B/DIFFIO_RX_B90p
DQ12B/DIFFIO_RX_B90n
DQ12B/DIFFIO_TX_B91p
DQ12B/DIFFIO_RX_B92p
DQ12B/DIFFIO_RX_B92n
DQS12B/DIFFIO_RX_B88p
DQSn12B/DIFFIO_RX_B88n
DQ13B/DIFFIO_TX_B93p
DQ13B/DIFFIO_RX_B94p
DQ13B/DIFFIO_RX_B94n
DQ13B/DIFFIO_TX_B95p
DQ13B/DIFFIO_TX_B97p
DQ13B/DIFFIO_RX_B98p
DQ13B/DIFFIO_RX_B98n
DQ13B
DQ13B/DIFFIO_RX_B99p
DQ13B/DIFFIO_RX_B99n
DQS13B/DIFFIO_RX_B96p
DQSn13B/DIFFIO_RX_B96n
DQ14B/DIFFIO_TX_B100p
DQ14B/DIFFIO_RX_B101p
DQ14B/DIFFIO_RX_B101n
DQ14B/DIFFIO_TX_B102p
DQ14B/DIFFIO_TX_B104p
DQ14B/DIFFIO_RX_B105p
DQ14B/DIFFIO_RX_B105n
DQ14B/DIFFIO_TX_B106p
DQ14B/DIFFIO_RX_B107p
DQ14B/DIFFIO_RX_B107n
DQS14B/DIFFIO_RX_B103p
DQSn14B/DIFFIO_RX_B103n
DIFFIO_TX_B85n
DIFFIO_TX_B87n
DIFFIO_TX_B89n
DIFFIO_TX_B91n
DIFFIO_TX_B93n
DIFFIO_TX_B95n
DIFFIO_TX_B97n
DIFFIO_TX_B100n
DIFFIO_TX_B102n
DIFFIO_TX_B104n
DIFFIO_TX_B106n
C
B
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
17
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 2, Bank 7
E
E
VCCIO = 2.5V
U13E
VCCIO = 2.5V
U13F
Arria V GX Bank 7
Arria V GX Bank 7
Bank 7C
Bank 7A
D
C2C_DIN_P6
C2C_DIN_P8
F7
C7
USER2_PB2
K7
FMC_HA_N10
C2C_DIN_N6
C2C_DIN_N8
C2C_DIN_N7
C2C_DIN_N28
C2C_DIN_N2
C2C_DIN_N5
G6
G7
D7
G9
L9
C9
J9
DQ1T/DIFFIO_TX_T4p
DQ1T/DIFFIO_TX_T6p
F6
RZQ_5/DQ1T/DIFFIO_TX_T2p
DQ3T/DIFFIO_RX_T16p
DQ3T/DIFFIO_RX_T16n
DQ3T/DIFFIO_TX_T17p
DQ3T/DIFFIO_RX_T18p
DQ3T/DIFFIO_RX_T18n
DQ3T/DIFFIO_TX_T19p
DQ3T/DIFFIO_TX_T21p
DQ3T/DIFFIO_RX_T22p
DQ3T/DIFFIO_RX_T22n
DQ3T/DIFFIO_TX_T23p
DQ2T
DIFFIO_TX_T2n
DIFFIO_TX_T4n
DIFFIO_TX_T6n
DIFFIO_TX_T17n
DIFFIO_TX_T19n
DIFFIO_TX_T21n
DIFFIO_TX_T23n
DQS3T/DIFFIO_RX_T20p
DQSn3T/DIFFIO_RX_T20n
FMC_HA_P10
D9
E9
F9
C8
D8
K9
B9
A9
A8
H9
C2C_DOUT_P27
C2C_DOUT_N27
C2C_DIN_P7
USER2_DIPSW0
USER2_DIPSW1
C2C_DIN_P28
C2C_DIN_P2
C2C_DOUT_P23
C2C_DOUT_N23
C2C_DIN_P5
A7
B7
C2C_DOUT_P28
C2C_DOUT_N28
Bank 7B
C
C2C_DOUT_P24
C2C_DOUT_N24
C2C_DIN_P9
C2C_DOUT_P16
C2C_DOUT_N16
C2C_DIN_P17
C2C_DIN_P4
C2C_DOUT_P21
C2C_DOUT_N21
C2C_DIN_P12
E10
F10
N10
B10
C10
H10
R11
A11
A10
J11
C2C_DOUT_P8
C2C_DOUT_N8
P12
R12
C2C_DOUT_P26
C2C_DOUT_N26
USER2_LED_R3
C2C_DOUT_P17
C2C_DOUT_N17
C2C_DIN_P14
C2C_DIN_P16
C2C_DOUT_P13
C2C_DOUT_N13
C2C_DIN_P24
M12
N12
F11
C11
D11
K12
F12
P13
R13
H12
C2C_DOUT_P12
C2C_DOUT_N12
D12
E12
DQ4T/DIFFIO_RX_T24p
DQ4T/DIFFIO_RX_T24n
DQ4T/DIFFIO_TX_T25p
DQ4T/DIFFIO_RX_T26p
DQ4T/DIFFIO_RX_T26n
DQ4T/DIFFIO_TX_T27p
DQ4T/DIFFIO_TX_T29p
DQ4T/DIFFIO_RX_T30p
DQ4T/DIFFIO_RX_T30n
DQ4T/DIFFIO_TX_T31p
DQS4T/DIFFIO_RX_T28p
DQSn4T/DIFFIO_RX_T28n
DQ5T/DIFFIO_RX_T32p
DQ5T/DIFFIO_RX_T32n
DQ5T
DQ5T/DIFFIO_RX_T33p
DQ5T/DIFFIO_RX_T33n
DQ5T/DIFFIO_TX_T34p
DQ5T/DIFFIO_TX_T36p
DQ5T/DIFFIO_RX_T37p
DQ5T/DIFFIO_RX_T37n
DQ5T/DIFFIO_TX_T38p
DQ6T/DIFFIO_RX_T39p
DQ6T/DIFFIO_RX_T39n
DQ6T/DIFFIO_TX_T40p
DQ6T/DIFFIO_RX_T41p
DQ6T/DIFFIO_RX_T41n
DQ6T/DIFFIO_TX_T42p
DQ6T/DIFFIO_TX_T44p
DQ6T/DIFFIO_RX_T45p
DQ6T/DIFFIO_RX_T45n
DQ6T/DIFFIO_TX_T46p
DQS6T/DIFFIO_RX_T43p
DQSn6T/DIFFIO_RX_T43n
DIFFIO_TX_T25n
DIFFIO_TX_T27n
DIFFIO_TX_T29n
DIFFIO_TX_T31n
DIFFIO_TX_T34n
DIFFIO_TX_T36n
DIFFIO_TX_T38n
DIFFIO_TX_T40n
DIFFIO_TX_T42n
DIFFIO_TX_T44n
DIFFIO_TX_T46n
B12
C12
M13
A13
A12
J13
A14
C14
D14
G13
C2C_DOUT_P22
C2C_DOUT_N22
C2C_DIN_P10
C2C_DOUT_P11
C2C_DOUT_N11
C2C_DIN_P26
C2C_DIN_P20
C2C_DOUT_P0
C2C_DOUT_N0
C2C_DIN_P22
D13
E13
C2C_DOUT_P9
C2C_DOUT_N9
M11
J10
T11
K11
L12
G12
J12
N13
K13
B13
H13
C2C_DIN_N9
C2C_DIN_N17
C2C_DIN_N4
C2C_DIN_N12
C2C_DIN_N14
C2C_DIN_N16
C2C_DIN_N24
C2C_DIN_N10
C2C_DIN_N26
C2C_DIN_N20
C2C_DIN_N22
C2C_DOUT_P6
C2C_DOUT_N6
C2C_DIN_P0
C2C_DOUT_P10
C2C_DOUT_N10
C2C_DIN_P11
C2C_DIN_P1
C2C_DOUT_P18
C2C_DOUT_N18
C2C_DIN_P27
R14
T14
M14
F14
G14
L15
N15
E15
F15
J14
C2C_DOUT_P20
C2C_DOUT_N20
R15
T15
C2C_DIN_N0
C2C_DIN_N11
C2C_DIN_N1
C2C_DIN_N27
N14
M15
P15
K14
DQ8T/DIFFIO_RX_T55p
DQ8T/DIFFIO_RX_T55n
DQ8T
DQ8T/DIFFIO_RX_T56p
DQ8T/DIFFIO_RX_T56n
DQ8T/DIFFIO_TX_T57p
DQ8T/DIFFIO_TX_T59p
DQ8T/DIFFIO_RX_T60p
DQ8T/DIFFIO_RX_T60n
DQ8T/DIFFIO_TX_T61p
DQS7T/DIFFIO_RX_T51p
DQSn7T/DIFFIO_RX_T51n
DQS8T/DIFFIO_RX_T58p
DQSn8T/DIFFIO_RX_T58n
DIFFIO_TX_T48n
DIFFIO_TX_T50n
DIFFIO_TX_T52n
DIFFIO_TX_T54n
DIFFIO_TX_T57n
DIFFIO_TX_T59n
DIFFIO_TX_T61n
P16
R16
C15
M16
N16
H15
A15
D16
E16
J16
C2C_DOUT_P15
C2C_DOUT_N15
USER2_LED_R1
C2C_DOUT_P14
C2C_DOUT_N14
C2C_DIN_P23
C2C_DIN_P18
C2C_DOUT_P7
C2C_DOUT_N7
C2C_DIN_P19
G16
H16
C2C_DOUT_P19
C2C_DOUT_N19
J15
B15
K16
C2C_DIN_N23
C2C_DIN_N18
C2C_DIN_N19
CHIP-TO_CHIP INTERFACE
C2C_DOUT_P[28:0]
C2C_DOUT_P4
C2C_DOUT_N4
C2C_DIN_P21
C2C_DOUT_P2
C2C_DOUT_N2
C2C_DIN_P15
C2C_DIN_P25
C2C_DOUT_P1
C2C_DOUT_N1
C2C_DIN_P3
N18
P18
M17
B16
C16
J17
R17
C17
D17
K18
C2C_DOUT_P3
C2C_DOUT_N3
F17
G17
C2C_DOUT_P25
C2C_DOUT_N25
USER2_LED_G1
R19
T19
R18
E18
F18
H18
B18
A17
A16
L19
SDI_A_RX_BYPASS
N19
P19
C2C_DOUT_P5
C2C_DOUT_N5
C2C_FPGA1_CLKIN_P
C2C_DIN_P13
DQS5T/DIFFIO_RX_T35p
DQSn5T/DIFFIO_RX_T35n
Version = 1.86 Pin-out
DQ9T/DIFFIO_RX_T62p
DQ9T/DIFFIO_RX_T62n
DQ9T/DIFFIO_TX_T63p
DQ9T/DIFFIO_RX_T64p
DQ9T/DIFFIO_RX_T64n
DQ9T/DIFFIO_TX_T65p
DQ9T/DIFFIO_TX_T67p
DQ9T/DIFFIO_RX_T68p
DQ9T/DIFFIO_RX_T68n
DQ9T/DIFFIO_TX_T69p
DQS9T/DIFFIO_RX_T66p
DQSn9T/DIFFIO_RX_T66n
7
C2C_DOUT_N[28:0]
7
C2C_DIN_P[28:0]
7
D
C2C_DIN_N[28:0]
7
C2C_FPGA1_CLKIN_P
C2C_FPGA1_CLKIN_N
12
12
FMC INTERFACE
FMC_HA_P[23:0]
13,16,17,31
FMC_HA_N[23:0]
Bank 7D
5AGXB3H4F40
B
DQ7T/DIFFIO_RX_T47p
DQ7T/DIFFIO_RX_T47n
DQ7T/DIFFIO_TX_T48p
DQ7T/DIFFIO_RX_T49p
DQ7T/DIFFIO_RX_T49n
DQ7T/DIFFIO_TX_T50p
DQ7T/DIFFIO_TX_T52p
DQ7T/DIFFIO_RX_T53p
DQ7T/DIFFIO_RX_T53n
DQ7T/DIFFIO_TX_T54p
DQ11T/DIFFIO_RX_T77p
DQ11T/DIFFIO_RX_T77n
DQ11T/DIFFIO_TX_T78p
DQ11T/DIFFIO_RX_T79p
DQ11T/DIFFIO_RX_T79n
DQ11T/DIFFIO_TX_T80p
DQ11T/DIFFIO_TX_T82p
DQ11T/DIFFIO_RX_T83p
DQ11T/DIFFIO_RX_T83n
DQ11T/DIFFIO_TX_T84p
DQS11T/DIFFIO_RX_T81p
DQSn11T/DIFFIO_RX_T81n
F19
G19
J19
C19
D19
J20
R20
F20
G20
M20
13,16,17,31
USER2_LED_G3
SDI INTERFACE
SDI_A_RX_BYPASS
SDI_A_TX_SD_HDn
SDI_A_RX_BYPASS
USER2_LED_G5
USER2_LED_G7
18,27,29
29
18,27,29
SDI_A_TX_SD_HDn
USER I/O INTERFACES
A18
A19
USER2_LED_R[7:0]
13,35,37
USER2_LED_G[7:0]
DQ10T/DIFFIO_RX_T70p
DQ10T/DIFFIO_RX_T70n
DQ10T
DQ10T/DIFFIO_RX_T71p
DQ10T/DIFFIO_RX_T71n
DQ10T/DIFFIO_TX_T72p
DQ10T/DIFFIO_TX_T74p
DQ10T/DIFFIO_RX_T75p
DQ10T/DIFFIO_RX_T75n
DQ10T/DIFFIO_TX_T76p
DQS10T/DIFFIO_RX_T73p
DQSn10T/DIFFIO_RX_T73n
DIFFIO_TX_T63n
DIFFIO_TX_T65n
DIFFIO_TX_T67n
DIFFIO_TX_T69n
DIFFIO_TX_T72n
DIFFIO_TX_T74n
DIFFIO_TX_T76n
DIFFIO_TX_T78n
DIFFIO_TX_T80n
DIFFIO_TX_T82n
DIFFIO_TX_T84n
N17
K17
T17
L18
J18
C18
M19
K19
K20
T20
N20
C
C2C_DIN_N21
C2C_DIN_N15
C2C_DIN_N25
C2C_DIN_N3
C2C_FPGA1_CLKIN_N
C2C_DIN_N13
USER2_LED_G0
USER2_LED_G2
USER2_LED_G4
USER2_LED_G6
USER2_LED_R0
35
USER2_PB[2:0]
13,35
USER2_DIPSW[7:0]
13,35,37
B
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
18
of
1
46
8
7
6
5
4
3
2
1
Arria V GX FPGA 2, Bank 8
E
E
U13G
VCCIO = 1.5V
U13H
Arria V GX Bank 8
Arria V GX Bank 8
Bank 8A
D
B30
C30
E31
B31
A30
A31
H31
C31
D31
C32
DDR3B_A4
DDR3B_A5
A33
B33
DDR3B_A3
DDR3B_A7
DDR3B_A11
F31
A32
J31
D32
K32
DQ20T/DIFFIO_RX_T146p
DQ20T/DIFFIO_RX_T146n
DQ20T/DIFFIO_TX_T147p
DQ20T/DIFFIO_RX_T148p
DQ20T/DIFFIO_RX_T148n
DQ20T/DIFFIO_TX_T149p
DQ20T/DIFFIO_TX_T151p
DQ20T/DIFFIO_RX_T152p
DQ20T/DIFFIO_RX_T152n
DQ20T/DIFFIO_TX_T153p
DQ21T/DIFFIO_RX_T154p
DQ21T/DIFFIO_RX_T154n
DQ21T/DIFFIO_TX_T155p
DQ21T/DIFFIO_RX_T156p
DQ21T/DIFFIO_RX_T156n
DQ21T/DIFFIO_TX_T157p
DQ21T/DIFFIO_TX_T159p
DQ21T/DIFFIO_TX_T161p
DQS21T/DIFFIO_RX_T158p
DQSn21T/DIFFIO_RX_T158n
DQS20T/DIFFIO_RX_T150p
DQSn20T/DIFFIO_RX_T150n
DQ22T
DQ22T/DIFFIO_TX_T166p
DQ22T/DIFFIO_TX_T168p
DIFFIO_TX_T147n
DIFFIO_TX_T149n
DIFFIO_TX_T151n
DIFFIO_TX_T153n
DIFFIO_TX_T155n
DIFFIO_TX_T157n
DIFFIO_TX_T159n
DIFFIO_TX_T161n
DIFFIO_TX_T166n
F33
N31
P31
J32
M32
N32
J34
L31
L34
RZQIN_B_1_5V 100, 1%
R227
DDR3C_DQ26
DDR3C_DQ30
DDR3C_DQ25
DDR3C_DQ28
DDR3C_DQ31
DDR3C_DQ24
DDR3C_DQ29
DDR3C_DM3
DDR3C_DQ27
DDR3B_A12
DDR3B_A13
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_ODT
DDR3B_CSn
C
DDR3B_DQS_P1
DDR3B_DQS_N1
L28
M28
H28
C28
D28
F28
J29
M29
N29
F29
R29
T29
J28
G28
K29
G29
DQ18T/DIFFIO_RX_T131p
DQ18T/DIFFIO_RX_T131n
DQ18T/DIFFIO_TX_T132p
DQ18T/DIFFIO_RX_T133p
DQ18T/DIFFIO_RX_T133n
DQ18T/DIFFIO_TX_T134p
DQ18T/DIFFIO_TX_T136p
DQ18T/DIFFIO_RX_T137p
DQ18T/DIFFIO_RX_T137n
DQ18T/DIFFIO_TX_T138p
DQS18T/DIFFIO_RX_T135p
DQSn18T/DIFFIO_RX_T135n
DIFFIO_TX_T132n
DIFFIO_TX_T134n
DIFFIO_TX_T136n
DIFFIO_TX_T138n
DQ19T/DIFFIO_RX_T139p
DQ19T/DIFFIO_RX_T139n
DQ19T
DQ19T/DIFFIO_RX_T140p
DQ19T/DIFFIO_RX_T140n
DQ19T/DIFFIO_TX_T141p
DQ19T/DIFFIO_TX_T143p
DQ19T/DIFFIO_RX_T144p
DQ19T/DIFFIO_RX_T144n
DQ19T/DIFFIO_TX_T145p
DQS19T/DIFFIO_RX_T142p
DQSn19T/DIFFIO_RX_T142n
DIFFIO_TX_T141n
DIFFIO_TX_T143n
DIFFIO_TX_T145n
T26
T25
G25
N24
P24
R24
K24
D25
E25
P25
L33 DDR3B_CASn
M33 DDR3B_WEn
DDR3C_DQS_P3
DDR3C_DQS_N3
A25
B25
J33
F32
E33
DDR3B_DQ24
DDR3B_DQ25
DDR3B_DQ26
DDR3B_DQ27
DDR3B_DQ28
DDR3B_DQ29
DDR3B_DM3
DDR3B_DQ30
DDR3B_DQ31
C26
D26
K25
R26
T27
A26
J26
F26
G26
M25
DDR3B_DQS_P3
DDR3B_DQS_N3
M26
N26
DDR3C_DM0
DDR3C_DQ2
M21
D21
R21
DDR3C_DQ15
DDR3C_DQ9
DDR3C_DQ13
DDR3C_DQ8
DDR3C_DQ10
DDR3C_DQ12
DDR3C_DQ14
J22
E22
F22
A23
L22
N22
P22
R22
K34 DDR3B_RASn
M31
M34
G32
Bank 8B
DDR3B_DQ8
DDR3B_DQ9
DDR3B_DQ10
DDR3B_DQ11
DDR3B_DQ12
DDR3B_DQ13
DDR3B_DM1
DDR3B_DQ14
DDR3B_DQ15
DDR3B x32 HMC
& DDR3C x64 SMC INTERFACE
Bank 8C
RZQ_6/DIFFIO_TX_T168n
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_CKE
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A6
DDR3B_A8
DDR3B_A9
DDR3B_A10
VCCIO = 1.5V
B28
C29
R30
A29
A28
L30
J30
D30
D29
F30
DDR3B_DQ0
DDR3B_DQ1
DDR3B_DQ2
DDR3B_DQ3
DDR3B_DQ4
DDR3B_DQ5
DDR3B_DM0
DDR3B_DQ6
DDR3B_DQ7
N30 DDR3B_DQS_P0
P30 DDR3B_DQS_N0
M30
K30
G30 DDR3B_RESETn
DDR3C_DQS_P1
DDR3C_DQS_N1
5AGXB3H4F40
C23
D23
Version = 1.86. Pin-out
N21
E21
T21
A24
B
DQ15T/DIFFIO_RX_T108p
DQ15T/DIFFIO_RX_T108n
DQ15T/DIFFIO_TX_T109p
DQ15T/DIFFIO_RX_T110p
DQ15T/DIFFIO_RX_T110n
DQ15T/DIFFIO_TX_T111p
DQ15T/DIFFIO_TX_T113p
DQ15T/DIFFIO_RX_T114p
DQ15T/DIFFIO_RX_T114n
DQ15T/DIFFIO_TX_T115p
DQS15T/DIFFIO_RX_T112p
DQSn15T/DIFFIO_RX_T112n
DQ17T/DIFFIO_RX_T123p
DQ17T/DIFFIO_RX_T123n
DQ17T/DIFFIO_TX_T124p
DQ17T/DIFFIO_RX_T125p
DQ17T/DIFFIO_RX_T125n
DQ17T/DIFFIO_TX_T126p
DQ17T/DIFFIO_TX_T128p
DQ17T/DIFFIO_RX_T129p
DQ17T/DIFFIO_RX_T129n
DQ17T/DIFFIO_TX_T130p
DQS17T/DIFFIO_RX_T127p
DQSn17T/DIFFIO_RX_T127n
DQ16T/DIFFIO_RX_T116p
DQ16T/DIFFIO_RX_T116n
DQ16T
DQ16T/DIFFIO_RX_T117p
DQ16T/DIFFIO_RX_T117n
DQ16T/DIFFIO_TX_T118p
DQ16T/DIFFIO_TX_T120p
DQ16T/DIFFIO_RX_T121p
DQ16T/DIFFIO_RX_T121n
DQ16T/DIFFIO_TX_T122p
DQS16T/DIFFIO_RX_T119p
DQSn16T/DIFFIO_RX_T119n
Bank 8D
DQ12T/DIFFIO_TX_T86p
DQ12T/DIFFIO_TX_T88p
DQ12T/DIFFIO_TX_T92p
DQ13T
DQ13T/DIFFIO_RX_T94p
DQ13T/DIFFIO_RX_T94n
DQ13T/DIFFIO_TX_T95p
DQ13T/DIFFIO_TX_T97p
DQ13T/DIFFIO_RX_T98p
DQ13T/DIFFIO_RX_T98n
DQ13T/DIFFIO_TX_T99p
DQS13T/DIFFIO_RX_T96p
DQSn13T/DIFFIO_RX_T96n
DIFFIO_TX_T86n
DIFFIO_TX_T88n
DIFFIO_TX_T92n
DIFFIO_TX_T95n
DIFFIO_TX_T109n
DIFFIO_TX_T111n
DIFFIO_TX_T113n
DIFFIO_TX_T115n
DIFFIO_TX_T118n
DIFFIO_TX_T120n
DIFFIO_TX_T122n
DIFFIO_TX_T124n
DIFFIO_TX_T126n
DIFFIO_TX_T128n
DIFFIO_TX_T130n
P27
R27
H27
B27
C27
E27
K27
M27
N27
N28
DDR3B_DQ[31:0]
DDR3B_DQ16
DDR3B_DQ17
DDR3B_DQ18
DDR3B_DQ19
DDR3B_DQ20
DDR3B_DQ21
DDR3B_DM2
DDR3B_DQ22
DDR3B_DQ23
24
DDR3B_A[13:0]
24,25
DDR3B_DQS_P[3:0]
24
DDR3B_DQS_N[3:0]
24
DDR3B_DM[3:0]
24
DDR3B_BA[2:0]
R28 DDR3B_DQS_P2
T28 DDR3B_DQS_N2
24,25
DDR3B_CSn
DDR3B_CASn
DDR3B_CKE
DDR3B_WEn
DDR3B_RASn
DDR3B_RESETn
DDR3B_CLK_P
DDR3B_CLK_N
DDR3B_ODT
H25
T24
L24
R25
A27
K26
N25
J27
F27
L27
P28
24,25
24,25
24,25
24,25
24,25
24,25
24,25
24,25
24,25
DDR3C_DQ[31:0]
13,25
DDR3C_DQS_P[3:0]
13,25
DDR3C_DQS_N[3:0]
DQ14T/DIFFIO_RX_T100p
DQ14T/DIFFIO_RX_T100n
DQ14T/DIFFIO_TX_T101p
DQ14T/DIFFIO_RX_T102p
DQ14T/DIFFIO_RX_T102n
DQ14T/DIFFIO_TX_T103p
DQ14T/DIFFIO_TX_T105p
DQ14T/DIFFIO_RX_T106p
DQ14T/DIFFIO_RX_T106n
DQ14T/DIFFIO_TX_T107p
DQS14T/DIFFIO_RX_T104p
DQSn14T/DIFFIO_RX_T104n
DIFFIO_TX_T97n
DIFFIO_TX_T99n
DIFFIO_TX_T101n
DIFFIO_TX_T103n
DIFFIO_TX_T105n
DIFFIO_TX_T107n
F23
G23
R23
B24
C24
M23
J23
F24
G24
H24
13,25
DDR3C_DM[3:0]
DDR3C_DQ23
DDR3C_DQ21
DDR3C_DQ19
DDR3C_DQ18
DDR3C_DQ16
DDR3C_DQ17
DDR3C_DM2
DDR3C_DQ22
DDR3C_DQ20
D
C
13,25
D24 DDR3C_DQS_P2
E24 DDR3C_DQS_N2
M22
T22
T23
N23
K23
J24
B
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
19
of
1
46
8
7
6
5
4
3
2
1
Arria V GX Transceivers and Power (FPGA 2)
U13R
U13Q
Arria V GX Transceivers
Arria V GX Transceivers
Bank GXB_L0
E
C2C_TXA_P0
C2C_TXA_N0
C2C_TXA_P1
C2C_TXA_N1
C2C_TXA_P2
C2C_TXA_N2
C2C_TXA_P3
C2C_TXA_N3
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C2C_TXA_P4
C2C_TXA_N4
0.1uF
0.1uF
C2C_RXB_P0 AW37
C2C_RXB_N0 AW36
C2C_RXB_P1 AT39
C2C_RXB_N1 AT38
C2C_RXB_P2 AP39
C2C_RXB_N2 AP38
C2C_RXB_P3 AM39
C2C_RXB_N3 AM38
AK39
AK38
C18 C2C_RXB_P4 AH39
C17
C2C_RXB_N4 AH38
C10
C9
C12
C11
C14
C13
C16
C15
D
AG32
AG33
AE31
AE32
REFCLK0_B_QL0_P
REFCLK0_B_QL0_N
REFCLK1_B_QL0_P
REFCLK1_B_QL0_N
10
10
10
10
Bank GXB_R0
GXB_RX_L0p/GXB_REFCLK_L0p
GXB_RX_L0n/GXB_REFCLK_L0n
GXB_RX_L1p/GXB_REFCLK_L1p
GXB_RX_L1n/GXB_REFCLK_L1n
GXB_RX_L2p/GXB_REFCLK_L2p
GXB_RX_L2n/GXB_REFCLK_L2n
GXB_RX_L3p/GXB_REFCLK_L3p
GXB_RX_L3n/GXB_REFCLK_L3n
GXB_RX_L4p/GXB_REFCLK_L4p
GXB_RX_L4n/GXB_REFCLK_L4n
GXB_RX_L5p/GXB_REFCLK_L5p
GXB_RX_L5n/GXB_REFCLK_L5n
GXB_TX_L0p
GXB_TX_L0n
GXB_TX_L1p
GXB_TX_L1n
GXB_TX_L2p
GXB_TX_L2n
GXB_TX_L3p
GXB_TX_L3n
GXB_TX_L4p
GXB_TX_L4n
GXB_TX_L5p
GXB_TX_L5n
AU37
AU36
AR37
AR36
AN37
AN36
AL37
AL36
AJ37
AJ36
AG37
AG36
C2C_TXB_P0
C2C_TXB_N0
C2C_TXB_P1
C2C_TXB_N1
C2C_TXB_P2
C2C_TXB_N2
C2C_TXB_P3
C2C_TXB_N3
HSMB_RX_P3
HSMB_RX_N3
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P0
HSMB_RX_N0
SDI_A_RX_P
SDI_A_RX_N
30
30
30
30
30
30
30
30
29
29
C2C_TXB_P4
C2C_TXB_N4
10.0K
REFCLK0_B_QR0_P
REFCLK0_B_QR0_N
REFCLK1_B_QR0_P
REFCLK1_B_QR0_N
AF8
AF7
AD9
AD8
FMC_DP_M2C_P0
FMC_DP_M2C_N0
SMA_B_RX_R6_P
SMA_B_RX_R6_N
FMC_DP_M2C_P1
FMC_DP_M2C_N1
SMA_B_RX_R9_P
SMA_B_RX_R9_N
FMC_DP_M2C_P2
FMC_DP_M2C_N2
FMC_DP_M2C_P3
FMC_DP_M2C_N3
AE1
AE2
AC1
AC2
AA1
AA2
W1
W2
U1
U2
R1
R2
C810 FMC_REFCLK_P0
C811 FMC_REFCLK_N0
AB9
AB8
Y9
Y8
11
11
10
10
REFCLK0Lp
REFCLK0Ln
REFCLK1Lp
REFCLK1Ln
R339
AU1
AU2
AR1
AR2
AN1
AN2
AL1
AL2
AJ1
AJ2
AG1
AG2
GXB_RX_R0p/GXB_REFCLK_R0p
GXB_RX_R0n/GXB_REFCLK_R0n
GXB_RX_R1p/GXB_REFCLK_R1p
GXB_RX_R1n/GXB_REFCLK_R1n
GXB_RX_R2p/GXB_REFCLK_R2p
GXB_RX_R2n/GXB_REFCLK_R2n
GXB_RX_R3p/GXB_REFCLK_R3p
GXB_RX_R3n/GXB_REFCLK_R3n
GXB_RX_R4p/GXB_REFCLK_R4p
GXB_RX_R4n/GXB_REFCLK_R4n
GXB_RX_R5p/GXB_REFCLK_R5p
GXB_RX_R5n/GXB_REFCLK_R5n
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C20
C19
C22
C21
C24
C23
C2C_RXB_P5
C2C_RXB_N5
C2C_RXB_P6
C2C_RXB_N6
C2C_RXB_P7
C2C_RXB_N7
AC31
AC32
AA31
AA32
REFCLK2_B_QL1_P
REFCLK2_B_QL1_N
10
10
10.0K
AF39
AF38
AD39
AD38
AB39
AB38
Y39
Y38
V39
V38
T39
T38
R241
C
B39
R216 RREFB_TL
GXB_TX_L6p
GXB_TX_L6n
GXB_TX_L7p
GXB_TX_L7n
GXB_TX_L8p
GXB_TX_L8n
GXB_TX_L9p
GXB_TX_L9n
GXB_TX_L10p
GXB_TX_L10n
GXB_TX_L11p
GXB_TX_L11n
AE37
AE36
AC37
AC36
AA37
AA36
W37
W36
U37
U36
R37
R36
C2C_TXB_P5
C2C_TXB_N5
C2C_TXB_P6
C2C_TXB_N6
C2C_TXB_P7
C2C_TXB_N7
31
31
10
10
REFCLK2Lp
REFCLK2Ln
REFCLK3Lp
REFCLK3Ln
FMC_GBTCLK_M2C_P0 0.1uF
FMC_GBTCLK_M2C_N0 0.1uF
REFCLK2_B_QR1_P
REFCLK2_B_QR1_N
2.00K
SMA_B_RX_L15_P
SMA_B_RX_L15_N
10.0K
B
10.0K
10
10
R220
R242
REFCLK4_B_QL2_P
REFCLK4_B_QL2_N
W31
W32
U31
U32
R345
RREFB_BR
AW2
GXB_RX_R6p/GXB_REFCLK_R6p
GXB_RX_R6n/GXB_REFCLK_R6n
GXB_RX_R7p/GXB_REFCLK_R7p
GXB_RX_R7n/GXB_REFCLK_R7n
GXB_RX_R8p/GXB_REFCLK_R8p
GXB_RX_R8n/GXB_REFCLK_R8n
GXB_RX_R9p/GXB_REFCLK_R9p
GXB_RX_R9n/GXB_REFCLK_R9n
GXB_RX_R10p/GXB_REFCLK_R10p
GXB_RX_R10n/GXB_REFCLK_R10n
GXB_RX_R11p/GXB_REFCLK_R11p
GXB_RX_R11n/GXB_REFCLK_R11n
AD3
AD4
AB3
AB4
Y3
Y4
V3
V4
T3
T4
P3
P4
FMC_DP_C2M_P0
FMC_DP_C2M_N0
SMA_B_TX_R6_P
SMA_B_TX_R6_N
FMC_DP_C2M_P1
FMC_DP_C2M_N1
SMA_B_TX_R9_P
SMA_B_TX_R9_N
FMC_DP_C2M_P2
FMC_DP_C2M_N2
FMC_DP_C2M_P3
FMC_DP_C2M_N3
30
30
30
30
30
30
30
30
29
29
E
GXB_RX_L12p,GXB_REFCLK_L12p
GXB_RX_L12n,GXB_REFCLK_L12n
GXB_RX_L13p,GXB_REFCLK_L13p
GXB_RX_L13n,GXB_REFCLK_L13n
GXB_RX_L14p,GXB_REFCLK_L14p
GXB_RX_L14n,GXB_REFCLK_L14n
GXB_RX_L15p,GXB_REFCLK_L15p
GXB_RX_L15n,GXB_REFCLK_L15n
GXB_RX_L16p,GXB_REFCLK_L16p
GXB_RX_L16n,GXB_REFCLK_L16n
GXB_RX_L17p,GXB_REFCLK_L17p
GXB_RX_L17n,GXB_REFCLK_L17n
GXB_TX_L12p
GXB_TX_L12n
GXB_TX_L13p
GXB_TX_L13n
GXB_TX_L14p
GXB_TX_L14n
GXB_TX_L15p
GXB_TX_L15n
GXB_TX_L16p
GXB_TX_L16n
GXB_TX_L17p
GXB_TX_L17n
GXB_TX_R6p
GXB_TX_R6n
GXB_TX_R7p
GXB_TX_R7n
GXB_TX_R8p
GXB_TX_R8n
GXB_TX_R9p
GXB_TX_R9n
GXB_TX_R10p
GXB_TX_R10n
GXB_TX_R11p
GXB_TX_R11n
D
REFCLK2Rp
REFCLK2Rn
REFCLK3Rp
REFCLK3Rn
Reference Resistor
C
RREF_BR
RREF_TL
ONLY AVAILABLE IN GT DEVICES
Bank GXB_R2
ONLY AVAILABLE IN GT DEVICES
Bank GXB_L2
P39
P38
M39
M38
K39
K38
H39
H38
F39
F38
D39
D38
HSMB_TX_P3
HSMB_TX_N3
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P0
HSMB_TX_N0
SDI_A_TX_P
SDI_A_TX_N
Bank GXB_R1
GXB_RX_L6p/GXB_REFCLK_L6p
GXB_RX_L6n/GXB_REFCLK_L6n
GXB_RX_L7p/GXB_REFCLK_L7p
GXB_RX_L7n/GXB_REFCLK_L7n
GXB_RX_L8p/GXB_REFCLK_L8p
GXB_RX_L8n/GXB_REFCLK_L8n
GXB_RX_L9p/GXB_REFCLK_L9p
GXB_RX_L9n/GXB_REFCLK_L9n
GXB_RX_L10p/GXB_REFCLK_L10p
GXB_RX_L10n/GXB_REFCLK_L10n
GXB_RX_L11p/GXB_REFCLK_L11p
GXB_RX_L11n/GXB_REFCLK_L11n
Reference Resistor
2.00K
AT3
AT4
AP3
AP4
AM3
AM4
AK3
AK4
AH3
AH4
AF3
AF4
REFCLK0Rp
REFCLK0Rn
REFCLK1Rp
REFCLK1Rn
Bank GXB_L1
C2C_TXA_P5
C2C_TXA_N5
C2C_TXA_P6
C2C_TXA_N6
C2C_TXA_P7
C2C_TXA_N7
GXB_TX_R0p
GXB_TX_R0n
GXB_TX_R1p
GXB_TX_R1n
GXB_TX_R2p
GXB_TX_R2n
GXB_TX_R3p
GXB_TX_R3n
GXB_TX_R4p
GXB_TX_R4n
GXB_TX_R5p
GXB_TX_R5n
N37
N36
L37
L36
J37
J36
G37
G36
E37
E36
C37
C36
FMC_DP_M2C_P5
FMC_DP_M2C_N5
FMC_DP_M2C_P6
FMC_DP_M2C_N6
FMC_DP_M2C_P4
FMC_DP_M2C_N4
FMC_DP_M2C_P7
FMC_DP_M2C_N7
FMC_DP_M2C_P8
FMC_DP_M2C_N8
FMC_DP_M2C_P9
FMC_DP_M2C_N9
SMA_B_TX_L15_P
SMA_B_TX_L15_N
31
31
FMC_GBTCLK_M2C_P1 0.1uF
FMC_GBTCLK_M2C_N1 0.1uF
10
10
REFCLK4Lp
REFCLK4Ln
REFCLK5Lp
REFCLK5Ln
C812 FMC_REFCLK_P1
C813 FMC_REFCLK_N1
REFCLK3_B_QR2_P
REFCLK3_B_QR2_N
N1
N2
L1
L2
J1
J2
G1
G2
E1
E2
C1
C2
V9
V8
T9
T8
GXB_RX_R12p,GXB_REFCLK_R12p
GXB_RX_R12n,GXB_REFCLK_R12n
GXB_RX_R13p,GXB_REFCLK_R13p
GXB_RX_R13n,GXB_REFCLK_R13n
GXB_RX_R14p,GXB_REFCLK_R14p
GXB_RX_R14n,GXB_REFCLK_R14n
GXB_RX_R15p,GXB_REFCLK_R15p
GXB_RX_R15n,GXB_REFCLK_R15n
GXB_RX_R16p,GXB_REFCLK_R16p
GXB_RX_R16n,GXB_REFCLK_R16n
GXB_RX_R17p,GXB_REFCLK_R17p
GXB_RX_R17n,GXB_REFCLK_R17n
GXB_TX_R12p
GXB_TX_R12n
GXB_TX_R13p
GXB_TX_R13n
GXB_TX_R14p
GXB_TX_R14n
GXB_TX_R15p
GXB_TX_R15n
GXB_TX_R16p
GXB_TX_R16n
GXB_TX_R17p
GXB_TX_R17n
M3
M4
K3
K4
H3
H4
F3
F4
D3
D4
B3
B4
FMC_DP_C2M_P5
FMC_DP_C2M_N5
FMC_DP_C2M_P6
FMC_DP_C2M_N6
FMC_DP_C2M_P4
FMC_DP_C2M_N4
FMC_DP_C2M_P7
FMC_DP_C2M_N7
FMC_DP_C2M_P8
FMC_DP_C2M_N8
FMC_DP_C2M_P9
FMC_DP_C2M_N9
REFCLK4Rp
REFCLK4Rn
REFCLK5Rp
REFCLK5Rn
B
5AGXB3H4F40
Version = 1.86 Pin-out
5AGXB3H4F40
Version = 1.86 Pin-out
0.1uF
C82 SMA_B_10G_RX_N01
1
J25
SMA_B_TX_R9_P
1
SMA_B_TX_R9_N
1
CHIP-TO-CHIP XCVR INTERFACE
FMC XCVR INTERFACE
SMA_B_TX_L15_P
SMA_B_TX_L15_N
SMA_B_TX_R6_P
SMA_B_TX_R6_N
C2C_TXA_P[7:0]
FMC_DP_C2M_P[9:0]
J13
SMA_B_RX_L15_P
SMA_B_RX_L15_N
SMA_B_RX_R6_P
SMA_B_RX_R6_N
J24
2
3
4
5
SMA_B_RX_R9_N
C83 SMA_B_10G_RX_P0
J12
2
3
4
5
SMA_B_RX_R9_P 0.1uF
FPGA 2 BULLSEYE SMA INTERFACE
9
9
9
9
2
3
4
5
Title
5
4
9
31
FMC_DP_C2M_N[9:0]
31
FMC_DP_M2C_P[9:0]
31
FMC_DP_M2C_N[9:0]
31
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Date:
6
9
C2C_TXB_N[7:0]
B
7
9
C2C_TXB_P[7:0]
Size
8
9
C2C_TXA_N[7:0]
2
3
4
5
A
9
9
9
9
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
20
of
1
46
8
7
DDR3A_CLK_P
100, 1%
6
5
4
3
DDR3A For FPGA 1, (x72 devices) - Part 1 of 2
DDR3A_CLK_N
R340
VTT_DDR3A
Uses Soft Controller
DDR3A_BA[2:0]
8,22
VTT_DDR3A
DDR3A_DM[8:0]
8,22
E
1
2
3
4
DDR3A_DQS_P[8:0]
8,22
DDR3A_DQS_N[8:0]
8,22
CN3
VTT_DDR3A
8
7
6
5
0.1uF
1
2
3
4
VTT_DDR3A
CN1
8
1
7
2
6
3
5
4
CN2
DDR3A_A0
DDR3A_A1
DDR3A_CSn
DDR3A_A2
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
1.5V
8
7
6
5
DDR3A_RESETn
R291
51
DDR3A_CKE
R311
4.70K, 1%
0.1uF
0.1uF
1
4
7
2
5
8
3
6
RN3A
RN3D
RN3G
RN2B
RN2E
RN2H
RN1C
RN1F
16
13
10
15
12
9
14
11
51
51
51
51
51
51
51
51
1
VTT_DDR3A
DDR3A_A8
DDR3A_A9
RN3B
RN3E
RN3H
RN2C
RN2F
RN1A
RN1D
RN1G
DDR3A_A11
DDR3A_A12
DDR3A_A13
DDR3A_A10
2
5
8
3
6
1
4
7
15
12
9
14
11
16
13
10
51
51
51
51
51
51
51
51
VTT_DDR3A
DDR3A_BA0
DDR3A_WEn
DDR3A_RASn
DDR3A_A3
DDR3A_BA1
DDR3A_BA2
DDR3A_CASn
DDR3A_ODT
RN3C
RN3F
RN2A
RN2D
RN2G
RN1B
RN1E
RN1H
3
6
1
4
7
2
5
8
14
11
16
13
10
15
12
9
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3A_DQ0
DDR3A_DQ1
DDR3A_DQ2
DDR3A_DQ3
DDR3A_DQ4
DDR3A_DQ5
DDR3A_DQ6
DDR3A_DQ7
DDR3A_DQ8
DDR3A_DQ9
DDR3A_DQ10
DDR3A_DQ11
DDR3A_DQ12
DDR3A_DQ13
DDR3A_DQ14
DDR3A_DQ15
F3
G3
C7
B7
DDR3A_DQS_P0
DDR3A_DQS_N0
DDR3A_DQS_P1
DDR3A_DQS_N1
51
51
51
51
51
51
51
51
E
DDR3A_DQ[71:0]
8,12,22
DDR3A_A[13:0]
8,22
U11
U18
DDR3 Device
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
D
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
K9
DDR3A_CKE
DDR3A_CLK_P J7
DDR3A_CLK_N K7
C
B
1.5V
DDR3A_DM6
DDR3A_DM7
E7
D3
DDR3A_CSn
DDR3A_WEn
DDR3A_RASn
DDR3A_CASn
L2
L3
J3
K3
M2
DDR3A_BA0
N8
DDR3A_BA1
M3
DDR3A_BA2
DDR3A_RESETnT2
K1
DDR3A_ODT
L8
DDR3A_ZQ04
VREF_DDR3A
H1
M8
R267
C946
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
DM0
DM1
CS
WE
RAS
CAS
NC1
NC2
NC3
NC4
NC5
NC6
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U21
DDR3 Device
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3A_DQ48
DDR3A_DQ49
DDR3A_DQ50
DDR3A_DQ51
DDR3A_DQ52
DDR3A_DQ53
DDR3A_DQ54
DDR3A_DQ55
DDR3A_DQ56
DDR3A_DQ57
DDR3A_DQ58
DDR3A_DQ59
DDR3A_DQ60
DDR3A_DQ61
DDR3A_DQ62
DDR3A_DQ63
F3
G3
C7
B7
DDR3A_DQS_P6
DDR3A_DQS_N6
DDR3A_DQS_P7
DDR3A_DQS_N7
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
K9
DDR3A_CKE
DDR3A_CLK_P J7
DDR3A_CLK_N K7
J1
J9
L1
L9
M7
T7
DDR3A_DM4
DDR3A_DM5
E7
D3
DDR3A_CSn
DDR3A_WEn
DDR3A_RASn
DDR3A_CASn
L2
L3
J3
K3
M2
DDR3A_BA0
N8
DDR3A_BA1
M3
DDR3A_BA2
DDR3A_RESETnT2
K1
DDR3A_ODT
L8
DDR3A_ZQ03
VREF_DDR3A
H1
M8
R314
C877
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
Place These Caps Near DDR3
(U11, U18, U21, U28)
MT41J128M16HA
A
2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC1
NC2
NC3
NC4
NC5
NC6
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U28
DDR3 Device
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3A_DQ32
DDR3A_DQ33
DDR3A_DQ34
DDR3A_DQ35
DDR3A_DQ36
DDR3A_DQ37
DDR3A_DQ38
DDR3A_DQ39
DDR3A_DQ40
DDR3A_DQ41
DDR3A_DQ42
DDR3A_DQ43
DDR3A_DQ44
DDR3A_DQ45
DDR3A_DQ46
DDR3A_DQ47
F3
G3
C7
B7
DDR3A_DQS_P4
DDR3A_DQS_N4
DDR3A_DQS_P5
DDR3A_DQS_N5
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
K9
DDR3A_CKE
DDR3A_CLK_P J7
DDR3A_CLK_N K7
J1
J9
L1
L9
M7
T7
DDR3A_DM2
DDR3A_DM3
E7
D3
DDR3A_CSn
DDR3A_WEn
DDR3A_RASn
DDR3A_CASn
L2
L3
J3
K3
M2
DDR3A_BA0
N8
DDR3A_BA1
M3
DDR3A_BA2
DDR3A_RESETnT2
K1
DDR3A_ODT
L8
DDR3A_ZQ02
VREF_DDR3A
H1
M8
R346
C705
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J128M16HA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC1
NC2
NC3
NC4
NC5
NC6
DDR3 Device
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3A_DQ16
DDR3A_DQ17
DDR3A_DQ18
DDR3A_DQ19
DDR3A_DQ20
DDR3A_DQ21
DDR3A_DQ22
DDR3A_DQ23
DDR3A_DQ24
DDR3A_DQ25
DDR3A_DQ26
DDR3A_DQ27
DDR3A_DQ28
DDR3A_DQ29
DDR3A_DQ30
DDR3A_DQ31
F3
G3
C7
B7
DDR3A_DQS_P2
DDR3A_DQS_N2
DDR3A_DQS_P3
DDR3A_DQS_N3
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
K9
DDR3A_CKE
DDR3A_CLK_P J7
DDR3A_CLK_N K7
8,22
12,22
12,22
8,22
8,22
8,22
8,22
J1
J9
L1
L9
M7
T7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DDR3A_DM0
DDR3A_DM1
E7
D3
DDR3A_CSn
DDR3A_WEn
DDR3A_RASn
DDR3A_CASn
L2
L3
J3
K3
M2
DDR3A_BA0
N8
DDR3A_BA1
M3
DDR3A_BA2
DDR3A_RESETn T2
K1
DDR3A_ODT
L8
DDR3A_ZQ01
VREF_DDR3A
H1
M8
R409
C529
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
8,22
8,22
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J128M16HA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
NC1
NC2
NC3
NC4
NC5
NC6
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D
J1
J9
L1
L9
M7
T7
C
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J128M16HA
C774
C775
C629 C628 C627
C626
C943
C397
C876
C772
C945
C949
C920
C919
C918
C917
C922
C948
C702
C859
C530
C531
C921
C776
C527
C858
C833
C773
2.2nF
2.2nF
2.2nF 2.2nF 2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3.3nF
3.3nF
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
1.5V
Title
C944
C878
C947
C528
C495
C707
C708
C706
C704
C625
C624
C879
C875
C703
C453
C400
C401
C496
C399
C398
Size
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
21
of
1
46
8
7
6
5
4
3
2
1
DDR3A For FPGA 1, (x72 devices) - Part 2 of 2
Uses Soft Controller
U7
E
E
DDR3 Device
DDR3A_A0
DDR3A_A1
DDR3A_A2
DDR3A_A3
DDR3A_A4
DDR3A_A5
DDR3A_A6
DDR3A_A7
DDR3A_A8
DDR3A_A9
DDR3A_A10
DDR3A_A11
DDR3A_A12
DDR3A_A13
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
DDR3A_CKE
DDR3A_CLK_P
DDR3A_CLK_N
G9
F7
G7
DDR3A_DM8
DDR3A_DQS_P8
DDR3A_DQS_N8
B7
A7
C3
D3
8,21
8,21
8,21
8,21
DDR3A_CSn
DDR3A_WEn
DDR3A_RASn
DDR3A_CASn
H2
H3
F3
G3
8,21
8,21
DDR3A_BA0
DDR3A_BA1
DDR3A_BA2
DDR3A_RESETn
DDR3A_ODT
J2
K8
J3
N2
G1
DDR3A_ZQ05
1.5V
R232
H8
8,21
12,21
12,21
D
C
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
NC1
NC2
NC3
NC4
NC5
NC6
NC7
CKE
CK_P
CK_N
B3
C7
C2
C8
E3
E8
D2
E7
DDR3A_DQ64
DDR3A_DQ65
DDR3A_DQ66
DDR3A_DQ67
DDR3A_DQ68
DDR3A_DQ69
DDR3A_DQ70
DDR3A_DQ71
A3
F1
F9
H1
H9
J7
N7
DDR3A INTERFACE
DDR3A_BA[2:0]
8,21
DDR3A_DM[8:0]
8,21
DDR3A_DQS_P[8:0]
8,21
D
DDR3A_DQS_N[8:0]
8,21
DDR3A_DQ[71:0]
DM/TDQS_P
NF/TDQS_N
DQS_P
DQS_N
8,12,21
DDR3A_A[13:0]
8,21
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
E9
E2
B9
C1
VDDQ
VDDQ
VDDQ
VDDQ
240
M9
M1
K9
K1
G8
G2
D7
A9
A2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
C
VREF_DDR3A
VREFCA
VREFDQ
J8
E1
C259
MT41J128M8JP
0.1uF
B
B
Place These Caps Near DDR3 (U7)
1.5V
C309
C310
C351
C261
C352
C262
C274
C258
C350
C263
C257
C260
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.47uF
0.1uF
0.01uF
0.1uF
0.01uF
0.01uF
4.7nF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
22
of
1
46
8
7
6
5
4
3
2
1
QDRII+
E
U8A
QDRII_D0
QDRII_D1
QDRII_D2
QDRII_D3
QDRII_D4
QDRII_D5
QDRII_D6
QDRII_D7
QDRII_D8
QDRII_D9
QDRII_D10
QDRII_D11
QDRII_D12
QDRII_D13
QDRII_D14
QDRII_D15
QDRII_D16
QDRII_D17
QDRII_D18
QDRII_D19
QDRII_D20
QDRII_D21
QDRII_D22
QDRII_D23
QDRII_D24
QDRII_D25
QDRII_D26
QDRII_D27
QDRII_D28
QDRII_D29
QDRII_D30
QDRII_D31
QDRII_D32
QDRII_D33
QDRII_D34
QDRII_D35
P10
N11
M11
K10
J11
G11
E10
D11
C11
N10
M9
L9
J9
G10
F9
D10
C9
B9
B3
C3
D2
F3
G2
J3
L3
M3
N2
C1
D1
E2
G1
J1
K2
M1
N1
P2
5
5
5
5
5
5
QDRII_BWSn0
QDRII_BWSn1
QDRII_BWSn2
QDRII_BWSn3
QDRII_WPSn
QDRII_RPSn
B7
A7
A5
B5
A4
A8
5
5
QDRII_K_P
QDRII_K_N
B6
A6
5
5
QDRII_C_P
QDRII_C_N
P6
R6
5
5
QDRII_CQ_P
QDRII_CQ_N
A11
A1
5
QDRII_DOFFn
H1
D
1.8V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
C
QDRII+ QVLD = QDRII C_P
QDRII+ ODT = QDRII C_N
B
10.0K
R277
R234
178
H11
BWS0
BWS1
BWS2
BWS3
WPS
RPS
K_P
K_N
QVLD
ODT
CQ_P
CQ_N
DOFF
TMS
TDI
TDO
TCK
JTAG
R10
R11
R1
R2
1.8V
NC36
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
NC/72M
NC/144M
NC/288M
VREF
VREF
ZQ
P11
M10
L11
K11
J10
F11
E11
C10
B11
P9
N9
L10
K9
G9
F10
E9
D9
B10
B2
D3
E3
F2
G3
K3
L2
N3
P3
B1
C2
E1
F1
J2
K1
L1
M2
P1
E
U8B
F5
F7
G5
G7
H5
H7
J5
J7
K5
K7
QDRII_Q0
QDRII_Q1
QDRII_Q2
QDRII_Q3
QDRII_Q4
QDRII_Q5
QDRII_Q6
QDRII_Q7
QDRII_Q8
QDRII_Q9
QDRII_Q10
QDRII_Q11
QDRII_Q12
QDRII_Q13
QDRII_Q14
QDRII_Q15
QDRII_Q16
QDRII_Q17
QDRII_Q18
QDRII_Q19
QDRII_Q20
QDRII_Q21
QDRII_Q22
QDRII_Q23
QDRII_Q24
QDRII_Q25
QDRII_Q26
QDRII_Q27
QDRII_Q28
QDRII_Q29
QDRII_Q30
QDRII_Q31
QDRII_Q32
QDRII_Q33
QDRII_Q34
QDRII_Q35
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1.8V
E4
E8
F4
F8
L8
G4
G8
H3
H4
H8
H9
J4
J8
K4
K8
L4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C4
C8
D4
D5
D6
D7
D8
E5
E6
E7
F6
G6
H6
J6
K6
L5
L6
L7
M4
M5
M6
M7
M8
N4
N8
Altera recomends to use external termination for QDRII/+ address
and command signals. In this case external termination was not
used, because simulations showed that with the short trace
length and a point to point connection the external temination
was not necessary. As a result since there is limited board space
external termination is not used.
QDRII+ INTERFACE
QDRII_A[20:0]
5,12
QDRII_Q[35:0]
5,12
D
QDRII_D[35:0]
5
R1QDA7236ABG_19IB0
C
C6
R9
R8
B4
B8
C5
C7
N5
N6
N7
P4
P5
P7
P8
R3
R4
R5
R7
A9
A3
A10
A2
QDRII_A0
QDRII_A1
QDRII_A2
QDRII_A3
QDRII_A4
QDRII_A5
QDRII_A6
QDRII_A7
QDRII_A8
QDRII_A9
QDRII_A10
QDRII_A11
QDRII_A12
QDRII_A13
QDRII_A14
QDRII_A15
QDRII_A16
QDRII_A17
QDRII_A18
QDRII_A19
QDRII_A20
QDRII_C_N
49.9
B
Place These Caps Near QDRII+
1.8V
H2
H10
R264
1.8V
VDD DECOUPLING
VDDQ DECOUPLING
VREF_QDRII
C365
C325
C374
C364
C424
C425
C327
C328
C285
C421
C420
C371
C423
C368
0.1uF
0.1uF
0.1uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
1.0uF
0.1uF
0.01uF
2.2nF
3.3nF
1.0nF
C369
C422
C370
C372
C373
C366
C367
C329
2.2nF
3.3nF
4.7nF
4.7nF
4.7nF
22nF
22nF
2.2uF
R1QDA7236ABG_19IB0
C509
C508
0.1uF
0.1uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
23
of
1
46
8
7
6
5
4
3
DDR3 For FPGA 2, (x32 Hard IP devices)
VTT_DDR3B
DDR3B_CLK_P
100, 1%
DDR3B_CLK_N
R247
1
2
3
4
E
VTT_DDR3B
CN4
8
7
6
5
1
2
3
4
0.1uF
VTT_DDR3B
CN6
8
1
7
2
6
3
5
4
CN5
V29
V27
V26
V16
V28
V15
V25
V14
8
7
6
5
0.1uF
0.1uF
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
RN6A
RN6D
RN6G
RN8B
RN8E
RN8H
RN7C
RN7F
2
VTT_DDR3B
1
4
7
2
5
8
3
6
16
13
10
15
12
9
14
11
51
51
51
51
51
51
51
51
1
VTT_DDR3B
V22
V23
DDR3B_A8
DDR3B_A9
V24
V30
V21
V33
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_A10
RN6B
RN6E
RN6H
RN8C
RN8F
RN7A
RN7D
RN7G
2
5
8
3
6
1
4
7
15
12
9
14
11
16
13
10
51
51
51
51
51
51
51
51
VTT_DDR3B
V18
V34
V20
V17
V31
V32
V36
V19
DDR3B_CSn
DDR3B_WEn
DDR3B_RASn
DDR3B_BA0
DDR3B_BA1
DDR3B_BA2
DDR3B_CASn
DDR3B_ODT
RN6C
RN6F
RN8A
RN8D
RN8G
RN7B
RN7E
RN7H
3
6
1
4
7
2
5
8
14
11
16
13
10
15
12
9
51
51
51
51
51
51
51
51
E
U6
DDR3 Device
U12
DDR3 Device
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
D
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
K9
DDR3B_CKE
DDR3B_CLK_P J7
DDR3B_CLK_N K7
DDR3B_DM2
DDR3B_DM3
DDR3B_CSn
DDR3B_WEn
DDR3B_RASn
DDR3B_CASn
E7
D3
L2
L3
J3
K3
M2
DDR3B_BA0
N8
DDR3B_BA1
M3
DDR3B_BA2
DDR3B_RESETnT2
K1
DDR3B_ODT
L8
DDR3B_ZQ1
VREF_DDR3B
H1
R276
M8
C348
B2
D9
0.1uF
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
C
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
NC1
NC2
NC3
NC4
NC5
NC6
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
DDR3B_DQ16
DDR3B_DQ17
DDR3B_DQ18
DDR3B_DQ19
DDR3B_DQ20
DDR3B_DQ21
DDR3B_DQ22
DDR3B_DQ23
DDR3B_DQ24
DDR3B_DQ25
DDR3B_DQ26
DDR3B_DQ27
DDR3B_DQ28
DDR3B_DQ29
DDR3B_DQ30
DDR3B_DQ31
K9
DDR3B_CKE
DDR3B_CLK_P J7
DDR3B_CLK_N K7
19,25
19,25
19,25
DDR3B_DQS_P2
DDR3B_DQS_N2
DDR3B_DQS_P3
DDR3B_DQS_N3
19,25
19,25
19,25
19,25
J1
J9
L1
L9
M7
T7
19,25
19,25
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
DDR3B_DM0
DDR3B_DM1
E7
D3
DDR3B_CSn
DDR3B_WEn
DDR3B_RASn
DDR3B_CASn
L2
L3
J3
K3
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
DM0
DM1
NC1
NC2
NC3
NC4
NC5
NC6
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DDR3B_DQ0
DDR3B_DQ1
DDR3B_DQ2
DDR3B_DQ3
DDR3B_DQ4
DDR3B_DQ5
DDR3B_DQ6
DDR3B_DQ7
DDR3B_DQ8
DDR3B_DQ9
DDR3B_DQ10
DDR3B_DQ11
DDR3B_DQ12
DDR3B_DQ13
DDR3B_DQ14
DDR3B_DQ15
F3
G3
C7
B7
DDR3B_DQS_P0
DDR3B_DQS_N0
DDR3B_DQS_P1
DDR3B_DQS_N1
1.5V
V13
DDR3B_RESETn
R290
51
V35
DDR3B_CKE
R310
4.70K, 1%
D
DDR3B INTERFACE
DDR3B_BA[2:0]
DDR3B_DM[3:0]
DDR3B_DQS_P[3:0]
DDR3B_DQS_N[3:0]
CS
WE
RAS
CAS
M2
DDR3B_BA0
N8
DDR3B_BA1
M3
DDR3B_BA2
DDR3B_RESETn T2
DDR3B_ODT
K1
L8
DDR3B_ZQ2
VREF_DDR3B
H1
M8
R243
C621
B2
D9
0.1uF
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
J1
J9
L1
L9
M7
T7
DDR3B_DQ[31:0]
DDR3B_A[13:0]
19,25
19
19
19
19
19,25
C
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
B
MT41J128M16HA
MT41J128M16HA
1.5V
Place These Caps Near DDR3 (U6 and U12)
C392
C302
C225
C227
C252
C305
C306
C273
C304
C303
C490
C489
C395
C396
C228
C391
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3.3nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
1.5V
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C488
C223
C224
C491
C390
C492
C493
C393
C253
C394
0.01uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
24
of
1
46
8
7
6
5
4
3
2
1
DDR3C For FPGA 2, (x64 Using Soft Controller Option)
U22
DDR3 Device
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
E
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
K9
DDR3B_CKE
DDR3B_CLK_P J7
DDR3B_CLK_N K7
D
DDR3C_DM2
DDR3C_DM3
E7
D3
DDR3B_CSn
DDR3B_WEn
DDR3B_RASn
DDR3B_CASn
L2
L3
J3
K3
CKE
CK_P
CK_N
DQS_P0
DQS_N0
DQS_P1
DQS_N1
DM0
DM1
CS
WE
RAS
CAS
M2
DDR3B_BA0
N8
DDR3B_BA1
M3
DDR3B_BA2
DDR3B_RESETnT2
K1
DDR3B_ODT
L8
DDR3B_ZQ3
VREF_DDR3B
H1
M8
R371
C769
B2
0.1uF
D9
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
C
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC1
NC2
NC3
NC4
NC5
NC6
BA0
BA1
BA2
RESETn
ODT
ZQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
U19
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
F3
G3
C7
B7
DDR3C_DQ16
DDR3C_DQ17
DDR3C_DQ18
DDR3C_DQ19
DDR3C_DQ20
DDR3C_DQ21
DDR3C_DQ22
DDR3C_DQ23
DDR3C_DQ24
DDR3C_DQ25
DDR3C_DQ26
DDR3C_DQ27
DDR3C_DQ28
DDR3C_DQ29
DDR3C_DQ30
DDR3C_DQ31
DDR3 Device
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
DDR3B_A0
DDR3B_A1
DDR3B_A2
DDR3B_A3
DDR3B_A4
DDR3B_A5
DDR3B_A6
DDR3B_A7
DDR3B_A8
DDR3B_A9
DDR3B_A10
DDR3B_A11
DDR3B_A12
DDR3B_A13
K9
DDR3B_CKE
DDR3B_CLK_P J7
DDR3B_CLK_N K7
19,24
19,24
19,24
DDR3C_DQS_P2
DDR3C_DQS_N2
DDR3C_DQS_P3
DDR3C_DQS_N3
J1
J9
L1
L9
M7
T7
19,24
19,24
19,24
19,24
E7
D3
DDR3B_CSn
DDR3B_WEn
DDR3B_RASn
DDR3B_CASn
L2
L3
J3
K3
M2
DDR3B_BA0
N8
DDR3B_BA1
M3
DDR3B_BA2
DDR3B_RESETn T2
K1
DDR3B_ODT
L8
DDR3B_ZQ4
VREF_DDR3B
H1
M8
R322
C226
B2
D9
0.1uF
G7
240
K2
K8
N1
N9
R1
R9
1.5V
A1
A8
C1
C9
D2
E9
F1
H2
H9
19,24
19,24
B1
B9
D1
D8
E2
E8
F9
G1
G9
DDR3C_DM0
DDR3C_DM1
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
MT41J128M16HA
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BCn
A13
CKE
CK_P
CK_N
DM0
DM1
CS
WE
RAS
CAS
BA0
BA1
BA2
RESETn
ODT
ZQ
VREFDQ
VREFCA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS_P0
DQS_N0
DQS_P1
DQS_N1
NC1
NC2
NC3
NC4
NC5
NC6
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
DDR3C_DQ0
DDR3C_DQ1
DDR3C_DQ2
DDR3C_DQ3
DDR3C_DQ4
DDR3C_DQ5
DDR3C_DQ6
DDR3C_DQ7
DDR3C_DQ8
DDR3C_DQ9
DDR3C_DQ10
DDR3C_DQ11
DDR3C_DQ12
DDR3C_DQ13
DDR3C_DQ14
DDR3C_DQ15
F3
G3
C7
B7
DDR3C_DQS_P0
DDR3C_DQS_N0
DDR3C_DQS_P1
DDR3C_DQS_N1
E
DDR3C INTERFACE
DDR3C_DM[3:0]
13,19
DDR3C_DQS_P[3:0]
13,19
DDR3C_DQS_N[3:0]
13,19
DDR3C_DQ[31:0]
13,19
DDR3B INTERFACE
DDR3B_A[13:0]
19,24
DDR3B_BA[2:0]
19,24
D
J1
J9
L1
L9
M7
T7
B1
B9
D1
D8
E2
E8
F9
G1
G9
C
J2
J8
A9
M1
M9
B3
P1
P9
E1
T1
T9
G8
B
MT41J128M16HA
1.5V
Place These Caps Near DDR3 (U19 and U22)
C622
C695
C623
C620
C616
C618
C871
C828
C698
C874
C870
C872
C619
C830
C771
C869
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
2.2nF
3.3nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
0.01uF
1.5V
C873
C617
C829
C768
C699
C700
C696
C697
C767
C770
0.01uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
25
of
1
46
8
7
6
5
4
3
2
1
FLASH
E
E
FM BUS INTERFACE
FM_D[15:0]
5,12,27
FM_A[26:0]
3.3V
8
14,27
5,12,27
FLASH 1Gb
U4
U57
FPGA_DCLK
FPGA1_CONFIG_D4
6
1
4
VCC
DQ0
CLK
DQ1
CSn W#/VPP/DQ2
HOLD#/DQ3
GND
TAB_DNC
5
2
3
7
9
PC28FxxxP30B85
FLASH
FPGA1_CONFIG_D0
FPGA1_CONFIG_D1
FPGA1_CONFIG_D2
FPGA1_CONFIG_D3
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_A23
FM_A24
FM_A25
FM_A26
DNI
D
3.3V
3.3V
C71
C72
0.1uF
0.1uF
R51
R52
R53
R48
R426
R46
DNI
DNI
DNI
DNI
DNI
DNI
1.8V
FPGA1_CONFIG_D0
FPGA1_CONFIG_D1
FPGA1_CONFIG_D2
FPGA1_CONFIG_D3
FPGA_DCLK
FPGA1_CONFIG_D4
C
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
B8
5,27
FLASH_CLK
E6
12,27
5,27
5,27
5,27
5,27
FLASH_RESETn
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_ADVn
FLASH_WPn
D4
B4
F8
G8
F6
C6
VPP
A1
A2
VCC
A3
VCC
A4
A5
VCCQ
A6
VCCQ
A7
VCCQ
A8
A9
D0
A10
D1
A11
D2
A12
D3
A13
D4
A14
D5
A15
D6
A16
D7
A17
A18
D8
A19
D9
A20
D10
A21
D11
A22
D12
NC(64M)/A23
D13
NC(64M,128M)/A24 D14
NC/A25(512M)
D15
NC/A26(1G)
WAIT
CLK
GND
RESET#
GND
CE#
GND
OE#
GND
WE#
ADV#
RFU0
WP#
RFU1
RFU2
RFU3
A4
FPGA CONFIG BUS INTERFACE
FPGA1_CONFIG_D[15:0]
A6
H3
14,27
1.8V
D5
D6
G4
D
F2
E2
G3
E4
E5
G5
G6
H7
FM_D0
FM_D1
FM_D2
FM_D3
FM_D4
FM_D5
FM_D6
FM_D7
E1
E3
F3
F4
F5
H5
G7
E7
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
C
F7 FLASH_RDYBSYn
5,27
B2
H2
H4
H6
H1
G2
F1
E8
PC28F00AP30BF
B
1.8V
1.8V
B
1.8V
C197
C150
C198
C187
C188
C151
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R218
R201
R211
10K
10K
10K
FLASH_WPn
FLASH_WEn
FLASH_RDYBSYn
R217
10K
FLASH_RESETn
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
26
of
1
46
8
7
6
5
EPM2210 System Controller
U2A
C2
C3
D2
E
FPGA1_CONFIG_D0
FPGA1_CONFIG_D1
FPGA1_CONFIG_D2
FPGA1_CONFIG_D3
FPGA1_CONFIG_D4
FPGA1_CONFIG_D5
FPGA1_CONFIG_D6
FPGA1_CONFIG_D7
FPGA1_CONFIG_D8
FPGA1_CONFIG_D9
FPGA1_CONFIG_D10
FPGA1_CONFIG_D11
FPGA1_CONFIG_D12
FPGA1_CONFIG_D13
FPGA1_CONFIG_D14
FPGA1_CONFIG_D15
D
D1
D3
E2
D4
E1
E3
F3
E4
F2
E5
F1
F4
G3
F5
G2
F6
G1
G4
H3
G5
H2
G6
H1
G7
J3
H4
J2
H5
J1
H6
K1
C
J6
K6
USB_CLK
CLK_CONFIG
MAX II
BANK1
IOB1_2
IOB1_3
IOB1_4
TDO
TCK
TDI
TMS
IOB1_79
IOB1_78
IOB1_76
IOB1_75
IOB1_74
IOB1_73
IOB1_72
IOB1_71
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
IOB1_68
IOB1_67
IOB1_66
IOB1_65
IOB1_64
IOB1_63
IOB1_62
IOB1_61
IOB1_60
IOB1_59
IOB1_58
IOB1_57
IOB1_56
IOB1_55
IOB1_54
IOB1_53
IOB1_35
IOB1_36
IOB1_37
IOB1_38
IOB1_39
IOB1_40
IOB1_50
IOB1_49
IOB1_48
IOB1_47
IOB1_46
IOB1_45
IO/GCLK0
IO/GCLK1
T3
T2
N6
R4
M7
P5
R3
R2
JTAG_BLASTER_TDI
JTAG_TCK
JTAG_EPM2210_TDI
JTAG_TMS
VCCINT_SCL
VCCINT_SDA
R1
P3
P2
P4
P1
N4
N3
N5
N2
M4
N1
M5
M3
M6
M2
L4
M1
L5
L3
L6
L2
K4
L1
K5
K3
J5
K2
J4
FPGA_DCLK
FPGA1_CONF_DONE
FPGA1_nSTATUS
FPGA1_nCONFIG
FPGA2_CONF_DONE
FPGA2_nSTATUS
FPGA2_nCONFIG
CLOCK_SDA
FPGA1_CvP_CONFDONE
FPGA1_PR_ERROR
FPGA1_PR_READY
FPGA1_PR_REQUEST
FPGA1_PR_DONE
FPGA1_CEn
FPGA2_CEn
FM_A0
FM_A1
FM_A2
T17
R15
T16
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A15
FM_A16
FM_A12
FM_A13
FM_A14
R16
P15
R17
P14
R18
N15
P16
N14
P17
N13
P18
M15
N16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_D0
FM_D6
FM_D7
FM_D1
FM_D2
FM_D3
FM_D4
FM_D5
M14
N17
M13
N18
M12
M16
L16
M17
L15
M18
L14
L17
L13
L18
FM_D8
FM_D9
FM_A25
FM_A24
FM_A23
K16
K17
K15
K18
K14
CLKIN_MAX_50K13
J13
EPM2210GF324
U2B
B18
FPGA2_CvP_CONFDONE
FPGA2_PR_ERROR D14
FPGA2_PR_READY A17
FPGA2_PR_REQUESTE13
B16
FPGA2_PR_DONE
D13
DEVICE1_LED
C15
DEVICE2_LED
F12
SENSE_CS0n
B15
SENSE_CS1n
E12
SENSE_SCK
A15
SENSE_SDI
D12
SENSE_SDO
B
A
CLOCK_SCL
OVERTEMP2
OVERTEMP1
FPGA1_CEOn
HSMA_PRSNTn
HSMB_PRSNTn
SI571_EN
CLK50_EN
CLK125A_EN
FPGA2_CEOn
Si570_EN
FACTORY_STATUS
C14
C12
B14
F11
A14
E11
C13
D11
B13
C11
A13
F10
B12
E10
A12
D10
B11
C10
A11
C9
B10
FLASH_ACCESSn
MAX_CTL0
MAX_CTL1
MAX_CTL2
MAX_BEn0
MAX_BEn1
MAX_BEn2
MAX_BEn3
EXTRA_SIG0
IOB2_277
IOB2_278
IOB2_279
IOB2_280
IOB2_281
IOB2_282
IOB2_283
IOB2_284
IOB2_285
IOB2_286
IOB2_287
IOB2_288
IOB2_291
IOB2_292
IOB2_293
IOB2_294
IOB2_295
IOB2_296
IOB2_297
IOB2_298
IOB2_299
IOB3_177
IOB3_178
IOB3_179
IOB3_180
IOB3_181
IOB3_182
IOB3_183
IOB3_184
IOB3_185
IOB3_186
IOB3_187
IOB3_188
IOB3_189
IOB3_251
IOB3_250
IOB3_249
IOB3_248
IOB3_247
IOB3_246
IOB3_245
IOB3_244
IOB3_243
IOB3_242
IOB3_241
IOB3_240
IOB3_239
IOB3_192
IOB3_193
IOB3_194
IOB3_195
IOB3_196
IOB3_197
IOB3_198
IOB3_199
IOB3_200
IOB3_201
IOB3_202
IOB3_203
IOB3_204
IOB3_205
FM_D10
FM_D11
FM_D12
FM_D13
D16
E14
D17
F15
E16
F14
D18
F13
E17
G15
E18
G14
F16
FMC_SDA
FMC_SCL
FMC_C2M_PG
FMC_M2C_PG
FMC_PRSNT
FM_D14
FM_D15
FLASH_WEn
FM_A3
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
FLASH_RESETn
FLASH_CLK
FLASH_ADVn
MAX_RESETn
USB_CFG10
EXTRA_SIG1
31
IOB3_236
IOB3_235
IOB3_234
IOB3_233
IOB3_232
IOB3_231
IOB3_230
IOB3_229
IOB3_228
IOB3_227
IOB3_226
IOB3_225
IOB3_222
IOB3_221
IOB3_220
IOB3_219
IOB3_218
IOB3_217
IO/GCLK2
IO/GCLK3
G13
F17
G12
F18
H16
G16
H15
G17
H14
G18
H13
H17
SDI_A_TX_EN
SDI_A_RX_BYPASS
SDI_A_RX_EN
MAX_CTL[2:0]
J16
H18
J15
J17
J14
J18
MAX_OEn
MAX_CSn
MAX_WEn
MAX_CLK
2.5V
R235
10.0K
IOB2_339
IOB2_338
IOB2_337
IOB2_335
IOB2_334
IOB2_333
IOB2_332
IOB2_331
IOB2_330
IOB2_329
IOB2_328
IOB2_327
IOB2_324
IOB2_323
IOB2_322
IOB2_321
IOB2_320
IOB2_319
IOB2_318
IOB2_317
IOB2_316
IOB2_315
IOB2_314
IOB2_313
IOB2_312
IOB2_311
IOB2_308
IOB2_307
IOB2_306
IOB2_305
IOB2_304
IOB2_303
IOB2_301
2.5V
X3
MAX_OEn
MAX_CSn
MAX_WEn
MAX_CLK
B1
D5
A2
1
2
B3
E6
C4
D6
B4
C6
A4
F7
C5
MAX_CONF_DONE1
CPU2_RESETn
FACTORY_USER2
PGM1_SEL
PGM1_CONFIG
E7
B5
D7
A5
C7
B6
F8
A6
E8
B7
D8
A7
C8
B8
CLK_SEL
CLK_ENABLE
CLK125B_EN
FACTORY_USER1
MAX_ERROR1
MAX_LOAD1
FPGA1_MSEL0
FPGA1_MSEL1
FPGA1_MSEL2
FPGA1_MSEL3
FPGA1_MSEL4
EN
VCC
GND
OUT
INIT_DONE1
INIT_DONE2
3
CPU1_RESETn
F9
A8
E9
B9
D9
A9
SDI_A_TX_EN
SDI_A_RX_BYPASS
SDI_A_RX_EN
FACTORY_REQUEST
M570_PCIE_JTAG_EN
A10
M570_CLOCK
DNI
C126
C125
2.2uF
0.1uF
2.5V
FPGA2_MSEL0
FPGA2_MSEL1
FPGA2_MSEL2
FPGA2_MSEL3
FPGA2_MSEL4
2.5V VCCIO
PHASE0
1.8V
G8
H7
J8
J10
K9
K11
L12
M11
A1
A18
B2
B17
H8
H9
H10
H11
L8
L9
L10
L11
U2
U17
V1
V18
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
GNDINT
MAX II
Power
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
G11
H12
J9
J11
K8
K10
L7
M8
C232
C233
C135
C134
C136
C234
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VCCINT_SDA
VCCINT_SCL
PHASE0
V2
R5
U3
P6
T4
R6
U4
T6
V4
N7
T5
P7
U5
R7
V5
T7
U6
N8
V6
P8
U7
R8
V7
T8
U8
2.5V
P9
V8
R9
U9
T9
V9
1.8V VCCIO
C137
C235
C142
C189
C156
C145
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
U10
1.8V
C18
J12
K12
T18
5
5
5
5
39
39
41
U2D
MAX II
BANK4
IOB4_91
IOB4_93
IOB4_94
IOB4_95
IOB4_96
IOB4_97
IOB4_98
IOB4_99
IOB4_100
IOB4_101
IOB4_102
IOB4_103
IOB4_104
IOB4_107
IOB4_108
IOB4_109
IOB4_110
IOB4_111
IOB4_112
IOB4_113
IOB4_114
IOB4_115
IOB4_116
IOB4_117
IOB4_118
IOB4_119
IOB4_122
IOB4_123
IOB4_124
IOB4_125
IOB4_126
IOB4_127
IOB4_129
VCCINT
IOB4_168
IOB4_167
IOB4_165
IOB4_164
IOB4_163
IOB4_162
IOB4_161
IOB4_160
IOB4_159
IOB4_158
IOB4_157
IOB4_156
IOB4_155
IOB4_154
IOB4_151
IOB4_150
IOB4_149
IOB4_148
IOB4_147
IOB4_146
IOB4_145
IOB4_144
IOB4_143
IOB4_142
IOB4_141
IOB4_140
IOB4_137
IOB4_136
IO/DEV_CLRn
IO/DEV_OE
IOB4_133
IOB4_132
IOB4_131
1.8V
C157
C144
C153
C141
C143
C152
C154
C155
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
7
6
V17
T13
U16
R13
V15
P13
U15
T12
T15
R12
V14
P12
14,26
FPGA1_nSTATUS
FPGA1_CONF_DONE
FPGA_DCLK
FPGA1_nCONFIG
FPGA1_PR_DONE
FPGA1_PR_REQUEST
FPGA1_PR_READY
FPGA1_PR_ERROR
FPGA1_CvP_CONFDONE
FPGA1_CEOn
FPGA1_MSEL0
FPGA1_MSEL1
FPGA1_MSEL2
FPGA1_MSEL3
FPGA1_MSEL4
INIT_DONE1
FPGA1_CEn
14
14
14,26
14
14
14
14
14
14
14
14
14
14
14
14
14
14
FPGA2_nSTATUS
FPGA2_CONF_DONE
FPGA2_nCONFIG
FPGA2_PR_DONE
FPGA2_PR_REQUEST
FPGA2_PR_READY
FPGA2_PR_ERROR
FPGA2_CvP_CONFDONE
FPGA2_CEOn
FPGA2_MSEL0
FPGA2_MSEL1
FPGA2_MSEL2
FPGA2_MSEL3
FPGA2_MSEL4
INIT_DONE2
FPGA2_CEn
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
M9
M10
V3
V16
Title
Size
B
5
E
D
ON-BOARD USB BLASTER II
USB_CFG[11:0]
33
EXTRA_SIG[2:0]
33
USB_CLK
M570_PCIE_JTAG_EN
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
12,33
33
33
33
33
C
DIPSWITCH INTERFACE
CLK_SEL
CLK_ENABLE
FACTORY_USER1
FACTORY_USER2
U14
N12
T14
T11
V13
R11
U13
P11
V12
N11
U12
T10
10,34
34
34
34
PUSH BUTTON INTERFACE
PGM1_SEL
PGM1_CONFIG
CPU1_RESETn
CPU2_RESETn
34
34
14,34
14,35
LED INTERFACE
V11
R10
B
N10
N9
U11
P10
V10
34
MAX_RESETn
MAX_ERROR1
MAX_LOAD1
MAX_CONF_DONE1
DEVICE1_LED
DEVICE2_LED
HSMA_PRSNTn
HSMB_PRSNTn
34
34
34
34
35
35
6,30,34
16,30,35
OVERTEMP1
OVERTEMP2
SENSE_SDO
SENSE_CS0n
SENSE_CS1n
SENSE_SDI
SENSE_SCK
43
43
43
43
43
43
43
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
2.5V
Date:
8
R14
U18
EPM2210GF324
EPM2210GF324
EPM2210GF324
11
11
11
11
10
11
6,10,11
10,11
FPGA1_CONFIG_D[15:0]
PGM1_LED[2:0]
1.8V
C1
J7
K7
T1
A3
A16
G9
G10
POWER CTL INTERFACES
JTAG_BLASTER_TDI
CLK_CONFIG
U2E
PGM1_LED0
PGM1_LED1
PGM1_LED2
R192
INSTALL R192 ONLY WHEN MAX II IS NOT POPULATED.
4
100MHz
JTAG_EPM2210_TDI
6,12
U1
EXTRA_SIG2
6
5,26
5,26
5,26
5,26
5,26
12,26
5,26
6
FLASH_ACCESSn
FMC_SDA
FMC_SCL
FMC_PRSNT
FMC_C2M_PG
FMC_M2C_PG
5,12,26
CLKIN_MAX_50
CLK125A_EN
CLK125B_EN
CLK50_EN
Si570_EN
SI571_EN
CLOCK_SDA
CLOCK_SCL
16,29
18,29
13,29
MAX CTL INTERFACE
USB_CFG2
USB_CFG3
USB_CFG4
USB_CFG5
USB_CFG6
USB_CFG7
USB_CFG8
USB_CFG9
USB_CFG0
USB_CFG11
USB_CFG1
FM_A26
5,12,26
CLOCK INTERFACES
SDI INTERFACE
1
FPGA CONFIG INTERFACE
15,33
FM_A[26:0]
14,15,30,31,33
15
FLASH_ACCESSn
14,15,33
FLASH_WEn
FLASH_CEn
FLASH_OEn
FLASH_RDYBSYn
31
FLASH_ADVn
31
FLASH_RESETn
31
FLASH_CLK
31
MAX_BEn[3:0]
IOB3_208
IOB3_209
IOB3_210
IOB3_211
IOB3_212
2.5V
FLASH INTERFACE
FMC INTERFACE
EPM2210GF324
MAX II
BANK2
IOB2_263
IOB2_264
IOB2_265
IOB2_266
IOB2_267
IOB2_268
IOB2_269
IOB2_270
IOB2_271
IOB2_272
IOB2_273
IOB2_274
IOB3_256
IOB3_255
IOB3_254
IOB3_253
D15
C17
E15
C16
2
FM_D[15:0]
JTAG_BLASTER_TDI
JTAG_TCK
JTAG_EPM2210_TDI
JTAG_TMS
MAX II
BANK3
IOB3_173
IOB3_174
IOB3_175
3
JTAG INTERFACE
U2C
IOB1_85
IOB1_84
IOB1_6
IOB1_7
IOB1_8
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
4
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
27
of
1
46
8
7
6
5
4
3
2
1
Small Form Factor Pluggable Plus (SFP+) Connector
E
SFP_VCCR_1
3.3V_ATX
E
SFP_VCCT_1
SFP_VCCT_1
1
L14
J10
16
15
2 4.7uH
C760
C798
0.1uF
0.1uF
13
12
SFP_RX_P1
SFP_RX_N1
C797
SFP_VCCR_1
10uF
1
L16
2 4.7uH
C796
0.1uF
SFP_TX_DIS1
SFP_TX_RS01
SFP_TX_RS11
3
7
9
SFP_MOD_ABS1
SFP_SCL1
SFP_SDA1
6
5
4
C849
10uF
21
22
23
24
25
26
27
28
29
30
31
Level I power is < 1W (0.3 A)
Level II power is < 1.5W (0.45 A)
D
VCCT
VCCR
TD_P
TD_N
RD_P
RD_N
RX_LOS
TX_FAULT
TX_DISABLE
RS0
RS1
VEET
VEET
VEET
MOD_ABS
SCL
SDA
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
VEER
VEER
VEER
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
MH1
MH2
18
19
SFP_TX_P1
SFP_TX_N1
8
2
SFP_OP_RX_LOS1
SFP_OP_TX_FLT1
1
17
20
SFP+ INTERFACE
3.3V_ATX
SFP_TX_RS01
SFP_TX_RS11
SFP_OP_TX_FLT1
SFP_TX_DIS1
SFP_MOD_ABS1
SFP_OP_RX_LOS1
10
11
14
32
33
34
35
36
37
38
39
40
41
42
R353
R363
R343
R344
R352
R362
SFP_TX_P[2:1]
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
9
SFP_TX_N[2:1]
9
SFP_TX_RS0[2:1]
6
SFP_TX_RS1[2:1]
6
SFP_RX_P[2:1]
9
B2
SFP_RX_N[2:1]
9
SFP_OP_RX_LOS[2:1]
6
SFP_OP_TX_FLT[2:1]
6
SFP+_CAGE
SFP_TX_DIS[2:1]
6
SFP_MOD_ABS[2:1]
SFP+_AND_CAGE
GND_CAGE
6
SFP_SCL[2:1]
GND_CAGE
6
SFP_SDA[2:1]
Optical (SFP+) Transceiver Cage & Connector 1
D
6
THIS SFP+ INTERFACE IS ONLY AVAILABLE WITH ARRIA GT DEV KITS
C
SFP_VCCR_2
3.3V_ATX
SFP_VCCT_2
SFP_VCCT_2
L20
1
J15
16
15
2 4.7uH
C950
C956
13
12
SFP_RX_P2
SFP_RX_N2
C952
0.1uF
0.1uF
SFP_VCCR_2
10uF
L21
1
2 4.7uH
C951
C955
0.1uF
10uF
C
R39
B
Level I power is < 1W (0.3 A)
Level II power is < 1.5W (0.45 A)
SFP_TX_DIS2
SFP_TX_RS02
SFP_TX_RS12
3
7
9
SFP_MOD_ABS2
SFP_SCL2
SFP_SDA2
6
5
4
4.70K, 1%
21
22
23
24
25
26
27
28
29
30
31
VCCT
VCCR
TD_P
TD_N
RD_P
RD_N
RX_LOS
TX_FAULT
TX_DISABLE
RS0
RS1
VEET
VEET
VEET
MOD_ABS
SCL
SDA
VEER
VEER
VEER
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
CAGE_GND
MH1
MH2
18
19
SFP_TX_P2
SFP_TX_N2
8
2
SFP_OP_RX_LOS2
SFP_OP_TX_FLT2
1
17
20
3.3V_ATX
SFP_TX_RS02
SFP_TX_RS12
SFP_OP_TX_FLT2
SFP_TX_DIS2
SFP_MOD_ABS2
SFP_OP_RX_LOS2
10
11
14
32
33
34
35
36
37
38
39
40
41
42
R435
R437
R427
R428
R434
R436
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
B
B10
DNI
DNI
GND_CAGE
GND_CAGE
Optical (SFP+) Transceiver Cage & Connector 2
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
28
of
1
46
8
7
6
5
4
3
2
1
SDI Cable Driver, Equalizer, and SMB
75 Ohm Impedance
E
L18
1
E
5.6nH
2
3.3V_SDI_A
R377
750
R391
3.3V_SDI_A
SDI_A_TX_P
C852
20
SDI_A_TX_N
C853
18
SDI_A_TX_SD_HDn
4.7uF
1
2
SDI_A_TXCAP_P
SDI_A_TXCAP_N
4.7uF
SDI_A_TX_EN
R378
49.9
SDO
SDO
RSTO
FAULT
RSTI
ENABLE
SDA
SCL
14
15
49.9
VCC
SD/HD
RREF
5
6
7
8
D
Cable
Driver
SDI
SDI
10
4
SDI_A_TX_RSET
R379
4.7uF
SDI_A_TXBNC_P
1
U24
3.3V_SDI_A
16,27
C933
NC5
NC6
9
R392
12
11
75
SDI_A_TXDRV_P
SDI_A_TXDRV_N
16
13
R389
VEE
CENTERPAD
J27
BNC
2
3
4
5
20
75
3.3V_SDI_A
75
3
17
D
R390
L17
1
LMH0303
75
C932
4.7uF
SDI_A_TXBNC_N
5.6nH
2
R421
75
C898
3.3V
3.3V_SDI_A
0.01uF
L7
120 Ohm FB
C69
C78
C79
C76
0.1uF
0.1uF
220nF
220nF
C77
22uF
75 Ohm Impedance
C
C
L19
3.9nH
1
1
J26
BNC
2
SDI_A_IN_P1
C899
75
5
4
3
2
R408
1uF
R407
75
3.3V_SDI_A
U23
C900
2
3
SDI_A_EQIN_P1
SDI_A_EQIN_N1
1uF
R393
7
15
4
12
3.3V_SDI_A
SDI_A_RX_CDn
B
37.4 R381
10K
18,27
SDI_A_RX_BYPASS
13,27
SDI_A_RX_EN
3.3V_SDI_A
AEC1
1uF
C70
R47
5
6
14
8
R380
SDI
SDI
BYPASS
CD
SPI_EN
AUTO_SLEEP
VCC1
VCC2
SDO
SDO
11
10
SDO_A_P
SDO_A_N C61
C60
4.7uF
4.7uF
SDI_A_RX_P
SDI_A_RX_N
20
20
B
AEC+
AECMUTE
MUTEref
13
16
VEE1
VEE2
DAP
1
9
17
LMH0384
3.3V_SDI_A
0
D45
75
0
R406
Green_LED
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
29
of
1
46
6
5
0 HSMA_TX_CP7 1
0 HSMA_TX_CN7 3
0 HSMA_TX_CP6 5
0 HSMA_TX_CN6 7
0 HSMA_TX_CP5 9
11
0 HSMA_TX_CN5
0 HSMA_TX_CP413
15
0 HSMA_TX_CN4
0 HSMA_TX_CP317
19
0 HSMA_TX_CN3
0 HSMA_TX_CP221
23
0 HSMA_TX_CN2
0 HSMA_TX_CP125
0 HSMA_TX_CN1
27
0 HSMA_TX_CP029
31
0 HSMA_TX_CN0
33
HSMA_SDA
35
JTAG_TCK
HSMA_JTAG_TDO
37
39
HSMA_CLK_OUT0
HSMA_D0
HSMA_D2
HSMA_TX_D_P0
HSMA_TX_D_N0
D
HSMA_TX_D_P1
HSMA_TX_D_N1
HSMA_TX_D_P2
HSMA_TX_D_N2
HSMA_TX_D_P3
HSMA_TX_D_N3
HSMA_TX_D_P4
HSMA_TX_D_N4
HSMA_TX_D_P5
HSMA_TX_D_N5
HSMA_TX_D_P6
HSMA_TX_D_N6
C
HSMA_TX_D_P7
HSMA_TX_D_N7
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_TX_D_P8
HSMA_TX_D_N8
HSMA_TX_D_P9
HSMA_TX_D_N9
HSMA_TX_D_P10
HSMA_TX_D_N10
HSMA_TX_D_P11
HSMA_TX_D_N11
B
HSMA_TX_D_P12
HSMA_TX_D_N12
HSMA_TX_D_P13
HSMA_TX_D_N13
HSMA_TX_D_P14
HSMA_TX_D_N14
HSMA_TX_D_P15
HSMA_TX_D_N15
HSMA_TX_D_P16
HSMA_TX_D_N16
12V_ATX
3.3V_ATX
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
A
C94
C103
10uF
10uF
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
3.3V_ATX
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
A
BANK 3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
6
14,15,27,31,33
15
6
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMA_RX_P7
HSMA_RX_N7
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P0
HSMA_RX_N0
HSMA_SCL
HSMA_JTAG_TMS
AVB_JTAG_TDO
HSMA_CLK_IN0
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
6
15
14,15
12
20
20
20
20
20
20
20
20
HSMB_TX_P3
HSMB_TX_N3
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P0
HSMB_TX_N0
R98
R97
R96
R95
R94
R93
R92
R91
16
15
13
HSMB_D0
HSMB_D2
HSMA_D1
HSMA_D3
HSMB_TX_D_P0
HSMB_TX_D_N0
HSMA_RX_D_P0
HSMA_RX_D_N0
HSMB_TX_D_P1
HSMB_TX_D_N1
HSMA_RX_D_P1
HSMA_RX_D_N1
HSMB_TX_D_P2
HSMB_TX_D_N2
HSMA_RX_D_P2
HSMA_RX_D_N2
HSMB_TX_D_P3
HSMB_TX_D_N3
HSMA_RX_D_P3
HSMA_RX_D_N3
HSMB_TX_D_P4
HSMB_TX_D_N4
HSMA_RX_D_P4
HSMA_RX_D_N4
HSMB_TX_D_P5
HSMB_TX_D_N5
HSMA_RX_D_P5
HSMA_RX_D_N5
HSMB_TX_D_P6
HSMB_TX_D_N6
HSMA_RX_D_P6
HSMA_RX_D_N6
HSMB_TX_D_P7
HSMB_TX_D_N7
HSMA_RX_D_P7
HSMA_RX_D_N7
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMB_TX_D_P8
HSMB_TX_D_N8
HSMA_RX_D_P8
HSMA_RX_D_N8
HSMB_TX_D_P9
HSMB_TX_D_N9
HSMA_RX_D_P9
HSMA_RX_D_N9
HSMB_TX_D_P10
HSMB_TX_D_N10
HSMA_RX_D_P10
HSMA_RX_D_N10
HSMB_TX_D_P11
HSMB_TX_D_N11
HSMA_RX_D_P11
HSMA_RX_D_N11
HSMB_TX_D_P12
HSMB_TX_D_N12
HSMA_RX_D_P12
HSMA_RX_D_N12
HSMB_TX_D_P13
HSMB_TX_D_N13
HSMA_RX_D_P13
HSMA_RX_D_N13
HSMB_TX_D_P14
HSMB_TX_D_N14
HSMA_RX_D_P14
HSMA_RX_D_N14
HSMB_TX_D_P15
HSMB_TX_D_N15
HSMA_RX_D_P15
HSMA_RX_D_N15
HSMB_TX_D_P16
HSMB_TX_D_N16
HSMA_RX_D_P16
HSMA_RX_D_N16
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMA_PRSNTn
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
3.3V
47
49
3.3V
53
55
3.3V
59
61
3.3V
65
67
3.3V
71
73
3.3V
77
79
3.3V
83
85
3.3V
89
91
3.3V
95
97
3.3V
101
103
3.3V
107
109
3.3V
113
115
3.3V
119
121
3.3V
125
127
3.3V
131
133
3.3V
137
139
3.3V
143
145
3.3V
149
151
3.3V
155
157
3.3V
3.3V_ATX
12V_ATX
2
ASP-122953-01
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BANK 1
42
44
12V
48
50
12V
54
56
12V
60
62
12V
66
68
12V
72
74
12V
78
80
12V
84
86
12V
90
92
12V
96
98
12V
BANK 2
B
BANK 3
102
104
12V
108
110
12V
114
116
12V
120
122
12V
126
128
12V
132
134
12V
138
140
12V
144
146
12V
150
152
12V
156
158
PSNTn
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HSMB_D1
HSMB_D3
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
HSMB_RX_D_P8
HSMB_RX_D_N8
Title
Date:
6
5
4
3
20
20
20
20
20
20
20
20
16
15
15
13
HSMB_RX_D_P0
HSMB_RX_D_N0
HSMB_RX_D_P1
HSMB_RX_D_N1
HSMB_RX_D_P2
HSMB_RX_D_N2
HSMB_RX_D_P3
HSMB_RX_D_N3
HSMB_RX_D_P4
HSMB_RX_D_N4
HSMB_RX_D_P5
HSMB_RX_D_N5
HSMB_RX_D_P6
HSMB_RX_D_N6
HSMC PORT A INTERFACE
D
HSMA_D[3:0]
6
HSMA_TX_D_P[16:0]
6
HSMA_TX_D_N[16:0]
6
HSMA_RX_D_P[16:0]
6
HSMA_RX_D_N[16:0]
6
HSMA_CLK_OUT_P[2:1]
6,12
HSMA_CLK_OUT_N[2:1]
6,12
HSMA_CLK_IN_P[2:1]
12
HSMA_CLK_IN_N[2:1]
12
HSMA_PRSNTn
6,27,34
HSMB_RX_D_P7
HSMB_RX_D_N7
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_RX_D_P9
HSMB_RX_D_N9
HSMB_RX_D_P10
HSMB_RX_D_N10
HSMB_RX_D_P11
HSMB_RX_D_N11
HSMB_RX_D_P12
HSMB_RX_D_N12
HSMB_RX_D_P13
HSMB_RX_D_N13
C
HSMC PORT B INTERFACE
HSMB_D[3:0]
16
HSMB_TX_D_P[16:0]
16
HSMB_TX_D_N[16:0]
16
HSMB_RX_D_P[16:0]
16
HSMB_RX_D_N[16:0]
16
HSMB_CLK_OUT_P[2:1]
13,16
HSMB_CLK_OUT_N[2:1]
13,16
B
HSMB_CLK_IN_P[2:1]
13
HSMB_CLK_IN_N[2:1]
13
HSMB_PRSNTn
16,27,35
HSMB_RX_D_P14
HSMB_RX_D_N14
HSMB_RX_D_P15
HSMB_RX_D_N15
HSMB_RX_D_P16
HSMB_RX_D_N16
12V_ATX
3.3V_ATX
C89
C101
10uF
10uF
12V_ATX
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
HSMB_PRSNTn
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
B
7
E
HSMB_RX_P3
HSMB_RX_N3
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P0
HSMB_RX_N0
HSMB_SCL
HSMB_JTAG_TMS
HSMB_JTAG_TDI
HSMB_CLK_IN0
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Size
8
1
J3
0 HSMB_TX_CP3
0 HSMB_TX_CN3
0 HSMB_TX_CP2
0 HSMB_TX_CN2
0 HSMB_TX_CP1
0 HSMB_TX_CN1
0 HSMB_TX_CP0
0 HSMB_TX_CN0
HSMB_SDA
JTAG_TCK
HSMB_JTAG_TDO
HSMB_CLK_OUT0
161
162
163
164
165
166
167
168
169
170
171
172
HSMA_TX_P7
HSMA_TX_N7
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P0
HSMA_TX_N0
3
HSMC Port A & Port B
J2
9
9
9
9
9
E 9
9
9
9
9
9
9
9
9
9
9
4
GND_1_1
GND_1_2
GND_1_3
GND_1_4
GND_2_1
GND_2_2
GND_2_3
GND_2_4
GND_3_1
GND_3_2
GND_3_3
GND_3_4
7
161
162
163
164
165
166
167
168
169
170
171
172
8
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
30
of
1
46
8
7
6
5
4
3
2
FMC
J9F
J9A
J9B
E
D
FMC_LA_P0
FMC_LA_N0
FMC_LA_P1
FMC_LA_N1
FMC_LA_P2
FMC_LA_N2
FMC_LA_P3
FMC_LA_N3
G6
G7
D8
D9
H7
H8
G9
G10
FMC_LA_P4
FMC_LA_N4
FMC_LA_P5
FMC_LA_N5
FMC_LA_P6
FMC_LA_N6
FMC_LA_P7
FMC_LA_N7
H10
H11
D11
D12
C10
C11
H13
H14
FMC_LA_P8
FMC_LA_N8
FMC_LA_P9
FMC_LA_N9
FMC_LA_P10
FMC_LA_N10
FMC_LA_P11
FMC_LA_N11
G12
G13
D14
D15
C14
C15
H16
H17
FMC_LA_P12
FMC_LA_N12
FMC_LA_P13
FMC_LA_N13
FMC_LA_P14
FMC_LA_N14
FMC_LA_P15
FMC_LA_N15
G15
G16
D17
D18
C18
C19
H19
H20
LA_P0_CC
LA_P16
LA_N0_CC
LA_N16
LA_P1_CC
LA_P17
LA_N1_CC
LA_N17
LA_P2
LA_P18_CC
LA_N2
LA_N18_CC
LA_P3
LA_P19
LA_N3
LA_N19
LA_P4
LA_N4
LA_P5
LA_N5
LA_P6
LA_N6
LA_P7
LA_N7
LA_P20
LA_N20
LA_P21
LA_N21
LA_P22
LA_N22
LA_P23
LA_N23
LA_P8
LA_N8
LA_P9
LA_N9
LA_P10
LA_N10
LA_P11
LA_N11
LA_P24
LA_N24
LA_P25
LA_N25
LA_P26
LA_N26
LA_P27
LA_N27
LA_P12
LA_N12
LA_P13
LA_N13
LA_P14
LA_N14
LA_P15
LA_N15
LA_P28
LA_N28
LA_P29
LA_N29
LA_P30
LA_N30
LA_P31
LA_N31
LA_P32
LA_N32
LA_P33
LA_N33
C
G18
G19
D20
D21
C22
C23
H22
H23
FMC_LA_P16
FMC_LA_N16
FMC_LA_P17
FMC_LA_N17
FMC_LA_P18
FMC_LA_N18
FMC_LA_P19
FMC_LA_N19
FMC_HA_P0
FMC_HA_N0
FMC_HA_P1
FMC_HA_N1
FMC_HA_P2
FMC_HA_N2
FMC_HA_P3
FMC_HA_N3
F4
F5
E2
E3
K7
K8
J6
J7
G21
G22
H25
H26
G24
G25
D23
D24
FMC_LA_P20
FMC_LA_N20
FMC_LA_P21
FMC_LA_N21
FMC_LA_P22
FMC_LA_N22
FMC_LA_P23
FMC_LA_N23
FMC_HA_P4
FMC_HA_N4
FMC_HA_P5
FMC_HA_N5
FMC_HA_P6
FMC_HA_N6
FMC_HA_P7
FMC_HA_N7
F7
F8
E6
E7
K10
K11
J9
J10
H28
H29
G27
G28
D26
D27
C26
C27
FMC_LA_P24
FMC_LA_N24
FMC_LA_P25
FMC_LA_N25
FMC_LA_P26
FMC_LA_N26
FMC_LA_P27
FMC_LA_N27
FMC_HA_P8
FMC_HA_N8
FMC_HA_P9
FMC_HA_N9
FMC_HA_P10
FMC_HA_N10
FMC_HA_P11
FMC_HA_N11
F10
F11
E9
E10
K13
K14
J12
J13
H31
H32
G30
G31
H34
H35
G33
G34
H37
H38
G36
G37
FMC_LA_P28
FMC_LA_N28
FMC_LA_P29
FMC_LA_N29
FMC_LA_P30
FMC_LA_N30
FMC_LA_P31
FMC_LA_N31
FMC_LA_P32
FMC_LA_N32
FMC_LA_P33
FMC_LA_N33
J9C
HA_P0_CC
HA_N0_CC
HA_P1_CC
HA_N1_CC
HA_P2
HA_N2
HA_P3
HA_N3
HA_P4
HA_N4
HA_P5
HA_N5
HA_P6
HA_N6
HA_P7
HA_N7
HA_P12
HA_N12
HA_P13
HA_N13
HA_P14
HA_N14
HA_P15
HA_N15
HA_P16
HA_N16
HA_P17_CC
HA_N17_CC
HA_P18
HA_N18
HA_P19
HA_N19
HA_P8
HA_N8
HA_P9
HA_N9
HA_P10
HA_N10
HA_P11
HA_N11
HA_P20
HA_N20
HA_P21
HA_N21
HA_P22
HA_N22
HA_P23
HA_N23
F13
F14
E12
E13
J15
J16
F16
F17
FMC_HA_P12
FMC_HA_N12
FMC_HA_P13
FMC_HA_N13
FMC_HA_P14
FMC_HA_N14
FMC_HA_P15
FMC_HA_N15
E15
E16
K16
K17
J18
J19
F19
F20
FMC_HA_P16
FMC_HA_N16
FMC_HA_P17
FMC_HA_N17
FMC_HA_P18
FMC_HA_N18
FMC_HA_P19
FMC_HA_N19
E18
E19
K19
K20
J21
J22
K22
K23
FMC_HA_P20
FMC_HA_N20
FMC_HA_P21
FMC_HA_N21
FMC_HA_P22
FMC_HA_N22
FMC_HA_P23
FMC_HA_N23
D40
C39
D36
D38
10K FMC_C2M_PG
D1
J9D
B
FMC_DP_C2M_P5
FMC_DP_C2M_N5
FMC_DP_C2M_P6
FMC_DP_C2M_N6
FMC_DP_C2M_P7
FMC_DP_C2M_N7
FMC_DP_C2M_P8
FMC_DP_C2M_N8
FMC_DP_C2M_P9
FMC_DP_C2M_N9
A38
A39
B36
B37
B32
B33
B28
B29
B24
B25
DP0_C2M_P
DP0_C2M_N
DP1_C2M_P
DP1_C2M_N
DP2_C2M_P
DP2_C2M_N
DP3_C2M_P
DP3_C2M_N
DP4_C2M_P
DP4_C2M_N
DP0_M2C_P
DP0_M2C_N
DP1_M2C_P
DP1_M2C_N
DP2_M2C_P
DP2_M2C_N
DP3_M2C_P
DP3_M2C_N
DP4_M2C_P
DP4_M2C_N
DP5_C2M_P
DP5_C2M_N
DP6_C2M_P
DP6_C2M_N
DP7_C2M_P
DP7_C2M_N
DP8_C2M_P
DP8_C2M_N
DP9_C2M_P
DP9_C2M_N
DP5_M2C_P
DP5_M2C_N
DP6_M2C_P
DP6_M2C_N
DP7_M2C_P
DP7_M2C_N
DP8_M2C_P
DP8_M2C_N
DP9_M2C_P
DP9_M2C_N
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GBTCLK1_M2C_P
GBTCLK1_M2C_N
A
A18
A19
B16
B17
B12
B13
B8
B9
B4
B5
FMC_DP_M2C_P5
FMC_DP_M2C_N5
FMC_DP_M2C_P6
FMC_DP_M2C_N6
FMC_DP_M2C_P7
FMC_DP_M2C_N7
FMC_DP_M2C_P8
FMC_DP_M2C_N8
FMC_DP_M2C_P9
FMC_DP_M2C_N9
D4
D5
B20
B21
FMC_GBTCLK_M2C_P0
FMC_GBTCLK_M2C_N0
FMC_GBTCLK_M2C_P1
FMC_GBTCLK_M2C_N1
FMC_HB_P8
FMC_HB_N8
FMC_HB_P9
FMC_HB_N9
FMC_HB_P10
FMC_HB_N10
F28
F29
E27
E28
K31
K32
HB_P4
HB_N4
HB_P5
HB_N5
HB_P6_CC
HB_N6_CC
HB_P7
HB_N7
HB_P15
HB_N15
HB_P16
HB_N16
HB_P17_CC
HB_N17_CC
HB_P18
HB_N18
HB_P8
HB_N8
HB_P9
HB_N9
HB_P10
HB_N10
HB_P19
HB_N19
HB_P20
HB_N20
HB_P21
HB_N21
J30
J31
F31
F32
E30
E31
K34
K35
FMC_HB_P11
FMC_HB_N11
FMC_HB_P12
FMC_HB_N12
FMC_HB_P13
FMC_HB_N13
FMC_HB_P14
FMC_HB_N14
J33
J34
F34
F35
K37
K38
J36
J37
FMC_HB_P15
FMC_HB_N15
FMC_HB_P16
FMC_HB_N16
FMC_HB_P17
FMC_HB_N17
FMC_HB_P18
FMC_HB_N18
E33
E34
F37
F38
E36
E37
FMC_HB_P19
FMC_HB_N19
FMC_HB_P20
FMC_HB_N20
FMC_HB_P21
FMC_HB_N21
3.3V_ATX
3.3V_ATX
R432
FMC_DP_M2C_P0
FMC_DP_M2C_N0
FMC_DP_M2C_P1
FMC_DP_M2C_N1
FMC_DP_M2C_P2
FMC_DP_M2C_N2
FMC_DP_M2C_P3
FMC_DP_M2C_N3
FMC_DP_M2C_P4
FMC_DP_M2C_N4
F25
F26
E24
E25
K28
K29
J27
J28
HB_P11
HB_N11
HB_P12
HB_N12
HB_P13
HB_N13
HB_P14
HB_N14
A5_VCCIO_FMC
3P3VAUX
VADJ
VADJ
VADJ
VADJ
3P3V
3P3V
3P3V
3P3V
VIO_B_M2C
VIO_B_M2C
12V_ATX
C6
C7
A2
A3
A6
A7
A10
A11
A14
A15
FMC_HB_P4
FMC_HB_N4
FMC_HB_P5
FMC_HB_N5
FMC_HB_P6
FMC_HB_N6
FMC_HB_P7
FMC_HB_N7
HB_P0_CC
HB_N0_CC
HB_P1
HB_N1
HB_P2
HB_N2
HB_P3
HB_N3
ASP-134486-01
C35
C37
C2
C3
A22
A23
A26
A27
A30
A31
A34
A35
K25
K26
J24
J25
F22
F23
E21
E22
J9E
ASP-134486-01
FMC_DP_C2M_P0
FMC_DP_C2M_N0
FMC_DP_C2M_P1
FMC_DP_C2M_N1
FMC_DP_C2M_P2
FMC_DP_C2M_N2
FMC_DP_C2M_P3
FMC_DP_C2M_N3
FMC_DP_C2M_P4
FMC_DP_C2M_N4
FMC_HB_P0
FMC_HB_N0
FMC_HB_P1
FMC_HB_N1
FMC_HB_P2
FMC_HB_N2
FMC_HB_P3
FMC_HB_N3
ASP-134486-01
D32
27
FMC_PRSNT
27
27
FMC_SDA
FMC_SCL
3.3V_ATX
R433
10K
H2
C31
C30
FMC_CLK_BIDIR_P2
FMC_CLK_BIDIR_N2
FMC_CLK_BIDIR_P3
FMC_CLK_BIDIR_N3
K4
K5
J2
J3
FMC_CLK_DIR
B1
C34
D35
12P0V
12P0V
VREF_B_M2C
VREF_A_M2C
PG_C2M
PG_M2C
PRSNT_M2C_L
SDA
SCL
TRST
TMS
TDO
TDI
TCK
CLK2_BIDIR_P
CLK2_BIDIR_N
CLK3_BIDIR_PCLK0_M2C_P
CLK3_BIDIR_NCLK0_M2C_N
CLK1_M2C_P
CLK_DIR
CLK1_M2C_N
GA0
GA1
RES0
E39
F40
G39
H40
FMC INTERFACE
FMC_LA_P[33:0]
10K
10K
13,16,17
FMC_LA_N[33:0]
FMC_VCCIO_MODULE
K40
J39
13,16,17
FMC_HA_P[23:0]
VREFB_FMC
VREFA_FMC
K1
H1
13,16,17,18
FMC_HA_N[23:0]
13,16,17,18
FMC_HB_P[21:0]
F1
FMC_M2C_PG R431
D34
D33
D31
D30
D29
FMC_JTAG_TRST R265
FMC_JTAG_TMS
FMC_JTAG_TDO
FMC_JTAG_TDI
JTAG_TCK
H4
H5
G2
G3
FMC_CLK_M2C_P0
FMC_CLK_M2C_N0
FMC_CLK_M2C_P1
FMC_CLK_M2C_N1
17
FMC_HB_N[21:0]
3.3V_ATX
10K
17
FMC_DP_C2M_P[9:0]
20
FMC_DP_C2M_N[9:0]
10K
15
15
15
14,15,27,30,33
20
FMC_DP_M2C_P[9:0]
20
FMC_DP_M2C_N[9:0]
20
FMC_CLK_BIDIR_P[3:2]
16
FMC_CLK_BIDIR_N[3:2]
16
FMC_CLK_M2C_P[1:0]
B40
13
FMC_CLK_M2C_N[1:0]
ASP-134486-01
R429
R430
13
FMC_CLK_DIR
FMC_M2C_PG
FMC_C2M_PG
16
27
27
VREFB_FMC
VREFA_FMC
20
20
20
20
E20
E23
E26
E29
E38
E32
E35
E40
K2
K3
K6
K9
K12
K15
K18
K21
K24
K27
K30
K33
K36
K39
J1
J4
J5
J8
J11
J14
J17
J20
J23
J26
J29
J32
J35
J38
J40
H3
H6
H9
H12
H15
H18
H21
H24
H27
H30
H33
H36
H39
D2
D3
D6
D7
D10
D13
D16
D19
D22
D25
D28
D37
D39
C1
C4
C5
C8
C9
C12
C13
C16
C17
C20
C21
C24
C25
C28
C29
C32
C33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E17
E14
E11
E8
E5
E4
E1
F39
F36
F33
F30
F27
F24
F21
F18
F15
F12
F9
F6
F3
F2
G40
G38
G35
G32
G29
G26
G23
G20
G17
G14
G11
G8
G5
G4
G1
A40
A37
A36
A33
A32
A29
A28
A25
A24
A21
A20
A17
A16
A13
A12
A9
A8
A5
A4
A1
B39
B38
B35
B34
B31
B30
B27
B26
B23
B22
B19
B18
B15
B14
B11
B10
B7
B6
B3
B2
C40
C38
C36
E
D
C
B
ASP-134486-01
ASP-134486-01
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
1
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
31
of
1
46
8
7
6
5
4
3
2
1
10/100/1000 Ethernet
RGMII Mode (default)
U14A
ENET_RESETn
R32
R31
R33
R34
4.7K
4.7K
4.7K
4.7K
ENET_MDIO
ENET_MDC
ENET_INTn
ENET_RESETn
6
6
6
6
2.5V
J8
2.5V
ENET_LED_DUPLEX
0.01uF
C513
0.01uF
C470
0.01uF
C550
0.01uF
R279
R299
R278
R298
R296
R297
R300
R309
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
TD0_P
TD0_N
TD1_P
TD1_N
TD2_P
TD2_N
R295
10.0K
1
2
GND
3
6
4
5
7
8
10
MDI_P0
MDI_N0
MDI_P1
MDI_N1
MDI_P2
MDI_N2
MDI_P3
MDI_N3
29
31
33
34
39
41
42
43
ENET_MDIO
ENET_MDC
ENET_INTn
24
25
23
37
38
HFJ11-1G02E
30
56
ENET_RSET
2.5V
X5
EN
VCC
GND
OUT
3
22
55
54
53
ENET_XTAL_25MHZ
C468
13
51
B
97
NC1
NC2
R37
4.7K
RXCLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
125CLK
XTAL1
XTAL2
VSSC
TRST_N
TCK
TDI
TDO
TMS
ENET_GTX_CLK
11
12
14
16
17
18
19
20
ENET_TX_D0
ENET_TX_D1
ENET_TX_D2
ENET_TX_D3
2
94
3
ENET_RX_CLK
ENET_RX_DV
95
92
93
91
90
89
87
86
ENET_RX_D0
ENET_RX_D1
ENET_RX_D2
ENET_RX_D3
E
ENET_TX_EN
S_CLK_P
S_CLK_N
S_IN_P
S_IN_N
S_OUT_P
S_OUT_N
LED_TX
LED_RX
LED_DUPLEX
LED_LINK1000
LED_LINK100
LED_LINK10
D
ENET_TX_D[3:0]
6
ENET_RX_D[3:0]
6
ENET_GTX_CLK
ENET_TX_EN
ENET_RX_DV
ENET_RX_CLK
ENET_LED_LINK1000
84
83
CRS
COL
RSET
SEL_FREQ
8
4
9
7
79
80
82
81
77
75
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
68
69
70
73
74
76
ENET_LED_TX
ENET_LED_RX
ENET_LED_DUPLEX
ENET_LED_LINK1000
ENET_LED_LINK100
ENET_LED_LINK10
6
6
6
12
6
6
6
6
6
C
88E1111
72
66
52
VDDOH
VDDOH
VDDOH
VDDO
VDDO
VDDO
VDDO
VDDOX
VDDOX
5
21
88
96
R36
4.99K
26
48
2.5V
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
HSDAC_P
HSDAC_N
JTAG
47
49
44
50
46
0.01uF
C
32
36
35
40
45
78
MDIO
MDC
INT_N
4
25.00MHz
U14B
MDI0_P
MDI0_N
MDI1_P
MDI1_N
MDI2_P
MDI2_N
MDI3_P
MDI3_N
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TEST
12
11
2.5V
TD3_P
TD3_N
ENET_LED_RX
1
2
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
MGMT
GND_TAB
GND_TAB
D
9
GTX_CLK
TX_CLK
TX_EN
TX_ER
MDI INTERFACE
C471
VCC
65
64
63
61
60
59
58
COMA
RESET_N
GMII/MII/TBI INTERFACE
2.5V
27
28
SGMII INTERFACE
E
ENET_DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
1
6
10
15
57
62
67
71
85
D36
Green_LED
ENET_LED_TX
R319
2.5V
220
D37
Green_LED
ENET_LED_RX
R318
220
B
D39
Green_LED
VSS
ENET_LED_LINK1000 R316
88E1111
220
D38
Green_LED
ENET_LED_LINK100
Place near 88E1111 PHY
2.5V
R317
220
ENET_DVDD
D40
Green_LED
ENET_LED_LINK10
C594
C595
C548
C549
C428
C430
C469
C512
C426
C429
C511
C427
C510
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A
R315
220
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
32
of
1
46
8
7
6
5
4
3
2
On-Board USB Blaster II
1
USB INTERFACE
USB_DATA[7:0]
FX2_SDA
R204
0
MAX_SDA
J7
USB MINI-AB
1
2
3
4
5
C207
1
DNI
100K
R239
FX2_RESETn
2
GND
VCC
RESET
MR
4
U1A
U46
1M
R258
GND
D+
D-
1
2
3.3V
U5
TPD2EUSB30
D1
D2
4.7nF
G1
A5
B5
C5
E7
E8
C332
D
E1
E2
4
Y3
3
2
1
C286
12pF
G2
C1
C2
USB_CLK
24M_XTALIN
24M_XTALOUT
24.00MHz
C331
12pF
FX2_PA1
FX2_PA2
FX2_PA3
FX2_PA4
FX2_PA5
FX2_PA6
FX2_PA7
C
G8
G6
F8
F7
F6
C8
C7
C6
H2
F1
F2
H1
A4
B4
C4
D7
D8
3.3V
AVCC
AVCC
RESET
SCL
SDA
VCC
VCC
VCC
VCC
VCC
VCC
WAKEUP
CTL0
CTL1
CTL2
DMINUS
DPLUS
RDY0
RDY1
IFCLK
XTALIN
XTALOUT
CLKOUT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESERVED
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
AGND
AGND
GND
GND
GND
GND
GND
GND
B8
F3
G3
FX2_RESETn
FX2_SCL R237
FX2_SDA R236
B7
FX2_WAKEUP
H7
G7
H8
FX2_FLAGA
FX2_FLAGB
FX2_FLAGC
A1
B1
FX2_SLRDn
FX2_SLWRn
2.00K
2.00K
FX2_PA6
FX2_PB2
FX2_FLAGB
FX2_PB0
FX2_PA1
FX2_PB5
USB_DISABLEn
B2
H3
F4
H4
G4
H5
G5
F5
H6
FX2_PB0
FX2_PB1
FX2_PB2
FX2_PB3
FX2_PB4
FX2_PB5
FX2_PB6
FX2_PB7
A8
A7
B6
A6
B3
A3
C3
A2
FX2_PD0
FX2_PD1
FX2_PD2
FX2_PD3
FX2_PD4
FX2_PD5
FX2_PD6
FX2_PD7
10.0K
C287
20.0K
0.1uF
F2
E1
FX2_RESETn
MAX_SDA
K8
L8
JTAG_TX
SC_RX
SC_TX
JTAG_RX
FACTORY_REQUEST
USB_CFG5
USB_RESETn
USB_OEn
C199
C200
C201
C202
C203
C204
C205
C206
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
F10
G11
USB_CFG7
M570_CLOCK
1.8V
R127
IOB1/GCLK0
IOB1/GCLK1
TCK
TDI
TDO
TMS
IOB1/DEV_CLRn
IOB1/DEV_OE
L11
L2
L3
L4
L5
L6
L7
L9
FX2_SLRDn
FX2_PD7
FX2_PD5
FX2_PA5
C_JTAG_TDO
C_JTAG_TMS
C_JTAG_TDI
K1
J2
K2
J1
C_USB_MAX_TCK
C_USB_MAX_TDI
C_USB_MAX_TDO
C_USB_MAX_TMS
M570_PCIE_JTAG_EN
27
MAX II USB INTERFACE
USB_CFG[11:0]
27
EXTRA_SIG[2:0]
27
D
USB_DISABLEn
M570_CLOCK
FACTORY_STATUS
FACTORY_REQUEST
R257
R256
R254
R255
0
0
0
0
15
27
27
27
FX2_PD0
FX2_PD2
FX2_PD3
FX2_PD1
JTAG INTERFACE
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
MAX II
BANK2
IOB2_1
IOB2_2
IOB2_3
IOB2_4
IOB2_5
IOB2_6
IOB2_7
IOB2_8
IOB2_17
IOB2_18
IOB2_19
IOB2_20
IOB2_21
IOB2_22
IOB2_23
IOB2_24
IOB2_9
IOB2_10
IOB2_11
IOB2_12
IOB2_13
IOB2_14
IOB2_15
IOB2_16
IOB2_25
IOB2_26
IOB2_27
IOB2_28
IOB2_29
IOB2_30
IOB2_31
IOB2_32
IOB2/GCLK2
IOB2/GCLK3
IOB2_33
IOB2_34
IOB2_35
IOB2_36
IOB2_37
IOB2_38
B5
B6
B7
B8
B9
C10
C11
C6
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3
USB_DATA4
USB_DATA5
USB_DATA6
USB_DATA7
D10
D11
D9
E10
E11
F11
F9
G10
USB_CFG8
USB_ADDR0
USB_ADDR1
USB_FULL
USB_EMPTY
USB_SCL
USB_CFG11
USB_SDA
H10
H11
H9
J10
J11
K11
USB_CFG10
USB_CFG0
EXTRA_SIG2
USB_CFG1
USB_CFG2
USB_CFG9
14,15,27,30,31
14,15,27
15,27
14,15
C
U1C
C5
E8
G4
J5
D5
D7
E4
G8
H5
H7
1.8V
MAX II
Power
GNDINT
GNDINT
GNDINT
GNDINT
VCCINT
VCCINT
VCCINT
VCCINT
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
C7
E9
G3
J7
3.3V
E3
J4
J8
1.5V
C4
C8
G9
EPM570GM100
B
PLACE NEAR MAX II (U34)
3.3V
1.5V
56.2
Green_LED
D3
RESn_JTAG_TX
R126
56.2
1.8V
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
R182
R181
R183
R184
1.00k
1.00k
1.00k
1.00k
USB_SCL
USB_SDA
USB_FULL
USB_EMPTY
R214
1.00k
FACTORY_REQUEST
0
0
0
0
R180
R205
R194
R213
JTAG_TCK
JTAG_TMS
JTAG_BLASTER_TDI
JTAG_BLASTER_TDO
DNI
JTAG_BLASTER_TDI
C190
C158
C191
C147
C148
C146
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.5V
Green_LED
D10
SC_RX
IOB1_25
IOB1_26
IOB1_27
IOB1_28
IOB1_29
IOB1_30
IOB1_31
IOB1_32
FX2_PB6
FX2_PB1
FX2_PB3
FX2_SCL
FX2_PD6
FX2_PD4
FX2_SLWRn
C_JTAG_TCK
E
1.5V
RESn_JTAG_RX
JTAG_TX
IOB1_9
IOB1_10
IOB1_11
IOB1_12
IOB1_13
IOB1_14
IOB1_15
IOB1_16
K3
K4
K5
K6
K7
K9
L1
L10
8
8
8
8
12,27
8
8
8
8
EPM570GM100
D2
JTAG_RX
A1
A10
A11
A2
A3
A4
A5
A6
A7
USB_RDn
A8
USB_WRn
A9
FACTORY_STATUS
B10
USB_CFG3
M570_PCIE_JTAG_EN B11
B2
USB_CFG4
B3
EXTRA_SIG1
B4
USB_CFG6
FX2_WAKEUP
R246
USB_CLK
FX2_PB7
IOB1_17
IOB1_18
IOB1_19
IOB1_20
IOB1_21
IOB1_22
IOB1_23
IOB1_24
U1B
PLACE NEAR CY7C68013A
3.3V
B
F3
G1
G2
H1
H2
H3
J6
K10
IOB1_1
IOB1_2
IOB1_3
IOB1_4
IOB1_5
IOB1_6
IOB1_7
IOB1_8
EPM570GM100
CY7C68013A_VFBGA
VBUS_5V R238
B1
C1
C2
D1
D2
D3
E2
F1
FX2_PA2
FX2_FLAGC
FX2_PA7
FX2_FLAGA
FX2_PA3
FX2_PA4
EXTRA_SIG0
FX2_PB4
MAX811
3
MAX II
BANK1
3
8
USB_FULL
USB_EMPTY
USB_SCL
USB_SDA
USB_CLK
USB_RESETn
USB_OEn
USB_RDn
USB_WRn
0.1uF
U44
7
6
E
VBUS_5V
FX2_D_N
FX2_D_P
R215
8
USB_ADDR[1:0]
3.3V
RESn_SC_RX
R136
56.2
3.3V
3.3V
R193
J31
R99
Green_LED
D11
A
SC_TX
RESn_SC_TX
R135
56.2
R100
Green_LED
1.00K C_USB_MAX_TCK 1
C_USB_MAX_TDO 3
1.00K C_USB_MAX_TMS 5
7
C_USB_MAX_TDI 9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
Title
Size
DNI
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
33
of
1
46
8
7
6
5
4
3
2
1
User I/O - (For Arria V GX FPGA 1)
E
E
LED INTERFACE
D14
PGM1_LED0
D13
PGM1_LED1
D12
PGM1_LED2
Green_LED
RESn_PGM1_LED0
Green_LED
RESn_PGM1_LED1
Green_LED
RESn_PGM1_LED2
2.5V
R131
2.5V
56.2
R132
R133
RES_MAX_ERROR1 R130
D17
Green_LED
RES_MAX_LOAD1
MAX_LOAD1
D16
MAX_CONF_DONE1
75
R163
USER1_LED_R0
75
R164
75
R165
USER1_LED_R1
75
R128
56.2
R
1
2
USER1_LED_G0
2
S2
1
2
4
R
S1
1
2
USER1_LED_G1
2
100, 1%
R166
75
56.2
R167
USER1_LED_R2
75
56.2
R168
2.5V
R169
4
R
RESn_HSMA_RX_LED R115
USER1_LED_R3
75
56.2
RESn_HSMA_TX_LED R114
56.2
Green_LED
3.3V
D6
HSMA_PRSNTn
R125
75
R171
USER1_LED_R4
75
R172
75
USER1_LED_G2
4
R
1
2
USER1_LED_G3
S6
1
2
2
S5
1
2
R173
USER1_LED_R5
75
R395
R174
75
R175
USER1_LED_R6
75
R176
75
R383
R177
RN5A
RN5B
RN5C
RN5D
RN5E
RN5F
RN5G
RN5H
USER1_DIPSW0
USER1_DIPSW1
USER1_DIPSW2
USER1_DIPSW3
USER1_DIPSW4
USER1_DIPSW5
USER1_DIPSW6
USER1_DIPSW7
1
2
3
4
5
6
7
8
R
MAX_RESETn
R79
10.0K
CPU1_RESETn
R113
10.0K
6,7
USER1_LED_R[7:0]
6,12
1.8V
MAX_ERROR1
MAX_LOAD1
MAX_CONF_DONE1
2.5V
HSMA_RX_LED
HSMA_TX_LED
HSMA_PRSNTn
6
6
6,27,30
6
6
6
USER1_PB0
R110
10.0K
PCIE_LED_X1
PCIE_LED_X4
PCIE_LED_X8
USER1_PB1
R111
10.0K
PUSH BUTTON INTERFACE
USER1_PB2
R112
10.0K
2.5V
3
4
PB Switch
3
4
PB Switch
3
4
PB Switch
27
27
27
USER1_PB[2:0]
7
PGM1_SEL
PGM1_CONFIG
MAX_RESETn
CPU1_RESETn
27
27
27
14,27
R
16
15
14
13
12
11
10
9
4
R
USER1_LED_G6
LCD1_WEn
LCD1_DATA0
LCD1_DATA2
LCD1_DATA4
LCD1_DATA6
2
1
3
5
7
9
11
13
CLK_SEL
CLK_ENABLE
FACTORY_USER1
FACTORY_USER2
1
3
5
7
9
11
13
2
4
6
8
10
12
14
2
4
6
8
10
12
14
LCD1_D_Cn
LCD1_CSn
LCD1_DATA1
LCD1_DATA3
LCD1_DATA5
LCD1_DATA7
10,27
27
27
27
2
B4
B5
2x16 LCD
2x7 HDR
C
LCD INTERFACE
LCD1_DATA[7:0]
7
HDR2X7
USER1_LED_G7
LCD1_CSn
LCD1_D_Cn
LCD1_WEn
7
7
7
2.5V
SW5
8
7
6
5
10K
10K
10K
10K
10K
10K
10K
10K
7
5.0V
J29
4
D
DIP SWITCH INTERFACE
2
D18 LED_GR
1 G
3
USER1_LED_R7
75
2.5V
SW2
1
2
3
4
5
6
7
8
10.0K
56.2
D42
16
15
14
13
12
11
10
9
R66
USER1_LED_G5
56.2
OPEN
YELLOW LED
4
D19 LED_GR
1 G
3
D43
B
PGM1_SEL
2
56.2
D44
YELLOW LED
27
USER1_LED_G[7:0]
USER1_DIPSW[7:0]
R412
YELLOW LED
PCIE_LED_X8
R
D20 LED_GR
1 G
3
2.5V
PCIE_LED_X4
4
USER1_LED_G4
PGM1_LED[2:0]
10.0K
Green_LED
56.2
C
PCIE_LED_X1
3
4
PB Switch
R65
S7
D21 LED_GR
1 G
3
R170
Green_LED
D5
HSMA_TX_LED
PGM1_CONFIG
2
D22 LED_GR
1 G
3
75
1
2
D4
HSMA_RX_LED
3
4
PB Switch
3
4
PB Switch
3
4
PB Switch
S4
D23 LED_GR
1 G
3
Green_LED
RES_CONF_DONE1nR129
4
D24 LED_GR
1 G
3
Red_LED
MAX_ERROR1
D
R162
2.5V
S3
56.2
2.5V
D15
D25 LED_GR
1 G
3
1
2
3
4
CLK_SEL
CLK_ENABLE
FACTORY_USER1
FACTORY_USER2
R331
R330
R329
R328
B
10.0K
10.0K
10.0K
10.0K
TDA04H0SB1
TDA08H0SB1
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
34
of
1
46
8
7
6
5
4
3
2
1
User I/O - (For Arria V GX FPGA 2)
E
E
PUSH BUTTON INTERFACE
CPU2_RESETn
14,27
USER2_PB[2:0]
13,18
2.5V
2.5V
D7
RESn_HSMB_RX_LED R107
HSMB_RX_LED
D
DEVICE1_LED
RESn_HSMB_TX_LED R106
D35
Green_LED
Green_LED
RESn_DEVICE1_LED R221
D34
DEVICE2_LED
Green_LED
RESn_DEVICE2_LED R200
HSMB_PRSNTn
R121
R143
USER2_LED_R0
75
56.2
4
R
16
15
14
13
12
11
10
9
USER2_LED_G0
2
D32 LED_GR
1 G
3
R144
75
USER2_LED_R1
75
4
R145
R146
75
1
USER2_LED_R2
75
4
R147
R148
75
1
USER2_LED_R3
75
4
R149
56.2
R
USER2_LED_G1
D31 LED_GR
G
3
C
B
R151
USER2_LED_R4
75
RN4A
RN4B
RN4C
RN4D
RN4E
RN4F
RN4G
RN4H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
10K
10K
10K
10K
10K
10K
10K
10K
LED INTERFACE
USER2_LED_G[7:0]
R
2
D30 LED_GR
G
3
R
18
USER2_LED_R[7:0]
13,18,37
D
HSMB_RX_LED
HSMB_TX_LED
HSMB_PRSNTn
DEVICE1_LED
DEVICE2_LED
USER2_LED_G2
16
16
16,27,30
27
27
2.5V
S8
1
2
56.2
75
USER2_DIPSW0
USER2_DIPSW1
USER2_DIPSW2
USER2_DIPSW3
USER2_DIPSW4
USER2_DIPSW5
USER2_DIPSW6
USER2_DIPSW7
2
Green_LED
R150
1
2
3
4
5
6
7
8
TDA08H0SB1
56.2
3.3V_ATX
D9
75
2.5V
SW3
56.2
Green_LED
D8
HSMB_TX_LED
R142
D33 LED_GR
1 G
3
3
CPU2_RESETn
4
PB Switch
R105
10.0K
DIP SWITCH INTERFACE
USER2_DIPSW[7:0]
13,18,37
USER2_LED_G3
2.5V
2
S11
D29 LED_GR
1 G
3
4
R152
75
1
USER2_LED_R5
75
4
R153
R154
75
1
USER2_LED_R6
75
4
R155
R156
75
1
USER2_LED_R7
75
4
R157
R
1
2
USER2_LED_G5
R102
10.0K
R103
10.0K
R104
10.0K
C
USER2_LED_G6
2
D26 LED_GR
G
3
R
1
2
3
USER2_PB0
4
S10 PB Switch
3
USER2_PB1
4
PB Switch
S9
3
USER2_PB2
4
PB Switch
2
D27 LED_GR
G
3
R
USER2_LED_G4
2
D28 LED_GR
G
3
R
1
2
USER2_LED_G7
2
B
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
35
of
1
46
8
7
6
5
4
3
2
1
Power - Arria V GX Power (FPGA 1)
E
E
U16K
U16P
U16L
Arria V GX Power
Arria V GX I/O Power
A5_VCCIO_1.8V
AA10
AA12
AA14
AA16
AA18
AA20
Y29
AA22
AA24
Y11
AA26
AB11
Y25
AB17
U10
U12
Y15
V11
Y17
V15
V17
Y19
V23
Y21
Y23
V29
W10
W12
W14
W16
W18
W20
W22
W24
W26
W28
D
C
A5A_VCCP
AA21
AA25
AB15
U16
V13
V22
V25
V27
Y13
Y27
B
Auxiliary
Supply
Core and
Periphery
A5A_VCCINT
A5A_VCCPD_PGM_IO_2.5V
N11
AG29
(2.5V)
A5A_VCCD_PLL_1.5V
R33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_AUX
VCC_AUX
2.5V
VCC_AUX
VCC_AUX
I/O Pre-Driver
2.5V
3.0V/3.3V
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD4A
VCCPD4A
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
1.1V
VCCPD7A
VCCPD7A
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCP
VCCP
PLL
VCCP
VCCP
VCCP
VCCP
1.5V
VCCP
VCCP
VCCP
VCCP
Configuration
PLL
VCCPGM
VCCPGM
1.8V/2.5V/
2.5V
3.0V/3.3V
Battery
Back-up
VCCBAT
Arria V GX Transceiver Power
A5A_VCCPD_PGM_IO_2.5V
AH29
AJ30
AK35
AM30
AP35
AT35
AJ31
A5A_VCCA_2.5V
AB14
AB26
U14
U28
A5A_VCCPD_PGM_IO_2.5V
AA27
AA28
AA29
AB22
AB23
AB24
AB30
VREF_QDRII
(2.5V)
AJ24
AL25
AM24
AP25
AR24
AU25
AK26
AC10
AE10
AB12
AB13
AB16
AB18
AB19
AJ22
AL21
AM22
AP21
AR22
AU21
AJ21
P8
R10
U18
T12
T13
T16
U19
A5A_VCCPD_PGM_IO_2.5V
U29
R32
T30
U21
U22
U24
U26
A5A_VCCD_PLL_1.5V
Digital
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
Analog
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
AK28
AL27
AN28
AT28
AL28
W9
AB20
AD31
AE9
V19
W30
R9
T31
AG10
AJ5
AL5
AN5
AR5
AU5
AH7
AK13
AM12
AN10
AN13
AR12
AT10
AN11
AJ15
AM15
AR15
AV15
AG15
A5A_VCCA_2.5V
Y30
AA9
AB21
AC30
AC9
V20
U9
V31
AJ19
AK18
AM19
AN18
AR19
AT18
AF18
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREFB3AN0
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VREFB3BN0
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VREFB7AN0
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VREFB7BN0
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VREFB3CN0
VCCIO7C
VCCIO7C
VCCIO7C
VCCIO7C
VREFB7CN0
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VREFB3DN0
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VREFB7DN0
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREFB4AN0
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREFB8AN0
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VREFB4BN0
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8B
VREFB8BN0
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO4C
VREFB4CN0
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VREFB8CN0
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VREFB4DN0
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VREFB8DN0
A5A_VCCR_VCCL_GXB
E5
G5
H7
J5
L5
M9
J7
A5A_VCCD_PLL_1.5V
AD33
Y33
T33
AC7
W7
R7
C13
D10
F13
G10
K10
L13
G11
A5A_VCCR_VCCL_GXB
AD34
AD35
Y34
Y35
T34
T35
F16
G15
K15
L16
D15
AC5
AC6
W5
W6
R5
R6
B19
D18
E19
G18
H19
M18
T18
A5A_VCCIO_1.5V
B35
G31
G33
K31
K33
P33
H33
A5A_VCCA_2.5V
AF33
AB33
V33
AE7
AA7
U7
Analog Power
TX Buffer Block
Analog Power
RX
VCCH_GXBL0
VCCH_GXBL1 1.5V
VCCH_GXBL2
VCCH_GXBR0
VCCH_GXBR1
VCCH_GXBR2
Digital Power
1.1V
VCCL_GXBL0
VCCL_GXBL0
VCCL_GXBL1
VCCL_GXBL1
VCCL_GXBL2 1.1V
VCCL_GXBL2
VCCL_GXBR0
VCCL_GXBR0
VCCL_GXBR1
VCCL_GXBR1
VCCL_GXBR2
VCCL_GXBR2
Analog Power
VCCA_GXBL0
VCCA_GXBL1
VCCA_GXBL2 2.5V
VCCA_GXBR0
VCCA_GXBR1
VCCA_GXBR2
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
VCCR_GXBR
Analog Power
TX
VCCT_GXBL0
VCCT_GXBL0
VCCT_GXBL1
VCCT_GXBL1
1.1V VCCT_GXBL2
VCCT_GXBL2
VCCT_GXBR0
VCCT_GXBR0
VCCT_GXBR1
VCCT_GXBR1
VCCT_GXBR2
VCCT_GXBR2
R35
AC34
AC35
AG34
AG35
W34
W35
P5
AB5
AB6
AF5
AF6
V5
V6
D
A5A_VCCT_GXB
AE34
AF35
AA34
AB35
U34
V35
AD6
AE5
AA5
Y6
U5
T6
C
5AGXB3H4F40
Version = 1.86 Pin-out
VREF_DDR3A
E28
E30
H30
K28
R31
C25
D27
F25
G27
J25
M24
L25
B
C21
D22
F21
G22
K22
L21
H22
5AGXB3H4F40
1.2V-3V
Version = 1.86 Pin-out
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
36
of
1
46
8
7
6
5
4
3
2
1
Power - Arria V GX Power (FPGA 2)
XJ3
E
U13K
E
2mm Shunt
Arria V GX Power
AA10
AA12
AA14
AA16
AA18
AA20
Y29
AA22
AA24
Y11
AA26
AB11
Y25
AB17
U10
U12
Y15
V11
Y17
V15
V17
Y19
V23
Y21
Y23
V29
W10
W12
W14
W16
W18
W20
W22
W24
W26
W28
D
C
A5B_VCCP
AA21
AA25
AB15
U16
V13
V22
V25
V27
Y13
Y27
B
Auxiliary
Supply
Core and
Periphery
A5B_VCCINT
A5B_VCCPD_PGM_IO_2.5V
N11
AG29
(2.5V)
A5B_VCCD_PLL_1.5V
R33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_AUX
VCC_AUX
2.5V
VCC_AUX
VCC_AUX
I/O Pre-Driver
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
VCCPD3
2.5V
3.0V/3.3V
1.1V
VCCPD4A
VCCPD4A
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD4BCD
VCCPD7A
VCCPD7A
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD7BCD
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCPD8
VCCP
VCCP
PLL
VCCP
VCCP
VCCP
VCCP
1.5V
VCCP
VCCP
VCCP
VCCP
Configuration
PLL
VCCPGM
VCCPGM
1.8V/2.5V/
2.5V
3.0V/3.3V
Battery
Back-up
VCCBAT
Digital
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
VCCD_FPLL
Analog
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
VCCA_FPLL
A5B_VCCPD_PGM_IO_2.5V
A5B_VCCA_2.5V
FMC_VCCPD
J5
1
AB14
(1-2) FMC
2
AB26
(2-3) FMC
3
U14
U28
3.3V
TMM-103-01-G-S
AA27
AA28
AA29
AB22
AB23
AB24
AB30
U13L
at 2.5V or lower operation (default)
at 3.0V or greater operation
A5B_VCCPD_PGM_IO_2.5V
U13P
Arria V GX Transceiver Power
(2.5V or 3.3V)
A5B_VCCD_PLL_1.5V
AD33
Y33
T33
A5B_VCCR_VCCL_GXB
Analog Power
TX Buffer Block
VCCH_GXBL0
VCCH_GXBL1 1.5V
VCCH_GXBL2
Analog Power
RX
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
VCCR_GXBL
USER2_LED_R4
R35
AC34
AC35
AG34
AG35
W34
W35
AC10
AE10
AC7
USER2_LED_R2
1.1V
AB12
W7 VCCH_GXBR0
VCCH_GXBR1
A5_VCCIO_FMC
AB13
R7
VCCH_GXBR2
AB16
Digital Power
AB18
P5
A5B_VCCR_VCCL_GXB
VCCR_GXBR AB5
AB19
AD34
VCCL_GXBL0
VCCR_GXBR
AD35
AB6
A5B_VCCPD_PGM_IO_2.5V
VCCR_GXBR AF5
VREFA_FMC
P8
Y34 VCCL_GXBL0
VCCL_GXBL1
VCCR_GXBR
R10
Y35
AF6
VCCL_GXBL1
VCCR_GXBR
U18
T34
V5
(2.5V)
VCCR_GXBR V6
T12
T35 VCCL_GXBL2 1.1V
VCCL_GXBL2
VCCR_GXBR
T13
Analog Power
A5B_VCCT_GXB
T16
AC5
TX
U19
AC6 VCCL_GXBR0
AE34
VCCL_GXBR0
VCCT_GXBL0
W5
AF35
VCCT_GXBL0 AA34
U29
W6 VCCL_GXBR1
VCCL_GXBR1
VCCT_GXBL1
R32
R5
AB35
VCCT_GXBL1 U34
T30
R6 VCCL_GXBR2
VCCL_GXBR2
VCCT_GXBL2
1.1V
U21
V35
VCCT_GXBL2
Analog Power
U22
A5B_VCCA_2.5V
U24
AF33
AD6
VCCT_GXBR0 AE5
U26
AB33 VCCA_GXBL0
VCCA_GXBL1
VCCT_GXBR0
V33
AA5
VCCT_GXBR1 Y6
AE7 VCCA_GXBL2 2.5V
A5B_VCCD_PLL_1.5V
VCCA_GXBR0
VCCT_GXBR1
AA7
U5
VCCT_GXBR2 T6
W9
U7 VCCA_GXBR1
FMC_VCCIO
VCCA_GXBR2
VCCT_GXBR2
AB20
5AGXB3H4F40
A5_VCCIO_FMC
AD31
AE9
Version = 1.86 Pin-out
V19
J28
1
W30
2
R9
(1-2) VCCIO on Board (default)
3
T31
(2-3) VCCIO from FMC
TMM-103-01-G-S
XJ4
A5B_VCCA_2.5V
Y30
AA9
AB21
AC30
AC9
V20
U9
V31
Arria V GX I/O Power
A5B_VCCPD_PGM_IO_2.5V
FMC_VCCIO_MODULE
VREFB_FMC
AH29
AJ30
AK35
AM30
AP35
AT35
AJ31
AK28
AL27
AN28
AT28
AL28
AJ24
AL25
AM24
AP25
AR24
AU25
AK26
AJ22
AL21
AM22
AP21
AR22
AU21
AJ21
AG10
AJ5
AL5
AN5
AR5
AU5
AH7
AK13
AM12
AN10
AN13
AR12
AT10
AN11
AJ15
AM15
AR15
AV15
AG15
2mm Shunt
AJ19
AK18
AM19
AN18
AR19
AT18
AF18
1.2V-3V
5AGXB3H4F40
Version = 1.86 Pin-out
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VCCIO3A
VREFB3AN0
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VCCIO7A
VREFB7AN0
VCCIO3B
VCCIO3B
VCCIO3B
VCCIO3B
VREFB3BN0
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VCCIO7B
VREFB7BN0
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VCCIO3C
VREFB3CN0
VCCIO7C
VCCIO7C
VCCIO7C
VCCIO7C
VREFB7CN0
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VCCIO3D
VREFB3DN0
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VCCIO7D
VREFB7DN0
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VCCIO4A
VREFB4AN0
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VCCIO8A
VREFB8AN0
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VCCIO4B
VREFB4BN0
VCCIO8B
VCCIO8B
VCCIO8B
VCCIO8B
VREFB8BN0
VCCIO4C
VCCIO4C
VCCIO4C
VCCIO4C
VREFB4CN0
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VCCIO8C
VREFB8CN0
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VCCIO4D
VREFB4DN0
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VCCIO8D
VREFB8DN0
E5
G5
H7
J5
L5
M9
J7
USER I/O INTERFACES
USER2_LED_R[7:0]
13,18,35
USER2_DIPSW[7:0]
C13
D10
F13
G10
K10
L13
G11
USER2_DIPSW7
F16
G15
K15
L16
D15
USER2_DIPSW6
13,18,35
D
B19
D18
E19
G18
H19
M18
T18
A5B_VCCIO_1.5V
B35
G31
G33
K31
K33
P33
H33
C
VREF_DDR3B
E28
E30
H30
K28
R31
C25
D27
F25
G27
J25
M24
L25
B
C21
D22
F21
G22
K22
L21
H22
5AGXB3H4F40
Version = 1.86 Pin-out
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
37
of
1
46
8
7
6
5
4
3
2
1
Power 1 - DC Input & 12V, 3.3V Output
12V
12V_OUT
R219
8
7
6
5
19V
DC Input
4
3
2
U40
5
GATE
IN
1
6
4
7
OUT
VDD
GND
EP_GND
NC
5
U42
FDMC8878
1
2
3
12V_MUX
DC_IN
GATE
IN
NC
1
6
4
7
OUT
VDD
GND
EP_GND
C4
C3
47uF
35V
47uF
35V
DC_IN
C127
22uF
25V
INTVCC_1
MMBD1205
D47
CMDSH-3
U3
This should be a copper
pour not a trace.
8
7
6
5
C128
22uF
25V
LTC4357
D48
LTC4357
D
E
U39
4
3
2
8
7
6
5
1
2
3
26
25
24
C138
R185
VIN
INTVCC
EXTVCC
TG1
BOOST1
4.7uF
3.3V_SHDNn
DNI
U45
3
2
5
R195
GATE
IN
OUT
VDD
GND
EP_GND
NC
1
6
4
7
R186
12V_SHDNn
DNI
DNI
R196
LTC4357
SI4816BDY-T1
Q7
5.0V
INTVCC_1
4
C130
22uF
25V
38
37
14
2
1
13
36
15
6
7
SW1
RUN1
ITEMP1
ILIM1
ITH1
TK/SS1
BG1
VFB1
RUN2
ITEMP2
ILIM2
ITH2
TK/SS2
SENSE1+
SENSE1PGOOD1
30
C5
L2
29
2
CH1
1
27
CH2
V3
2
SW1
4
3
2
3
1
SNS RSNS
SENSE_PAD
LTC3855_S1P
LTC3855_S1N
R189
2.37K
R188
5.76K
C7
16
V4
C2
100uF
6.3v
0.1uF
1
10
12
11
8
1 2 3
VIN
3
4
UV
OV
D51
LTC4352CDD
2
VCC
CPO
SOURCE
GATE
OUT
C31
56pF
C162
REV
EP
GND
7
13
9
39pF
0.1uF
C161
10pF
C30
22pF
TG2
BOOST2
SW2
R22
82.5K
R208
118.0K
B
BG2
VFB2
U49
FDMC8878
4
20
21
C6
1
RJK0301DPB
SENSE2+
SENSE2-
DIFFOUT
DIFFP
DIFFN
PGOOD2
DC_IN
VFB2
2
1
8
9
LTC3855_S2P
LTC3855_S2N
R101
C32
4.02K
100K
R120
17 PG_12V
0.1uF
R206
215.0K
V2
C33
C34
C8
100uF
16V
100uF
16V
220uF
16V
VFB2
R198
11.3K
SENSE_PAD
B
R90
4
1
5
6
2
3
R89
100K
3.3V_MUX
5.0V
LTC4352CDD
GND
EP
REV
R88
20.0K
9
13
7
R86
1.00k
VIN
VCC
3.3V_SHDNn
R87
20.0K
SW1
SW_SLIDE_DPDT
POWER LED
CPO
3
4
1
UV
OV
10
OUT
GATE
SOURCE
STATUS
FAULT
D52
8
11
12
5
6
12V_SHDNn
2
D1
BLUE LED
C514
0.1uF
Title
B
3.3V_MUXVCC
Date:
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Size
8
SNS RSNS
DC_IN
100K
4
3.3V_MUX
V1
4
5
2
0.68uH
Q4
drain-tab
23
12V_MUX
L1
R197
100K
FDMC8878
U50
A
drain-tab RJK0305DPB
4
LTC3855EUJ
8 7 6 5
R280
DNI
0.1uF
19
8 7 6 5
1 2 3
Q5
SENSE_PAD
DIFFOUT 12
10
11
3.3V_MUX
5
6
4
C431
SGND1
SGND2
PGND1
PGND2
NC
gnd-pad
STATUS
FAULT
R266
DNI
Q6
drain-tab
4
41
28
22
18
3.3V_PCIE
RJK0305DPB
2
R187
169.0K
RSNS SNS
3.3V_MUXVCCP
C
R207
2.55K
C129
22uF
25V
1
1000pF
5
1000pF
DC_IN
CMDSH-3
D46
1
2
3
C159
5
C160
1
2
3
DNI
R281
R199 DIFFOUT
11.5K
5
3.3V
0.003
FREQ
MODE/PLLIN
PHSASMD
CLKOUT
1
2
3
3.3V_OUT
C
C1
330uF
4V
SENSE_PAD
INTVCC_1
35
34
33
32
D
1
2.2uH
7
6
5
31 SW1
39
40
3.3V_MUX
8
0.1uF
2
1
2
3
12V_PCIE
U35
FDMC8878
J6
CONN JACK PWR
2
1
3
RSNS SNS
U41
FDMC8878
E
DC_INPUT
1
0.003
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
38
of
1
46
8
7
6
5
4
3
2
1
Power 2 - 1.1V (VCCINT)
40
AV_VCCINT_PG
27
27
VCCINT_SCL
VCCINT_SDA
E
E
A5A_VCCP
12V
L10
3A, 30 Ohm FB
C540
5.0V_LTC3880
12V
10uF
A5A_VCCINT
22uF
25V
CMDSH-3
D49
D50
CMDSH-3
VIN
BG0
14
2
C333
C375
GPIO0
GPIO1
1
2
R273
R271
R272
R270
R282
8
4.99K
10K
VCCINT_SDA 10
10K
VCCINT_SCL 9
11
10K
24
10K
23
12 PG_VCCINT 10K
13
10K
R288
R287
SYNC
SDA
SCL
ALERT
SHARE_CLK
WP
TG1
18
19
R268
R283
DNI
DNI
20
21
VOUT0_CFG
VOUT1_CFG
VDD25
BOOST1
SW1
ASEL
VDD25
R301
R302
10K
23.2K
C211
C212
D
L11
V7
22uF
4V
22uF
4V
100uF
6.3V
100uF
6.3V
330uF
2.5V
330uF
2.5V
3A, 30 Ohm FB
C444
10uF
SENSE_PAD
806
C41
0.1uF
31
29
Q12
2
drain-tab
RJK0301DPB
3
4
PGND
GND_PAD
0.22uH
Q2
4
V11
RJK0301DPB
2
SNS RSNS
C29
1
SENSE_PAD
R30
LTC3880_IS1P
LTC3880_IS1N
27
C
1
drain-tab
4
32
1.1V
L4
RJK0305DPB
806
R27
DNI
C335
0.1uF
FREQ_CFG
16
C213
C266
22uF
25V
A5A_VCCINT
VSENSE1
17
30.1K
1.96K
ISENSE1+
ISENSE1-
VTRIM0_CFG
VTRIM1_CFG
VDD25
R285
R286
R23
Q8
1
2
3
24.9K
4.32K
806
C193
12V
4
30
VDD25
R269
R284
1
R25
DNI
C376
0.1uF
drain-tab
BG1
B
R26
VDD33
C
SNS RSNS
C27
VDD33
ITH1
270pF
2
LTC3880_IS0P
LTC3880_IS0N
5
1500pF
R259
4.64K
VSENSE0+
VSENSE0-
0.001
A5B_VCCP
C26
V12
RJK0301DPB
A5A_VCCINT
ITH0
26
6
7
1
2
3
0.01uF
3
2
3
0.01uF
ISENSE0+
ISENSE0-
TSNS0
TSNS1
5
C432
4
R21
SENSE_PAD
RUN1
40
28
1.1V_TSNS0
1.1V_TSNS1
Q15
MMBT3906
1
1
drain-tab
4
36
RUN0
15
Q14
MMBT3906
C435 1
drain-tab
RJK0301DPB
A5B_VCCINT
0.22uH
Q13
2
R303 3880_RUN
39
2
Q1
1.1V
R28
V10
C28
22uF
4V
RSNS SNS
4.7uF
C36
0.1uF
5
VDD33
10K
SW0
37
L3
RJK0305DPB
1
2
3
10uF
BOOST0
INTVCC
C334
1uF
VDD33
4
38
5
1uF
TG0
1
33
C433 C434
D
drain-tab
VDD25
2
25
5.0V_LTC3880
C472
0.001
RSNS SNS
VDD33
R24
1
22
5
VDD25
Q9
1
2
3
35
5
U9
C35
22uF
25V
1
2
3
47uF
20V
C208
1
2
3
C265
22uF
25V
5
C42
22uF
4V
C192
100uF
6.3V
C214
100uF
6.3V
C210
C209
330uF
2.5V
330uF
2.5V
SENSE_PAD
806
34
41
B
LTC3880
A5A_VCCINT
3.3V
R387
R388
12.0K
15.0K
U55
5
3.3V
VM_0P5V
R405
R386
A
4
0 MANUAL_RESETn 2
7
DNI
RT
3
6
3.3V
VCC
RST
8
AV_VCCINT_PG
R404
10K
VM
TOL/MR
RT
SEL1
SEL2
3.3V
GND
EPAD
1
9
Title
0.1uF
Size
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
C916
LTC2915
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
39
of
1
46
8
7
2.5V
5.0V
VOUTS2_1P2
E
4.7uF
C5
C8
F5
PG_1.2V
RUN_LTM4628 F9
3.3V
DNI
R399
J6
E5
D8
1.1V
R365
42.2K
C6
G4
C894
0.1uF
R384
150K
R364
51.1K
5
U27A
H8
J7
C929
6
F4
2.5V
VOUTS1
VOUTS2
PGOOD1
PGOOD2
INTVCC
EXTVCC
SW1
VFB1
RUN1
RUN2
G9
G8
PG_2.5V
PG_1.2V
R420
R419
SW2
VFB2
TRACK1
TRACK2
CLKOUT
DIFFOUT
FSET
PHASMD
COMP1
COMP2
MODE-PLLIN
DIFFP
DIFFN
AV_VCCINT_PG R44
39
1.8V
VOUTS2_1P5
C5
C8
H8
J7
3.3V
10K
C930
F5
F9
4.7uF
J6
R43
PG_1.2V
E5
D8
C
C6
G4
C915
0.1uF R376
150K
F4
INTVCC
EXTVCC
SW1
VFB1
RUN1
RUN2
SW2
TEMP
VFB2
TRACK1
TRACK2
CLKOUT
DIFFOUT
FSET
PHASMD
COMP1
COMP2
MODE-PLLIN
DIFFP
DIFFN
B
A
A6
A7
B6
B7
D1
D2
D3
D4
D9
D10
D11
D12
E1
E2
E3
E4
E10
E11
E12
F1
F2
F3
F10
C7
F6
F7
G6
G7
D6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SGND
SGND
SGND
SGND
SGND
SGND
C935
C936
C938
C937
10uF
35V
10uF
35V
10uF
35V
10uF
35V
G11
D7
60.4K
G5
F8
47uF
20V
R398
VOUTS2_1P2
E6
E7
1.2V
E8
E9
RUN_LTM4628
G9
G8
PG_1.8V
PG_1.5V
R403
R401
10K
10K
G2
D5
R400
30.1K
F11
F12
G1
G10
G12
H1
H2
H3
H4
H5
H6
H7
H9
H10
H11
H12
J1
J5
J8
J12
K1
K5
K6
G3
M12
M1
L12
L1
K12
K8
K7
A6
A7
B6
B7
D1
D2
D3
D4
D9
D10
D11
D12
E1
E2
E3
E4
E10
E11
E12
F1
F2
F3
F10
C7
F6
F7
G6
G7
D6
LTM4628
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SGND
SGND
SGND
SGND
SGND
SGND
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C892
22uF
6.3V
C862
22uF
6.3V
C850
22uF
6.3V
C863
100uF
6.3V
C893
R355
0.003
A5A_VCCPD_PGM_IO_2.5V
R354
0.003
A5B_VCCPD_PGM_IO_2.5V
R356
0.003
C58
0.1uF
1.2V
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
C12
C11
C10
C9
B12
B11
B10
B9
B8
A8
A9
A10
A11
A12
E
A5A_VCCR_VCCL_GXB
C799
22uF
4V
C801
22uF
4V
C800
22uF
4V
C864
100uF
6.3V
C895
D
A5A_VCCT_GXB
470uF
6.3V
L6
3A, 30 Ohm FB
C730
0.1uF
A5B_VCCR_VCCL_GXB
G11
D7
G5
F8
R402
40.2K
12V
1.8V
VOUTS2_1P5
C931
E6
E7
47uF
20V
1.5V
C941
C940
C942
C939
10uF
35V
10uF
35V
10uF
35V
10uF
35V
E8
E9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U26B
F11
F12
G1
G10
G12
H1
H2
H3
H4
H5
H6
H7
H9
H10
H11
H12
J1
J5
J8
J12
K1
K5
K6
G3
M12
M1
L12
L1
K12
K8
K7
J9
J10
J11
K2
K3
K4
K9
K10
K11
M2
M3
M4
L8
L7
L6
L5
L4
L3
L2
M11
M10
M9
M8
M7
M6
M5
J4
J3
J2
L11
L10
L9
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C804
22uF
4V
C803
22uF
4V
C802
22uF
4V
C865
100uF
6.3V
C12
C11
C10
C9
B12
B11
B10
B9
B8
A8
A9
A10
A11
A12
R357
A5_VCCIO_1.8V
0.003
C
C761
0.1uF
C896
470uF
6.3V
L15
3A, 30 Ohm FB
R385
0.003
A5A_VCCIO_1.5V
C731
0.1uF
R366
0.003
1.5V
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
R358
0.003
A5B_VCCT_GXB
A5B_VCCIO_1.5V
B
C762
22uF
4V
C805
22uF
4V
C732
22uF
4V
C866
100uF
6.3V
C897
470uF
6.3V
LTM4628
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
LTM4628
7
A5B_VCCA_2.5V
470uF
6.3V
B
Date:
8
R229
0.003
LTM4628
U26C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A5A_VCCA_2.5V
2.5V
LTM4628
U27C
U27B
J9
J10
J11
K2
K3
K4
K9
K10
K11
M2
M3
M4
L8
L7
L6
L5
L4
L3
L2
M11
M10
M9
M8
M7
M6
M5
J4
J3
J2
L11
L10
L9
R397
19.1K
1.8V
PGOOD1
PGOOD2
R230
0.003
3A, 30 Ohm FB
12V
D5
0
VOUTS1
VOUTS2
VCCA_25V
1
L5
G2
U26A
5.0V
2
10K
DNI
LTM4628
D
3
Power 3 - 2.5V, 1.2V, 1.8V and 1.5V
C934
TEMP
4
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
40
of
1
46
8
7
6
5
4
3
2
1
Power 3 - 3.3V_ATX and FMC Variable
PHASE0
27
12V_ATX_IN
J4
5
4
6
3.3V_ATX
U20B
8
7
6
5
12V ATX INPUT
Q10
Si7463DP
U10
VIN
GND
CTL
R29
1
2
3
4
LTC4412
1
2
3
C37
0.1uF
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
12V_ATX
12V_PCIE_ATX
E
6
5
4
SENSE
GATE
STAT
R35
680.0K
LTC4412
0
D
12V
8
7
6
5
12V INPUT
Q11
Si7463DP
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
F8
F9
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
H12
U20A
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
LTM4601
1
2
3
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
E
1
12V
SENSE
12V GND
12V GND
+
C646
100uF
C645
100uF
2
1
2
3
C45
470uF
10V
Tantalum
100uF
16V
1
3
5
12V
R323
R338
DNI
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
B4
B5
B6
C1
C2
C3
C4
C5
C6
C51
C675
220uF
16V
22uF
B2
D41
20V Zener
3.3V_ATX
12V_ATX
100K
U20D
1000pFPHASE0
C727 0.01uF
R336
787K
A
R313
1.00k
C647
A8
A9
A11
A12
C12
D12
PLLIN
TRACK/SS
COMP
MPGM
MARG0
MARG1
VOSNS+
FSET
VOSNS-
G12
F12
J12
B12
M12
3.3V_ATX
R337
C599
1000pF
DNI
C677
C649
100uF
10uF
10uF
H2
D4
D5
D6
D7
E3
E4
E5
E6
E7
H4
H3
H1
M7
F7
G5
G6
G7
H5
H6
100pF
R320
C57
C5
B6
A6
A7
A5
B5
B7
C6
C7
C3
C2
B4
B3
3.3V_ATX
K12
L12
B1
A3
12V
B
DIFFVOUT
VOUT_LCL
A2
K6
C1
C4
LTM4601
C728
31.6K
10.0K
C676
0.1uF
U20C
PGOOD
VFB
13.3K
C729
1000pF
LTM4601
RUN
INTVCC
PGOOD
VFB
NC
FREQ
TK/SS
MODE/PLLIN
SW
COMP
EXTVCC
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
SGND
SGND
SGND
SGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
D2
2
4
6
R58
R57
R56
D1
R321
69.8K
A1
C551
100pF
C552
L1
L2
L3
L4
M1
M2
M3
M4
K4
K3
K2
K1
J4
J3
J2
J1
A5_VAR
100pF
C648
100uF
6.3V
F6
F5
A4
K7
L7
F3
F4
G1
G2
G3
G4
F2
F1
E2
E1
M6
M5
L6
L5
K5
J7
J6
J5
H7
C600
100uF
6.3V
C515
6
5
4
A5_VCCIO_FMC
C
R38
0.003
470uF
6.3V
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
7
158.0K
48.7K
26.7K
2x3_2mm
LTM4618
8
D
U17
12V_ATX
RUN
INTVCC
DRVCC
VCCIO FMC SELECT
Setting
1.5V
NO JUMPER
JUMPER 1-2 1.8V
JUMPER 3-4 2.5V
JUMPER 5-6 3.3V
XJ2
2mm Shunt
D3
A10
A7
E12
10uF
J11
R324
R335
10uF
LTM4601
4
A1
A2
A3
A4
A5
A6
B1
B2
B3
C598
FMC Voltage
C596
C
C597
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
41
of
1
46
8
7
6
5
4
3
2
1
Power 4 - Linear Regulators
1.5V
E
E
C907
DDR3 DEVICE A VTT, VREF
12V
5.0V
10uF
3.3V
C118
R109
15
10.0K
10uF
11
12
10
5
17
D
VIN1
VIN1
VOUT1
VOUT1
SHDN1
BYP1
ADJ1
VIN2
VIN2
NC
SHDN2
VOUT2
VOUT2
GND
EP_GND
BYP2
ADJ2
3
4
C93
C96
0.01uF
R84
R85
1
16
R394
10.0K
10uF
11.3K
3.65K
5.37V_MONITOR
6
7
VIN
EN
PGOOD
VREF_DDR3A
C906
2
10
7
9
6
1uF
REFOUT
C905
TPS51200
C92
C102
0.01uF
R83
R108
8
9
0.1uF
VLDOIN
REFIN
GND_PAD
PGND
GND
13
14
U54
2
1
10.0K
R372
VTT_DDR3A
VO
VOSNS
R359
10.0K
C857
3
5
11
4
8
U32
10uF
C831
C52
C48
C59
C44
10uF
10uF
10uF
10uF
10uF
C832
1.0nF
10uF
10.2K
3.01K
D
LT3029EDE
1.5V
1.8V
5.0V
U43
4
2.5V
6
100K
SHDN
C229
10uF
3
11
C
C230
1uF
1.5V_VCCD_PLL
C308
DDR3 DEVICE B/C VTT, VREF
10
9
OUT2
OUT1
SW
GND
GND
R17
5
BST
8
7
ADJ
PG
A5A_VCCD_PLL_1.5V
R210
R18
VCCD_PLL_PG
R20
U47
2.74K
A5B_VCCD_PLL_1.5V
4.7K
R209
R19
1.00k
LTC3026
10uF
3.3V
.009
.009
C25
R231
10.0K
VIN
EN
PGOOD
VREF_DDR3B
C255
10uF
10
7
9
6
1uF
REFOUT
C256
TPS51200
5.0V
0.1uF
VLDOIN
REFIN
GND_PAD
PGND
GND
IN1
IN2
11
4
8
1
2
2
1
10.0K
R260
VTT_DDR3B
VO
VOSNS
R248
10.0K
C254
3
5
10uF
C570
C494
C349
C745
C701
10uF
10uF
10uF
10uF
10uF
C307
C
1.0nF
C546
ENET_DVDD
U15
1uF
1
3.3V
3
C547
10uF
6
ENET_DVDD = 1.0V/0.253A
BIAS
OUT
IN
ADJ
SHDN
GND
EP_GND
4
QDRII+ VREF
5
2
7
R308
15.0K
VREF_QDRII
R307
C47
C593
22uF
2.2uF
R251
100, 1%
LTC3025-1
10.0K
B
1.8V
C326
R245
100, 1%
B
47nF
A
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
42
of
1
46
8
7
6
5
4
3
2
1
Power 6 - Power Monitor
5.37V_MONITOR
V9
SENSE_PAD
A5A_VCCPD_PGM_IO_2.5V V48
1
RSNS SNS
SENSE_PAD
V45
1
RSNS SNS
A5A_VCCA_2.5V
2
2
V46 SENSE_PAD
1
2
RSNS SNS
VCCA_25V
A5A_VCCR_VCCL_GXB
SENSE_PAD
V49
1
RSNS SNS
SENSE_PAD
V51
1
RSNS SNS
A5_VCCIO_1.8V
2
SENSE_PAD
V60
1
RSNS SNS
A5A_VCCIO_1.5V
C
A5A_VCCD_PLL_1.5V
SENSE_PAD
V42
1
RSNS SNS
A5A_VCCPD_PGM_N
A5A_VCCPD_PGM_P
A5A_VCCPD_PGM_N
25
26
A5A_VCCINT_P
A5A_VCCINT_N
27
28
REF+
1
2
A5A_VCCD_PLL_1.5V_P
A5A_VCCD_PLL_1.5V_N
3
4
A5A_XCVR_GXB_P
A5A_VCCIO_1.8V_P
A5A_VCCIO_1.8V_N
5
6
CH2
CH3
REF-
CH4
CH5
F0
CH8
CH9
9
R70
0
R82
0
SDO
SDI
SCK
CSn
12
R69
DNI
A5A_VCCIO_1.8V_P
COM
GND
17
20
18
16
REF-
CH2
CH3
F0
CH4
CH5
13
14
CH6
CH7
17
20
18
16
SENSE5_CS1n
SDO
SDI
SCK
CSn
2.5V
C109
C110
C108
0.1uF
1uF
0.1uF
CH12
CH13
13
14
15
5.0V
2.5V
NC1
NC2
CH14
CH15
GND
COM
U33
14
13
12
11
10
9
8
2.5V
R137
10.0K
21
22
A5B_XCVR_GXB_P
A5B_XCVR_GXB_N
23
24
A5B_VCCA_P
A5B_VCCA_N
25
26
A5B_VCCPD_PGM_P
A5B_VCCPD_PGM_N
27
28
A5B_VCCINT_P
A5B_VCCINT_N
1
2
A5B_VCCIO_1.5V_P
A5B_VCCIO_1.5V_N
3
4
A5B_VCCD_PLL_1.5V_P
A5B_VCCD_PLL_1.5V_N
5
6
A5B_VCCIO_FMC_P
A5B_VCCIO_FMC_N
D
7
8
10
LTC2418
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
TSENSE_FAN1_CNTL
CH8
CH9
CH10
CH11
15
12V
1
2
REF+
R64
DNI
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
SENSE5_CS0n
J14
CH0
CH1
R71
0
SENSE5_CS1n
A5A_VCCIO_1.5V_P
VCC
19
A5A_VCCIO_1.8V_N
2
9
19
CH12
CH13
NC1
NC2
U31
12
5.0V
CH14
CH15
E
C90
0.1uF
11
CH10
CH11
7
8
C91
10uF
11
R62
0
CH6
CH7
A5A_VCCA_P
A5A_VCCIO_1.5V_P
A5A_VCCIO_1.5V_N
VCC
C88
10uF
LTC2418
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
SENSE_CS1n
27
MAX3378
A5A_VCCIO_1.5V_N
C
22_23_2021
Q3
5.0V
OVERTEMP1
2
V41 SENSE_PAD
1
2
RSNS SNS
1.5V_VCCD_PLL
23
24
CH0
CH1
10
2
V59 SENSE_PAD
1
2
RSNS SNS
1.5V
A5A_VCCPD_PGM_P
A5A_VCCA_P
A5A_VCCA_N
A5A_XCVR_GXB_N
V56 SENSE_PAD
1
2
RSNS SNS
1.8V
21
22
A5A_VCCA_N
V54 SENSE_PAD
1
2
RSNS SNS
1.2V
A5A_XCVR_GXB_P
A5A_XCVR_GXB_N
A5A_VCCINT_N
V53 SENSE_PAD
1
2
RSNS SNS
2.5V
C95
0.1uF
U29
R63
SENSE_PAD
2
RSNS SNS
A5A_VCCINT_P
V8
1
D
2
10K
1.1V
5.0V
RSNS SNS
R67
R80
R68
R61
1
E
10K
10K
10K
10K
A5A_VCCINT
5.37V_MONITOR
A5A_VCCD_PLL_1.5V_P
B9
FDV305N
U30
27
SENSE5_CS0n
SENSE5_SDO
SENSE5_SDI
SENSE5_SCK
A5A_VCCD_PLL_1.5V_N
SENSE_PAD
2.5V
2.5V
R81
FAN_2pin_Conn
10.0K
14
13
12
11
10
9
8
VCC
IO VCC1
IO VCC2
IO VCC3
IO VCC4
NC2
/TS
VL
IO VL1
IO VL2
IO VL3
IO VL4
NC1
GND
1
2
3
4
5
6
7
SENSE_CS0n
SENSE_SDO
SENSE_SDI
SENSE_SCK
27
27
27
27
5.0V
2.5V
C97
C98
C100
1uF
0.1uF
0.1uF
MAX3378
A5_VCCIO_FMC
V37
1
A5B_VCCINT
V5
1
B
1.1V
J23
1
2
22_23_2021
Q16
2.5V
OVERTEMP2
B8
FDV305N
27
FAN_2pin_Conn
A
SENSE_PAD
V43
1
RSNS SNS
2
SENSE_PAD
V50
1
RSNS SNS
A5B_VCCPD_PGM_P
1.5V
1
A5B_VCCD_PLL_1.5V
A5B_VCCA_P
1.5V_VCCD_PLL
1
B
2
V57 SENSE_PAD
2
RSNS SNS
A5B_VCCIO_1.5V_P
A5B_VCCIO_1.5V_N
2
V40 SENSE_PAD
2
RSNS SNS
A5B_VCCD_PLL_1.5V_P
A5B_VCCD_PLL_1.5V_N
SENSE_PAD
A5B_VCCA_N
2
A5B_VCCIO_FMC_P
A5B_VCCIO_FMC_N
SENSE_PAD
V39
1
RSNS SNS
A5B_VCCPD_PGM_N
2
V38 SENSE_PAD
2
RSNS SNS
SENSE_PAD
V58
1
RSNS SNS
A5B_VCCIO_1.5V
V44 SENSE_PAD
1
2
RSNS SNS
A5B_VCCR_VCCL_GXB
1.2V
A5_VAR
A5B_VCCINT_N
V52 SENSE_PAD
1
2
RSNS SNS
A5B_VCCA_2.5V
VCCA_25V
A5B_VCCINT_P
1
SENSE_PAD
2
RSNS SNS
SENSE_PAD
A5B_VCCPD_PGM_IO_2.5V V47
1
RSNS SNS
TSENSE_FAN2_CNTL
2
V6
1
12V
RSNS SNS
2
RSNS SNS
Title
V55 SENSE_PAD
1
2
RSNS SNS
A5B_XCVR_GXB_N
Size
SENSE_PAD
B
Date:
8
7
6
5
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
A5B_XCVR_GXB_P
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
43
of
1
46
8
7
6
5
4
3
2
1
Decoupling - FPGA 1
A5A_VCCINT
A5A_VCCPD_PGM_IO_2.5V FPGA VCCD PLL, VCCPGM and VCCIO = 2.5V
E
C419
C759
C363
C543
C498
C467
C497
C726
C673
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF
100uF 22nF
C459 C463 C536 C535 C501 C755 C539 C408 C360 C717 C718 C747 C635 C636
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
E
22nF
C914
C361
C410
100uF
22nF
0.01uF
C638
C464
C460
100uF
22nF
22nF
C314
C719
C465
C753
0.1uF
0.22uF
0.47uF
C500
C580
C583
C579
C665
C663
22nF
47nF
0.1uF
0.22uF
0.47uF
2.2uF
47nF
C362 C538 C534 C504 C324 C634 C507 C666 C505 C584 C578 C664 C662 C637 C533 C277 C641 C888 C910 C571 C532 C323 C454 C466 C455
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
0.01uF
A5A_VCCP
C672 C724 C671 C642 C417 C418 C313 C885 C883 C884 C358 C838 C882 C889 C581 C582 C633 C506 C839 C746 C794 C537 C458 C359 C503 C462
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
C231 C887 C886 C592 C499 C414 C415 C416 C456 C409 C357 C356 C282 C413 C412 C411 C502 C457 C461 C725 C312 C758 C757 C541 C716
47nF
47nF
47nF
47nF
47nF
0.1uF 0.1uF 0.1uF 0.1uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.47uF 0.47uF 1uF
47nF
A5A_VCCT_GXB
VREF_QDRII
D
2.2uF
VREF_DDR3A
A5A_VCCA_2.5V
C790
C911
C784
C785
C316
C791
C890
C320
C586
C667
C591
C542
C721
C715
C575
C779
A5A_VCCD_PLL_1.5V
0.47uF
22nF
22nF
0.01uF
0.22uF
47nF
0.1uF
4.7uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2
22uF
C754
+
C661
1
47nF
C631
10uF
10V
Tantalum
+
1uF
2
0.01uF 0.01uF 0.01uF 0.01uF 47nF
1
D
C630
10uF
10V
Tantalum
C
C
A5A_VCCR_VCCL_GXB
C787 C793 C317 C795
C847
C283
C318
C278
C279
C280
C281
C322
C786
C315
C841
C284
C913
C912
C891
22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
47nF
47nF
100uF
100uF
100uF
100uF
22nF
22nF
22nF
C792
C789
C788
C840
C783
C782
C842
C861
C836
C319
C321
C264
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.22uF
0.47uF
1uF
A5_VCCIO_1.8V
C643
B
C848
4.7uF
A5A_VCCIO_1.5V
C640
C590
C669
C756
C722
C720
C588
C587
C589
C657
C778 C780
C781
C837
C713
C750
C576
C660
C748
C572
SCREW1
SCREW2
STANDOFF1
SPACER1
100uF 22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
100uF
22nF
22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
SCREW3
SCREW4
STANDOFF2
SPACER2
SCREW5
STANDOFF3
C670
C723
C846
C845
C844
C585
C639
C843
C668
C574
C573
C577
C712
C749
C658
C714
C659
C632
SCREW6
STANDOFF4
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
47nF
0.1uF
0.1uF
0.47uF
4.7nF
4.7nF
0.01uF
0.01uF
47nF
47nF
0.1uF
0.22uF
0.47uF
SCREW7
STANDOFF5
SCREW8
STANDOFF6
A
PCB1
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
44
of
1
46
8
7
6
5
4
3
2
1
Decoupling - FPGA 2
A5B_VCCINT
A5B_VCCP
E
C650
C601
C516
C336
C615
C49
C46
C569
C181 C383 C386 C443 C442 C440 C480 C483 C182 C341
22uF
22uF
100uF
100uF
100uF
100uF
100uF
100uF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C567
C560
C524
C566
C343
C441
22uF
22nF
22nF
47nF
0.1uF
0.47uF
22nF
E
C387
4.7uF
C482 C523 C522 C564 C565 C563 C561 C521 C520 C382 C384 C385 C180 C342 C179 C296 C295
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
22nF
A5B_VCCA_2.5V
1
C820 C337 C518 C553 C554 C288 C652 C185 C289 C338 C519 C678 C452 C568 C186 C562 C607
A5B_VCCD_PLL_1.5V
C293
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
C268
+
2
0.47uF
C437 C183 C184 C610 C611 C481 C651 C479 C517 C526 C525 C487 C486 C608 C609 C603 C602 C679 C680 C821
D
0.01uF 0.01uF 0.01uF 47nF
47nF
47nF
47nF
47nF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.22uF 0.22uF 0.47uF 0.47uF 0.47uF 1uF
1
22nF
C301
10uF
10V
Tantalum
+
1uF
2
22nF
22nF
C389
10uF
10V
Tantalum
2.2uF
D
A5B_VCCT_GXB
A5B_VCCIO_1.5V
A5B_VCCPD_PGM_IO_2.5V FPGA VCCD PLL, VCCPGM and VCCIO = 2.5V
C
C851
C684
C765
C763
C733
C685
C764
C236
C339
C484
C291
C485
C290
C292
C612
C613
100uF
22nF
0.01uF
47nF
0.1uF
0.1uF
0.47uF
100uF 22nF
22nF
0.01uF
0.01uF
47nF
0.1uF
0.47uF
0.47uF
C614
C388 C445
C448
C271
C346
C347
C345
C446
C449
C450
100uF
22nF
22nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
C220
C250
C300
C269
C270
C299
C272
C298
C451
4.7nF
4.7nF
0.01uF
0.01uF
47nF
47nF
0.1uF
0.22uF
0.47uF
C
A5B_VCCR_VCCL_GXB
C245 C218 C219 C215 C216 C237 C238
22nF
22nF
22nF
22nF
22nF
22nF
22nF
C687
C688
C689
C690
C741
C742
C692
C247
C739
C686
C267
C50
C807
C808
C691
C809
C195
C867
C854
C149
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
47nF
47nF
47nF
47nF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
100uF
100uF
100uF
100uF
C217
C244
C241
C243
C242
C239
C240
C246
C222
C818
C817
C815
C819
C682
C814
C196
C194
C248
C740
C683
C251
C221
C816
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
0.1uF
0.1uF
0.22uF
0.22uF
0.47uF
1uF
2.2uF
2.2uF
A5_VCCIO_FMC
B
FMC_VCCIO
C63
C558 C378
100uF 22nF
22nF
FMC_VCCPD
C438
C475
C380
C476
C653
C738
C736
C735
C557
C62
C606
C478
C381
C654
C605
C294
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
4.7nF
47nF
2.2uF
22nF
22nF
47nF
0.22uF
4.7uF
10uF
C734
C556
C473
C555
C806
C377
C737
C379
C474
C436
4.7nF
4.7nF
4.7nF
0.01uF
0.01uF
0.01uF
47nF
0.1uF
0.22uF
1uF
B
VREF_DDR3B
VREFA_FMC
A
VREFB_FMC
C249
C447
C297
C344
C559
C681
C439
C340
C477
C604
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
Title
Size
B
Date:
8
7
6
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
45
of
1
46
8
7
6
5
4
3
2
1
Power - Arria V GX Ground Power
U16O
U13O
U16M
U13M
U16N
Arria V GX Power
E
D
C
B
W39
H23
H26
H29
H32
H36
H37
H5
H8
J3
J35
J38
J39
J4
K1
K2
K36
K37
K5
L11
L14
L17
L20
L23
L26
L29
L3
L32
L35
L38
L39
L4
L8
M1
M2
M36
M37
M5
N3
N35
N38
N39
N4
N5
N8
P1
P11
P14
P17
P2
P20
P23
P26
P29
P32
P36
P37
P6
P7
R3
Y10
Y12
Y14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5AGXB3H4F40
Version = 1.86 Pin-out
U13N
Arria V GX Power
R34
R38
R39
R4
R8
T1
T10
T2
T32
T36
T37
T5
T7
U11
U13
U15
U17
U20
U23
U25
U27
U3
U30
U33
U35
U38
U39
U4
U6
U8
V1
V10
V12
V14
V16
V18
V2
V21
V24
V26
V28
V30
V32
V34
V36
V37
V7
W11
W13
W15
W17
W19
W21
W23
W25
W27
W29
W3
W33
W38
W4
W8
Y1
AM1
AM11
AM14
AM17
AM2
AM20
AM23
AM26
AM29
AM32
AM36
AM37
AM5
AM8
AN3
AN35
AN38
AN39
AN4
AP1
AP2
AP36
AP37
AP5
AR11
AR14
AR17
AR20
AR23
AR26
AR29
AR3
AR32
AR35
AR38
AR39
AR4
AR8
AT1
AT2
AT36
AT37
AT5
AU3
AU35
AU38
AU39
AU4
AV1
AV11
AV14
AV17
AV2
AV20
AV23
AV26
AV29
AV32
AV35
AV36
Y16
Y2
Y20
Y24
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Arria V GX Power
AV37
AV38
AV39
AV5
AV8
AW35
AW38
B1
B11
B14
B17
B2
B20
B23
B26
B29
B32
B36
B37
B5
B8
C3
C35
C38
C39
C4
D1
D2
D36
D37
D5
E11
E14
E17
E20
E23
E26
E29
E3
E32
E35
E38
E39
E4
E8
F1
F2
F36
F37
F5
G3
G35
G38
G39
G4
H1
H11
H14
H17
H2
H20
Y18
Y22
Y26
N6
P35
A2
A3
A4
A5
AA11
AA13
AA15
AA17
AA19
AA23
AA3
AA30
AA33
AA35
AA38
AA39
AA4
AA6
AA8
AB1
AB10
AB2
AB31
AB32
AB34
AB36
AB37
AB7
AC11
AC14
AC17
AC20
AC23
AC26
AC28
AC3
AC33
AC38
AC39
AC4
AC8
AD1
AD10
AD2
AD30
AD32
AD36
AD37
AD5
AD7
AE3
AE30
AE33
AE35
AE38
AE39
AE4
AE6
Y28
Y31
Y32
Y36
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Arria V GX Power
AE8
AF1
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF29
AF30
AF31
AF32
AF34
AF36
AF37
AF9
AG3
AG31
AG38
AG39
AG4
AG5
AG6
AG7
AG8
AG9
AH1
AH2
AH32
AH33
AH34
AH35
AH36
AH37
AH5
AJ11
AJ14
AJ17
AJ20
AJ23
AJ26
AJ29
AJ3
AJ32
AJ35
AJ38
AJ39
AJ4
AJ8
AK1
AK2
AK36
AK37
AK5
AL3
AL35
AL38
AL39
AL4
Y7
Y5
Y37
U16S
Arria V GX Power
AV3
AW3
A38
B38
AE20
AH31
C5
P21
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
5AGXB3H4F40
Version = 1.86 Pin-out
U13S
Arria V GX Power
AV3
AW3
A38
B38
AE20
AH31
C5
P21
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
5AGXB3H4F40
Version = 1.86 Pin-out
W39
H23
H26
H29
H32
H36
H37
H5
H8
J3
J35
J38
J39
J4
K1
K2
K36
K37
K5
L11
L14
L17
L20
L23
L26
L29
L3
L32
L35
L38
L39
L4
L8
M1
M2
M36
M37
M5
N3
N35
N38
N39
N4
N5
N8
P1
P11
P14
P17
P2
P20
P23
P26
P29
P32
P36
P37
P6
P7
R3
Y10
Y12
Y14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Arria V GX Power
R34
R38
R39
R4
R8
T1
T10
T2
T32
T36
T37
T5
T7
U11
U13
U15
U17
U20
U23
U25
U27
U3
U30
U33
U35
U38
U39
U4
U6
U8
V1
V10
V12
V14
V16
V18
V2
V21
V24
V26
V28
V30
V32
V34
V36
V37
V7
W11
W13
W15
W17
W19
W21
W23
W25
W27
W29
W3
W33
W38
W4
W8
Y1
AM1
AM11
AM14
AM17
AM2
AM20
AM23
AM26
AM29
AM32
AM36
AM37
AM5
AM8
AN3
AN35
AN38
AN39
AN4
AP1
AP2
AP36
AP37
AP5
AR11
AR14
AR17
AR20
AR23
AR26
AR29
AR3
AR32
AR35
AR38
AR39
AR4
AR8
AT1
AT2
AT36
AT37
AT5
AU3
AU35
AU38
AU39
AU4
AV1
AV11
AV14
AV17
AV2
AV20
AV23
AV26
AV29
AV32
AV35
AV36
Y16
Y2
Y20
Y24
5AGXB3H4F40
5AGXB3H4F40
5AGXB3H4F40
Version = 1.86 Pin-out
Version = 1.86 Pin-out
Version = 1.86 Pin-out
A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Arria V GX Power
AV37
AV38
AV39
AV5
AV8
AW35
AW38
B1
B11
B14
B17
B2
B20
B23
B26
B29
B32
B36
B37
B5
B8
C3
C35
C38
C39
C4
D1
D2
D36
D37
D5
E11
E14
E17
E20
E23
E26
E29
E3
E32
E35
E38
E39
E4
E8
F1
F2
F36
F37
F5
G3
G35
G38
G39
G4
H1
H11
H14
H17
H2
H20
Y18
Y22
Y26
N6
P35
A2
A3
A4
A5
AA11
AA13
AA15
AA17
AA19
AA23
AA3
AA30
AA33
AA35
AA38
AA39
AA4
AA6
AA8
AB1
AB10
AB2
AB31
AB32
AB34
AB36
AB37
AB7
AC11
AC14
AC17
AC20
AC23
AC26
AC28
AC3
AC33
AC38
AC39
AC4
AC8
AD1
AD10
AD2
AD30
AD32
AD36
AD37
AD5
AD7
AE3
AE30
AE33
AE35
AE38
AE39
AE4
AE6
Y28
Y31
Y32
Y36
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5AGXB3H4F40
5AGXB3H4F40
Version = 1.86 Pin-out
Version = 1.86 Pin-out
E
AE8
AF1
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF29
AF30
AF31
AF32
AF34
AF36
AF37
AF9
AG3
AG31
AG38
AG39
AG4
AG5
AG6
AG7
AG8
AG9
AH1
AH2
AH32
AH33
AH34
AH35
AH36
AH37
AH5
AJ11
AJ14
AJ17
AJ20
AJ23
AJ26
AJ29
AJ3
AJ32
AJ35
AJ38
AJ39
AJ4
AJ8
AK1
AK2
AK36
AK37
AK5
AL3
AL35
AL38
AL39
AL4
Y7
Y5
Y37
D
C
B
A
Altera Corporation, 9330 Scranton Rd #400, San Diego, CA 92121
Title
Size
B
Date:
8
7
6
5
4
3
Arria V GX FPGA Development Kit Board
Copyright (c) 2012, Altera Corporation. All Rights Reserved.
Document Number
150-0320804-B1
Tuesday, July 31, 2012
2
Rev
B
(6XX-44096R)
Sheet
46
of
1
46
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