DN309 - 3A, 2MHz Monolithic Synchronous Step-Down Regulator Provides a Compact Solution for DDR Memory Termination

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3A, 2MHz Monolithic Synchronous Step-Down Regulator Provides
a Compact Solution for DDR Memory Termination – Design Note 309
Joey M. Esteves
Introduction
The LTC ®3413 is a monolithic synchronous, step-down
switching regulator that is capable of generating a bus
termination voltage for DDR/DDR2 memory applications. While sourcing and sinking up to 3A of current,
the LTC3413 allows switching frequencies as high as
2MHz. Increasing the switching frequency makes compact solutions possible by allowing the use of smaller
inductors and capacitors. The internal power switches
have a mere 85mΩ of on-resistance making it possible
to achieve efficiencies as high as 90% while generating
an output voltage as low as 0.6V. For improved thermal
handling, the LTC3413 is offered in a 16-Lead TSSOP
package with an exposed pad.
The LTC3413 utilizes a constant frequency, current
mode architecture that operates from an input voltage
range of 2.25V to 5.5V and provides a regulated output
voltage equal to VREF/2. The switching frequency can
be set between 300kHz to 2MHz by a single external
VIN
2.5V
1
PGOOD
RITH
5.11k
CITH
CC
2200pF 100pF
X7R
2
3
RSS
4.7M
CSS
330pF X7R
PGOOD
SW
ITH
SW
VFB
PGND
CIN1**
100μF
16
L, LT, LTC, LTM, Linear Technology, the Linear logo and OPTI-LOOP are registered
trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
15
14
100
4
13
L1*
0.47μH
6
7
8
RT
VREF
RUN/SS
SGND
PGND
SW
SW
PVIN
12
11
COUT**
100μF
w2
10
VIN = 2.5V
f = 1MHz
80
70
60
50
40
30
20
9
GND
CIN2**
100μF
DN309 F01
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
Figure 1. 2.5V to 1.25V, ±3A DDR Memory
Termination Supply
04/03/309_conv
90
VOUT
1.25V
±3A
LTC3413
5
ROSC
309k
PVIN
3A, 2.5V to 1.25V Step-Down DC/DC Converter
Figure 1 illustrates a design solution for a 2.5V to 1.25V
step-down DC/DC converter that is capable of sourcing
and sinking up to 3A of output current. Efficiency for this
circuit is as high as 90% as shown in Figure 2. Because
of their low cost and low ESR, ceramic capacitors were
selected for the input and output capacitors. Although
many switching regulators have difficulty operating
with ceramic capacitors and rely on the zero that is
generated by the larger ESR of tantalum capacitors,
OPTI-LOOP® compensation allows the LTC3413 to
operate successfully with ceramic input and output
capacitors. The frequency for this circuit is set at 1MHz
EFFICIENCY (%)
RPG
100k
SVIN
resistor. Output voltage ripple is inversely proportional
to the switching frequency and the inductor value.
Having the ability to increase the switching frequency
as high as 2MHz allows lower inductor values to be
used while still maintaining low output voltage ripple.
Because smaller case sizes are usually offered for lower
inductor values, the overall solution footprint can be
reduced. An internal voltage divider halves the reference
voltage, eliminating the need for external resistors to
perform this task.
10
0
0.01
0.1
1
LOAD CURRENT (A)
10
DN309 F02
Figure 2. Efficiency vs Load Current, VIN = 2.5V
by a single external resistor. Operating at frequencies
this high allows the use of smaller external components
such as the inductor and capacitors shown in Figure 1.
Many DDR termination applications require the bus
termination voltage to be stepped down from a higher
system voltage while tracking one-half of a reference
voltage. This option is allowable in most systems since
a reference voltage is typically available. Figure 3 shows
a design solution for a 3.3V to 1.25V, ±3A DDR memory
termination supply with a 2.5V external reference.
VIN
3.3V
RPG
100k
PGOOD
RITH
5.11k
CITH
CC
2200pF 100pF
X7R
2
3
4
6
2.5V
RSS
4.7M
7
CSS
330pF X7R
PVIN
PGOOD
SW
ITH
SW
VFB
PGND
CIN1**
100μF
16
15
100
90
14
8
RT
VREF
RUN/SS
SGND
PGND
SW
SW
PVIN
VIN = 3.3V
f = 1MHz
80
13
L1*
0.47μH
VOUT
1.25V
±3A
LTC3413
5
ROSC
309k
SVIN
Conclusion
The LTC3413 is a monolithic, synchronous step-down
DC/DC converter that is well suited for DDR memory
termination applications requiring up to ±3A of output
current. Its high switching frequency and internal low
RDS(ON) power switches allow the LTC3413 to offer
compact, high efficiency design solutions.
12
11
EFFICIENCY (%)
1
Efficiency for this circuit is as high as 90% as shown in
Figure 4. Figure 5 shows another design solution for a
3.3V to 0.9V, ±3A termination supply with a 1.8V external
reference. Stepping down from a higher system voltage
has the advantage of reducing the resistive losses due to
the internal power switches, thus improving efficiency.
COUT**
100μF
w2
70
60
50
40
30
20
10
10
0
0.01
9
0.1
1
LOAD CURRENT (A)
GND
CIN2**
100μF
10
DN309 F04
DN309 F03
Figure 4. Efficiency vs Load Current, VIN = 3.3V
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
Figure 3. 1.25V, ±3A DDR Memory Termination
Supply from 3.3V
VIN
3.3V
1
RPG
100k
PGOOD
RITH
10k
CITH
CC
2200pF 100pF
X7R
2
3
4
ROSC
309k
6
RSS
4.7M
7
CSS
330pF X7R
PVIN
PGOOD
SW
ITH
SW
VFB
PGND
CIN1**
100μF
16
*VISHAY DALE IHLP-2525CZ-01 0.47μH
**TDK C4532X5R0J107M
†TAIYO YUDEN JMK325BJ226MM
†† SANYO POSCAP 4TPD470M
15
14
13
L1*
0.47μH
VOUT
0.9V
±3A
LTC3413
5
1.8V
SVIN
8
RT
VREF
RUN/SS
SGND
PGND
SW
SW
PVIN
12
COUT†
22μF
11
+
10
COUT††
470μF
9
GND
CIN2**
100μF
DN309 F05
Figure 5. 0.9V, ±3A HSTL Memory Termination Supply
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