PSoC 4 TRM PSoC 4100/4200 Family PSoC® 4 Architecture TRM (Technical Reference Manual) Document No. 001-85634 Rev. *D December 4, 2015 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights License © 2013-2015, Cypress Semiconductor Corporation. All rights reserved. This software, and associated documentation or materials (Materials) belong to Cypress Semiconductor Corporation (Cypress) and may be protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Unless otherwise specified in a separate license agreement between you and Cypress, you agree to treat Materials like any other copyrighted item. You agree to treat Materials as confidential and will not disclose or use Materials without written authorization by Cypress. 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Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Flash Code Protection Cypress products meet the specifications contained in their particular Cypress Datasheets. Cypress believes that its family of PSoC products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Contents Overview Section A: Overview 15 1. Introduction ........................................................................................................... 17 2. Getting Started ...................................................................................................... 23 3. Document Construction ......................................................................................... 25 Section B: CPU System 29 4. Cortex-M0 CPU ..................................................................................................... 31 5. Interrupts .............................................................................................................. 37 Section C: Memory System 6. 47 Memory Map ......................................................................................................... 49 Section D: System-Wide Resources 51 7. I/O System ............................................................................................................ 53 8. Clocking System .................................................................................................... 63 9. Power Supply and Monitoring ................................................................................ 71 10. Chip Operational Modes ........................................................................................ 77 11. Power Modes ........................................................................................................ 79 12. Watchdog Timer .................................................................................................... 85 13. Reset System ........................................................................................................ 89 14. Device Security ..................................................................................................... 93 Section E: Digital System 95 15. Serial Communications Block (SCB) ...................................................................... 97 16. Universal Digital Blocks (UDB) ............................................................................. 131 17. Timer, Counter, and PWM .................................................................................... 171 Section F: Analog System 195 18. Precision Reference ............................................................................................ 197 19. SAR ADC ............................................................................................................ 201 20. Low-Power Comparator ....................................................................................... 229 21. Continuous Time Block mini (CTBm) .................................................................... 235 22. LCD Direct Drive ................................................................................................. 243 23. CapSense ........................................................................................................... 255 24. Temperature Sensor ............................................................................................ 265 Section G: Program and Debug PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 269 3 Contents Overview 25. Program and Debug Interface .............................................................................. 271 26. Nonvolatile Memory Programming ....................................................................... 279 Glossary 293 Index 309 4 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Contents Section A: Overview 15 Document Revision History ..............................................................................................................15 1. Introduction 17 1.1 1.2 1.3 Top Level Architecture............................................................................................................17 Features..................................................................................................................................19 CPU System ...........................................................................................................................19 1.3.1 Processor...............................................................................................................19 1.3.2 Interrupt Controller .................................................................................................20 1.4 Memory...................................................................................................................................20 1.4.1 Flash ......................................................................................................................20 1.4.2 SRAM.....................................................................................................................20 1.5 System-Wide Resources ........................................................................................................20 1.5.1 Clocking System ....................................................................................................20 1.5.2 Power System........................................................................................................20 1.5.3 GPIO ......................................................................................................................20 1.6 Programmable Digital .............................................................................................................20 1.7 Fixed-Function Digital .............................................................................................................20 1.7.1 Timer/Counter/PWM Block.....................................................................................20 1.7.2 Serial Communication Blocks ................................................................................20 1.8 Analog System........................................................................................................................21 1.8.1 SAR ADC ...............................................................................................................21 1.8.2 Continuous Time Block mini (CTBm) .....................................................................21 1.8.3 Low-Power Comparators .......................................................................................21 1.9 Special Function Peripherals ..................................................................................................21 1.9.1 LCD Segment Drive ...............................................................................................21 1.9.2 CapSense ..............................................................................................................21 1.9.2.1 IDACs and Comparator ..........................................................................21 1.10 Program and Debug ...............................................................................................................21 1.11 Device Feature Summary .......................................................................................................21 2. Getting Started 2.1 2.2 2.3 2.4 3. Support ...................................................................................................................................23 Product Upgrades...................................................................................................................23 Development Kits....................................................................................................................23 Application Notes....................................................................................................................23 Document Construction 3.1 3.2 23 25 Major Sections ........................................................................................................................25 Documentation Conventions...................................................................................................25 3.2.1 Register Conventions.............................................................................................25 3.2.2 Numeric Naming ....................................................................................................25 3.2.3 Units of Measure....................................................................................................26 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 5 3.2.4 Acronyms............................................................................................................... 26 Section B: CPU System 29 Top Level Architecture ..................................................................................................................... 29 4. Cortex-M0 CPU 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5. 31 Features ................................................................................................................................. 31 Block Diagram ........................................................................................................................ 32 How It Works .......................................................................................................................... 32 Address Map .......................................................................................................................... 32 Registers ................................................................................................................................ 33 Operating Modes .................................................................................................................... 34 Instruction Set......................................................................................................................... 34 4.7.1 Address Alignment ................................................................................................ 35 4.7.2 Memory Endianness ..............................................................................................35 Systick Timer .......................................................................................................................... 35 Debug ..................................................................................................................................... 35 Interrupts 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 37 Features ................................................................................................................................. 37 How It Works .......................................................................................................................... 37 Interrupts and Exceptions - Operation.................................................................................... 38 5.3.1 Interrupt/Exception Handling in PSoC 4 ................................................................ 38 5.3.2 Level and Pulse Interrupts ..................................................................................... 38 5.3.3 Exception Vector Table .......................................................................................... 39 Exception Sources.................................................................................................................. 39 5.4.1 Reset Exception .................................................................................................... 39 5.4.2 Non-Maskable Interrupt (NMI) Exception .............................................................. 40 5.4.3 HardFault Exception ..............................................................................................40 5.4.4 Supervisor Call (SVCall) Exception ....................................................................... 40 5.4.5 PendSV Exception................................................................................................. 40 5.4.6 SysTick Exception ................................................................................................. 40 Interrupt Sources .................................................................................................................... 41 Exception Priority.................................................................................................................... 42 Enabling and Disabling Interrupts...........................................................................................42 Exception States..................................................................................................................... 43 5.8.1 Pending Exceptions ............................................................................................... 43 Stack Usage for Exceptions ................................................................................................... 44 Interrupts and Low-Power Modes........................................................................................... 44 Exception - Initialization and Configuration ............................................................................ 45 Registers ................................................................................................................................ 45 Associated Documents...........................................................................................................45 Section C: Memory System 47 Top Level Architecture ..................................................................................................................... 47 6. Memory Map 6.1 6.2 49 Features ................................................................................................................................. 49 How It Works .......................................................................................................................... 49 Section D: System-Wide Resources 51 Top Level Architecture ..................................................................................................................... 51 6 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 7. I/O System 53 7.1 7.2 7.3 Features..................................................................................................................................53 GPIO Interface Overview........................................................................................................53 I/O Cell Architecture................................................................................................................54 7.3.1 Digital Input Buffer .................................................................................................55 7.3.2 Digital Output Driver...............................................................................................55 7.3.2.1 Drive Modes ...........................................................................................55 7.3.2.2 Slew Rate Control ..................................................................................56 7.4 High-Speed I/O Matrix ...........................................................................................................57 7.5 I/O State on Power Up............................................................................................................57 7.6 Behavior in Low-Power Modes ...............................................................................................58 7.7 Input and Output Synchronization ..........................................................................................58 7.8 Interrupt ..................................................................................................................................58 7.9 Peripheral Connections ..........................................................................................................60 7.9.1 Firmware Controlled GPIO.....................................................................................60 7.9.2 Analog I/O ..............................................................................................................60 7.9.2.1 AMUXBUS Connection and DSI ............................................................60 7.9.3 LCD Drive ..............................................................................................................60 7.9.4 CapSense ..............................................................................................................60 7.9.5 Serial Communication Block (SCB) .......................................................................61 7.10 Port Restrictions .....................................................................................................................61 7.11 Registers.................................................................................................................................61 8. Clocking System 8.1 8.2 8.3 8.4 8.5 9. Block Diagram ........................................................................................................................63 Clock Sources.........................................................................................................................64 8.2.1 Internal Main Oscillator ..........................................................................................64 8.2.1.1 Startup Behavior.....................................................................................65 8.2.1.2 IMO Frequency Spread ..........................................................................65 8.2.1.3 Programming Clock (36-MHz)................................................................65 8.2.2 Internal Low-speed Oscillator ................................................................................65 8.2.3 External Clock (EXTCLK) ......................................................................................65 Clock Distribution....................................................................................................................66 8.3.1 HFCLK Input Selection ..........................................................................................66 8.3.2 SYSCLK Prescaler Configuration ..........................................................................66 8.3.3 Peripheral Clock Divider Configuration ..................................................................66 8.3.4 Peripheral Clock Configuration ..............................................................................67 Low-Power Mode Operation ...................................................................................................69 Register List............................................................................................................................69 Power Supply and Monitoring 9.1 9.2 9.3 9.4 63 71 Block Diagram ........................................................................................................................72 Power Supply Scenarios.........................................................................................................73 9.2.1 Single 1.8 V to 5.5 V Unregulated Supply..............................................................73 9.2.2 Direct 1.71 V to 1.89 V Regulated Supply .............................................................74 How It Works ..........................................................................................................................75 9.3.1 Regulator Summary ...............................................................................................75 9.3.1.1 Active Digital Regulator ..........................................................................75 9.3.1.2 Quiet Regulator ......................................................................................75 9.3.1.3 Deep-Sleep Regulator............................................................................75 9.3.1.4 Hibernate Regulator ...............................................................................76 Voltage Monitoring..................................................................................................................76 9.4.1 Power-On-Reset (POR) .........................................................................................76 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 7 9.5 9.4.1.1 Brownout-Detect (BOD) ......................................................................... 76 9.4.1.2 Low-Voltage-Detect (LVD) ..................................................................... 76 Register List ........................................................................................................................... 76 10. Chip Operational Modes 10.1 10.2 10.3 10.4 Boot ........................................................................................................................................ 77 User ........................................................................................................................................ 77 Privileged................................................................................................................................ 77 Debug ..................................................................................................................................... 77 11. Power Modes 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 77 79 Active Mode............................................................................................................................ 80 Sleep Mode ............................................................................................................................ 80 Deep-Sleep Mode................................................................................................................... 80 Hibernate Mode ...................................................................................................................... 81 Stop Mode .............................................................................................................................. 81 Power Mode Summary ...........................................................................................................81 Low-Power Mode Entry and Exit ............................................................................................ 83 Register List............................................................................................................................ 84 12. Watchdog Timer 85 12.1 Features ................................................................................................................................. 85 12.2 Block Diagram ........................................................................................................................ 85 12.3 How It Works .......................................................................................................................... 86 12.3.1 Enabling and Disabling WDT................................................................................. 87 12.3.2 WDT Operating Modes ......................................................................................... 87 12.3.3 WDT Interrupts and Low-Power Modes.................................................................88 12.3.4 WDT Reset Mode .................................................................................................. 88 12.4 Register List ........................................................................................................................... 88 13. Reset System 89 13.1 Reset Sources ........................................................................................................................ 89 13.1.1 Power-on Reset ..................................................................................................... 89 13.1.2 Brownout Reset ..................................................................................................... 89 13.1.3 Watchdog Reset .................................................................................................... 89 13.1.4 Software Initiated Reset......................................................................................... 90 13.1.5 External Reset ....................................................................................................... 90 13.1.6 Protection Fault Reset ........................................................................................... 90 13.1.7 Hibernate Wakeup Reset....................................................................................... 90 13.1.8 Stop Wakeup Reset ............................................................................................... 90 13.2 Identifying Reset Sources....................................................................................................... 90 13.3 Register List............................................................................................................................ 91 14. Device Security 93 14.1 Features ................................................................................................................................. 93 14.2 How It Works .......................................................................................................................... 93 14.2.1 Device Security...................................................................................................... 93 14.2.2 Flash Security ........................................................................................................ 94 Section E: Digital System 95 Top Level Architecture ..................................................................................................................... 95 15. Serial Communications Block (SCB) 97 15.1 Features ................................................................................................................................. 97 8 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 15.2 Serial Peripheral Interface (SPI) .............................................................................................97 15.2.1 Features.................................................................................................................97 15.2.2 General Description ...............................................................................................98 15.2.3 SPI Modes of Operation.........................................................................................98 15.2.3.1 Motorola SPI...........................................................................................98 15.2.3.2 Texas Instruments SPI .........................................................................100 15.2.3.3 National Semiconductors SPI...............................................................102 15.2.4 SPI Registers .......................................................................................................103 15.2.5 SPI Interrupts .......................................................................................................103 15.2.6 Enabling and Initializing SPI ................................................................................104 15.2.7 Internally and Externally Clocked SPI Operations ...............................................105 15.3 UART ....................................................................................................................................106 15.3.1 Features...............................................................................................................106 15.3.2 General Description .............................................................................................107 15.3.3 UART Modes of Operation...................................................................................107 15.3.3.1 Standard Protocol.................................................................................107 15.3.3.2 SmartCard (ISO7816) ..........................................................................111 15.3.3.3 IrDA ......................................................................................................112 15.3.4 UART Registers ...................................................................................................113 15.3.5 UART Interrupts ...................................................................................................114 15.3.6 Enabling and Initializing UART ............................................................................114 15.4 Inter Integrated Circuit (I2C) .................................................................................................115 15.4.1 Features...............................................................................................................115 15.4.2 General Description .............................................................................................115 15.4.3 Terms and Definitions ..........................................................................................116 15.4.3.1 Clock Stretching ...................................................................................116 15.4.3.2 Bus Arbitration......................................................................................116 15.4.4 I2C Modes of Operation.......................................................................................116 15.4.4.1 Write Transfer.......................................................................................118 15.4.4.2 Read Transfer ......................................................................................118 15.4.5 I2C Registers .......................................................................................................119 15.4.6 I2C Interrupts .......................................................................................................119 15.4.7 Enabling and Initializing the I2C...........................................................................120 15.4.8 Internal and External Clock Operation in I2C.......................................................121 15.4.9 Wake up from Sleep ............................................................................................123 15.4.10 Master Mode Transfer Examples .........................................................................124 15.4.10.1 Master Transmit ...................................................................................124 15.4.10.2 Master Receive ....................................................................................125 15.4.11 Slave Mode Transfer Examples ...........................................................................126 15.4.11.1 Slave Transmit .....................................................................................126 15.4.11.2 Slave Receive ......................................................................................127 15.4.12 Multi-Master Mode Transfer Example ..................................................................128 15.4.12.1 Multi-Master - Slave Not Enabled.........................................................128 15.4.12.2 Multi-Master - Slave Enabled ...............................................................129 16. Universal Digital Blocks (UDB) 131 16.1 Features................................................................................................................................131 16.2 How It Works ........................................................................................................................132 16.2.1 PLDs ....................................................................................................................132 16.2.1.1 PLD Macrocells ....................................................................................133 16.2.1.2 PLD Carry Chain ..................................................................................134 16.2.1.3 PLD Configuration ................................................................................134 16.2.2 Datapath ..............................................................................................................134 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 9 16.2.2.1 Overview ..............................................................................................135 16.2.2.2 Datapath FIFOs....................................................................................136 16.2.2.3 FIFO Status..........................................................................................142 16.2.2.4 Datapath ALU.......................................................................................142 16.2.2.5 Datapath Inputs and Multiplexing.........................................................145 16.2.2.6 CRC/PRS Support ...............................................................................145 16.2.2.7 Datapath Outputs and Multiplexing ......................................................148 16.2.2.8 Datapath Parallel Inputs and Outputs ..................................................149 16.2.2.9 Datapath Chaining ...............................................................................150 16.2.2.10 Dynamic Configuration RAM................................................................151 16.2.3 Status and Control Module ..................................................................................152 16.2.3.1 Status and Control Mode .....................................................................153 16.2.3.2 Control Register Operation ..................................................................154 16.2.3.3 Parallel Input/Output Mode ..................................................................155 16.2.3.4 Counter Mode ......................................................................................156 16.2.3.5 Sync Mode ...........................................................................................157 16.2.3.6 Status and Control Clocking.................................................................157 16.2.3.7 Auxiliary Control Register.....................................................................157 16.2.3.8 Status and Control Register Summary.................................................158 16.2.4 Reset and Clock Control Module .........................................................................158 16.2.4.1 Clock Control........................................................................................159 16.2.4.2 Reset Control .......................................................................................160 16.2.4.3 UDB POR Initialization .........................................................................164 16.2.5 UDB Addressing ..................................................................................................164 16.2.6 System Bus Access Coherency ..........................................................................165 16.2.6.1 Simultaneous System Bus Access.......................................................165 16.2.6.2 Coherent Accumulator Access (Atomic Reads and Writes).................165 16.3 Port Adapter Block................................................................................................................166 16.3.1 PA Data Input Logic .............................................................................................166 16.3.2 PA Port Pin Clock Multiplexer Logic ....................................................................167 16.3.3 PA Data Output Logic ..........................................................................................167 16.3.4 PA Output Enable Logic.......................................................................................168 16.3.5 PA Clock Multiplexer............................................................................................169 16.3.6 PA Reset Multiplexer ...........................................................................................169 17. Timer, Counter, and PWM 171 17.1 Features ...............................................................................................................................171 17.2 Block Diagram ......................................................................................................................172 17.2.1 Enabling and Disabling Counter in TCPWM Block ..............................................172 17.2.2 Clocking ...............................................................................................................172 17.2.3 Events Based on Trigger Inputs...........................................................................173 17.2.4 Output Signals .....................................................................................................173 17.2.4.1 Signals upon Trigger Conditions ..........................................................174 17.2.4.2 Interrupts ..............................................................................................174 17.2.4.3 Outputs.................................................................................................174 17.2.5 Power Modes.......................................................................................................176 17.3 Modes of Operation ..............................................................................................................176 17.3.1 Timer Mode..........................................................................................................177 17.3.1.1 Block Diagram......................................................................................177 17.3.1.2 How It Works........................................................................................177 17.3.1.3 Configuring Counter for Timer Mode....................................................179 17.3.2 Capture Mode ......................................................................................................179 17.3.2.1 Block Diagram......................................................................................179 10 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 17.3.2.2 How it Works ........................................................................................179 17.3.2.3 Configuring Counter for Capture Mode ................................................180 17.3.3 Quadrature Decoder Mode ..................................................................................181 17.3.3.1 Block Diagram ......................................................................................181 17.3.3.2 How It Works ........................................................................................181 17.3.3.3 Configuring Counter for Quadrature Mode...........................................183 17.3.4 Pulse Width Modulation Mode .............................................................................184 17.3.4.1 Block Diagram ......................................................................................184 17.3.4.2 How It Works ........................................................................................184 17.3.4.3 Other Configurations ............................................................................186 17.3.4.4 Kill Feature ...........................................................................................186 17.3.4.5 Configuring Counter for PWM Mode ....................................................187 17.3.5 Pulse Width Modulation with Dead Time Mode ...................................................188 17.3.5.1 Block Diagram ......................................................................................188 17.3.5.2 How It Works ........................................................................................188 17.3.5.3 Configuring Counter for PWM with Dead Time Mode ..........................189 17.3.6 Pulse Width Modulation Pseudo-Random Mode .................................................190 17.3.6.1 Block Diagram ......................................................................................190 17.3.6.2 How It Works ........................................................................................190 17.3.6.3 Configuring Counter for Pseudo-Random PWM Mode ........................192 17.4 TCPWM Registers ..............................................................................................................193 Section F: Analog System 195 Top Level Architecture ...................................................................................................................195 18. Precision Reference 197 18.1 Features................................................................................................................................197 18.2 Block Diagram ......................................................................................................................197 18.3 How it Works.........................................................................................................................198 18.3.1 Precision Bandgap...............................................................................................198 18.3.2 Trim Buffer ...........................................................................................................198 18.3.3 Low-Power Buffers...............................................................................................198 18.3.4 Current Mirrors.....................................................................................................199 18.3.5 Temperature-Controlled Voltage Generator .........................................................199 18.3.6 Temperature-Controlled Current Generator .........................................................199 18.4 Configuration ........................................................................................................................199 19. SAR ADC 201 19.1 Features................................................................................................................................201 19.2 Block Diagram ......................................................................................................................202 19.3 How it Works.........................................................................................................................202 19.3.1 SAR ADC Core ....................................................................................................202 19.3.1.1 Single-ended and Differential Mode .....................................................203 19.3.1.2 Input Range..........................................................................................203 19.3.1.3 Result Data Format ..............................................................................203 19.3.1.4 Negative Input Selection ......................................................................204 19.3.1.5 Resolution ............................................................................................204 19.3.1.6 Acquisition Time ...................................................................................204 19.3.1.7 SAR ADC Clock ...................................................................................205 19.3.1.8 SAR ADC Timing..................................................................................205 19.3.2 SARMUX..............................................................................................................206 19.3.2.1 Analog Routing.....................................................................................206 19.3.2.2 Analog Interconnection.........................................................................207 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 11 19.3.3 SARREF .............................................................................................................. 211 19.3.3.1 Reference Options ...............................................................................212 19.3.3.2 Bypass Capacitors ...............................................................................212 19.3.3.3 Input Range versus Reference ............................................................212 19.3.4 SARSEQ..............................................................................................................213 19.3.4.1 Averaging .............................................................................................214 19.3.4.2 Range Detection ..................................................................................214 19.3.4.3 Double Buffer .......................................................................................214 19.3.4.4 Injection Channel .................................................................................214 19.3.5 Interrupt ...............................................................................................................215 19.3.5.1 End-of-Scan Interrupt (EOS_INTR) .....................................................215 19.3.5.2 Overflow Interrupt.................................................................................215 19.3.5.3 Collision Interrupt .................................................................................215 19.3.5.4 Injection End-of-Conversion Interrupt (INJ_EOC_INTR) .....................215 19.3.5.5 Range Detection Interrupts ..................................................................215 19.3.5.6 Saturate Detection Interrupts ...............................................................216 19.3.5.7 Interrupt Cause Overview ....................................................................216 19.3.6 Trigger .................................................................................................................216 19.3.6.1 DSI Trigger Configuration ....................................................................216 19.3.7 SAR ADC Status..................................................................................................217 19.3.8 Low-Power Mode.................................................................................................217 19.3.9 System Operation ................................................................................................217 19.3.10 Register Mode .....................................................................................................218 19.3.10.1 SARMUX Analog Routing ....................................................................218 19.3.10.2 Global SARSEQ Configuration ............................................................219 19.3.10.3 Channel Configurations........................................................................220 19.3.10.4 Channel Enables..................................................................................221 19.3.10.5 Interrupt Masks ....................................................................................221 19.3.10.6 Trigger..................................................................................................221 19.3.10.7 Retrieve Data after Each Interrupt .......................................................221 19.3.10.8 Injection Conversions...........................................................................221 19.3.11 DSI Mode.............................................................................................................221 19.3.11.1 Firmware Analog Routing.....................................................................222 19.3.11.2 DSI Analog Routing..............................................................................222 19.3.11.3 Global SARSEQ Configuration ............................................................223 19.3.11.4 DSI Channel Configuration ..................................................................223 19.3.11.5 Interrupt................................................................................................223 19.3.11.6 Trigger..................................................................................................224 19.3.11.7 Retrieve Data .......................................................................................224 19.3.11.8 DSI Output Enable ...............................................................................224 19.3.12 Analog Routing Configuration Example...............................................................224 19.3.13 Temperature Sensor Configuration......................................................................227 19.4 Registers ..............................................................................................................................228 20. Low-Power Comparator 229 20.1 Features ...............................................................................................................................229 20.2 Block Diagram ......................................................................................................................229 20.3 How It Works ........................................................................................................................230 20.3.1 Input Configuration ..............................................................................................230 20.3.2 Output and Interrupt Configuration ......................................................................230 20.3.3 Power Mode and Speed Configuration ................................................................232 20.3.4 Hysteresis ............................................................................................................232 20.3.5 Wakeup from Low-Power Modes.........................................................................233 12 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 20.3.6 Comparator Clock ................................................................................................233 20.3.7 Offset Trim ...........................................................................................................233 20.4 Register Summary ...............................................................................................................233 21. Continuous Time Block mini (CTBm) 235 21.1 Features................................................................................................................................235 21.2 Block Diagram ......................................................................................................................235 21.3 How It Works ........................................................................................................................236 21.3.1 Power Mode Configuration ..................................................................................237 21.3.2 Output Strength Configuration .............................................................................237 21.3.3 Compensation......................................................................................................238 21.3.4 Switch Control......................................................................................................238 21.3.4.1 Input Configuration ...............................................................................238 21.3.4.2 Output Configuration ............................................................................240 21.3.4.3 Comparator Mode ................................................................................241 21.3.4.4 Comparator Configuration ....................................................................241 21.3.4.5 Comparator Interrupt ............................................................................242 21.4 Register Summary ...............................................................................................................242 22. LCD Direct Drive 243 22.1 Features................................................................................................................................243 22.2 LCD Segment Drive Overview..............................................................................................243 22.2.1 Drive Modes.........................................................................................................244 22.2.1.1 PWM Drive ...........................................................................................244 22.2.1.2 Digital Correlation.................................................................................249 22.2.2 Recommended Usage of Drive Modes ................................................................252 22.2.3 Digital Contrast Control........................................................................................252 22.3 Block Diagram ......................................................................................................................253 22.3.1 How it Works........................................................................................................253 22.3.2 High-Speed and Low-Speed Master Generators .................................................253 22.3.3 Multiplexer and LCD Pin Logic.............................................................................254 22.3.4 Display Data Registers ........................................................................................254 22.4 Register List .........................................................................................................................254 23. CapSense 255 23.1 23.2 23.3 23.4 Features................................................................................................................................255 Block Diagram ......................................................................................................................255 How It Works ........................................................................................................................256 CapSense CSD Sensing ......................................................................................................257 23.4.1 GPIO Cell Capacitance to Current Converter ......................................................257 23.4.2 CapSense Clock Generator .................................................................................259 23.4.3 Sigma Delta Converter.........................................................................................259 23.5 CapSense CSD Shielding.....................................................................................................261 23.5.1 CMOD Precharge ................................................................................................262 23.6 General-Purpose Resources: IDACs....................................................................................263 23.7 Register List..........................................................................................................................263 24. Temperature Sensor 24.1 24.2 24.3 24.4 24.5 265 Features................................................................................................................................265 How it Works.........................................................................................................................265 Temperature Sensor Configuration ......................................................................................266 Algorithm...............................................................................................................................268 Registers...............................................................................................................................268 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 13 Section G: Program and Debug 269 Top Level Architecture ...................................................................................................................269 25. Program and Debug Interface 271 25.1 Features ...............................................................................................................................271 25.2 Functional Description ..........................................................................................................271 25.3 Serial Wire Debug (SWD) Interface......................................................................................272 25.3.1 SWD Timing Details.............................................................................................273 25.3.2 ACK Details .........................................................................................................273 25.3.3 Turnaround (Trn) Period Details ..........................................................................273 25.4 Cortex-M0 Debug and Access Port (DAP) ...........................................................................274 25.4.1 Debug Port (DP) Registers ..................................................................................274 25.4.2 Access Port (AP) Registers ................................................................................274 25.5 Programming the PSoC 4 Device.........................................................................................275 25.5.1 SWD Port Acquisition ..........................................................................................275 25.5.1.1 Primary and Secondary SWD Pin Pairs...............................................275 25.5.1.2 SWD Port Acquire Sequence..............................................................275 25.5.2 SWD Programming Mode Entry ..........................................................................275 25.5.3 SWD Programming Routines Executions ............................................................275 25.6 PSoC 4 SWD Debug Interface .............................................................................................276 25.6.1 Debug Control and Configuration Registers ........................................................276 25.6.2 Breakpoint Unit (BPU) .........................................................................................276 25.6.3 Data Watchpoint (DWT).......................................................................................276 25.6.4 Debugging the PSoC 4 Device ............................................................................276 25.7 Registers ..............................................................................................................................277 26. Nonvolatile Memory Programming 279 26.1 26.2 26.3 26.4 Features ...............................................................................................................................279 Functional Description ..........................................................................................................279 System Call Implementation.................................................................................................280 Blocking and Non-Blocking System Calls.............................................................................280 26.4.1 Performing a System Call ....................................................................................280 26.5 System Calls.........................................................................................................................281 26.5.1 Silicon ID .............................................................................................................281 26.5.2 Load Flash Bytes .................................................................................................282 26.5.3 Write Row ............................................................................................................283 26.5.4 Program Row.......................................................................................................284 26.5.5 Erase All ..............................................................................................................284 26.5.6 Checksum............................................................................................................285 26.5.7 Write Protection ...................................................................................................285 26.5.8 Non-Blocking Write Row......................................................................................286 26.5.9 Non-Blocking Program Row ................................................................................287 26.5.10 Resume Non-Blocking .........................................................................................288 26.6 System Call Status ...............................................................................................................288 26.7 Non-Blocking System Call Pseudo Code .............................................................................289 Glossary 293 Index 309 14 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section A: Overview This section encompasses the following chapters: ■ Introduction chapter on page 17 ■ Getting Started chapter on page 23 ■ Document Construction chapter on page 25 Document Revision History Revision Issue Date Origin of Change ** 23 January, 2013 XKJ Initial release *A 18 April, 2013 RLIU Extensive updates throughout the document *B 18 July, 2013 RLIU Multiple fixes across the document Description of Change Interrupts chapter: Change PICU to GPIO interrupt I/O System chapter: Change PICU to GPIO interrupt. Added the limitation of Analog/DSI switching of GPIOs *C 12 March, 2014 NIDH Power Modes chapter: Removed XRES from Table 11-1 and added as a note. Changed the regular analog peripherals in Deep-Sleep to "off" in Table 11-2. Added brownout to table 3. changed PICU to GPIO interrupt. Minor grammar fixes throughout the document. Updated section 11.7 to include LPM_READY condition. TCPWM chapter: Changed main clock to HFCLK. Minor fixes to images. Minor grammar fixes throughout the document CapSense chapter: Updated the IDAC names and explanations to match new IDAC nomenclature Corrected links to the datasheet and register TRM. Added the following sections: 1.11 Device Feature Summary, 2.4 Application Notes, 18.1 Features, 14.2.2 Flash Security, and 24.5 Registers. *D 03 December, 2015 NIDH Updated the following sections: 5.3.3 Exception Vector Table, 8.2 Clock Sources, UART Local Interconnect Network (LIN) Mode, 19.3.1.6 Acquisition Time Added Table 8-1, Table 21-2, Table 21-9, and Table 22-2. Modified multiple sections in the I/O System chapter on page 53. Minor text edits across the document. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 15 16 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 1. Introduction PSoC® 4 is a programmable embedded system controller with an ARM® Cortex®-M0 CPU. It combines programmable analog, programmable interconnect, user-programmable digital logic, and commonly used fixed-function peripherals with a high-performance ARM Cortex-M0 subsystem.PSoC an enhanced version of the PSoC 4000 family and is The PSoC 4100/ 4200 families are the first members of the PSoC 4 architecture. They are upward-compatible with larger members of PSoC 4. PSoC 4 devices have these characteristics: ■ High-performance, 32-bit single-cycle Cortex-M0 CPU core ■ Fixed-function and configurable digital blocks ■ Programmable digital logic ■ High-performance analog system ■ Flexible and programmable interconnect ■ Capacitive touch sensing (CapSense®) ■ Low-power operating modes – Sleep, Deep-Sleep, Hibernate, and Stop modes This document describes each functional block of the PSoC 4100/4200 device in detail. This information will help designers to create system-level designs. 1.1 Top Level Architecture Figure 1-1 shows the major components of the PSoC 4100 architecture and Figure 1-2 shows the architecture of the PSoC 4200 family. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 17 Introduction Figure 1-1. PSoC 4100 Family Block Diagram CPU Subsystem PSoC 4100 32-bit AHB-Lite SWD/TC Cortex M0 24 MHz FLASH Up to 32 kB SRAM Up to 4 kB SROM 4 kB FAST MUL NVIC, IRQMX Read Accelerator SRAM Controller ROM Controller System Resources Peripherals Reset Reset Control XRES Test DFT Logic DFT Analog SAR (12-bit) SMX CTBm 2x OpAmp x1 36x GPIO x1 LCD Programmable Analog Capsense Peripheral Interconnect (MMIO) 2x LP Comparator PCLK 2x SCB-I2C/SPI/UART Clock Clock Control WDT IMO ILO System Interconnect (Single Layer AHB) 4x TCPWM Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches Port Interface & Digital System Interconnect (DSI) High Speed I/O Matrix Active/Sleep Deep Sleep Hibernate I/O Pins (Analog, Digital, Special, ESD) I/O Subsystem 18 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Introduction Figure 1-2. PSoC 4200 Family Block Diagram CPU Subsystem PSoC 4200 SWD/TC 32-bit AHB-Lite Cortex M0 48 MHz FLASH Up to 32 kB SRAM Up to 4 kB SROM 4 kB FAST MUL NVIC, IRQMX Read Accelerator SRAM Controller ROM Controller System Resources System Interconnect (Single Layer AHB) Peripherals Reset Reset Control XRES UDB SAR (12-bit) UDB x4 UDB Test DFT Logic DFT Analog SMX CTBm 2x OpAmp x1 36x GPIO x1 LCD Programmable Digital Capsense Programmable Analog 2x LP Comparator Clock Clock Control WDT IMO ILO Peripheral Interconnect (MMIO) 2x SCB-I2C/SPI/UART PCLK 4x TCPWM Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches UDB Port Interface & Digital System Interconnect (DSI) High Speed I/O Matrix Active/Sleep Deep Sleep Hibernate I/O Pins (Analog, Digital, Special, ESD) I/O Subsystem 1.2 Features The PSoC 4100/4200 components: families have these major ■ 32-bit Cortex-M0 CPU with single-cycle multiply, delivering up to 43 DMIPS at 48 MHz ■ Up to 32 KB flash and 4 KB SRAM ■ Four independent center-aligned pulse-width modulators (PWMs) with complementary, dead-band programmable outputs ■ Up to four programmable logic blocks, known as universal digital blocks (UDBs) ■ CapSense ■ Segment LCD direct drive ■ Low-power operating modes: Sleep, Deep-Sleep, Hibernate, and Stop ■ Programming and debugging system through serial wire debug (SWD) ■ Fully supported by PSoC Creator™ IDE tool ■ Twelve-bit SAR ADC (with sampling rate of 1 Msps in PSoC 4200 and 806 ksps in PSoC 4100) with hardware sequencing for multiple channels 1.3 ■ Up to two opamps that can be used for analog signal conditioning and as a comparator 1.3.1 ■ Two low-power comparators ■ Two serial communication blocks (SCB) that can work as SPI, UART, I2C, and local interconnect network (LIN) slave serial communication channels The heart of the PSoC 4 is a 32-bit Cortex-M0 CPU core running up to 48 MHz for PSoC 4200 and 24 MHz for PSoC 4100. It is optimized for low-power operation with extensive clock gating. It uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully CPU System Processor PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 19 Introduction compatible binary upward migration of the code to higher performance processors such as Cortex M3 and M4. The CPU has a hardware multiplier that provides a 32-bit result in one cycle. 1.3.2 Interrupt Controller The CPU subsystem includes a nested vectored interrupt controller (NVIC) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor from Deep-Sleep mode. The Cortex-M0 CPU of PSoC 4 implements a non-maskable interrupt (NMI) input, which can be tied to digital routing for general-purpose use. default Active mode. In Active mode, the CPU runs with all the logic powered. In Sleep mode, the CPU is powered off with all other peripherals functional. In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention; the main system clock is off while the low-frequency clock is on and the low-frequency peripherals are in operation. In Hibernate mode, even the low-frequency clock is off and low-frequency peripherals stop operating. Multiple internal regulators are available in the system to support power supply schemes in different power modes. 1.5.3 GPIO Every GPIO in PSoC 4 has the following characteristics: 1.4 Memory The PSoC 4 memory subsystem consists of flash and SRAM. A supervisory ROM, containing boot and configuration routines, is also present. 1.4.1 Flash ■ Eight drive strength modes ■ Individual control of input and output disables ■ Hold mode for latching previous state ■ Selectable slew rates ■ Interrupt generation – edge triggered ■ CapSense and LCD drive support The PSoC 4 has a flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block. The flash accelerator delivers 85 percent of single-cycle SRAM access performance on an average. The pins are organized in a port of 8-bit width. A high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed. 1.4.2 1.6 SRAM The PSoC 4 provides SRAM, which is retained during Hibernate mode. 1.5 1.5.1 System-Wide Resources Clocking System The clocking system for the PSoC 4 device consists of the internal main oscillator (IMO) and internal low-speed oscillator (ILO) as internal clocks and has provision for an external clock The IMO with an accuracy of ±2 percent is the primary source of internal clocking in the device. The default IMO frequency is 24 MHz and it can be adjusted between 3 MHz and 48 MHz in steps of 1 MHz. Multiple clock derivatives are generated from the main clock frequency to meet various application needs. The ILO is a low-power, less accurate oscillator and is used to generate clocks for peripheral operation in Deep-Sleep mode. Its clock frequency is 32kHz with ±60 percent accuracy. An external clock source ranging from 0 MHz to 48 MHz can be pulled in to generate the clock derivatives for the functional blocks instead of the IMO. 1.5.2 The PSoC 4 operates with a single external supply in the range 1.71 V to 5.5 V. PSoC 4 has four low-power modes – Sleep, Deep-Sleep, Hibernate, and Stop – in addition to the 20 The PSoC 4200 has up to four UDBs. Each UDB contains structured data-path logic and uncommitted PLD logic with flexible interconnect. The UDB array provides a switched routing fabric called the digital signal interconnect (DSI). The DSI allows routing of signals from peripherals and ports to and within the UDBs. The UDB arrays in PSoC 4200 enable custom logic or additional timers/PWMs and communication interfaces such as I2C, SPI, I2S, and UART. Note PSoC 4100 does not have UDBs. 1.7 1.7.1 Fixed-Function Digital Timer/Counter/PWM Block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. The functionality of these counters can be synchronized. Each block has a capture register, period register, and compare register. The block supports complementary, dead-band programmable outputs. It also has a kill input to force outputs to a predetermined state. Other features of the block include center-aligned PWM, clock prescaling, pseudo random PWM, and quadrature decoding. 1.7.2 Power System Programmable Digital Serial Communication Blocks The device has two SCBs. Each SCB can implement a serial communication interface as I2C, UART, local interconnect network (LIN) slave, or SPI. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Introduction The features of each SCB include: ■ Standard I2C multi-master and slave function ■ Standard SPI master and slave function with Motorola, Texas Instruments, and National (MicroWire) mode ■ Standard UART transmitter and receiver function with SmartCard reader (ISO7816), IrDA protocol, and LIN ■ Standard LIN slave with LIN v1.3 and LIN v2.1/2.2 specification compliance ■ EZ function mode support for SPI and I2C with 32-byte buffer 1.8 Analog System 1.8.1 SAR ADC PSoC 4200 has a configurable 12-bit 1-Msps SAR ADC and PSoC 4100 has a similar 12-bit SAR ADC with 806 ksps. The ADC provides the choice of three internal voltage references (VDDA, VDDA/2, and VREF) and an external reference through a GPIO pin. The SAR hardware sequencer is available, which scans multiple channels without CPU intervention. 1.8.2 Continuous Time Block mini (CTBm) The CTBm block provides continuous time functionality at the entry and exit points of the analog subsystem. The CTBm has two highly configurable and high-performance opamps with a switch routing matrix. The opamps can also work in comparator mode. PSoC 4100/4200 has one such CTBm block. The block allows open-loop opamp, linear buffer, and comparator functions to be performed without external components. PGAs, voltage buffers, filters, and transimpedance amplifiers can be realized with external components used. 1.11 1.8.3 Low-Power Comparators The PSoC 4100/4200 has a pair of low-power comparators, which can operate in all device power modes. This allows the CPU and other system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. Two input voltages can both come from pins, or one from an internal signal through the AMUXBUS. 1.9 Special Function Peripherals 1.9.1 LCD Segment Drive The PSoC 4100/4200 has an LCD controller, which can drive up to four commons and every GPIO can be configured to drive common or segment. It uses full digital methods (digital correlation and PWM) to drive the LCD segments, and does not require generation of internal LCD voltages. 1.9.2 CapSense PSoC 4 devices have the CapSense feature, which allows you to use the capacitive properties of your fingers to toggle buttons, sliders, and wheels. CapSense functionality is supported on all GPIO pins in PSoC 4 through a CapSense Sigma-Delta (CSD) block. The CSD also provides waterproofing capability. 1.9.2.1 IDACs and Comparator The CapSense block has two IDACs and a comparator with a 12-V reference, which can be used for general purposes, if CapSense is not used. 1.10 Program and Debug PSoC 4 devices support programming and debugging features of the device via the on-chip SWD interface. The PSoC Creator IDE provides fully integrated programming and debugging support. The SWD interface is also fully compatible with industry standard third-party tools. Device Feature Summary Table 1-1 shows the PSoC 4100/4200 device summary. Table 1-1. PSoC 4100/4200 Device Summary Feature PSoC 4100 PSoC 4200 Maximum CPU Frequency 24 MHz 48 MHz Flash 16 KB – 32 KB 16 KB – 32 KB SRAM 4 KB 4 KB GPIOs (max) 36 36 CapSense Available Available LCD Driver Available Available Timer, Counter, PWM (TCPWM) 4 4 Serial Communication Block (SCB) 2 2 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 21 Introduction Table 1-1. PSoC 4100/4200 Device Summary Feature PSoC 4100 PSoC 4200 Universal Digital Block (UDB) 0 4 IDAC (part of CapSense) 2 2 Opamp 2 2 Comparator 2 2 ADC 12-bit SAR, 806 ksps 12-bit SAR, 1 Msps 22 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 2. Getting Started 2.1 Support Free support for PSoC® 4 products is available online at www.cypress.com/psoc4. Resources include training seminars, discussion forums, application notes, PSoC consultants, CRM technical support email, knowledge base, and application support engineers. For application assistance, visit www.cypress.com/support/ or call 1-800-541-4736. 2.2 Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available from your distributor on DVD-ROM; you can also download them directly from www.cypress.com/psoccreator. Critical updates to system documentation are also provided in the Documentation section. 2.3 Development Kits Development kits are available from Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC projects. Visit the Cypress Online Store website at www.cypress.com/cypress-store. Under Products, click Programmable System-on-Chip to view a list of available items. 2.4 Application Notes Refer to application note AN79953 - Getting Started with PSoC 4 for additional information on PSoC 4 device capabilities and to quickly create a simple PSoC application using PSoC Creator and PSoC 4 development kits. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 23 Getting Started 24 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 3. Document Construction This document includes the following sections: ■ Section B: CPU System on page 29 ■ Section D: System-Wide Resources on page 51 ■ Section E: Digital System on page 95 ■ Section F: Analog System on page 195 ■ Section G: Program and Debug on page 269 3.1 Major Sections For ease of use, information is organized into sections and chapters that are divided according to device functionality. ■ Section – Presents the top-level architecture, how to get started, and conventions and overview information about any particular area that inform the reader about the construction and organization of the product. ■ Chapter – Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementation and use information for some aspect of the integrated circuit. ■ Glossary – Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are presented in bold, italic font throughout. ■ Registers Technical Reference Manual – Supplies all device register details summarized in the technical reference manual. These are additional documents. 3.2 Documentation Conventions This document uses only four distinguishing font types, besides those found in the headings. ■ The first is the use of italics when referencing a document title or file name. ■ The second is the use of bold italics when referencing a term described in the Glossary of this document. ■ The third is the use of Times New Roman font, distinguishing equation examples. ■ The fourth is the use of Courier New font, distinguishing code examples. 3.2.1 Register Conventions Register conventions are detailed in the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 3.2.2 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 25 Document Construction 3.2.3 Units of Measure 3.2.4 Acronyms This table lists the units of measure used in this document. This table lists the acronyms used in this document Table 3-1. Units of Measure Table 3-2. Acronyms Abbreviation Unit of Measure Acronym Definition bits per second ABUS analog output bus degrees Celsius AC alternating current dB decibels ADC analog-to-digital converter fF femtofarads AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus Hz Hertz API application programming interface k kilo, 1000 APOR analog power-on reset K kilo, 2^10 BC broadcast clock KB 1024 bytes, or approximately one thousand bytes BOD brownout detect Kbit 1024 bits BOM bill of materials kHz kilohertz (32.000) BR bit rate k kilohms BRA bus request acknowledge MHz megahertz BRQ bus request M megaohms CAN controller area network µA microamperes CI carry in µF microfarads CMP compare µs microseconds CO carry out µV microvolts CPU central processing unit µVrms microvolts root-mean-square CRC cyclic redundancy check mA milliamperes CSD CapSense sigma delta ms milliseconds CT continuous time mV millivolts CTB continuous time block nanoamperes CTBm continuous time block mini ns nanoseconds DAC digital-to-analog converter nV nanovolts DAP debug access port DC direct current DI digital or data input DMA direct memory access DNL differential nonlinearity DO digital or data output DSI digital signal interface DSM deep-sleep mode DW data wire ECO external crystal oscillator EEPROM electrically erasable programmable read only memory EMIF external memory interface FB feedback FIFO first in first out FSR full scale range GPIO general purpose I/O HCI host-controller interface bps °C nA ohms pF picofarads pp peak-to-peak ppm parts per million SPS samples per second sigma: one standard deviation V volts 26 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Document Construction Table 3-2. Acronyms (continued) Acronym Definition Table 3-2. Acronyms (continued) Acronym Definition HFCLK high-frequency clock PSSDC power system sleep duty cycle HSIOM high-speed I/O matrix PWM pulse width modulator I C inter-integrated circuit RAM random-access memory IDE integrated development environment RETI return from interrupt ILO internal low-speed oscillator RF radio frequency ITO indium tin oxide ROM read only memory IMO internal main oscillator RMS root mean square integral nonlinearity RW read/write I/O input/output SAR successive approximation register IOR I/O read SC switched capacitor IOW I/O write SCB serial communication block IRES initial power on reset SIE serial interface engine IRA interrupt request acknowledge SIO special I/O IRQ interrupt request SE0 single-ended zero ISR interrupt service routine SNR signal-to-noise ratio interrupt vector read SOF start of frame LCD liquid crystal display SOI start of instruction LFCLK low-frequency clock SP stack pointer LIN local interconnect network SPD sequential phase detector LPCOMP low-power comparator SPI serial peripheral interconnect LRb last received bit SPIM serial peripheral interconnect master LRB last received byte SPIS serial peripheral interconnect slave LSb least significant bit SRAM static random-access memory least significant byte SROM supervisory read only memory LUT lookup table SSADC single slope ADC MISO master-in-slave-out SSC supervisory system call MMIO memory mapped input/output SYSCLK system clock MOSI master-out-slave-in SWD single wire debug MSb most significant bit TC terminal count MSB most significant byte TCPWM timer, counter, PWM NMI non-maskable interrupt TD transaction descriptors nested vectored interrupt controller UART universal asynchronous receiver/transmitter PC program counter UDB universal digital block PCB printed circuit board USB universal serial bus PCH program counter high USBIO USB I/O PCL program counter low WCO watch crystal oscillator PD power down WDT watchdog timer PGA programmable gain amplifier WDR watchdog reset PM power management XRES external reset PMA PSoC memory arbiter XRES_N external reset, active low POR power-on reset PPOR precision power-on reset PRS pseudo random sequence 2 INL IVR LSB NVIC PSoC ® PSRR Programmable System-on-Chip power supply rejection ratio PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 27 Document Construction 28 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section B: CPU System This section encompasses the following chapters: ■ Cortex-M0 CPU chapter on page 31 ■ Interrupts chapter on page 37 Top Level Architecture CPU System Block Diagram SWD/TC Cortex-M0 48 MHz (PSoC 4200) 24 MHz (PSoC 4100) NVIC, IRQMX System Interconnect (Single Layer AHB) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 29 30 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 4. Cortex-M0 CPU The PSoC® 4 ARM Cortex-M0 core is a 32-bit CPU optimized for low-power operation. It has an efficient three-stage pipeline, a fixed 4-GB memory map, and supports the ARMv6-M Thumb instruction set. The Cortex-M0 also features a single-cycle 32bit multiply instruction and low-latency interrupt handling. Other subsystems tightly linked to the CPU core include a nested vectored interrupt controller (NVIC), a SYSTICK timer, and debug. This section gives an overview of the Cortex-M0 processor. For more details, see the ARM Cortex-M0 user guide or technical reference manual, both available at www.arm.com. 4.1 Features The PSoC 4 Cortex-M0 has the following features: ■ Easy to use, program, and debug, ensuring easier migration from 8- and 16-bit processors ■ Operates at up to 0.9 DMIPS/MHz; this helps to increase execution speed or reduce power ■ Maximum CPU clock frequency of 24 MHz in PSoC 4100 and 48 MHz in PSoC 4200. ■ Supports the Thumb instruction set for improved code density, ensuring efficient use of memory ■ NVIC unit to support interrupts and exceptions for rapid and deterministic interrupt response ■ Extensive debug support including: ❐ SWD port ❐ Breakpoints ❐ Watchpoints PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 31 Cortex-M0 CPU 4.2 Block Diagram CPU Subsystem Fixed Interrupts DSI Interrupts Figure 4-1. PSoC 4 CPU Subsystem Block Diagram Interrupt MUX ARM Cortex-M0 CPU Test Controller DAP System Interconnect Flash Programming Interface Flash Accelerator SRAM Controller SROM Controller Flash SRAM SROM CPU & Memory Subsystem AHB Bridge 4.3 How It Works The Cortex-M0 is a 32-bit processor with a 32-bit data path, 32-bit registers, and a 32-bit memory interface. It supports most 16-bit instructions in the Thumb instruction set and some 32-bit instructions in the Thumb-2 instruction set. The processor supports two operating modes (see Operating Modes on page 34). It has a single-cycle 32-bit multiplication instruction. 4.4 Address Map The ARM Cortex-M0 has a fixed address map allowing access to memory and peripherals using simple memory access instructions. The 32-bit (4 GB) address space is divided into the regions shown in Table 4-1. Note that code can be executed from the code and SRAM regions. Table 4-1. Cortex-M0 Address Map Address Range 0x00000000 - 0x1FFFFFFF Name Use Program code region. You can also place data here. Includes the exception vector table, which starts at address 0. Code 0x20000000 - 0x3FFFFFFF SRAM Data region. You can also execute code from this region. 0x40000000 - 0x5FFFFFFF Peripheral All peripheral registers. You cannot execute code from this region. 0xE0000000 - 0xE00FFFFF PPB Peripheral registers within the CPU core. 0xE0100000 - 0xFFFFFFFF Device PSoC 4 implementation-specific. 0x60000000 - 0xDFFFFFFF 32 Not used. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Cortex-M0 CPU 4.5 Registers The Cortex-M0 has 16 32-bit registers, as Table 4-2 shows: ■ R0 to R12 – General-purpose registers. R0 to R7 can be accessed by all instructions; the other registers can be accessed by a subset of the instructions. ■ R13 – Stack pointer (SP). There are two stack pointers, with only one available at a time. In thread mode, the CONTROL register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP). ■ R14 – Link register. Stores the return program counter during function calls. ■ R15 – Program counter. This register can be written to control program flow. Table 4-2. Cortex-M0 Registers Name R0-R12 Typea Reset Value RW Undefined Description R0-R12 are 32-bit general-purpose registers for data operations. The stack pointer (SP) is register R13. In thread mode, bit[1] of the CONTROL register indicates which stack pointer to use: MSP (R13) PSP (R13) RW 0 = Main stack pointer (MSP). This is the reset value. [0x00000000] 1 = Process stack pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. LR (R14) RW Undefined PC (R15) RW [0x00000004] The link register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. The program counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value from address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1. The program status register (PSR) combines: PSR RW Application Program Status Register (APSR). Undefined Execution Program Status Register (EPSR). Interrupt Program Status Register (IPSR). Undefined The APSR contains the current state of the condition flags from previous instruction executions. APSR RW EPSR RO IPSR RO 0 The IPSR contains the exception number of the current ISR. PRIMASK RW 0 The PRIMASK register prevents activation of all exceptions with configurable priority. CONTROL RW 0 The CONTROL register controls the stack used when the processor is in thread mode. [0x00000004].0 On reset, EPSR is loaded with the value bit[0] of the register [0x00000004]. a. Describes access type during program execution in thread mode and handler mode. Debug access can differ. Table 4-3 shows how the PSR bits are assigned. Table 4-3. Cortex-M0 PSR Bit Assignments Bit PSR Register Name 31 APSR N Usage Negative flag 30 APSR Z Zero flag 29 APSR C Carry or borrow flag 28 APSR V Overflow flag PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 33 Cortex-M0 CPU Table 4-3. Cortex-M0 PSR Bit Assignments Bit PSR Register Name 27 – 25 – – Reserved Usage 24 EPSR T Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0 results in a HardFault exception. 23 – 6 – – Reserved Exception number of current ISR: 5–0 IPSR 0 = thread mode 1 = reserved 2 = NMI 3 = HardFault 4 – 10 = reserved 11 = SVCall 12, 13 = reserved 14 = PendSV 15 = SysTick 16 = IRQ0 … 47 = IRQ31 N/A Use the MSR or CPS instruction to set or clear bit 0 of the PRIMASK register. If the bit is 0, exceptions are enabled. If the bit is 1, all exceptions with configurable priority, that is, all exceptions except HardFault, NMI, and Reset, are disabled. See the Interrupts chapter on page 37 for a list of exceptions. 4.6 Operating Modes The Cortex-M0 processor supports two operating modes: ■ ■ Thread Mode – used by all normal applications. In this mode, the MSP or PSP can be used. The CONTROL register bit 1 determines which stack pointer is used: ❐ 0 = MSP is the current stack pointer ❐ 1 = PSP is the current stack pointer Handler Mode – used to execute exception handlers. The MSP is always used. In thread mode, use the MSR instruction to set the stack pointer bit in the CONTROL register. When changing the stack pointer, use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. In handler mode, explicit writes to the CONTROL register are ignored, because the MSP is always used. The exception entry and return mechanisms automatically update the CONTROL register. 4.7 Instruction Set The Cortex-M0 implements a version of the Thumb instruction set, as Table 4-4 shows. For details, see the Cortex-M0 Generic User Guide. An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. Many instructions are unable to use, or have restrictions on using, the PC or SP for the operands or destination register. 34 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Cortex-M0 CPU Table 4-4. Thumb Instruction Set Table 4-4. Thumb Instruction Set Mnemonic Brief Description Mnemonic Brief Description SEV Send event ADCS Add with carry STM Store multiple registers, increment after ADD{S}a Add STR Store register as word ADR PC-relative address to register STRB Store register as byte ANDS Bit wise AND STRH ASRS Arithmetic shift right SUB{S} B{cc} Branch {conditionally} SVC Supervisor call BICS Bit clear SXTB Sign extend byte BKPT Breakpoint SXTH Sign extend half-word BL Branch with link TST Logical AND-based test BLX Branch indirect with link UXTB Zero extend a byte BX Branch indirect UXTH Zero extend a half-word CMN Compare negative WFE Wait for event CMP Compare WFI Wait for interrupt CPSID Change processor state, disable interrupts CPSIE Change processor state, enable interrupts DMB Data memory barrier DSB Data synchronization barrier EORS Exclusive OR ISB Instruction synchronization barrier LDM Load multiple registers, increment after LDR Load register from PC-relative address LDRB Load register with word LDRH Load register with half-word LDRSB Load register with signed byte 4.7.2 LDRSH Load register with signed half-word LSLS Logical shift left LSRS Logical shift right The PSoC 4 Cortex-M0 uses the little-endian format, where the least-significant byte of a word is stored at the lowest address and the most significant byte is stored at the highest address. MOV{S}a Move MRS Move to general register from special register MSR Move to special register from general register MULS Multiply, 32-bit result MVNS Bit wise NOT NOP No operation ORRS Logical OR POP Pop registers from stack PUSH Push registers onto stack REV Byte-reverse word REV16 Byte-reverse packed half-words REVSH Byte-reverse signed half-word RORS Rotate right RSBS Reverse subtract SBCS Subtract with carry Store register as half-word a Subtract a. The ‘S’ qualifier causes the ADD, SUB, or MOV instructions to update APSR condition flags. 4.7.1 Address Alignment An aligned access is an operation where a word-aligned address is used for a word or multiple word access, or where a half-word-aligned address is used for a half-word access. Byte accesses are always aligned. No support is provided for unaligned accesses on the Cortex-M0 processor. Any attempt to perform an unaligned memory access operation results in a HardFault exception. 4.8 Memory Endianness Systick Timer The Systick timer is integrated with the NVIC and generates the SYSTICK interrupt. This interrupt can be used for task management in a real-time system. The timer has a reload register with 24 bits available to use as a countdown value. The Systick timer uses the Cortex-M0 internal clock as a source. 4.9 Debug PSoC 4 contains a debug interface based on SWD; it features four breakpoint (address) comparators and two watchpoint (data) comparators. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 35 Cortex-M0 CPU 36 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 5. Interrupts The ARM Cortex-M0 (CM0) CPU in PSoC® 4 supports interrupts and exceptions. Interrupts refer to those events generated by peripherals external to the CPU such as timers, serial communication block, and port pin signals. Exceptions refer to those events that are generated by the CPU such as memory access faults and internal system timer events. Both interrupts and exceptions result in the current program flow being stopped and the exception handler or interrupt service routine (ISR) being executed by the CPU. PSoC 4 provides a unified exception vector table for both interrupt handlers/ISR and exception handlers. 5.1 Features PSoC 4 supports the following interrupt features: ■ Supports 32 interrupts ■ Nested vectored interrupt controller (NVIC) integrated with CPU core, yielding low interrupt latency ■ Vector table may be placed in either flash or SRAM ■ Configurable priority levels from 0 to 3 for each interrupt ■ Level-triggered and pulse-triggered interrupt signals 5.2 How It Works Figure 5-1. PSoC 4 Interrupts Block Diagram Cortex-M0 Processor IRQ0 IRQ1 Interrupt signals from PSoC 4 on-chip peripherals Nested Vectored Interrupt Controller (NVIC) Cortex-M0 Processor Core IRQ31 Figure 5-1 shows the interaction between interrupt signals and the Cortex-M0 CPU. PSoC 4 has 32 interrupts; these interrupt signals are processed by the NVIC. The NVIC takes care of enabling/disabling individual interrupts, priority resolution, and communication with the CPU core. The exceptions are not shown in Figure 5-1 because they are part of CM0 core generated events, unlike interrupts, which are generated by peripherals external to the CPU. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 37 Interrupts 5.3 Interrupts and Exceptions Operation 5.3.1 Interrupt/Exception Handling in PSoC 4 The following sequence of events occurs when an interrupt or exception event is triggered: 1. Assuming that all the interrupt signals are initially low (idle or inactive state) and the processor is executing the main code, a rising edge on any one of the interrupt lines is registered by the NVIC. The interrupt line is now in a pending state waiting to be serviced by the CPU. 2. On detecting the interrupt request signal from the NVIC, the CPU stores its current context by pushing the contents of the CPU registers onto the stack. 3. The CPU also receives the exception number of the triggered interrupt from the NVIC. All interrupts and exceptions in PSoC 4 have a unique exception number, as given in Table 5-1. By using this exception number, the CPU fetches the address of the specific exception handler from the vector table. When the NVIC receives an interrupt request while another interrupt is being serviced or receives multiple interrupt requests at the same time, it evaluates the priority of all these interrupts, sending the exception number of the highest priority interrupt to the CPU. Thus, a higher priority interrupt can block the execution of a lower priority ISR at any time. Exceptions are handled in the same way that interrupts are handled. Each exception event has a unique exception number, which is used by the CPU to execute the appropriate exception handler. 5.3.2 Level and Pulse Interrupts PSoC 4 NVIC supports both level and pulse signals on the interrupt lines (IRQ0 to IRQ31). The classification of an interrupt as level or pulse is based on the interrupt source. Figure 5-3. Level Interrupts IRQn CPU Execution main State 4. The CPU then branches to this address and executes the exception handler that follows. 5. Upon completion of the exception handler, the CPU registers are restored to their original state using stack pop operations; the CPU resumes the main code execution. Figure 5-2. Interrupt Handling When Triggered Rising Edge on Interrupt Line is registered by the NVIC CPU detects the request signal from NVIC and stores its current context by pushing contents onto the stack CPU receives exception number of triggered interrupt and fetches the address of the specific exception handle from vector table. CPU branches to the received address and executes exception handler CPU registers are restored using stack upon completion of exception handler. 38 ISR IRQn is still high ISR main ISR main Figure 5-4. Pulse Interrupts IRQn CPU Execution main State ISR ISR main ISR main Figure 5-3 and Figure 5-4 show the working of level and pulse interrupts, respectively. Assuming the interrupt signal is initially inactive (logic low), the following sequence of events explains the handling of level and pulse interrupts: 1. On a rising edge event of the interrupt signal, the NVIC registers the interrupt request. The interrupt is now in the pending state, which means the interrupt requests have not yet been serviced by the CPU. 2. The NVIC then sends the exception number along with the interrupt request signal to the CPU. When the CPU starts executing the ISR, the pending state of the interrupt is cleared. 3. When the ISR is being executed by the CPU, one or more rising edges of the interrupt signal are logged as a single pending request. The pending interrupt is serviced again after the current ISR execution is complete (see Figure 5-4 for pulse interrupts). 4. If the interrupt signal is still high after completing the ISR, it will be pending and the ISR is executed again. Figure 5-3 illustrates this for level triggered interrupts, where the ISR is executed as long as the interrupt signal is high. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Interrupts 5.3.3 Exception Vector Table The exception vector table (Table 5-1), stores the entry point addresses for all exception handlers in PSoC 4. The CPU fetches the appropriate address based on the exception number. Table 5-1. PSoC 4 Exception Vector Table Exception Number Exception Exception Priority Vector Address – Initial Stack Pointer Value Not applicable (NA) Base_Address - 0x00000000 (start of flash memory) or 0x20000000 (start of SRAM) 1 Reset –3, the highest priority Base_Address + 0x04 2 Non Maskable Interrupt (NMI) –2 Base_Address + 0x08 3 HardFault –1 Base_Address + 0x0C 4-10 Reserved NA Base_Address + 0x10 to Base_Address + 0x28 11 Supervisory Call (SVCall) Configurable (0 - 3) Base_Address + 0x2C Base_Address + 0x30 to Base_Address + 0x34 12-13 Reserved NA 14 PendSupervisory (PendSV) Configurable (0 - 3) Base_Address + 0x38 15 System Timer (SysTick) Configurable (0 - 3) Base_Address + 0x3C 16 External Interrupt(IRQ0) Configurable (0 - 3) Base_Address + 0x40 … … Configurable (0 - 3) … 47 External Interrupt(IRQ31) Configurable (0 - 3) Base_Address + 0xBC In Table 5-1, the first word (4 bytes) is not marked as exception number zero. This is because the first word in the exception table is used to initialize the main stack pointer (MSP) value on device reset; it is not considered as an exception. In PSoC 4, the vector table can be configured to be located either in flash memory (base address of 0x00000000) or SRAM (base address of 0x20000000). This configuration is done by writing to the VECT_IN_RAM bit field (bit 0) in the CPUSS_CONFIG register. When the VECT_IN_RAM bit field is ‘1’, CPU fetches exception handler addresses from the SRAM vector table location. When this bit field is ‘0’ (reset state), the vector table in flash memory is used for exception address fetches. You must set the VECT_IN_RAM bit field as part of the device boot code to configure the vector table to be in SRAM. The advantage of moving the vector table to SRAM is that the exception handler addresses can be dynamically changed by modifying the SRAM vector table contents. However, the nonvolatile flash memory vector table must be modified by a flash memory write. Reads of flash addresses 0x00000000 and 0x00000004 are redirected to the first eight bytes of SROM to fetch the stack pointer and reset vectors, unless the NO_RST_OVR bit of the CPUSS_SYSREQ register is set. To allow flash read from addresses 0x00000000 and 0x00000004, the NO_RST_OVR bit should be set to ‘1’. The stack pointer vector holds the address that the stack pointer is loaded with on reset. The reset vector holds the address of the boot sequence. This mapping is done to use the default addresses for the stack pointer and reset vector from SROM when the device reset is released. For reset, boot code in SROM is executed first and then the CPU jumps to address 0x00000004 in flash to execute the handler in flash. The reset exception address in the SRAM vector table is never used because VECT_IN_RAM is 0 on reset. Also, when the SYSREQ bit of the CPUSS_SYSREQ register is set, reads of flash address 0x00000008 are redirected to SROM to fetch the NMI vector address instead of from flash. Reset CPUSS_SYSREQ to read the flash at address 0x00000008. The exception sources (exception numbers 1 to 15) are explained in 5.4 Exception Sources. The exceptions marked as Reserved in Table 5-1 are not used in PSoC 4, although they have addresses reserved for them in the vector table. The interrupt sources (exception numbers 16 to 47) are explained in 5.5 Interrupt Sources. 5.4 Exception Sources This section explains the different exception sources listed in Table 5-1 (exception numbers 1 to 15). 5.4.1 Reset Exception Device reset is treated as an exception in PSoC 4. It is always enabled with a fixed priority of –3, the highest priority exception. A device reset can occur due to multiple reasons, such as power-on-reset (POR), external reset signal on XRES pin, or watchdog reset. When the device is reset, the initial boot code for configuring the device is executed out of supervisory read-only memory (SROM). The boot code and other data in SROM memory are programmed by Cypress, and are not read/write accessible to external users. After completing the SROM boot sequence, the CPU code execution jumps to flash memory. Flash memory address 0x00000004 (Exception#1 in Table 5-1) stores the location of the startup code in flash memory. The CPU starts executing code out of this address. Note that the reset exception address in the SRAM vector table will never be used because the device comes out of reset with the flash vector table selected. The register configuration to select the SRAM vector table can be done only as part of the startup code in flash after the reset is de-asserted. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 39 Interrupts 5.4.2 Non-Maskable Interrupt (NMI) Exception Non-maskable interrupt (NMI) is the highest priority exception other than reset. It is always enabled with a fixed priority of –2. There are three ways to trigger an NMI exception in PSoC 4: ■ NMI exception due to a hardware signal (user NMI exception): PSoC 4 provides an option to trigger an NMI exception using a digital signal. This digital signal is referred to as irq_out[0] in Table 5-3. The NMI exception triggered due to irq_out[0] will execute the NMI handler pointed to by the active vector table (flash or SRAM vector table). ■ NMI exception by setting NMIPENDSET bit (user NMI exception): An NMI exception can be triggered in software by setting the NMIPENDSET bit in the interrupt control state register (CM0_ICSR register). Setting this bit will execute the NMI handler pointed to by the active vector table (flash or SRAM vector table). ■ System Call NMI exception: This exception is used for nonvolatile programming operations in PSoC 4 such as flash write operation and flash checksum operation. It is triggered by setting the SYSCALL_REQ bit in the CPUSS_SYSREQ register. An NMI exception triggered by SYSCALL_REQ bit always executes the NMI exception handler code that resides in SROM. Flash or SRAM exception vector table is not used for system call NMI exception. The NMI handler code in SROM is not read/write accessible because it contains nonvolatile programming routines that should not be modified by the user. 5.4.3 HardFault Exception HardFault is an always-enabled exception that occurs because of an error during normal or exception processing. HardFault has a fixed priority of –1, meaning it has higher priority than any exception with configurable priority. HardFault exception is a catch-all exception for different types of fault conditions, which include executing an undefined instruction and accessing an invalid memory addresses. The CM0 CPU does not provide fault status information to the HardFault exception handler, but it does permit the handler to perform an exception return and continue execution in cases where software has the ability to recover from the fault situation. 5.4.4 Supervisor Call (SVCall) Exception page 73 for details on privileged mode.) There is no other privileged mode support for SVCall at the architecture level in PSoC 4. The application developer must define the SVCall exception handler according to the end application requirements. The priority of a SVCall exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_11[31:30] of the System Handler Priority Register 2 (SHPR2). When the SVC instruction is executed, the SVCall exception enters the pending state and waits to be serviced by the CPU. The SVCALLPENDED bit in the System Handler Control and State Register (SHCSR) can be used to check or modify the pending status of the SVCall exception. 5.4.5 PendSV Exception PendSV is another supervisor call related exception similar to SVCall, normally being software-generated. PendSV is always enabled and its priority is configurable. The PendSV exception is triggered by setting the PENDSVSET bit in the Interrupt Control State Register, CM0_ICSR. On setting this bit, the PendSV exception enters the pending state, and waits to be serviced by the CPU. The pending state of a PendSV exception can be cleared by setting the PENDSVCLR bit in the Interrupt Control State Register, CM0_ICSR. The priority of a PendSV exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_14[23:22] of the System Handler Priority Register 3 (CM0_SHPR3). See the ARMv6-M Architecture Reference Manual for more details. 5.4.6 SysTick Exception CM0 CPU in PSoC 4 supports a system timer, referred to as SysTick, as part of its internal architecture. SysTick provides a simple, 24-bit decrementing counter for various timekeeping purposes such as an RTOS tick timer, highspeed alarm timer, or simple counter. The SysTick timer can be configured to generate an interrupt when its count value reaches zero, which is referred to as SysTick exception. The exception is enabled by setting the TICKINT bit in the SysTick Control and Status Register (CM0_SYST_CSR). The priority of a SysTick exception can be configured to a value between 0 and 3 by writing to the two bit fields PRI_15[31:30] of the System Handler Priority Register 3 (SHPR3). The SysTick exception can always be generated in software at any instant by writing a one to the PENDSTSETb bit in the Interrupt Control State Register, CM0_ICSR. Similarly, the pending state of the SysTick exception can be cleared by writing a one to the PENDSTCLR bit in the Interrupt Control State Register, CM0_ICSR. Supervisor Call (SVCall) is an always-enabled exception caused when the CPU executes the SVC instruction as part of the application code. Application software uses the SVC instruction to make a call to an underlying operating system and provide a service. This is known as a supervisor call. The SVC instruction enables the application to issue a supervisor call that requires privileged access to the system. Note that the CM0 in PSoC 4 uses a privileged mode for the system call NMI exception, which is not related to the SVCall exception. (See the Chip Operational Modes chapter on 40 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Interrupts 5.5 Interrupt Sources PSoC 4 supports 32 interrupts (IRQ0 - IRQ31 or exception numbers 16 - 47) from peripherals. The source of each interrupt is listed in Table 5-3. PSoC 4 provides flexible sourcing options for each of the 32 interrupt lines. Figure 5-5 shows the multiplexing options for interrupt source. Each interrupt has two sources: a fixed-function interrupt source and a DSI interrupt source. The CPUSS_INTR_SELECT register is used to select between these sources. Figure 5-5. Interrupt Source Multiplexing Fixed Function Interrupt Source DSI Interrupt Source (irq_out[n]) Level 0 IRQn (n = 0 to 31) 0 1 Rising Edge Detect To NVIC 1 INT_CFG register INTR_SELECT register Note The DSI interrupt signal naming (irq_out[n]) is not readily accessible, but the PSoC Creator IDE simplifies the task by doing the routing of the digital signals through the DSI interrupt path. You do not need to manually configure the DSI path. The fixed-function interrupts include standard interrupts from the on-chip peripherals such as TCPWM, serial communication block,and CSD block. The fixed-function interrupt generated is usually the logical OR of the different peripheral states. The peripheral status register should be read in the ISR to detect which condition generated the interrupt. Fixed-function interrupts are usually level interrupts, which require that the peripheral status register be read in the ISR to clear the interrupt. If the status register is not read in the ISR, the interrupt will remain asserted and the ISR will be executed continuously.The second category of interrupt sources is the DSI interrupt signals. There are 32 DSI channels for the interrupts. Any digital signal on the chip, such as digital outputs from UDBs or digital input signals on pins, can be routed as DSI interrupt sources. This provides flexibility in the choice of interrupt sources. You also have the option of routing the DSI signal through a rising edge detect circuit, as shown in Figure 5-5. This edge detect circuit converts a rising edge signal on the DSI line to a pulse signal two system clocks wide. This ensures that the interrupt is triggered once on the rising edge of the signal on the DSI line. It is useful for interrupt sources, which cannot generate proper level interrupt signals to the NVIC. The UDB_INT_CFG register is used to select between the direct DSI path and the edge detect path. See the I/O System chapter on page 53 for details on GPIO interrupts. Table 5-2. List of PSoC 4 Interrupt Sources Interrupt Cortex-M0 Exception No. Fixed Function Interrupt Source DSI Interrupt Source NMI (see Exception Sources on page 39) 2 – irq_out[0] IRQ0 16 GPIO Interrupt - Port 0 irq_out[1] IRQ1 17 GPIO Interrupt - Port 1 irq_out[1] IRQ2 18 GPIO Interrupt - Port 2 irq_out[2] IRQ3 19 GPIO Interrupt - Port 3 irq_out[3] IRQ4 20 GPIO Interrupt - Port 4 irq_out[4] IRQ5 21 <DSI-only> irq_out[5] IRQ6 22 <DSI-only> irq_out[6] IRQ7 23 <DSI-only> irq_out[7] IRQ8 24 LPCOMP (low-power comparator) irq_out[8] IRQ9 25 WDT (Watchdog timer) irq_out[9] irq_out[10] IRQ10 26 SCB1 (Serial Communication Block 1) IRQ11 27 SCB2 (Serial Communication Block 2) irq_out[11] IRQ12 28 SPC (System Performance Controller) irq_out[12] IRQ13 29 PWR (Power Manager) irq_out[13] IRQ14 30 SAR (Successive Approximation ADC) irq_out[14] IRQ15 31 CSD (CapSense block counter overflow interrupt) irq_out[15] IRQ16 32 TCPWM0 (Timer/Counter/PWM 0) irq_out[16] PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 41 Interrupts Table 5-2. List of PSoC 4 Interrupt Sources Interrupt Cortex-M0 Exception No. Fixed Function Interrupt Source DSI Interrupt Source IRQ17 33 TCPWM1 (Timer/Counter/PWM 1) irq_out[17] IRQ18 34 TCPWM2 (Timer/Counter/PWM 2) irq_out[18] IRQ19 35 TCPWM3 (Timer/Counter/PWM 3) irq_out[19] IRQ20 36 <DSI-only> irq_out[20] IRQ21 37 <DSI-only> irq_out[21] IRQ22 38 <DSI-only> irq_out[22] IRQ23 39 <DSI-only> irq_out[23] IRQ24 40 <DSI-only> irq_out[24] IRQ25 41 <DSI-only> irq_out[25] IRQ26 42 <DSI-only> irq_out[26] IRQ27 43 <DSI-only> irq_out[27] IRQ28 44 <DSI-only> irq_out[28] IRQ29 45 <DSI-only> irq_out[29] IRQ30 46 <DSI-only> irq_out[30] IRQ31 47 <DSI-only> irq_out[31] 5.6 Exception Priority Exception priority is useful for exception arbitration when there are multiple exceptions that need to be serviced by the CPU. PSoC 4 provides flexibility in choosing priority values for different exceptions. All exceptions other than Reset, NMI, and HardFault can be assigned a configurable priority level. The Reset, NMI, and HardFault exceptions have a fixed priority of –3, –2, and –1 respectively. In PSoC 4, lower priority numbers represent higher priorities. This means that the Reset, NMI, and HardFault exceptions have the highest priorities. The other exceptions can be assigned a configurable priority level between 0 and 3. PSoC 4 supports nested exceptions in which a higher priority exception can obstruct (interrupt) the currently active exception handler. This pre-emption does not happen if the incoming exception priority is the same as active exception. The CPU resumes execution of the lower priority exception handler after servicing the higher priority exception. The CM0 CPU in PSoC 4 allows nesting of up to four exceptions. When the CPU receives two or more exceptions requests of the same priority, the lowest exception number is serviced first. The registers to configure the priority of exception numbers 1 to 15 are explained in Exception Sources on page 39. The priority of the 32 interrupts (IRQ0 - IRQ31) can be configured by writing to the Interrupt Priority registers (CM0_IPR). This is a group of eight 32-bit registers with each register storing the priority values of four interrupts, as given in Table 5-3. The other bit fields in the register are not used. Table 5-3. Interrupt Priority Register Bit Definitions Bits Name PRI_N0 Priority of interrupt number N. 15:14 PRI_N1 Priority of interrupt number N+1. 23:22 PRI_N2 Priority of interrupt number N+2. 31:30 PRI_N3 Priority of interrupt number N+3. 5.7 Enabling and Disabling Interrupts The NVIC provides registers to individually enable and disable the 32 interrupts in software. If an interrupt is not enabled, the NVIC will not process the interrupt requests on that interrupt line. The Interrupt Set-Enable Register (CM0_ISER) and the Interrupt Clear-Enable Register (CM0_ICER) are used to enable and disable the interrupts respectively. These registers are 32-bit wide and each bit corresponds to the same numbered interrupt. These registers can also be read in software to get the enable status of the interrupts. Table 5-4 shows the register access properties for these two registers. Note that writing zero to these registers has no effect. Table 5-4. Interrupt Enable/Disable Registers Register Operation Write Interrupt Set Enable Register (CM0_ISER) Read Interrupt Clear Write Enable Register (CM0_ICER) Read 42 Description 7:6 Bit Value Comment 1 To enable the interrupt 0 No effect 1 Interrupt is enabled 0 Interrupt is disabled 1 To disable the interrupt 0 No effect 1 Interrupt is enabled 0 Interrupt is disabled PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Interrupts The CM0_ISER and CM0_ICER registers are applicable only for the interrupts (IRQ0 - IRQ31). These registers cannot be used to enable or disable the exception numbers 1 to 11. The 15 exceptions have their own support for enabling and disabling, as explained in Exception Sources on page 39. ■ The PRIMASK register in Cortex-M0 (CM0) CPU can be used as a global exception enable register to mask all the configurable priority exceptions irrespective of whether they are enabled. Configurable priority exceptions include all the exceptions except Reset, NMI, and HardFault listed in Table 5-1. They can be configured to a priority level between 0 and 3, 0 being the highest priority and 3 being the lowest priority. When the PM bit (bit 0) in the PRIMASK register is set, none of the configurable priority exceptions can be serviced by the CPU, though they can be in the pending state waiting to be serviced by the CPU after the PM bit is cleared. When a peripheral generates an interrupt request signal to the NVIC or an exception event occurs, the corresponding exception enters the pending state. When the CPU starts executing the corresponding exception handler routine, the exception is changed from the pending state to the active state. 5.8 Exception States Each exception can be in one of the following states. The ISRPENDING bit (bit 22) in the CM0_ICSR indicates if a NVIC generated interrupt (IRQ0 to IRQ31) is in a pending state. 5.8.1 Pending Exceptions The NVIC allows software pending of the 32 interrupt lines by providing separate register bits for setting and clearing the pending states of the interrupts. The Interrupt SetPending register (CM0_ISPR) and the Interrupt ClearPending register (CM0_ICPR) are used to set and clear the pending status of the interrupt lines. These registers are 32 bits wide, and each bit corresponds to the same numbered interrupt. Table 5-6 shows the register access properties for these two registers. Note that writing zero to these registers has no effect. Table 5-5. Exception States Exception State Meaning Inactive The exception is not active and not pending. Either the exception is disabled or the enabled exception has not been triggered. Pending The exception request has been received by the CPU/NVIC and the exception is waiting to be serviced by the CPU. Active An exception that is being serviced by the CPU but whose exception handler execution is not yet complete. A high-priority exception can interrupt the execution of lower priority exception. In this case, both the exceptions are in the active state. Active and Pending The exception is being serviced by the processor and there is a pending request from the same source during its exception handler execution. The Interrupt Control State Register (CM0_ICSR) contains status bits describing the various exceptions states. ■ ■ The VECTACTIVE bits ([8:0]) in the CM0_ICSR store the exception number for the current executing exception. This value is zero if the CPU does not execute any exception handler (CPU is in thread mode). Note that the value in VECTACTIVE bit fields is the same as the value in bits [8:0] of the Interrupt Program Status Register (IPSR), which is also used to store the active exception number. Table 5-6. Interrupt Set Pending/Clear Pending Registers Register Operation Interrupt SetPending Register (CM0_ISPR) Write Read Interrupt ClearPending Register (CM0_ICPR) Write Read Bit Value Comment 1 To put an interrupt to pending state 0 No effect 1 Interrupt is pending 0 Interrupt is not pending 1 To clear a pending interrupt 0 No effect 1 Interrupt is pending 0 Interrupt is not pending Setting the pending bit when the same bit is already set results in only one execution of the ISR. The pending bit can be updated regardless of whether the corresponding interrupt is enabled. If the interrupt is not enabled, the interrupt line will not move to the pending state until it is enabled by writing to the CM0_ISER register. Note that the CM0_ISPR and CM0_ICPR registers are used only for the 32 peripheral interrupts (exception numbers 1647). These registers cannot be used for pending the exception numbers 1 to 11. These 15 exceptions have their own support for pending, as explained in Exception Sources on page 39. The VECTPENDING bits ([20:12]) in the CM0_ICSR store the exception number of the highest priority pending exception. This value is zero if there are no pending exceptions. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 43 Interrupts 5.9 Stack Usage for Exceptions When the CPU executes the main code (in thread mode) and an exception request occurs, the CPU stores the state of its general-purpose registers in the stack. It then starts executing the corresponding exception handler (in handler mode). The CPU pushes the contents of the eight 32-bit internal registers into the stack. These registers are the Program and Status Register (PSR), ReturnAddress, Link Register (LR or R14), R12, R3, R2, R1, and R0. Cortex-M0 has two stack pointers - MSP and PSP. Only one of the stack pointers can be active at a time. When in thread mode, the Active Stack Pointer bit in the Control register is used to define the current active stack pointer. When in handler mode, the MSP is always used as the stack pointer. The stack pointer in Cortex-M0 always grows downwards and points to the address that has the last pushed data. When the CPU is in thread mode and an exception request comes, the CPU uses the stack pointer defined in the control register to store the general-purpose register contents. After the stack push operations, the CPU enters handler mode to execute the exception handler. When another higher priority exception occurs while executing the current exception, the MSP is used for stack push/pop operations, because the CPU is already in handler mode. See the Cortex-M0 CPU chapter on page 35 for details. 5.10 Interrupts and Low-Power Modes PSoC 4 allows device wakeup from low-power modes when certain peripheral interrupt requests are generated. The Wakeup Interrupt Controller (WIC) block generates a wakeup signal that causes the device to enter Active mode when one or more wakeup sources generate an interrupt signal. After entering Active mode, the ISR of the peripheral interrupt is executed. The Wait For Interrupt (WFI) instruction, executed by the CM0 CPU, triggers the transition into Sleep, Deep-Sleep, and Hibernate modes. The sequence of entering the different low-power modes is detailed in the Power Modes chapter on page 75. Chip low-power modes have three categories of fixed-function interrupt sources: ■ Fixed-function interrupt sources that are available in the Active, Deep-Sleep, and Hibernate modes (GPIO interrupts, low-power comparators). ■ Fixed-function interrupt sources that are available only in the Active and Deep-Sleep modes (watchdog timer interrupt, and serial communication block interrupts) ■ Fixed-function interrupt sources that are available only in the Active mode (all other fixed-function interrupts) The Cortex-M0 uses two techniques, tail chaining and late arrival, to reduce latency in servicing exceptions. These techniques are not visible to the external user and are done as part of the internal processor architecture (infocenter.arm.com/help/topic/com.arm.doc.ddi0419c/ index.html). 44 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Interrupts 5.11 Exception - Initialization and Configuration This section covers the different steps involved in initializing and configuring exceptions in PSoC 4. 1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location as required - either in flash memory or SRAM. This configuration is done by writing either a ‘1’ (SRAM vector table) or ‘0’ (flash vector table) to the VECT_IN_RAM bit field (bit 0) in the CPUSS_CONFIG register. This register write is done as part of device initialization code. It is recommended that the vector table be available in SRAM if the application needs to change the vector addresses dynamically. If the table is located in flash, then a flash write operation is required to modify the vector table contents. PSoC Creator IDE uses the vector table in SRAM by default. 2. Configuring Individual Exceptions: The next step is to configure individual exceptions required in an application. a. Configure the exception or interrupt source; this includes setting up the interrupt generation conditions. The register configuration depends on the specific exception required. b. Define the exception handler function and write the address of the function to the exception vector table. Table 5-1 gives the exception vector table format; the exception handler address should be written to the appropriate exception number entry in the table. c. Set up the exception priority, as explained in Exception Priority on page 42. d. Enable the exception, as explained in Enabling and Disabling Interrupts on page 42. 5.12 Registers Table 5-7. List of Registers Register Name Description CM0_ISER Interrupt Set-Enable Register CM0_ICER Interrupt Clear Enable Register CM0_ISPR Interrupt Set-Pending Register CM0_ICPR Interrupt Clear-Pending Register CM0_IPR Interrupt Priority Registers CM0_ICSR Interrupt Control State Register CM0_AIRCR Application Interrupt and Reset Control Register CM0_SCR System Control Register CM0_CCR Configuration and Control Register CM0_SHPR2 System Handler Priority Register 2 CM0_SHPR3 System Handler Priority Register 3 CM0_SHCSR System Handler Control and State Register CM0_SYST_CSR Systick Control and Status CPUSS_CONFIG CPU Subsystem Configuration CPUSS_SYSREQ System Request Register CPUSS_INTR_SELECT Interrupt Multiplexer Select Register UDB_INT_CFG UDB Subsystem Interrupt Configuration 5.13 ■ Associated Documents ARMv6-M Architecture Reference Manual - This document explains the ARM Cortex-M0 architecture, including the instruction set, NVIC architecture, and CPU register descriptions. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 45 Interrupts 46 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section C: Memory System This section presents the following chapter: ■ Memory Map chapter on page 49 Top Level Architecture Memory System Block Diagram SPCIF FLASH 32 KB SRAM 4 kB SROM 4 kB Read Accelerator SRAM Controller ROM Controller System Interconnect (Single Layer AHB) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 47 48 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 6. Memory Map All PSoC® 4 memory (flash, SRAM, and SROM) and all registers are accessible by the CPU and in most cases by the debug system. This chapter contains an overall map of the addresses of the memories and registers. 6.1 Features The PSoC 4 memory system has the following features: ■ 32K bytes flash, 4K bytes SRAM ■ 4K byte SROM contains boot and configuration routines ■ ARM Cortex-M0 32-bit linear address space, with regions for code, SRAM, peripherals, and CPU internal registers ■ Flash is mapped to the Cortex-M0 code region ■ SRAM is mapped to the Cortex-M0 SRAM region ■ Peripheral registers are mapped to the Cortex-M0 peripheral region ■ The Cortex-M0 Private Peripheral Bus (PPB) region includes registers implemented in the CPU core. These include registers for NVIC, SysTick timer, and serial communication block (SCB). For more information, see the Cortex-M0 CPU chapter on page 31. 6.2 How It Works The PSoC 4 memory map is detailed in the following tables. For additional information, refer to the PSoC 4100/4200 Family: PSoC 4 Registers TRM. The ARM Cortex-M0 has a fixed address map allowing access to memory and peripherals using simple memory access instructions. The 32-bit (4 GB) address space is divided into the regions shown in Table 6-1. Note that code can be executed from the code and SRAM regions. Table 6-1. Cortex-M0 Address Map Address Range Name Use 0x00000000 – 0x1FFFFFFF Code Executable region for program code. You can also put data here. Includes the exception vector table, which starts at address 0. 0x20000000 – 0x3FFFFFFF SRAM Executable region for data. You can also put code here. 0x40000000 – 0x5FFFFFFF Peripheral All peripheral registers. Code cannot be executed out of this region. 0x60000000 – 0xDFFFFFFF – Not used 0xE0000000 – 0xE00FFFFF PPB Peripheral registers within the CPU core. 0xE0100000 – 0xFFFFFFFF Device PSoC 4 implementation-specific. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 49 Memory Map Table 6-2 shows the PSoC 4 address map. Table 6-2. PSoC 4 Address Map Address Range Use 0x00000000 - 0x00007FFF 32 KB flash 0x10000000 - 0x10000FFF 4 KB supervisory flash 0x20000000 - 0x20000FFF 4 KB SRAM 0x40000000 - 0x4000FFFF CPU subsystem registers 0x40010000 - 0x40010FFF I/O port control (high-speed I/O matrix) registers 0x40020000 - 0x4002FFFF Programmable clocks registers 0x40040000- -0x4004FFFF I/O port registers 0x40050000- -0x40050FFF TCPWM registers 0x40060000- -0x4006FFFF SCB registers 0x40080000- -0x4008FFFF CapSense registers 0x40090000- -0x4009FFFF LCD registers 0x400A0000- -0x400AFFFF Low-power comparator registers 0x400B0000- -0x400BFFFF Power, clock, reset control registers 0x400F0000- -0x400FFFFF UDB control registers (available only in PSoC 4200 family) 0xE0000000 - 0xE00FFFFF Cortex-M0 PPB registers 0xF0000000 - 0xF0000FFF CoreSight ROM 50 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section D: System-Wide Resources This section encompasses the following chapters: ■ I/O System chapter on page 53 ■ Clocking System chapter on page 63 ■ Power Supply and Monitoring chapter on page 71 ■ Chip Operational Modes chapter on page 77 ■ Power Modes chapter on page 79 ■ Watchdog Timer chapter on page 85 ■ Reset System chapter on page 89 ■ Device Security chapter on page 93 Top Level Architecture System-Wide Resources Block Diagram System Resources Power Sleep Control LVD REF BOD PWRSYS NVLatches Clock Clock Control WDT IMO ILO Peripheral Interconnect (MMIO) WIC POR Reset Reset Control XRES PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 51 52 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 7. I/O System This chapter explains the PSoC® 4 I/O system, its features, architecture, operating modes, and interrupts. The generalpurpose I/O (GPIOs) pins in PSoC 4 are grouped into ports; a port can have a maximum of eight GPIOs. The PSoC 4100/ 4200 family has a maximum of 36 GPIOs arranged in five ports. 7.1 Features The PSoC 4 GPIOs have these features: ■ Analog and digital input and output capabilities ■ Eight drive strength modes ■ Edge-triggered interrupts on rising edge, falling edge, or on both the edges, on pin basis ■ Slew rate control ■ Hold mode for latching previous state (used for retaining I/O state in Deep-Sleep mode) ■ Selectable CMOS and low-voltage LVTTL input buffer mode ■ Capsense Support ■ Segment LCD drive support 7.2 GPIO Interface Overview PSoC 4 is equipped with analog and digital peripherals. Figure 7-1 shows an overview of routing between the peripherals and pins. Figure 7-1. GPIO Interface Overview GPIO Port Control GPIO Pin Interface GPIO Interrupt GPIO Configuration CSD Controller Segment LCD Control Fixed Function Digital Peripherals UDB Array Port Adapter DSI High Speed IO Matrix (HSIOM) IO Cell CapSense SARMUX, CTBm, LPCOMP Pin AMUXBUS-A AMUXBUS-B GPIO pins are connected to I/O cells. These cells are equipped with an input buffer for the digital input, providing high input impedance and a driver for the digital output signals. The digital peripherals connect to the I/O cells via the high-speed I/O PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 53 I/O System matrix (HSIOM). HSIOM contains multiplexers to connect between a peripheral selected by the user and the pin. HSIOM also bridges the connection between the digital system interconnect (DSI) and the pins. This enables routing of pin signals to the DSI-connected peripherals such as UDBs. The analog peripherals such as SAR ADC, Continuous Time Block-mini (CTBm), Low Power Comparator (LPCOMP), and CapSense are either connected to the GPIO pins directly or through the AMUX buses. 7.3 I/O Cell Architecture Figure 7-2 shows the I/O cell architecture. It comprises of an input buffer and an output driver. This architecture is present in every GPIO cell. It connects to the HSIOM multiplexers for the digital input and the output signal. Analog peripherals connect directly to the pin. Figure 7-2. I/O Cell Architecture in PSoC 4100/4200 IO CELL PORT_VTRIP_SEL (GPIO_PRTx_PC[24]) INP_DIS (GPIO_PRTx_PC2[y]) EDGE_SEL (GPIO_PRTx_INTCFG[2y+1:2y]) GPIO Edge Detect DATA (GPIO_PRTx_INTSTAT[y]) Digital Input Path Pin Interrupt Signal Input Buffer Buffer Mode Select -------------------------CMOS LVTTL Disable DSI DATA (GPIO_PRTx_PS[y]) SCB (SPI, I2C, UART) HSIOM HSIOM_PORT_SELx[4y+3:4y] 4 Input Buffer Output Driver PORT_SLOW (GPIO_PRTx_PC[25]) HSIOM_PORT_SELx[4y+3:4y] 4 HSIOM GPIO_PRTx_DR[y] GPIO_DSI Digital Output Path DSI_DSI DSI_GPIO ACTIVE_0 (TCPWM) VDDD VDDD ACTIVE_1 (SCB) In ACTIVE_2 (Reserved) VDDD ACTIVE_3 (Reserved) DEEP_SLEEP_0 (LCD - COM) Digital Logic DEEP_SLEEP_1 (LCD-SEG) PIN Slew Control DEEP_SLEEP_2 DEEP_SLEEP_3 VSS GPIO_PRTx_PC[3y+2:3y] 3 Drive Mode OUTPUT ENABLE VSS VSS OE Analog Dedicated Analog Resources (CTBm, LPCOMP, SAR ADC) HSIOM_PORT_SELx[4y+3:4y] 4 Switches AMUXBUS-A (CapSense Source) AMUXBUS-B (CapSense Shield) x – Port Number y – Pin Number 54 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D I/O System 7.3.1 Digital Input Buffer 7.3.2 The digital input buffer provides a high-impedance buffer for the external digital input. The buffer is enabled and disabled by the INP_DIS bit of the Port Configuration Register 2 (GPIO_PRTx_PC2, where x is the port number). The buffer is configurable for the following modes: ■ CMOS ■ LVTTL These buffer modes are selected by the PORT_VTRIP_SEL bit (GPIO_PRTx_PC[24]) of the Port Configuration register. Table 7-1. Input Buffer Modes PORT_VTRIP_SEL Input Buffer Mode 0b CMOS 1b LVTTL The threshold values for each mode can be obtained from the device datasheet. The output of the input buffer is connected to the HSIOM for routing to the selected peripherals. Writing to the HSIOM port select register (HSIOM_PORT_SELx) selects the peripheral. The digital input peripherals in the HSIOM, shown in Figure 7-2, are pin dependent. See the device datasheet to know the functions available for each pin. Digital Output Driver Pins are driven by the digital output driver. It consists of circuitry to implement different drive modes and slew rate control for the digital output signals. The peripheral connects to the digital output driver through the HSIOM; a particular peripheral is selected by writing to the HSIOM port select register (HSIOM_PORT_SELx). In PSoC4100/4200, I/Os are driven with VDDD supply. Each GPIO pin has ESD diodes to clamp the pin voltage to the I/O supply source. Ensure that the voltage at the pin does not exceed the I/O supply voltage /VDDD and drop below VSS under any circumstances. For the absolute maximum and minimum GPIO voltage, see the device datasheet. The digital output driver can be enabled and disabled using the DSI signal from the peripheral or the data register (GPIO_PRTx_DR) associated with the output pin. See section 7.4 High-Speed I/O Matrix to know about the peripheral source selection for the data and to enable/ disable control source selection. 7.3.2.1 Drive Modes Each I/O is individually configurable into one of the eight drive modes using the Port Configuration Register, GPIO_PRTx_PC. Drive modes are listed in Table 7-2. Figure 7-2 is a simplified output driver diagram that shows the pin view based on each of the eight drive modes. Table 7-2. Drive Mode Settings GPIO_PRTx_PC ('x' denotes port number and 'y' denotes pin number) Bits Drive Mode Value 3y+2: 3y Data = 1 Data = 0 Selects Drive Mode for Pin 'y' (0 y 7) SEL'y’ High-Impedance Analog 0 High Z High Z High-impedance Digital 1 High Z High Z Resistive Pull Up 2 Weak 1 Strong 0 Resistive Pull Down 3 Strong 1 Weak 0 Open Drain, Drives Low 4 High Z Strong 0 Open Drain, Drives High 5 Strong 1 High Z Strong Drive 6 Strong 1 Strong 0 Resistive Pull Up and Down 7 Weak 1 Weak 0 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 55 I/O System Figure 7-3. I/O Drive Mode Block Diagram Vdd DR PS Pin 0 . High Impedance Analog DR PS Pin 1 . High Impedance Digital DR PS Pin 2 . Resistive Pull Up Vdd DR PS 4 . Open Drain, Drives Low ■ Pin DR PS Pin 5 . Open Drain, Drives High High-Impedance Analog To achieve the lowest device current in low-power modes, unused GPIOs must be configured to the high-impedance analog mode. High-Impedance Digital High-impedance digital mode is the standard highimpedance (High Z) state recommended for digital inputs. In this state, the input buffer is enabled for digital input signals. ■ Resistive Pull-Up or Resistive Pull-Down Resistive modes provide a series resistance in one of the data states and strong drive in the other. Pins can be used for either digital input or digital output in these modes. If resistive pull-up is required, a ‘1’ must be written to that pin’s Data Register bit. If resistive pull-down is required, a ‘0’ must be written to that pin’s Data Register. Interfacing mechanical switches is a common application of these drive modes. The resistive modes are also used to interface PSoC with open drain drive lines. Resistive pull-up is used when input is open drain low and resistive pull-down is used when input is open drain high. ■ Open Drain Drives High and Open Drain Drives Low Open drain modes provide high impedance in one of the 56 DR PS DR PS Pin 3 . Resistive Pull Down Vdd High-impedance analog mode is the default reset state; both output driver and digital input buffer are turned off. This state prevents an external voltage from causing a current to flow into the digital input buffer. This drive mode is recommended for pins that are floating or that support an analog voltage. High-impedance analog pins cannot be used for digital inputs. Reading the pin state register returns a 0x00 regardless of the data register value. ■ Vdd Vdd Pin DR PS Pin 7 . Resistive Pull Up and Pull Down 6 . Strong Drive data states and strong drive in the other. The pins can be used as digital input or output in these modes. Therefore, these modes are widely used in bi-directional digital communication. Open drain drive high mode is used when signal is externally pulled down and open drain drive low is used when signal is externally pulled high. A common application for open drain drives low mode is driving I2C bus signal lines. ■ Strong Drive The strong drive mode is the standard digital output mode for pins; it provides a strong CMOS output drive in both high and low states. Strong drive mode pins must not be used as inputs under normal circumstances. This mode is often used for digital output signals or to drive external transistors. ■ Resistive Pull-Up and Resistive Pull-Down In the resistive pull-up and resistive pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output states. The high data state is pulled up while the low data state is pulled down. This mode is used when the bus is driven by other signals that may cause shorts. 7.3.2.2 Slew Rate Control GPIO pins have fast and slow output slew rate options in strong drive mode; this is configured using PORT_SLOW bit of the Port Configuration register (GPIO_PRTx_PC[25]). Slew rate is individually configurable for each port. This bit is cleared by default and the port works in fast slew mode. This bit can be set if a slow slew rate is required. Slower slew rate results in reduced EMI and crosstalk; hence, the slow option is recommended for low-frequency signals or signals without strict timing constraints. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D I/O System 7.4 High-Speed I/O Matrix The high-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the peripherals inside the device. As the GPIOs are shared for multiple functions, HSIOM multiplexes the pin and connects to a particular peripheral selected by the user. The HSIOM_PORT_SELx register is provided to select the peripheral. It is a 32-bit wide register available for each port, with each pin occupying four bits. This provides up to 16 different options for a pin as listed in Table 7-3. Table 7-3. PSoC 4100/4200 HSIOM Port Settings HSIOM_PORT_SELx ('x' denotes port number and 'y' denotes pin number) Bits 4y+3 : 4y Name (SEL'y') Description (Selects pin 'y' source ((0 y 7) Value DR 0 Pin is regular firmware-controlled I/O or connected to dedicated hardware block. DR_DSI 1 Output is firmware controlled, but OE is controlled from DSI. DSI_DSI 2 Both output and OE are controlled from DSI. DSI_DR 3 Output is controlled from DSI, but OE is firmware controlled. CSD_SENSE 4 Pin is a CSD sense pin (analog mode). CSD_SHIELD 5 Pin is a CSD shield pin (analog mode). AMUXA 6 Pin is connected to AMUXBUS-A. AMUXB 7 Pin is connected to AMUXBUS-B. This mode is also used for CSD I/O charging. When CSD I/O charging is enabled in CSD_CONTROL, digital I/O driver is connected to csd_charge signal (pin is still connected to AMUXBUS-B). ACTIVE_0 8 Pin-specific Active source #0 (TCPWM). ACTIVE_1 9 Pin-specific Active source #1 (SCB-UART). ACTIVE_2 10 Reserved ACTIVE_3 11 Reserved DEEP_SLEEP_0 12 Pin-specific Deep-Sleep source #0 (LCD - COM) DEEP_SLEEP_1 13 Pin-specific Deep-Sleep source #1 (LCD - SEG) DEEP_SLEEP_2 14 Pin-specific Deep-Sleep source #2 (SCB-I2C, SWD). DEEP_SLEEP_3 15 Pin-specific Deep-Sleep source #3 (SCB-SPI). Note The Active and Deep-Sleep sources are pin dependent. See the “Pinouts” section of the device datasheet for more details on the features supported by each pin. 7.5 I/O State on Power Up During power up all the GPIOs are in high-impedance analog state and the input buffers are disabled. During run time, GPIOs can be configured by writing to the associated registers. Note that the pins supporting debug access port (DAP) connections (SWD lines) are always enabled as SWD lines during power-up. However, the DAP connection can be disabled or reconfigured for general-purpose use through HSIOM. However, this reconfiguration takes place only after the device boots and start executing code. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 57 I/O System 7.6 Behavior in Low-Power Modes Table 7-4 shows the status of GPIOs in low-power modes. Table 7-4. PSoC 4100/4200 GPIO in Low-Power Modes Low-Power Mode Status ■ Sleep ■ ■ Deep-Sleep ■ Hibernate Stop 7.7 ■ ■ ■ ■ GPIOs are active and can be driven by peripherals such as CapSense, TCPWM, and SCB, which can work in sleep mode. Input buffers are active; thus an interrupt on any I/O can be used to wake up the CPU. GPIOs connected to the deep-sleep domain peripherals are functional. Other pins, with its output enabled, are in the frozen state. Pin interrupts are functional on all I/Os. GPIO output pin states are latched and remain in the frozen state. Pin interrupts are functional on all I/Os. GPIO output pin states are latched and remain in the frozen state. Interrupt on only port P0[7] wakes up the device. Input and Output Synchronization For digital input and output signals, the I/O provides synchronization with an internal clock or a digital signal as clock. By default, HFCLK is used for synchronization but any other clock can also be used. This feature is implemented using the UDB port adapter. See the Universal Digital Blocks (UDB) chapter on page 131 for details on the port adapter. 7.8 Interrupt In the PSoC 4 device, all the port pins have the capability to generate interrupts. There are three routing possibilities for the pin signals to generate the interrupt, as shown in Figure 7-4. Figure 7-4. Interrupt Signal Routing DSI route Pin Signal from HSIOM Port Adapter GPIO Edge Detect DSI Fixed function route To the Interrupt Source Multiplexer ■ Through the “GPIO Edge Detect” block and direct connection to the interrupt source multiplexer ■ Through the “GPIO Edge Detect” block and to the interrupt source multiplexer via DSI ■ Pin signal to the interrupt source multiplexer via DSI bypassing the “GPIO Edge Detect” block Figure 7-5 shows the GPIO Edge Detect block architecture. 58 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D I/O System Figure 7-5. GPIO Edge Detect Block Architecture 50 ns Glitch Filter Edge Detector Pin 0 Edge Detector Pin 1 Edge Detector Pin 2 Edge Detector Pin 3 Edge Detector Pin 4 Edge Detector Pin 5 Edge Detector Pin 6 Edge Detector Pin 7 Edge Detector An edge detector is present at each pin. It is capable of detecting rising edge, falling edge, and both the edges without any reconfiguration. The edge detector is configured by writing into the EDGE_SEL bits of the Port Interrupt Configuration register GPIO_PRTx_INTCFG as shown in Table 7-5. Table 7-5. Edge Detector Configuration EDGE_SEL Configuration 00 Interrupt is disabled 01 Interrupt on Rising Edge 10 Interrupt on Falling Edge 11 Interrupt on Both Edges Writing ‘1’ to the corresponding status bit clears the pin interrupt. It is important to clear the interrupt status bit; otherwise, the interrupt will occur repeatedly for a single trigger or respond only once for multiple triggers, which is explained later in this section. Also, note that when the Port Interrupt Control Status register is read at the same time an interrupt is occurring on the corresponding port, it can result in the interrupt not being properly detected. Therefore, when using GPIO interrupts, it is recommended to read the status register only inside the corresponding interrupt service routine and not in any other part of the code. Table 7-7 shows the Port Interrupt Status register bit fields. Table 7-7. Port Interrupt Status Register GPIO_PRTx_INTSTAT Besides the pins, edge detector is also present at the glitch filter output. This filter can be used on one of the pins of a port. The selection of a pin is done by writing to the FLT_SEL field of the Port Interrupt Configuration register GPIO_PRTx_INTCFG as shown in Table 7-6. Table 7-6. Glitch filter Input Selection FLT_SEL Selected Pin 000 Pin 0 is selected 001 Pin 1 is selected 010 Pin 2 is selected 011 Pin 3 is selected 100 Pin 4 is selected 101 Pin 5 is selected 110 Pin 6 is selected 111 Pin 7 is selected The edge detector outputs of a port are ORed together and then routed to the interrupt controller (NVIC in the CPU subsystem). Thus, there is only one interrupt vector per port. On a pin interrupt, it is required to know which pin caused an interrupt. This is done by reading the Port Interrupt Status register GPIO_PRTx_INTSTAT. This register not only includes the information on which pin triggered the interrupt, it also includes the pin status; thus allowing the CPU to read both the information in a single read operation. This register has one more important use; that is, to clear the interrupt. Interrupt Signal 0000b to 0111b Description Interrupt status on pin 0 to pin 7. Writing ‘1’ to the corresponding bit clears the interrupt 1000b Interrupt status from the glitch filter 10000b to 10111 Pin 0 to Pin 7 status 11000b Glitch filter output status The edge detector block output is routed to the Interrupt Source Multiplexer shown in Figure 5-3 on page 38, which gives an option of Level and Rising Edge detect. If the Level option is selected, an interrupt is triggered repeatedly as long as the Port Interrupt Status register bit is set. If the Rising Edge detect option is selected, an interrupt is triggered only once if the Port Interrupt Status register is not cleared. Thus, it is important to clear the interrupt status bit if the Edge Detect block is used. There is a dedicated interrupt vector for each port when the interrupt signal is routed through the fixed-function route. However, when the signal is routed though the DSI, interrupt vector is flexible and can occupy any of the 32 interrupt lines of the NVIC. See the Interrupts chapter on page 37 for details. When the signal is routed to the DSI, bypassing the Edge Detect block, the edge detection is configurable in the Interrupt Source Multiplexer block. It is important to note that if the multiplexer is configured as Level, the interrupt is triggered repeatedly as long as the pin signal is high. It is recommended to use the Rising Edge detect option when this route is selected. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 59 I/O System 7.9 7.9.1 Peripheral Connections Firmware Controlled GPIO See Table 7-3 to know the HSIOM settings for a firmware controlled GPIO. GPIO_PRTx_DR is the data register used to read and write the output data for the GPIOs. A write operation to this register changes the GPIO output to the written value. Note that a read operation reflects the output data written to this register and not the current state of the GPIOs. Using this register, read-modify-write sequences can be safely performed on a port that has both input and output GPIOs. GPIO_PRTx_PS is the port I/O pad register that provides the state of the GPIOs when read. Writes to this register have no effect. 7.9.2 Analog I/O Analog resources, such as LPCOMP, SARMUX, and CTBm, which require low-impedance routing paths have dedicated pins. Dedicated analog pins provide direct connections to specific analog blocks. They help improve performance and should be given priority over other pins when using these analog resources. See the device datasheet for details on these dedicated pins of PSoC 4. To configure a GPIO as a dedicated analog I/O, it should be configured in high-impedance analog mode (see Table 7-2) and the respective connection should be enabled in the specific analog resource. This can be done via registers associated with the respective analog resources. To configure a GPIO as an analog pin connecting to AMUXBUS, it should be configured in high-impedance analog mode and then routed to AMUXBUS using the HSIOM_PORT_SELx register. 7.9.2.1 AMUXBUS Connection and DSI AMUXBUS A/B requires the user to configure a couple of DSI signals in addition to configuring the HSIOM_PORT_SELx register. The DSI output and the DSI output enable signal of the pin should be set high to enable the AMUXBUS connection. This option allows the use of DSI signals to control the AMUXBUS connection on a pin, thus enabling the user to implement hardware AMUXBUS switching through DSI. To properly configure a pin as AMUXBUS input, follow these steps: 1. Route the DSI output and DSI output enable signals out of the pin in the design and connect them to logic '1' for static AMUXBUS connection. The signals can be connected to a selection signal from DSI, if dynamic AMUXBUS connection is required in the design. This can be done within the device. 2. Configure the GPIO_PRTx_PC register to set the pin in Hi-Z analog mode – this enables the analog connectivity on the pin by disabling the input buffer. 3. Configure the HSIOM_PRT_SELx register to connect the pin to AMUXBUS A or B. 7.9.3 LCD Drive All GPIOs have the capability of driving an LCD common or segment. HSIOM_PORT_SELx registers are used to select the pins for LCD drive. See the LCD Direct Drive chapter on page 243 for details. 7.9.4 CapSense The pins that support CSD can be configured as CapSense widgets such as buttons, slider elements, touchpad elements, or proximity sensors. CapSense also requires external tank capacitors and shield lines. Table 7-8 shows the GPIO and HSIOM settings required for CapSense. See the CapSense chapter on page 255 for more information. In ports that support DSI connectivity, connecting a pin to Table 7-8. CapSense Settings CapSense Pin Sensor Shield CMOD (normal operation) CMOD (GPIO precharge, only available in select GPIO) CSH TANK (GPIO precharge, only available in select GPIO) 60 GPIO Drive Mode (GPIO_PRTx_PC) Digital Input Buffer Setting (GPIO_PRTx_PC2) HSIOM Setting High-Impedance Analog High-Impedance Analog High-Impedance Analog Disable Buffer Disable Buffer Disable Buffer CSD_SENSE CSD_SHIELD AMUXBUS A or CSD_COMP High-Impedance Analog Disable Buffer AMUXBUS B or CSD_COMP High-Impedance Analog Disable Buffer AMUXBUS B or CSD_COMP PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D I/O System 7.9.5 Serial Communication Block (SCB) SCB, which can be configured as UART, I2C, and SPI, has dedicated connections to the pin. See the device datasheet for details on these dedicated pins of PSoC 4. When the UART and SPI mode is used, the SCB controls the digital output buffer drive mode for the input pin to keep the pin in the high-impedance state. That is, the SCB block disables the output buffer at the UART Rx pin and MISO pin when configured as SPI master, and MOSI and select line when configured as SPI slave. This overrides the drive mode settings, which is done using the GPIO_PRTx_PC register. 7.10 Port Restrictions Port 4 and higher ports do not have the port adapter resulting in the following restrictions: ■ Cannot be routed through the DSI; thus UDB-based digital signals cannot be routed to the pins of these ports ■ No input/output synchronization ■ Cannot be used for analog blocks - SAR ADC, continuous time block - mini (CTBm) and low-power comparator (LPCOMP) However, these ports can be used in the following ways: ■ As GPIO controlled in firmware ■ Direct connection to TCPWM, SCB, or CAN ■ LCD and CapSense pins ■ Interrupts generation 7.11 Registers Table 7-9. I/O Registers Name Description GPIO_PRTx_DR Port Output Data Register GPIO_PRTx_PS Port Pin State Register - Reads the logical pin state of I/O GPIO_PRTx_PC Port Configuration Register - Configures the output drive mode, input threshold, and slew rate GPIO_PRTx_PC2 Port Secondary Configuration Register - Configures the input buffer of I/O pin GPIO_PRTx_INTCFG Port Interrupt Configuration Register GPIO_PRTx_INTSTAT Port Interrupt Status Register HSIOM_PORT_SELx HSIOM Port Selection Register Note The 'x' in the GPIO register name denotes the port number. For example, GPIO_PTR1_DR is the Port 1 output data register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 61 I/O System 62 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 8. Clocking System The PSoC® 4 clock system includes these clock resources: ■ Two internal clock sources: ❐ 3–48 MHz internal main oscillator (IMO) ±2 percent across all frequencies with trim ❐ 32-kHz internal low-speed oscillator (ILO) with ±60 percent accuracy with trim (can be calibrated using the IMO) ■ External clock (EXTCLK) generated using a signal from an I/O pin ■ High-frequency clock (HFCLK) of up to 48 MHz, selected from IMO orexternal clock ■ Low-frequency clock (LFCLK) sourced by ILO ■ Dedicated prescaler for system clock (SYSCLK) of up to 48 MHz sourced by HFCLK ■ Four peripheral clock dividers, each containing three chainable 16-bit dividers ■ Sixteen digital and analog peripheral clocks 8.1 Block Diagram Figure 8-1 gives a generic view of the clocking system in PSoC 4 devices. Figure 8-1. Clocking System Block Diagram IMO HFCLK SYSCLK Prescaler SYSCLK Cortex-M0 CPU EXTCLK Peripheral Divider 0 LFCLK ILO WDT Peripheral Divider 1 ... Peripheral Divider 2 Peripheral Clock 0 x16 Peripheral Divider 3 The three clock sources in the device are IMO, EXTCLK, and ILO, as shown in Figure 8-1. The HFCLK mux selects the HFCLK source from the EXTCLK or the IMO. The ILO sources the LFCLK. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 63 Clocking System 8.2 Clock Sources Table 8-1. IMO Frequency Configuration 8.2.1 The internal main oscillator operates with no external components and outputs a stable clock at frequencies spanning 3–48 MHz in 1-MHz increments. Frequencies are selected by setting the frequency in the CLK_IMO_TRIM2 register, setting the IMO trim in the CLK_IMO_TRIM1 register, and finally setting the bandgap trim in PWR_BG_TRIM4 and PWR_BG_TRIM5 registers The frequency setting in CLK_IMO_TRIM2 determines the IMO frequency output. Table 8-1 provides the setting corresponding to the IMO frequency output. In addition to setting the frequency in CLK_IMO_TRIM2, the user needs to load corresponding trim values in the CLK_IMO_TRIM1, PWR_BG_TRIM4, and PWR_BG_TRIM5. Frequency selection follows an algorithm to ensure no intermediate state is programmed to a value higher than 48 MHz. Each PSoC device has IMO trim settings determined during manufacturing to meet datasheet specifications; the trim is stored in manufacturing configuration data in SFLASH. There are TRIM values corresponding to the frequency selected by the user. The TRIM values from SFLASH are loaded in the corresponding trim register – CLK_IMO_TRIM1, PWR_BG_TRIM4, and PWR_BG_TRIM5. These values may be loaded at startup to achieve the desired configuration. Firmware can retrieve these trim values and reconfigure the device to change the frequency at run-time. To configure the IMO frequency, follow this algorithm: ■ If ((new_freq >= 43 MHz) and (old_freq >= 43MHz)), Change CLK_IMO_TRIM2 to a lower frequency such as 24 MHz Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and PWR_BG_TRIM5 for the new_freq Wait >= 5us Change CLK_IMO_TRIM2 to new_freq ■ else if (new_freq > old_freq), Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and PWR_BG_TRIM5 for new_freq Wait >= 5us Change CLK_IMO_TRIM2 to new_freq ■ else Change CLK_IMO_TRIM2 to new_freq Wait >= 5 cycles Apply CLK_IMO_TRIM1, PWR_BG_TRIM4, and PWR_BG_TRIM5 for new_freq 64 CLK_IMO_TRIM2 Internal Main Oscillator Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency in MHz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Clocking System 8.2.1.1 Startup Behavior After reset, the IMO is configured for 24-MHz operation. During the “boot” portion of startup, trim values are read from flash and the IMO is configured to achieve datasheet specified accuracy. 8.2.1.2 IMO Frequency Spread The IMO is capable of operating in a spread-spectrum mode to reduce the amplitude of noise generated at the IMO’s central operating frequency. This mode causes the IMO to vary in frequency across one of four distributions selected by a register. The four distribution options are fixed frequency, triangle wave, pseudo-random, and DSI input. The DSI input mode allows you to specify the pattern with a digital signal. The distribution options are selected with register CLK_IMO_SPREAD bits SS_MODE, which are shown in Table 8-2. The limits of the distribution are defined with register CLK_IMO_SPREAD bits SS_RANGE, which are shown in Table 8-3. All spread options are downspread, meaning that instantaneous clock frequency values are always at or below the configured frequency. Table 8-2. IMO Spread-Spectrum Distribution Mode Bits SS_MODE Name Description IMO spread-spectrum mode. Defines the shape of the spread-spectrum frequency distribution. 0: Off. IMO frequency is not changed. SS_MODE[1:0] 1: Triangle. IMO frequency forms a triangular distribution about the center frequency. Count limits are defined by bits SS_MAX. 2: Pseudo-random sequence using LFSR. IMO frequency forms a pseudo-random distribution about the center frequency. 3: DSI. IMO frequency distribution is determined using a DSI input signal. Table 8-3. IMO Spread Spectrum Distribution Range Bits SS_RANGE Name Description IMO spread-spectrum maximum range. Defines the frequency spread from nominal at the extreme count values of the spread-spectrum’s counter. 0: 1%. Spread-spectrum varies in frequency from 0 to –1% at the extreme count values. SS_RANGE[1:0] 1: 2%. Spread-spectrum varies in frequency from 0 to –2% at the extreme count values. 2: 4%. Spread-spectrum varies in frequency from 0 to –4% at the extreme count values. 3: Reserved. Do not use. The SS_MAX field in the CLK_IMO_SPREAD register sets the maximum count for the spread spectrum counters. Increasing this value increases the entire cycle time of a triangular spread when the SS_MODE is set to a triangular spread. The IMO spread spectrum logic requires a clock to be routed to it for functionality. The logic uses the peripheral clock 0 as its clock. The IMO spread spectrum needs the peripheral clock 0 to be routed with an appropriate clock from a peripheral clock divider. The frequency of this clock will determine the rate of the spread spectrum logic and hence the rate of change of the frequency. 8.2.1.3 Programming Clock (36-MHz) The IMO block has a 36-MHz output, which is used as clock for the flash programming block. This clock is only available for the flash programming block and is not available as a clock source into any of the clock dividers or the clock tree. 8.2.2 Internal Low-speed Oscillator The internal low-speed oscillator operates with no external components and outputs a stable clock at 32-kHz nominal. The ILO is relatively low power and low accuracy. It can be calibrated using a higher accuracy, high-frequency clock to improve accuracy. The ILO is available in all power modes except Hibernate and Stop modes. The ILO is always used as the system low-frequency clock LFCLK in PSoC 4. The ILO is a relatively inaccurate (±60 percent overvoltage and temperature) oscillator, which is used to generate lowfrequency clocks. If calibrated against the IMO when in operation, the ILO is accurate to ±10 percent for stable temperature and voltage.The ILO is enabled and disabled with register CLK_ILO_CONFIG bit ENABLE. 8.2.3 External Clock (EXTCLK) The external clock (EXTCLK) is a MHz range clock that can be generated from a signal on a designated PSoC 4 pin. This clock may be used instead of the IMO as the source of the system high-frequency clock, HFCLK. The allowable range of external clock frequencies is 0–48 MHz. PSoC 4 always starts up using the IMO and the external clock must be enabled in user mode; so the device cannot be started from a reset, which is clocked by the external clock. When manually configuring a pin as the input to the EXTCLK, the drive mode of the pin must be set to highimpedance digital to enable the digital input buffer. See the I/O System chapter on page 53 for more details. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 65 Clocking System 8.3 Clock Distribution PSoC 4 clocks are developed and distributed throughout the device, as shown in Figure 8-1. The distribution configuration options are as follows: ■ HFCLK input selection ■ SYSCLK prescaler configuration ■ Peripheral divider configuration 8.3.1 HFCLK Input Selection HFCLK in PSoC 4 has two input options: IMO and EXTCLK. The HFCLK input is selected using the CLK_SELECT register’s DIRECT_SEL bits, as described in Table 8-4. Table 8-4. HFCLK Input Selection Bits DIRECT_SEL Name Description HFCLK input clock selection DIRECT_SEL[2:0] 0: IMO. Uses the IMO as the source of the HFCLK 1: EXTCLK. Uses the EXTCLK as the source of the HFCLK 2–7: Reserved. Do not use 8.3.2 SYSCLK Prescaler Configuration The SYSCLK Prescaler allows the device to divide the HFCLK before use as SYSCLK, which allows for non-integer relationships between peripheral clocks and the system clock. SYSCLK must be equal to or faster than all other clocks in the device that are derived from HFCLK. The SYSCLK prescaler is capable of dividing the HFCLK bypowers of 2 between 2^0 = 1 and 2^7 = 128. The prescaler divide value is set using register CLK_SELECT bits SYSCLK_DIV, as described in Table 8-5. The prescaler is initially configured to divide by 1. Note The SYSCLK frequency cannot exceed 24 MHz for the PSoC 4100 family. Table 8-5. SYSCLK Prescaler Divide Value Bits SYSCLK_DIV Name Description SYSCLK prescaler divide value 0: SYSCLK = HFCLK 1: SYSCLK = HFCLK/2 2: SYSCLK = HFCLK/4 SYSCLK_DIV[3:0] 3: SYSCLK = HFCLK/8 4: SYSCLK = HFCLK/16 5: SYSCLK = HFCLK/32 6: SYSCLK = HFCLK/64 7: SYSCLK = HFCLK/128 8.3.3 Peripheral Clock Divider Configuration PSoC 4 has four divider banks, each of which contains three 16-bit dividers named A, B, and C, which can be cascaded to further divide clocks. One of the four banks is capable of fractional divides, which allows the clock divisor to include a fraction of 0..31/32. The fractional divider does not support a divider in the range of 1.0 to 2.0. This limitation prevents generating a clock of 40 MHz from a 48-MHz "clk_hf". These four divider banks are used to generate all of the analog and digital peripheral clocks in the device. Figure 8-2 shows a block diagram of the cascaded dividers. The peripheral clocks are generated from the intermediate and final outputs of the clock dividers. 66 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Clocking System Figure 8-2. Peripheral Clock Divider Block Diagram HFCLK Divider N-A ÷(1..65,536) Divider N-B ÷(1..65,536) Divider N-C ÷(1..65,536) ... x4 The three non-fractional clock divider banks are configured with the DIVIDER_A, DIVIDER_B, and DIVIDER_C registers. The fractional clock divider bank is configured with the DIVIDER_FRAC_A, DIVIDER_FRAC_B, and DIVIDER__FRAC_C registers. Table 8-6 and Table 8-7 describe the configurations for these registers. Table 8-6. Non Fractional Peripheral Clock Divider Configuration Register DIVIDER_x Bits 15:0 Name DIVIDER_x Description Divide value for divider x in the row. Output = input / (DIVIDER_x +1) Determines the input of divider x in the row. 30 CASCADE_x–1_x 31 ENABLE_x 0: DIVIDER_x clock input driven by HFCLK 1: DIVIDER_x clock input driven by the output of DIVIDER_x–1 Note No effect for DIVIDER_A Enables DIVIDER_x. Table 8-7. Fractional Peripheral Clock Divider Configuration Register DIVIDER_FRAC_x Bits Name Description 15:0 DIVIDER_x Divide value for divider x in the row. Output = input / (DIVIDER_x +1 + FRAC_x/32) 20:16 FRAC_x Fractional divider numerator value for divider x in the row. Output = input / (DIVIDER_x +1 + FRAC_x/32) Determines the input of divider x in the row. 30 CASCADE_x–1_x 31 ENABLE_x 0: DIVIDER_x clock input driven by HFCLK 1: DIVIDER_x clock input driven by the output of DIVIDER_x–1 Note No effect for DIVIDER_A 8.3.4 Enables DIVIDER_x. Peripheral Clock Configuration The four UDB clocks and 12 additional peripheral clocks, including the analog SAR clock, are sourced by peripheral clock dividers. Each divider input can be used to generate two versions of the clock: a gated clock and a divided clock. The gated version produces one in N clocking, where the pulse width of the clock is the same as the HFCLK, but the frequency is divided. The divided version has as close as possible to 50 percent duty cycle, with the edges of the divided clock always occurring on high edges of the HFCLK. When divided by n, the divided version will be high for n/2 rounded down cycles, and low for n/2 rounded up cycles. This is shown in Figure 8-3. Clk_gated is used by most peripherals because they are impacted only by rising edges. However, in certain peripherals that are negative edge sensitive as well, clk_divided may be preferred. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 67 Clocking System Figure 8-3. UDB and Peripheral Clock Timing Diagram Table 8-8 shows the mapping of the mux output to the corresponding peripheral blocks (shown in Figure 8-1). Any of the 12 digital peripheral clocks can be mapped to a specific digital peripheral by using their respective SELECT registers, as described in Table 8-9. Table 8-8. Peripheral Clock Mapping Peripheral Clock # Peripheral 0 IMO (SS) 1 SARPUMP 2 SCB0 3 SCB1 4 LCD 5 CSD (1) 6 CSD (2) 7 SAR 8 TCPWM0 9 TCPWM1 10 TCPWM2 11 TCPWM3 12 UDB0 (available only in PSoC 4200) 13 UDB1 (available only in PSoC 4200) 14 UDB2 (available only in PSoC 4200) 15 UDB3 (available only in PSoC 4200) Table 8-9. Peripheral Clock Configuration Register SELECT Bits Name Description Select divider bank row to source clock from. 3:0 DIVIDER_N 0 to 2: non-fractional divider 0 to 2 3: fractional divider 0 Selects which divider from row N to use: 0: Clock disabled 5:4 DIVIDER_ABC 1: Divider N-A 2: Divider N-B 3: Divider N-C The SAR clock is derived from the clock dividers similar to other peripheral clocks. Unlike the other peripheral clocks, the SAR clock generates two outputs: a skewed and un-gated 50 percent duty cycle version for analog circuits, and a version synchronized with HFCLK for digital circuits. The skew allows analog sampling to occur independently from digital clock transitions, which can improve analog performance. 68 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Clocking System 8.4 Low-Power Mode Operation The high-frequency clocks including the IMO, EXTCLK, HFCLK, SYSCLK, and peripheral clocks operate only in Active and Sleep modes. The ILO and LFCLK operate in all power modes except Hibernate and Stop. 8.5 Register List Table 8-10. Clocking System Register List Register Name Description CLK_IMO_TRIM1 IMO Trim Register - This register contains IMO trim, allowing fine manipulation of its frequency. CLK_IMO_TRIM2 IMO Frequency Selection Register - This register controls the frequency range of the IMO, allowing gross manipulation of its frequency. PWR_BG_TRIM4 PWR_BG_TRIM5 Bandgap Trim Registers - These registers control the trim of the bandgap reference, allowing manipulation of the voltage references in the device. CLK_IMO_SPREAD IMO Spread Spectrum Control Register - This register controls the IMO spread spectrum functionality. CLK_ILO_CONFIG ILO Configuration Register - This register controls the ILO configuration. CLK_IMO_CONFIG IMO Configuration Register - This register controls the IMO configuration. CLK_SELECT Clock Select - This register controls clock tree configuration, selecting different sources for the system clocks. DIVIDER_x Peripheral Clock Divider Control Registers - These registers configure the peripheral clock dividers, selecting the source clock, setting integer divide value, and enabling or disabling the divider. DIVIDER_FRAC_x Peripheral Clock Fractional Divider Control Registers - These registers configure the peripheral clock dividers, selecting the source clock, setting fractional divide value, and enabling or disabling the divider. SELECT_x Peripheral Clock Select Registers - These registers configure the output of the peripheral clock dividers, selecting the source from a specific divider within a specific row. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 69 Clocking System 70 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 9. Power Supply and Monitoring PSoC® 4 is capable of operating from a 1.71 V to 5.5 V externally supplied voltage. This is supported through one of the two following operating ranges: ■ 1.80 V to 5.50 V supply input to the internal regulators ■ 1.71 V to 1.89 V1 direct supply PSoC 4 devices have different internal regulators to support the various power modes. These include Active digital regulator, Quiet regulator, Deep-Sleep regulator, and Hibernate regulator. 1. When the system supply is in the range 1.80 V to 1.89 V, both direct supply and internal regulator options can be used. The selection can be made depending on the user’s system capability. Note that the supply voltage cannot go above 1.89 V for the direct supply option because it will damage the device. It should not go below 1.80 V for the internal regulator option because the regulator will turn off. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 71 Power Supply and Monitoring 9.1 Block Diagram Figure 9-1. Power System Block Diagram VDDA VDDD 0.1 uF 1 uF 1 uF 0.1 uF 1 uF VCCD VDDD Digital Regulator Quiet Regulator Deep-Sleep Regulator Active Domain Examples: CPU, IMO, Flash Analog Domain Bandgap Voltage Reference Examples: CTBm, SAR Deep-Sleep Domain Examples: ILO, I2C Hibernate Domain Examples: LP COMP, SRAM, UDB VSSD VSSA Hibernate Regulator The power system has separate digital and analog supply pins labeled VDDD and VDDA, as shown in Figure 9-1. Similarly, there are separate digital and analog ground pins named VSSD and VSSA. The digital and analog supply pins share ESD resources. To avoid turning on the ESD devices, the digital supply cannot exceed analog supply by more than 300 mV, not even on a transient basis. Thus, the VDDA supply must ramp up before or concurrently with the VDDD supply. In some PSoC 4 device packages, VDDD and VDDA are shorted internally and made available as a single VDD pin. In such devices, VDDA and VDDD supply ramp up concurrently inside the device. The Active digital regulator allows the external VDDDsupply to be regulated to the nominal 1.8 V required for the digital core. The output pin of this regulator has a specific capacitor requirement, as shown in Figure 9-1. This Active digital reg- 72 VDDA Note: Do not connect external load to VCCD ulator is designed to supply the internal circuits only; therefore, it should not be loaded externally. The primary regulated supply, labeled VCCD, can be configured for internal regulation or can be directly supplied by the pin. In internal regulation mode, VDDD can vary between 1.8 V and 5.5 V and the on-chip regulators generate the other low-voltage supplies. In direct supply configuration, VCCD and VDDD must be shorted together and connected to a supply of 1.71 V to 1.89 V. The Active digital regulator is still powered up and enabled by default. It must be disabled by the firmware to reduce power consumption; see 9.3.1.1 Active Digital Regulator. Two additional regulators are used to provide supplemental power domains including Deep-Sleep and Hibernate. In addition, a Quiet regulator powers sensitive analog circuitry including the bandgap reference and capacitive sensing sub-system. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Power Supply and Monitoring 9.2 Power Supply Scenarios The following diagrams illustrate the different ways in which the PSoC 4 device is powered. 9.2.1 Single 1.8 V to 5.5 V Unregulated Supply Depending on board design, the 1.8-V to 5.5-V supply can reach the PSoC 4 device via a single route or two different routes (on boards with separate analog and digital supply networks), as shown in Figure 9-2 and Figure 9-3, respectively. Figure 9-2. Single Regulated Power Supply 1.8 V - 5.5 V 0.1 uF VDDD VDDA 1 uF VCCD PSoC 4 1 uF VSSD VSSA Figure 9-3. Separate Regulated VDDA and VDDD Supplies VDDD 1.8 V - 5.5 V 0.1uF VSSD 1uF VDDA VSSD 1.8 V - 5.5 V VCCD 0.1 uF 1 uF PSoC 4 1 uF VSSD VSSA VSSA VSSD VSSA PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 73 Power Supply and Monitoring Some PSoC 4 device packages have a single power supply and ground pins labeled VDD and VSS, respectively. The 1.8-V to 5.5-V supply can be connected to these packages, as shown in Figure 9-4. Figure 9-4. Single Regulated VDD Supply 1.8 V - 5.5 V VDDD 1 uF 0.1 uF VCCD PSoC 4 0.1 uF VSS 9.2.2 Direct 1.71 V to 1.89 V Regulated Supply In direct supply configuration, VCCD and VDDD are shorted together and connected to a 1.71-V to 1.89-V supply. This supply can reach the PSoC 4 device via a single route or two different routes, as shown in the following diagrams. This regulated supply should be connected to the PSoC 4, as shown in Figure 9-5 and Figure 9-6. Figure 9-5. Single Unregulated Power Supply VDDD VDDA VCCD 1.71 V - 1.89 V 0.1 uF 1 uF PSoC 4 VSSD VSSA 74 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Power Supply and Monitoring Figure 9-6. Separate Unregulated Power Supplies 1.71 V - 1.89 V VDDD 0.1 uF 1 uF VSSA VSSA VDDA VCCD 1.71 V - 1.89 V VSSD 1 uF 0.1 uF VSSD PSoC 4 VSSD VSSA 9.3 How It Works (VCCD) and requires an external decoupling capacitor (1 µF X5R). The regulators in Figure 9-1 power the various domains of the device. All the core regulators and digital I/Os draw their input power from the VDDD pin supply. Digital I/Os are supplied from VDDD. The analog circuits run directly from the VDDA input. 9.3.1 Regulator Summary The Active digital regulator and Quiet regulator are enabled during the Active or Sleep power modes. They are turned off in the Deep-Sleep and Hibernate power modes (see Table 9-1 and Figure 9-1). The Deep-Sleep and Hibernate regulators are designed to fulfill power requirements in the low-power modes of the device. Table 9-1. Regulator Status in Different Power Modes Mode Stop Active Regulator Off Quiet Deep-Sleep Regulator Regulator Off Off Hibernate Regulator The Active digital regulator can be disabled by setting the EXT_VCCD bit in the PWR_CONTROL register. This reduces the power consumption in direct supply mode. The Active digital regulator is available only in Active and Sleep power modes. 9.3.1.2 Quiet Regulator In Active and Sleep modes, this regulator supplies analog circuits such as the bandgap reference and capacitive sensing subsystem, which require a quiet supply, free of digital switching noise and power supply noise. This regulator has a high-power supply rejection ratio. The Quiet regulator is available only in Active and Sleep power modes. Off 9.3.1.3 This regulator supplies the circuits that remain powered in Deep-Sleep mode, such as the ILO and SCB. The DeepSleep regulator is available in all power modes except the Hibernate mode. In Active and Sleep power modes, the main output of this regulator is connected to the output of the Active digital regulator (VCCD). This regulator also has a separate replica output that provides a stable voltage for the ILO. This output is not connected to VCCD in Active and Sleep modes. Hibernate Off Off Off On Deep Sleep Off Off On On Sleep On On On On Active On On On On 9.3.1.1 For supplies below 1.8 V, VCCD must be supplied directly. In this case, VCCD and VDDD must be shorted together, as shown in Figure 9-5. Active Digital Regulator For external supplies from 1.8 V and 5.5 V, the Active digital regulator provides the main digital logic in Active and Sleep modes. This regulator has its output connected to a pin Deep-Sleep Regulator PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 75 Power Supply and Monitoring 9.3.1.4 Hibernate Regulator This regulator supplies the circuits that remain powered in Hibernate mode, such as the sleep controller, low-power comparator, and SRAM. The Hibernate regulator is available in all power modes. In Active and Sleep modes, the output of this regulator is connected to the output of the digital regulator. In Deep-Sleep mode, the output of this regulator is connected to the output of the Deep-Sleep regulator. 9.4 Voltage Monitoring The voltage monitoring system includes power-on-reset (POR), brownout detection (BOD), and low-voltage detection (LVD). 9.4.1 Power-On-Reset (POR) POR circuits provide a reset pulse during the initial power ramp. POR circuits monitor VCCD voltage. Typically, the POR circuits are not very accurate with respect to trip-point. POR circuits are used during initial chip power-up and then disabled. 9.4.1.1 Brownout-Detect (BOD) The BOD circuit protects the operating or retaining logic from possibly unsafe supply conditions by applying reset to the device. BOD circuit monitors the VCCD voltage. The BOD circuit generates a reset if a voltage excursion dips below the minimum VCCD voltage required for safe operation (see the device datasheet device datasheet for details). The system will not come out of RESET until the supply is detected to be valid again. To enable firmware to distinguish a normal power cycle from a brownout event, a special register is provided (PWR_BOD_KEY), which will not be cleared after a BOD 9.5 generated RESET. However, this register will be cleared if the device goes through POR or XRES. BOD is available in all power modes except the Stop mode. 9.4.1.2 Low-Voltage-Detect (LVD) The LVD circuit monitors external supply voltage and accurately detects depletion of the energy source. The LVD detector generates an interrupt to cause the system to take preventive measures. The LVD is available only in Active and Sleep power modes. If LVD is required in Deep-Sleep mode, then the chip should be configured to periodically wake up from deep sleep using WDT as the wake up source; the LVD monitoring should be done in Active mode. LVD circuits generate interrupts at programmable levels within the safe operating voltage. The trip point of the LVD can be configured between 1.75 V to 4.5 V using the LVD_SEL field in the PWR_VMON_CONFIG register. When enabling the LVD circuit, it is possible to get a false interrupt during the initial settling time. Firmware can mask this by waiting for 1 µs after setting the LVD_EN bit in PWR_VMON_CONFIG register. The recommended firmware procedure to enable the LVD function is: 1. Ensure that the LVD bit in the PWR_INTR_MASK register is 0 to prevent propagating a false interrupt. 2. Set the required trip-point in the LVD_SEL field of the PWR_VMON_CFG register. 3. Enable the LVD by setting the LVD_EN bit in PWR_VMON_CFG. This may cause a false LVD event. 4. Wait at least 1 µs for the circuit to stabilize. 5. Clear the false event by writing a ‘1’ to the LVD bit in the PWR_INTR register. The bit will not clear if the LVD condition is truly present. 6. Unmask the interrupt using the LVD bit in PWR_INTR_MASK. Register List Table 9-2. Power Supply and Monitoring Register List Register Name PWR_CONTROL Description Power Mode Control Register – This register allows configuration of device power modes and regulator activity. PWR_INTR Power System Interrupt Register – This register indicates the power system interrupt status. PWR_INTR_MASK Power System Interrupt Mask Register – This register controls which interrupts are propagated to the interrupt controller of the CPU. PWR_VMON_CONFIG Power System Voltage Monitoring Trim and Configuration – This register contains trim and configuration bits for the voltage monitoring system. 76 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 10. Chip Operational Modes PSoC® 4 is capable of executing firmware in four different modes. These modes dictate execution from different locations in flash and ROM, with different levels of hardware privileges. Only three of these modes are used in end-applications; debug mode is used exclusively to debug designs during firmware development. PSoC 4’s operational modes are: ■ Boot ■ User ■ Privileged ■ Debug 10.1 Boot Boot mode is an operational mode where the device is configured by instructions hard-coded in the device SROM. This mode is entered after the end of a reset, provided no debug-acquire sequence is received by the device. Boot mode is a privileged mode; interrupts are disabled in this mode so that the boot firmware can set up the device for operation without being interrupted. During boot mode, hardware trim settings are loaded from flash to guarantee proper operation during power-up. When boot concludes, the device enters user mode and code execution from flash begins. This code in flash may include automatically generated instructions from the PSoC Creator IDE that will further configure the device. 10.2 User User mode is an operational mode where normal user firmware from flash is executed. User mode cannot execute code from SROM. Firmware execution in this mode includes the automatically generated firmware by the PSoC Creator IDE and the firmware written by the user. The automatically generated firmware can govern both the firmware startup and portions of normal operation. The boot process transfers control to this mode after it has completed its tasks. 10.3 Privileged Privileged mode is an operational mode, which allows execution of special subroutines that are stored in the device ROM. These subroutines cannot be modified by the user and are used to execute proprietary code that is not meant to be interrupted or observed. Debugging is not allowed in privileged mode. The CPU can transition to privileged mode through the execution of a system call. For more information on how to perform a system call, see Performing a System Call on page 280. Exit from this mode returns the device to user mode. 10.4 Debug Debug mode is an operational mode that allows observation of the PSoC 4 operational parameters. This mode is used to debug the firmware during development. The debug mode is entered when an SWD debugger connects to the device during the acquire time window, which occurs during the device reset. Debug mode allows IDEs such as PSoC Creator and ARM MDK to debug the firmware. Debug mode is only available on devices in open mode (one of the four protection modes). For more details on the debug interface, see the Program and Debug Interface chapter on page 271. For more details on protection modes, see the Device Security chapter on page 93. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 77 Chip Operational Modes 78 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 11. Power Modes The PSoC® 4 provides five power modes, intended to minimize the average power consumption for a given application. The power modes, in the order of decreasing power consumption, are: ■ Active ■ Sleep ■ Deep-Sleep ■ Hibernate ■ Stop Active, Sleep, and Deep-Sleep are standard ARM-defined power modes, supported by the ARM CPUs and instruction set architecture (ISA). Hibernate and Stop modes are additional low-power modes supported by PSoC 4. These modes are entered from firmware similar to Deep-Sleep, but on wakeup, the CPU and all peripherals go through a reset. The power consumption in different power modes is controlled by using the following methods: ■ Enabling/disabling peripherals ■ Powering on/off internal regulators ■ Powering on/off clock sources ■ Powering on/off other portions of the PSoC 4 Figure 11-1 illustrates the various power modes and the possible transitions between them. Figure 11-1. Power Mode Transitions State Diagram XRES / Brownout / Power On Reset KEY: RESET Power Mode Action Internal Reset Event Internal Resets External Reset Event Firmware Action ACTIVE Wakeup Interrupt Other External Event Firmware Action SLEEP HIBERNATE Wakeup Interrupt DEEP-SLEEP STOP WAKEUP Asserts PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 79 Power Modes Table 11-1 illustrates the power modes offered by PSoC 4 Table 11-1. PSoC 4 Power Modes Power Mode Description Entry Condition Wakeup Sources Active Clocks Active Wakeup from other Primary mode of operapower modes, intertion; all peripherals are nal and external available (programmable). resets, brownout, power on reset Sleep CPU enters Sleep mode and SRAM is in retention; all peripherals are available (programmable). DeepSleep All internal supplies are driven from the DeepSleep regulator. IMO and GPIO interrupt, high-speed peripherals are low-power off. Only the low-frequency ILO (32 kHz) (32 kHz) clock is available. Manual register write comparator, SCB, watchInterrupts from low-speed, dog timer asynchronous, or lowpower analog peripherals can cause a wakeup. Not applicable Manual register write Any interrupt All (programmable) All (programmable) Only SRAM and UDBs are retained; all internal supplies, except the hibernate GPIO interrupt, Hibernate supply are off. Wakeup is Manual register write low-power None possible from a pin intercomparator rupt or a low-power comparator. Stop All internal supplies are off. Only GPIO states are retained. Wakeup is possi- Manual register write WAKEUP pin ble from XRES or WAKEUP pins only. In addition to the wakeup sources mentioned in Table 11-1, external reset (XRES) and brownout reset bring the device to Active mode from any power mode. 11.1 Active Mode Active mode is the primary power mode of the PSoC device. This mode provides the option to use every possible subsystem/peripheral in the device. In this mode, the CPU is running and all the peripherals are powered. The firmware may be configured to disable specific peripherals that are not in use, to reduce power consumption. 11.2 None 11.3 Wakeup Action Available Regulators Interrupt All regulators are available. The Active digital regulator can be disabled if external regulation is used. Interrupt All regulators are available. The Active digital regulator can be disabled if external regulation is used. Interrupt Deep-Sleep regulator and Hibernate regulator Reset (with interrupt Hibernate regulator state retention) Reset None Deep-Sleep Mode In Deep-Sleep mode, the CPU, SRAM, UDB, and highspeed logic are in retention. The high-frequency clocks, including HFCLK and SYSCLK, are disabled. Optionally, the internal low-frequency (32 kHz) oscillator remains on and low-frequency peripherals continue to operate. Digital peripherals that do not need a clock or receive a clock from their external interface (for example, I2C slave) continue to operate. Interrupts from low-speed, asynchronous or lowpower analog peripherals can cause a wakeup from DeepSleep mode. The available wakeup sources are listed in Table 11-3. Sleep Mode This is a CPU-centric power mode. In this mode, the CortexM0 CPU enters Sleep mode and its clock is disabled. It is a mode that the PSoC 4 should come to very often or as soon as the CPU is idle, to accomplish low power consumption. It is identical to Active mode from a peripheral point of view. Any enabled interrupt can cause wakeup from Sleep mode. 80 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Power Modes 11.4 Hibernate Mode Mode Entry and Exit on page 83. External reset (XRES) triggers a full system restart. In this case, the cause is not readable after the device restarts, and I/O pins will not retain their “frozen” state. This is the lowest PSoC 4 power mode that retains SRAM. It is implemented by switching off all clocks and removing power from the CPU and all peripherals, with the exception of a few (asynchronous) peripherals that can wake up the system from an external event. Note that in this mode, the CPU and all peripherals lose state. 11.5 Stop Mode In the Stop mode, the CPU, all internal regulators, and all peripherals are switched off. Wakeup from Stop mode is a system reset and it is possible from XRES or WAKEUP pins only. I/O pins will be tri-stated after reset, unless they are explicitly frozen by firmware before entry into Stop mode. To know the cause of interrupt, use the TOKEN bits in PWR_STOP register, as described in Low-Power Mode Entry and Exit on page 83. In this mode, a Hibernate regulator with limited capacity is used to achieve an extremely low power consumption. This puts a constraint on the maximum frequency of any signals present on the input pins while in Hibernate mode. The combined toggle rate on all I/O pins (total frequency of signals in all inputs and outputs) must not exceed 10 kHz. Any system that has signals toggling at high rates can use Deep-Sleep mode without seeing a significant difference in total power consumption. External reset (XRES) triggers a full system restart. In this case, the cause is not readable after the device restarts, and I/O pins will not retain their "frozen" state. Wakeup from Hibernate mode is possible from a pin interrupt or a low-power comparator only. Wakeup from hibernate incurs a reset rather than a wakeup from interrupt. When waking up from hibernate, the CPU and most peripherals are in their reset state and firmware will start at the reset vector. I/O pins will be tri-stated after reset, unless they are explicitly frozen by firmware before entry into Hibernate mode. To know the cause of interrupt, use the TOKEN bits in PWR_STOP register, as described in Low-Power 11.6 Power Mode Summary Table 11-3 illustrates the peripherals available in each lowpower mode; Table 11-3 illustrates the wakeup sources available in each power mode. Table 11-2. Available Peripherals Peripheral Active Sleep Deep-Sleep Hibernate Stop CPU On Retentiona Retention Off Off SRAM On Retention Retention Retention Off High-speed peripherals (peripherals that operate from HFCLK) On On Retention Off Off CapSense On On Retention Off Off Universal digital block (UDB) On On Retention Off Off Low-speed peripherals (peripherals that operate from ILO) On On On (optional) Off Off Internal main oscillator (IMO) On On Off Off Off Internal low-speed oscillator (ILO 32 kHz) On On On (optional) Off Off Asynchronous peripherals On On On Off Off Power-on-reset, Brownout detection On On On Off Off Regular analog peripherals On On Off Off Off Low power comparator On On On On Off On/Frozen Frozenb Frozen GPIO output state On On a. The configuration and state of the peripheral is retained. Peripheral continues its operation when the device enters Active mode. b. The configuration, mode, and state of all GPIOs in the system are locked. Changing the GPIO state is not possible until the device enters Active mode. Table 11-3. Wakeup Sources Power Mode Sleep Wakeup Source Wakeup Action Any interrupt source Interrupt Any reset source Reset PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 81 Power Modes Table 11-3. Wakeup Sources Power Mode Deep-Sleep Wakeup Source GPIO interrupt Interrupt Low-power comparator Interrupt I2C address match Interrupt Watchdog timer XRES (external reset Interrupt / Reset pin)a, Brownout GPIO Interrupt Hibernate Wakeup Action Reset Low-power comparator XRES (external reset pin)a, Reset Brownout WAKEUP pin Stop XRES (external reset Reset Reset Reset pin)a, Brownout Reset a. XRES triggers a full system restart. All the states including frozen GPIOs are lost. In this case, the cause of wakeup is not readable after the device restarts. 82 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Power Modes 11.7 Low-Power Mode Entry and Exit A Wait For Interrupt (WFI) instruction from the Cortex-M0 (CM0) triggers the transitions into Sleep, Deep-Sleep, and Hibernate modes. The Cortex-M0 can delay the transition into a low-power mode until the lowest priority ISR is exited (if the SLEEPONEXIT bit in the CM0 System Control Register is set). ■ UNLOCK – This field must be written to 0x3A to unlock the Stop mode. The hardware ignores the STOP bit if this field has any other setting. ■ POLARITY – This bit sets the polarity of WAKEUP pin input. The device wakes up when the WAKEUP pin input matches the value of POLARITY bit. ■ FREEZE – Setting this bit freezes the configuration, mode, and state of all GPIOs in the system ■ STOP –This bit must be set to enter the Stop mode. The transition to Sleep, Deep-Sleep, and Hibernate modes are controlled by the flags SLEEPDEEP in the CM0 System Control Register (CM0_SCR) and HIBERNATE in the System Resources Power subsystem (PWR_CONTROL). The recommended procedure to enter Stop mode is: ■ Sleep is entered when the WFI instruction is executed, SLEEPDEEP = 0 and HIBERNATE = x. 4. Write FREEZE = 1 ■ Deep-Sleep is entered when the WFI instruction is executed, SLEEPDEEP = 1 and HIBERNATE = 0. ■ Hibernate is entered when the WFI instruction is executed, SLEEPDEEP = 1 and HIBERNATE = 1. The LPM READY bit in the PWR_CONTROL register shows the status of Deep-Sleep and Hibernate regulators. If the firmware tries to enter Deep-Sleep or Hibernate mode before the regulators are ready, then PSoC 4 goes to Sleep mode first, and when the regulators are ready, the device enters Deep-Sleep or Hibernate mode. This operation is automatically done in hardware. In Sleep and Deep-Sleep modes, a selection of peripherals are available (see Table 11-3), and firmware can either enable or disable their associated interrupts. Enabled interrupts can cause wakeup from low-power mode to Active mode. Additionally, any RESET returns the system to Active mode. See the Interrupts chapter on page 37 and the Reset System chapter on page 89 for details. 1. Write TOKEN = <any application-specified value> 2. Write UNLOCK = 0x3A 3. Write POLARITY = <application-specified polarity> 5. Write STOP = 1 It is recommended to add two NOP cycles after the third write. Stop mode exits when either the XRES or WAKEUP pins are toggled. Both events clear the STOP bit in the PWR_STOP register and trigger a POR. A wakeup event does not clear the other bits of the PWR_STOP register, but an XRES event clears all the bits. The recommended firmware procedure on wakeup from Stop or Hibernate mode is as follows: 1. Optionally read TOKEN for application-specific branching. 2. Optionally write I/O drive modes and output data registers to the required settings. A typical procedure for digital output ports is to set the pin description as output, read its frozen value, and set that value in the output data register. 3. Unfreeze the I/O. Before entering Deep-Sleep mode, change the IMO frequency to 12 MHz. After wakeup from Deep-Sleep mode, restore the previous IMO frequency. See the Clocking System chapter on page 63 for details on how to change the IMO frequency. Use the PWR_STOP register to freeze the GPIO states in these low-power modes. This is recommended for the Hibernate and Stop modes because the wakeup from these modes causes a system reset. Stop mode is entered directly using the PWR_STOP register in the System Resources Power subsystem. It removes power from all of the low-voltage logic in the system. Only the I/O state and PWR_STOP register contents are retained and wakeup (reset) happens on either XRES or toggling of a fixed WAKEUP pin. The fields in PWR_STOP register are: ■ TOKEN – This field contains an 8-bit token that is retained through a STOP/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event. Note that waking up from STOP using XRES resets this register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 83 Power Modes 11.8 Register List Table 11-4. Power Mode Register List Register Name Description CM0_SCR System Control - Sets or returns system control data. PWR_CONTROL Power Mode Control - Controls the device power mode options and allows observation of current state. PWR_STOP Power Stop - Controls entry/exit from the Stop power mode. 84 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 12. Watchdog Timer The watchdog timer (WDT) is used to automatically reset the device in the event of an unexpected firmware execution path. The WDT runs from the LFCLK, generated by the ILO. The timer, if enabled, must be serviced periodically in firmware to avoid a reset. Otherwise, the timer will elapse and generate a device reset. The WDT can be used as an interrupt source or a wakeup source in low-power modes. 12.1 Features The WDT has these features: ■ System reset generation after a configurable interval ■ Periodic interrupt/wake up generation in Active, Sleep, and Deep-Sleep power modes ■ Supports two 16-bit and one 32-bit independent counters, which can be cascaded to increase the interval 12.2 Block Diagram Figure 12-1. Watchdog Timer Block Diagram AHB Interface Register CFG/ STATUS INTERRUPT CPU Subsystem or WIC Watchdog Timer Low-Frequency Clock (LFCLK) CLK RESET PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Reset Block 85 Watchdog Timer Figure 12-2. Watchdog Timer Internal Block Diagram LFCLK WDT_CASCADE0_1 WDT0 (16-bit Counter) WDT_CASCADE1_2 WDT1 (16-bit Counter) WDT2 (32-bit Counter) WDT_CTR1 WDT_CTRHIGH WDT_CTR0 16 WDT_CTR0 == WDT_MATCH0 WDT_MODE0 2 32 16 WDT_CTR1 == WDT_MATCH1 WDT Mode Configuration RESET WDT_MODE1 2 WDT_INT0 WDT_BITS2 5 WDT Mode Configuration RESET WDT_MODE2 1 WDT_INT1 WDT Mode Configuration WDT_INT2 INTERRUPT RESET 12.3 How It Works The WDT asserts an interrupt or a hardware reset to the device after a programmable interval, unless it is periodically serviced in firmware. The WDT has two 16-bit counters (WDT0 and WDT1) and one 32-bit counter (WDT2). These counters can be configured to work independently or in cascade. WDT0 and WDT1 can be configured to generate an interrupt on a match event, that is, when the counter value equals the match value. The WDT0 and WDT1 counters can also be configured to generate a reset on a match event or after three successive match events that are not handled (match event interrupt not cleared). WDT2 can be configured to generate an interrupt based on the value stored in the WDT_BITS2[4:0] bits in the WDT_CONFIG register. WDT2 cannot generate a system reset or an interrupt with any match value similar to WDT1 or WDT0. WDT2 can generate an interrupt only on a rising edge on one of the 32 bits present in the counter. The WDT_BITS2[4:0] bits in the WDT_CONFIG register control the bit that generates the interrupt. See the WDT_CONFIG register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM for details. in the WDT_MATCH register. The WDT1 will have a period defined by WDT_MATCH1[31:16] bits in the WDT_MATCH register. The same logic applies to WDT1 and WDT2 cascading. When the WDT is used to protect against system crashes, clearing the WDT interrupt bit to reset the watchdog must be done from a portion of the code that is not directly associated with the WDT interrupt. Otherwise, even if the main function of the firmware crashes or is in an endless loop, the WDT interrupt vector can still be intact and feed the WDT periodically. The safest way to use the WDT against system crashes is to: ■ Configure the watchdog reset period such that firmware is able to reset the watchdog at least once during the period, even along the longest firmware delay path. ■ Reset the watchdog by clearing the interrupt bit regularly in the main body of the firmware code. If configured to generate a reset on a match event, reset the watchdog by clearing the WDTx counter. The WDTx counter can be cleared by setting the WDT_RESETx bit in the WDT_CONFIG register. For details, refer to the WDT_CONFIG register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM. ■ It is not recommended to reset watchdog in the WDT interrupt service routine (ISR), if WDT is being used as a reset source to protect the system against crashes. Hence, it is not recommended to use the same watchdog counter for generating system reset and interrupt. For example, if WDT0 is used for generating system reset against crashes, then WDT1 or WDT2 should be used for periodic interrupt generations. WDT_MODEx bits are used to configure the watchdog counters as described above. The cascade configuration shown in Figure 12-2 provides an option to increase the reset or interrupt interval. Note that cascading two 16-bit counters will not provide a 32-bit counter; instead, you will obtain a 16-bit period counter with a 16bit prescaler. For example, when cascading WDT0 and WDT1, WDT0 acts as a prescaler for WDT1 and the prescaler value will be defined by the WDT_MATCH0[15:0] bits 86 Watchdog Timer PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Watchdog Timer Follow these steps to use WDT as a periodic interrupt generator: 1. Set the WDT_CLEAR0 or WDT_CLEAR1 bit in the WDT_CONFIG register for WDT0 or WDT1 to reset the corresponding watchdog counter to ‘0’ on a match event. 2. Write the desired match value to the WDT_MATCH register for WDT0/WDT1 and the WDT_BITS2 value to the WDT_CONFIG register for WDT2. 3. Clear the WDT_INTx bit in WDT_CONTROL to clear any pending interrupt. 4. Enable the WDT interrupt by configuring the WDT_MODEx bits in WDT_CONFIG. Configure the WDT_MODE0 or WDT_MODE1 bits in WDT_CONFIG for WDT0 or WDT1 to ‘1’ (interrupt on match) or ‘3’ (interrupt on match and reset on third unhandled match). For WDT2, set the WDT_MODE2 bit in the WDT_CONFIG register. 5. Enable global WDT interrupt in the CM0_ISER register (See the Interrupts chapter on page 37 for details). 6. In the ISR, clear the WDT interrupt. For more details on interrupts, see the Interrupts chapter on page 37. Changing WDT_MATCH requires three LFCLK cycles to come into effect. After changing WDT_MATCH, do not enter the Deep-Sleep mode for one LFCLK cycle to ensure the WDT updates to the new setting. 12.3.1 Enabling and Disabling WDT The WDT counters are enabled by setting the WDT_ENABLEx bit in the WDT_CONTROL register and are disabled by clearing it. Enabling or disabling a WDT requires three LFCLK cycles to come into effect. Therefore, the WDT_ENABLEx bit value must not be changed more than once in that period. After WDT is enabled, it is not recommended to write to the WDT configuration (WDT_CONFIG) and control the (WDT_CONTROL) registers. Accidental corruption of WDT registers can be prevented by setting the WDT_LOCK[15:14] bits of the CLK_SELECT register. If the application requires updating the match value (WDT_MATCH) when the WDT is running, the WDT_LOCK bits must be cleared. The WDT_LOCK bits require two different writes to clear both the bits. Writing a '1' to the bits clears bit 0. Writing a '2' clears bit 1. Writing a '3' sets both the bits and writing '0' does not have any effect. For details, refer to the CLK_SELECT register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 12.3.2 WDT Operating Modes The WDT0 and WDT1 can be used to generate a reset to stop the system from going into the unresponsive state or to generate an interrupt to wake up the system from Sleep or Deep-Sleep power modes. The bit field WDT_MODEx[1:0] in the WDT_CONFIG register can be configured to select the required action when the count value stored in the WDT_CTRx register bits equals the match values (WDT_MATCHx) stored in the WDT_MATCH register. See the WDT_CTRHIGH, WDT_CTRLOW, and WDT_MATCH registers in the PSoC 4100/4200 Family: PSoC 4 Registers TRM for details. Table 12-1. WDT0 and WDT1 Modes Bit-field Name Description Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0) or (WDT_CTR1=WDT_MATCH1): WDT_MODE0[1:0] 00: Do nothing or 01: Assert WDT_INT0 or WDT_INT1 WDT_MODE1[1:0] 10: Assert WDT Reset 11: Assert WDT_INT0 or WDT_INT1, assert WDT reset after the third unhandled interrupt The WDT2 can be used to generate interrupts based on the status of the WDT_BITS2[4:0] register bits. Table 12-2. WDT2 Mode Bit-field Name Description 0: Free-running counter with no interrupt requests WDT_MODE2 1: Free-running counter with interrupt request on the rising edge of the bit specified by WDT_BITS2 bits in the WDT_CONFIG register Note: When the watchdog counters are configured to generate an interrupt every LFCLK cycle, make sure you read the WDT_CONTROL register after clearing the watchdog interrupt (setting the WDT_INTx bit in the WDT_CONTROL register). Failure to do this may result in missing the next interrupt; it will also result in an interrupt cycle of LFCLK/2. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 87 Watchdog Timer 12.3.3 WDT Interrupts and Low-Power Modes The watchdog counter can send interrupt requests to the CPU in Active power mode and to the WakeUp Interrupt Controller (WIC) in Sleep and Deep-Sleep power modes. It works as follows: ■ Active Mode: In Active power mode, the WDT can send the interrupt to the CPU. The CPU acknowledges the interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware. ■ Sleep or Deep-Sleep Mode: In this mode, the CPU subsystem is powered down. Therefore, the interrupt request from the WDT is directly sent to the WIC, which will then wake up the CPU. The CPU acknowledges the 12.4 interrupt request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware. For more details on device power modes, see the Power Modes chapter on page 79. 12.3.4 WDT Reset Mode The RESET_WDT bit in the RES_CAUSE register indicates the reset generated by the WDT. This bit remains set until cleared or until a power-on reset (POR), brownout reset (BOD), or external reset (XRES) occurs. All other resets leave this bit untouched. For more details, see the Reset System chapter on page 89. Register List Table 12-3. WDT Registers Register Name Description WDT_CTRLOW Watchdog counters 0 and 1 WDT_CTRHIGH Watchdog counter 2 WDT_MATCH Match value for watchdog counters 0 and 1 WDT_CONFIG Contains WDT configuration bits WDT_CONTROL Controls the behavior of WDT counters 88 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 13. Reset System PSoC® 4 supports several types of resets that guarantee error-free operation during power up and allow the device to reset based on user-supplied external hardware or internal software reset signals. PSoC 4 also contains hardware to enable the detection of certain resets. The reset system has these sources: ■ Power-on reset (POR) to hold the device in reset while the power supply ramps up ■ Brownout reset (BOD) to reset the device if the power supply falls below specifications during operation ■ Watchdog reset (WRES) to reset the device if firmware execution fails to service the watchdog timer ■ Software initiated reset (SRES) to reset the device on demand using firmware ■ External reset (XRES) to reset the device using an electrical signal external to the PSoC 4 ■ Protection fault reset (PROT_FAULT) to reset the device if unauthorized operating conditions occur ■ Hibernate wakeup reset to bring the device out of the Hibernate low-power mode ■ Stop wakeup reset to bring the device out of the Stop low-power mode 13.1 Reset Sources The following sections provide a description of the reset sources available in PSoC 4. 13.1.1 Power-on Reset Power-on reset is provided for system reset at power-up. POR holds the device in reset until the supply voltage, VDDD, is according to the datasheet specification. The POR activates automatically at power-up. POR events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no other reset event is detected, then the reset is caused by POR, BOD, or XRES. 13.1.2 Brownout Reset Brownout reset monitors the chip digital voltage supply VCCD and generates a reset if VCCD is below the minimum logic operating voltage specified in the device datasheet. BOD is available in all power modes except the Stop mode. BOD events do not set a reset cause status bit, but in some cases they can be detected. In some BOD events, VCCD will fall below the minimum logic operating voltage, but remain above the minimum logic retention voltage. Thus, some BOD events may be distinguished from POR events by checking for logic retention. This is explained further in Identifying Reset Sources on page 90. 13.1.3 Watchdog Reset Watchdog reset (WRES) detects errant code by causing a reset if the watchdog timer is not cleared within the user-specified time limit. This feature is enabled by setting the WDT_ENABLEx bit in the WDT_CONTROL register. The RESET_WDT status bit of the RES_CAUSE register is set when a watchdog reset occurs. This bit remains set until cleared or until a POR, XRES, or undetectable BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched. For more details, see the Watchdog Timer chapter on page 85. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 89 Reset System 13.1.4 Software Initiated Reset Software initiated reset (SRES) is a mechanism that allows a software-driven reset. The Cortex-M0 application interrupt and reset control register (CM0_AIRCR) forces a device reset when a ‘1’ is written into the SYSRESETREQ bit. CM0_AIRCR requires a value of A05F written to the top two bytes for writes. Therefore, write A05F0004 for the reset. The RESET_SOFT status bit of the RES_CAUSE register is set when a software reset occurs. This bit remains set until cleared or until a POR, XRES or undetectable BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched. 13.1.5 External Reset External reset (XRES) is a user-supplied reset that causes immediate system reset when asserted. The XRES pin is active low – a high voltage on the pin has no effect and a low voltage causes a reset. The pin is pulled high inside the device. XRES is available as a dedicated pin in most of the devices. For detailed pinout, refer to the pinout section of the device datasheet. The XRES pin holds the device in reset while held active. When the pin is released, the device goes through a normal boot sequence. The logical thresholds for XRES and other electrical characteristics, are listed in the Electrical Specifications section of thedevice datasheet. XRES events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no other reset event is detected, then the reset is caused by POR, undetectable BOD, or XRES. 13.1.6 Protection Fault Reset Protection fault reset (PROT_FAULT) detects unauthorized protection violations and causes a device reset if they occur. One example of a protection fault is if a debug breakpoint is reached while executing privileged code. For details about privilege code, see Privileged on page 77. The RESET_PROT_FAULT bit of the RES_CAUSE register is set when a protection fault occurs. This bit remains set until cleared or until a POR, XRES or undetectable BOD reset; for example, in the case of a device power cycle. All other resets leave this bit untouched. 13.1.7 Hibernate Wakeup Reset Hibernate wakeup reset detects hibernate wakeup sources and performs a device reset to return to the Active power mode. Hibernate wakeup resets are caused by interrupts. Both pin and comparator interrupts are available in the Hibernate low-power mode. After a hibernate wakeup reset, both SRAM and UDB register contents are retained, but code execution begins after reset as it does after any other reset source occurs. Hibernate resets can be detected by checking the interrupt registers for comparators and pins. These interrupt register states will be retained across hibernate wakeup resets. For more details, see Hibernate Mode on page 81. 13.1.8 Stop Wakeup Reset Stop wakeup reset detects stop wakeup sources and performs a device reset to return to the Active power mode. Stop wakeup resets are caused by the XRES pin or the WAKEUP pin. After a stop wakeup reset, no memory contents are retained; code execution begins after reset as it does after any other reset source occurs. Some stop wakeup resets can be detected by examining the TOKEN bit-field (bits 0:7) in the PWR_STOP register. This bit-field will be filled with a key when Stop mode is entered. Its contents will be retained if the device is woken up using the WAKEUP pin. If the device is woken up with the XRES pin, the wakeup source cannot be detected. For more details, see Stop Mode on page 81. 13.2 Identifying Reset Sources When the device comes out of reset, it is often useful to know the cause of the most recent or even older resets. This is achieved in the device primarily through the RES_CAUSE register. This register has specific status bits allocated for some of the reset sources. The RES_CAUSE register supports detection of watchdog reset, software reset, and protection fault reset. It does not record the occurrences of POR, BOD, XRES, or the Hibernate and Stop wakeup resets. The bits are set on the occurrence of the corresponding reset and remain set after the reset, until cleared or a loss of retention, such as a POR reset, external reset, or brownout detect. Hibernate wakeup resets can be detected by examining the comparator and pin interrupt registers that were configured to wake the device from Hibernate mode. Stop wakeup resets that occur as a result of a WAKEUP pin event can be detected by examining the PWR_STOP register, as described previously. Stop wakeup resets that occur as a result of an XRES cannot be detected. The other reset sources can be inferred to some extent by the status of RES_CAUSE shown in Table 13-1. Table 13-1. Reset Cause Bits to Detect Reset Source Bits Name Description 0 RESET_WDT A watchdog timer reset has occurred since the last power cycle. 3 RESET_PROT_FAULT A protection violation occurred that requires a RESET. 4 RESET_SOFT Cortex-M0 requested a system reset through its SYSRESETREQ. 90 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Reset System Brownout events can be subdivided into two categories: retention resets and non-retention resets. If VCCD dips below the minimum logic operating voltage, but not below the minimum logic retention voltage, then a BOD reset occurs; but retention of registers is maintained. If VCCD dips below both minimum operating and minimum retention voltage, then a BOD reset occurs without retention of registers. This register retention can be detected using a special register, PWR_BOD_KEY. The PWR_BOD_KEY register only changes value when written by firmware or when a non- 13.3 retention reset such as a non-retention BOD, XRES, or POR event. This register may be initialized by firmware, and then checked in subsequent executions of startup code to determine if a retention BOD occurred. If these methods cannot detect the cause of the reset, then it can be one of the non-recorded and non-retention resets: non-retention BOD, POR, XRES, or Stop Wakeup reset. These resets cannot be distinguished using on-chip resources. Register List Table 13-2. Reset System Register List Register Name Description WDT_CONTROL Watchdog Timer Control Register - This register allows configuration of the device watchdog timer. CM0_AIRCR Cortex-M0 Application Interrupt and Reset Control Register - This register allows initiation of software resets, among other Cortex-M0 functions. RES_CAUSE Reset Cause Register - This register captures the cause of recent resets. PWR_STOP This register controls entry/exit from the Stop power mode. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 91 Reset System 92 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 14. Device Security PSoC® 4 offers a number of options for protecting user designs from unauthorized access or copying. Disabling debug features and enabling flash protection provide a high level of security. In PSoC 4200 devices, additional security can be gained by implementing custom functionality in the universal digital blocks (UDBs) instead of in firmware. It is more difficult to reverse-engineer a hardware design implemented in the UDBs than it is to reverse-engineer object code. The debug circuits are enabled by default and can only be disabled in firmware. If disabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Permanently disabling interfaces is not recommended for most applications because the designer cannot access the device. For more information, as well as a discussion on flash row and chip protection, see the CY8C41XX, CY8C42XX Programming Specifications. Note Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, PSoC 4 devices with full device security enabled may not be returned for failure analysis. 14.1 Features The PSoC 4 device security system has the following features: ■ User-selectable levels of protection. ■ In the most secure case provided, the chip can be “locked” such that it cannot be acquired for test/debug and it cannot enter erase cycles. Interrupting erase cycles is a known way for hackers to leave chips in an undefined state and open to observation. ■ CPU execution in a privileged mode by use of the non-maskable interrupt (NMI). When in privileged mode, NMI remains asserted to prevent any inadvertent return from interrupt instructions causing a security leak. In addition to these, PSoC 4 offers protection for individual flash row data. 14.2 How It Works 14.2.1 Device Security The CPU operates in normal user mode or in privileged mode, and the device operates in one of four protection modes: BOOT, OPEN, PROTECTED, and KILL. Each mode provides specific capabilities for the CPU software and debug. You can change the mode by writing to the CPUSS_PROTECTION register. ■ BOOT mode: The device comes out of reset in BOOT mode. It stays there until its protection state is copied from supervisor flash to the protection control register (CPUSS_PROTECTION). The debug-access port is stalled until this has happened. BOOT is a transitory mode required to set the part to its configured protection state. During BOOT mode, the CPU always operates in privileged mode. ■ OPEN mode: This is the factory default. The CPU can operate in user mode or privileged mode. In user mode, flash can be programmed and debugger features are supported. In privileged mode, access restrictions are enforced. ■ PROTECTED mode: The user may change the mode from OPEN to PROTECTED. This disables all debug access to user code or memory. Access to most registers is still available; debug access to registers to reprogram flash is not available. The mode can be set back to OPEN but only after completely erasing the flash. ■ KILL mode: The user may change the mode from OPEN to KILL. This removes all debug access to user code or memory, and the flash cannot be erased. Access to most registers is still available; debug access to registers to reprogram flash is not available. The part cannot be taken out of KILL mode; devices in KILL mode may not be returned for failure analysis. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 93 Device Security 14.2.2 Flash Security The PSoC 4 devices include a flexible flash-protection system that controls access to flash memory. This feature is designed to secure proprietary code, but it can also be used to protect against inadvertent writes to the bootloader portion of flash. Flash memory is organized in rows. You can assign one of two protection levels to each row; see Table 14-1. Flash protection levels can only be changed by performing a complete flash erase. For more details, see the Nonvolatile Programming chapter on page 279. Memory Table 14-1. Flash Protection Levels Protection Setting Unprotected Full Protection Allowed External read and write, Internal read and write External reada Internal read Not Allowed – External write, Internal write a. To protect the PSoC 4 device from external read operations, you should change the device protection settings to PROTECTED. 94 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section E: Digital System This section encompasses the following chapters: ■ Serial Communications Block (SCB) chapter on page 97 ■ Universal Digital Blocks (UDB) chapter on page 131 ■ Timer, Counter, and PWM chapter on page 171 Top Level Architecture Digital System Block Diagram UDB UDB 4x TCPWM Programmable Digital x4 UDB 2x SCB- I2C/SPI/UART Peripheral Interconnect (MMIO) UDB Port Interface & Digital System Interconnect (DSI) High Speed I/O Matrix PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 95 96 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 15. Serial Communications Block (SCB) The Serial Communications Block (SCB) of PSoC® 4 supports three serial interface protocols: SPI, UART, and I2C. Only one of the protocols is supported by an SCB at any given time. PSoC 4 devices have two SCBs. Additional instances of the serial peripheral interface (SPI) and UART protocols can be implemented using the universal digital blocks (UDBs). 15.1 Features This block supports the following features: ■ Standard SPI master and slave functionality with Motorola, Texas Instruments, and National Semiconductor protocols ■ Standard UART functionality with SmartCard reader, Local Interconnect Network (LIN), and IrDA protocols ■ Standard I2C master and slave functionality ■ Standard LIN slave functionality with LIN v1.3 and LIN v2.1/2.2 specification compliance ■ Low-power (Deep-Sleep) mode of operation for SPI and I2C protocols (using external clocking) Each of the three protocols is explained in the following sections. 15.2 Serial Peripheral Interface (SPI) The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple slaves are supported with individual slave select lines. You can use the SPI master mode when the PSoC has to communicate with one or more SPI slave devices. The SPI slave mode can be used when the PSoC has to communicate with an SPI master device. 15.2.1 Features ■ Supports master and slave functionality ■ Supports three types of SPI protocols: ❐ Motorola SPI – modes 0, 1, 2, and 3 ❐ Texas Instruments SPI, with coinciding and preceding data frame indicator for mode 1 ❐ National Semiconductor (MicroWire) SPI for mode 0 ■ Supports up to four slave select lines ■ Data frame size programmable from 4 bits to 16 bits ■ Interrupts or polling CPU interface ■ Programmable oversampling ■ Supports externally clocked slave operation: ❐ In this mode, the slave operates in Active, Sleep, and Deep-Sleep system power modes PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 97 Serial Communications Block (SCB) 15.2.2 General Description Figure 15-1 illustrates an example of SPI master with four slaves. Figure 15-1. SPI Example SCLK MOSI SPI Master SPI Slave 1 MISO Slave Select (SS) 1 SPI Slave 2 Slave Select (SS) 2 SPI Slave 3 Slave Select (SS) 3 SPI Slave 4 Slave Select (SS) 4 A standard SPI interface consists of four signals as follows. ■ Texas Instruments SPI: A variation of the original SPI protocol, in which data frames are identified by a pulse on the SS line. ■ National Semiconductors SPI: A half duplex variation of the original SPI protocol. ■ SCLK: Serial clock (clock output from the master, input to the slave). ■ MOSI: Master-out-slave-in (data output from the master, input to the slave). ■ MISO: Master-in-slave-out (data input to the master, output from the slave). 15.2.3 ■ Slave Select (SS): Typically an active low signal (output from the master, input to the slave). 15.2.3.1 SPI Modes of Operation Motorola SPI A simple SPI data transfer involves the following: the master selects a slave by driving its SS line, then it drives data on the MOSI line and a clock on the SCLK line. The slave uses either of the edges of SCLK depending on the configuration to capture the data on the MOSI line; it also drives data on the MISO line, which is captured by the master. The original SPI protocol was defined by Motorola. It is a full duplex protocol. Multiple data transfers may happen with the SS line held at '0'. As a result, slave devices must keep track of the progress of data transfers to separate individual data frames. When not transmitting data, the SS line is held at '1' and SCLK is typically pulled low. By default, the SPI interface supports a data frame size of eight bits (1 byte). The data frame size can be configured to any value in the range 4 to 16 bits. The serial data can be transmitted either most significant bit (MSb) first or least significant bit (LSB) first. Modes of Motorola SPI Three different variants of the SPI protocol are supported by the SCB: ■ 98 Motorola SPI: This is the original SPI protocol. The Motorola SPI protocol has four different modes based on how data is driven and captured on the MOSI and MISO lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA). Clock polarity determines the value of the SCLK line when not transmitting data. CPOL = '0' indicates that SCLK is '0' when not transmitting data. CPOL = '1' indicates that SCLK is '1' when not transmitting data. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Clock phase determines when data is driven and captured. CPHA=0 means sample (capture data) on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. With CPHA=0, the data must be stable for setup time before the first clock cycle. ■ Mode 1; CPOL is '0', CPHA is '1': Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. ■ Mode 2: CPOL is '1', CPHA is '0': Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. ■ ■ Mode 3: CPOL is '1', CPHA is '1': Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Mode 0: CPOL is '0', CPHA is '0': Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Figure 15-2 illustrates driving and capturing of MOSI/MISO data as a function of CPOL and CPHA. Figure 15-2. SPI Motorola, 4 Modes CPOL = 0 CPHA = 0 SCLK MISO / MOSI MSB LSB CPOL = 0 CPHA = 1 SCLK MISO / MOSI MSB LSB CPOL = 1 CPHA = 0 SCLK MISO / MOSI MSB LSB CPOL = 1 CPHA = 1 SCLK MISO / MOSI MSB LSB LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 99 Serial Communications Block (SCB) Figure 15-3 illustrates a single 8-bit data transfer and two successive 8-bit data transfers in mode 0 (CPOL is '0', CPHA is '0'). Figure 15-3. SPI Motorola Data Transfer Example CPOL = 0, CPHA = 0 single data transfer SCLK Slave Select MOSI MISO MSB LSB MSB LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out LSB CPOL = 0, CPHA = 0 two successive data transfers SCLK Slave Select MOSI MISO MSB MSB Configuring SCB for SPI Motorola Mode To configure the SCB for SPI Motorola mode, set various register bits in the following order: 1. Select SPI by writing '01' to the MODE (bits [25:24]) of the SCB_CTRL register. 2. Select SPI Motorola mode by writing '00' to the MODE (bits [25:24]) of the SCB_SPI_CTRL register. LSB MSB LSB LSB MSB LSB CPHA is '1'): data is driven on a rising edge of SCLK and data is captured on a falling edge of SCLK. Figure 15-4 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse precedes the first data bit. Note how the SELECT pulse of the second data transfer coincides with the last data bit of the first data transfer. 3. Select the mode of operation in Motorola by writing to the CPHA and CPOL fields (bits 2 and 3 respectively) of the SCB_SPI_CTRL register. 4. Follow steps 2 to 4 mentioned in Enabling and Initializing SPI on page 104. Note that PSoC Creator does all this automatically with the help of GUIs. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 15.2.3.2 Texas Instruments SPI The Texas Instruments' SPI protocol redefines the use of the SS signal. It uses the signal to indicate the start of a data transfer, rather than a low active slave select signal, as in the case of Motorola SPI. As a result, slave devices need not keep track of the progress of data transfers to separate individual data frames. The start of a transfer is indicated by a high active pulse of a single bit transfer period. This pulse may occur one cycle before the transmission of the first data bit, or may coincide with the transmission of the first data bit. The TI SPI protocol supports only mode 1 (CPOL is '0' and 100 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Figure 15-4. SPI TI Data Transfer Example CPOL=0, CPHA=1 single data transfer SCLK Slave Select MOSI MSB LSB MISO MSB LSB LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out CPOL=0, CPHA=1 two successive data transfers SCLK Slave Select MOSI MSB LSB MSB LSB MISO MSB LSB MSB LSB Figure 15-5 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse coincides with the first data bit of a frame. Figure 15-5. SPI TI Data Transfer Example CPOL=0, CPHA=1 single data transfer SCLK Slave Select MOSI MSB LSB MISO MSB LSB LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out CPOL=0, CPHA=1 two successive data transfers SCLK Slave Select MOSI MSB LSB MSB LSB MISO MSB LSB MSB LSB PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 101 Serial Communications Block (SCB) Configuring SCB for SPI TI Mode 15.2.3.3 To configure the SCB for SPI TI mode, set various register bits in the following order: The National Semiconductors' SPI protocol is a half duplex protocol. Rather than transmission and reception occurring at the same time, they take turns. The transmission and reception data sizes may differ. A single "idle" bit transfer period separates transmission from reception. However, the successive data transfers are NOT separated by an "idle" bit transfer period. 1. Select SPI by writing '01' to the MODE (bits [25:24]) of the SCB_CTRL register. 2. Select SPI TI mode by writing '01' to the MODE (bits [25:24]) of the SCB_SPI_CTRL register. 3. Select the mode of operation in TI by writing to the SELECT_PRECEDE field (bit 1) of the SCB_SPI_CTRL register ('1' configures the SELECT pulse to precede the first bit of next frame and '0' otherwise). 4. Follow steps 2 to 5 mentioned in Enabling and Initializing SPI on page 104. Note that PSoC Creator does all this automatically with the help of GUIs. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. National Semiconductors SPI The National Semiconductors SPI protocol only supports mode 0: data is driven on a falling edge of SCLK and data is captured on a rising edge of SCLK. Figure 15-6 illustrates a single data transfer and two successive data transfers. In both cases the transmission data transfer size is eight bits and the reception data transfer size is four bits. Figure 15-6. SPI NS Data Transfer Example CPOL=0, CPHA=0 Transfer of one MOSI and one MISO data frame SCLK Slave Select MOSI MSB LSB MSB MISO LSB “idle” ‘0’ cycle CPOL=0, CPHA=0 Successive transfer of two MOSI and one MISO data frame SCLK Slave Select MOSI MSB MSB LSB MISO MSB “idle” ‘0’ cycle LSB No “idle” cycle LEGEND: CPOL : Clock Polarity CPHA : Clock Phase SCLK : SPI interface clock MOSI : SPI Master-Out-Slave-In MISO : SPI Master-In-Slave-Out 102 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Configuring SCB for SPI NS Mode To configure the SCB for SPI NS mode, set various register bits in the following order: 1. Select SPI by writing '01' to the MODE (bits [25:24]) of the SCB_CTRL register. 2. Select SPI NS mode by writing '10' to the MODE (bits [25:24]) of the SCB_SPI_CTRL register. 15.2.4 3. Follow steps 2 to 5 mentioned in Enabling and Initializing SPI on page 104. Note that PSoC Creator does all this automatically with the help of Component customizers. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. . SPI Registers The SPI interface is controlled using a set of 32-bit control and status registers listed in Table 15-1. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. Table 15-1. SPI Registers Register Name Operation SCB_CTRL Enables the SCB, selects the type of serial interface (SPI, UART, I2C), and selects internally and externally clocked operation. SCB_SPI_CTRL Configures the SPI as either a master or a slave, selects SPI protocols (Motorola, TI, National) and clockbased submodes in Motorola SPI (modes 0,1,2,3), selects the type of SELECT signal in TI SPI. SCB_SPI_STATUS Indicates whether the SPI bus is busy. SCB_TX_CTRL Enables the transmitter, specifies the data frame width, and specifies whether MSB or LSB is the first bit in transmission. SCB_RX_CTRL Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. SCB_TX_FIFO_CTRL Specifies the trigger level, clears the transmitter FIFO and shift registers, and performs the FREEZE operation of the transmitter FIFO. SCB_RX_FIFO_CTRL Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver. SCB_TX_FIFO_WR Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. SCB_RX_FIFO_RD Holds the data frame read from the receiver FIFO. Reading a data frame removes the data frame from the FIFO - behavior is similar to that of a POP operation. This register has a side effect when read by software: a data frame is removed from the FIFO. SCB_RX_FIFO_RD_SILENT Holds the data frame read from the receiver FIFO. Reading a data frame does not remove the data frame from the FIFO; behavior is similar to that of a PEEK operation. SCB_RX_MATCH Holds the slave device address and mask values. SCB_TX_FIFO_STATUS Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides if the transmitter FIFO holds the valid data. SCB_RX_FIFO_STATUS Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver. 15.2.5 SPI Interrupts The SPI supports both internal and external interrupt requests. The internal interrupt events are listed here. PSoC Creator generates the necessary interrupt service routines (ISRs) for handling buffer management interrupts. Custom ISRs can also be used by connecting external interrupt component to the interrupt output of the SPI component (with external interrupts enabled). The SPI predefined interrupts can be classified as TX interrupts and RX interrupts. The TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal goes high when any of the enabled TX interrupt sources are true. The RX interrupt output is the logical OR of the group of all possible RX interrupt sources. This signal goes high when any of the enabled Rx interrupt sources are true. Various interrupt registers are used to determine the actual source of the interrupt. The SPI supports interrupts on the following events: ■ SPI master transfer done ■ SPI Bus Error - Slave deselected at an unexpected time in the SPI transfer ■ TX ❐ TX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 103 Serial Communications Block (SCB) ■ ■ ❐ TX FIFO is not full ❐ TX FIFO is empty ❐ TX FIFO overflow ❐ TX FIFO underflow Table 15-2. SCB_CTRL Register Bits Name RX Value Description 00 I2C mode 01 SPI mode ❐ RX FIFO is full ❐ RX FIFO is not empty 10 UART mode ❐ RX FIFO overflow 11 Reserved ❐ RX FIFO underflow [25:24] 31 MODE ENABLED SPI Externally clocked ❐ Wake up request on slave select ❐ SPI STOP detection at the end of each transfer ❐ SPI STOP detection at the end of a write transfer 0 SCB block disabled 1 SCB block enabled Table 15-3. SCB_SPI_CTRL Register Bits Name Value Description 00 SPI Motorola submode. 01 SPI Texas Instruments submode. 10 SPI National Semiconductors submode. The SPI must be programmed in the following order: 11 Reserved. 1. Program protocol specific information using the SCB_SPI_CTRL register, according to Table 15-3. This includes selecting the submodes of the protocol and selecting master-slave functionality. 0 Slave mode. 1 Master mode. Note The SPI interrupt signal is hard-wired to the CortexM0 NVIC and cannot be routed to external pins. [25:24] 15.2.6 MODE Enabling and Initializing SPI 31 Table 15-4. SCB_TX_CTRL/SCB_RX_CTRL Registers 2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 15-4: a. Specify the data frame width. MASTER_M ODE Bits Name [3:0] DATA_ WIDTH 8 MSB_FIRST b. Specify whether MSB or LSB is the first bit to be transmitted/received. c. Enable the transmitter and receiver. 3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-5: 9 ENABLED In the SCB_TX_CTRL register, this is the transmitter enable bit. This bit should be set for all protocols when transmitting. Otherwise, the transmit protocol may not function. In SCB_RX_CTRL register, this is the receiver enable bit. This bit should be enabled for all protocols when receiving. Otherwise, the receive protocol may not function. 4. Program SCB_CTRL register to enable the SCB block. Also select the mode of operation. These register bits are shown in Table 15-2 104 31 1= MSB first 0= LSB first MEDIAN c. Freeze the TX and RX FIFO. 5. Enable the block (write a '1' to the ENABLED bit of the SCB_CTRL register). After the block is enabled, control bits should not be changed. Changes should be made after disabling the block; for example, to modify the operation mode (from Motorola mode to TI mode) or to go from externally clocked to internally clocked operation. The change takes effect only after the block is reenabled. Note that re-enabling the block causes re-initialization and the associated state is lost (for example, FIFO content). 'DATA_WIDTH + 1' is the number of bits in the transmitted or received data frame. The valid range is [3, 15]. This does not include start, stop, and parity bits. This is for SCB_RX_CTRL only. Decides whether a digital three-tap median filter is applied on the input interface lines. This filter should reduce susceptibility to errors, but it requires higher oversampling values. 1=Enabled 0=Disabled a. Set the trigger level. b. Clear the transmitter and receiver FIFO and Shift registers. Description PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Table 15-5. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL Registers Bits Name Description [2:0] Trigger level. When the transmitter FIFO has less entries or receiver FIFO TRIGGER_LE has more entries than the value of this VEL field, a transmitter or receiver trigger event is generated in the respective case. 16 CLEAR When '1', the transmitter or receiver FIFO and the shift registers are cleared. FREEZE When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze does not advance the TX or RX FIFO read/write pointer. 17 15.2.7 Internally and Externally Clocked SPI Operations The SCB supports both internally and externally clocked operations for SPI and I2C functions. An internally clocked operation uses a clock provided by the chip. An externally clocked operation uses a clock provided by the serial interface. Externally clocked operation enables operation in the Deep-Sleep system power mode. Internally clocked operation uses the high-frequency clock (HFCLK) of the system. For more information on system clocking, see the Clocking System chapter on page 61. It also supports oversampling. Oversampling is implemented with respect to the high-frequency clock. The OVS (bits [3:0]) of the SCB_CTRL register specify the oversampling. In SPI master mode, the valid range for oversampling is 4 to 16. Hence, with a clock speed of 48 MHz, the maximum bit rate is 12 Mbps. However, if you consider the I/O cell and routing delays, the oversampling must be set between 6 and 16 for proper operation. So, the maximum bit rate is 8 Mbps. Note To achieve maximum possible bit rate, LATE_MISO_SAMPLE must be set to '1' in SPI master mode. This has a default value of ‘0’. In SPI slave mode, the OVS field (bits [3:0]) of SCB_CTRL register is not used. However, there is a frequency requirement for the SCB clock with respect to the interface clock (SCLK). This requirement is expressed in terms of the ratio (SCB clock/SCLK). This ratio is dependent on two fields: MEDIAN of SCB_RX_CTRL register and LATE_MISO_SAMPLE of SCB_CTRL register. If the external SPI master supports Late MISO sampling and if the median bit is set to ‘0’, the maximum data rate that can be achieved is 16 Mbps. If the external SPI master does not support late MISO sampling, the maximum data rate is limited to 8 Mbps (with the median bit set to ‘0’). Based on these bits, the maximum bit rates are given in Table 15-6. Table 15-6. SPI Slave Maximum Data Rates Maximum Bit Rate at Peripheral Clock of 48 MHz Ratio Requirement Median of SCB_RX_CTRL LATE_MISO_SAMPLE of SCB_CTRL 8 Mbps 6 0 1 6 Mbps 8 1 1 4 Mbps 12 0 0 3 Mbps 16 1 0 Externally clocked operation is limited to: ■ Slave functionality. ■ Motorola mode 0. Internally and externally clocked operation is determined by two register fields of the SCB_CTRL register: ■ EC_AM_MODE: Indicates whether SPI slave selection is internally ('0') or externally ('1') clocked. SPI slave selection comprises the first part of the protocol. ■ EC_OP_MODE: Indicates whether the rest of the protocol operation (besides SPI slave selection) is internally ('0') or externally ('1') clocked. These two register fields determine the functional behavior of SPI. The register fields should be set based on the required behavior in Active, Sleep, and Deep-Sleep system power mode. Improper setting may result in faulty behavior in certain system power modes. Table 15-7 describes the settings for SPI. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 105 Serial Communications Block (SCB) EC_OP_MODE should always be set to '0'. However, EC_AM_MODE can be set to '0' or '1'. Table 15-7. SPI Operation SPI Mode EC_OP_MODE = 0 System Power Mode Active and Sleep Deep-Sleep Hibernate Stop EC_AM_MODE = 0 Selection using internal clock. Operation using internal clock. Not supported Not supported The SCB is not available in these modes (see the Power Modes chapter on page 75) In Active system power mode, the CPU and the block's internally clocked operation are active and the wakeup interrupt cause is disabled (associated MASK bit is '0'). But in the Sleep mode, wakeup interrupt cause can be either enabled or disabled (MASK bit can be either '1' or '0') based on the application. The remaining operations in the Sleep mode are same as that of the Active mode. The internally clocked operation takes care of the ongoing SPI transfer. In Deep-Sleep system power mode, the CPU needs to be woken up and the wakeup interrupt cause is enabled (MASK bit is '1'). Waking up takes time, so the ongoing SPI transfer is negatively acknowledged ('1' bit or "0xFF" byte is sent out on the MISO line) and the internally clocked operation takes care of the next SPI transfer when it is woken up. 106 EC_AM_MODE = 1 Selection using external clock: Wakeup interrupt cause is enabled (MASK = 1). Send 0xFF. EC_OP_MODE is '0' and EC_AM_MODE is '1': This setting works in Active and Sleep system power mode and provides limited (wake up) functionality in Deep-Sleep system power mode. SPI slave selection is performed by the externally clocked logic: in Active system power mode, both internally and externally clocked logic are active, and in Deep-Sleep system power mode, only the externally clocked logic is active. When the externally clocked logic detects slave selection, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wake up the CPU. ■ EC_AM_MODE = 0 Selection using external clock: Operation using internal clock. In Active mode, the Wakeup interrupt cause is disabled (MASK = 0). In Sleep mode, the MASK bit Not supported can be configured by the user. EC_OP_MODE is '0' and EC_AM_MODE is '0': This setting only works in Active and Sleep system power modes. The entire block's functionality is provided in the internally clocked domain. ■ EC_OP_MODE = 1 EC_AM_MODE = 1 15.3 UART The Universal Asynchronous Receiver/Transmitter (UART) protocol is an asynchronous serial interface protocol. UART communication is typically point-to-point. The UART interface consists of two signals: ■ TX: Transmitter output ■ RX: Receiver input 15.3.1 Features ■ Asynchronous transmitter and receiver functionality ■ Supports a maximum data rate of 3 Mbps ■ Supports UART protocol ■ ❐ Standard UART ❐ SmartCard (ISO7816) reader. ❐ IrDA Supports Local Interconnect Network (LIN) ❐ Break detection ❐ Baud rate detection ❐ Collision detection (ability to detect that a driven bit value is not reflected on the bus, indicating that another component is driving the same bus) ■ Multi-processor mode ■ Data frame size programmable from 4 to 9 bits ■ Programmable number of STOP bits, which can be set in terms of half bit periods between 1 and 4 ■ Parity support (odd and even parity) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) ■ Interrupt or polling CPU interface ■ Programmable oversampling 15.3.2 the parity bit is automatically disabled. Figure 15-8 depicts the default configuration of the UART interface of the SCB. Note UART interface does not support external clocking operation. Hence, UART operates only in the Active and Sleep system power modes. General Description Figure 15-7 illustrates a standard UART TX and RX. 15.3.3 Figure 15-7. UART Example RX TX 15.3.3.1 UART UART RX TX A typical UART transfer consists of a "Start Bit" followed by multiple "Data Bits", optionally followed by a "Parity Bit" and finally completed by one or more "Stop Bits". The Start and Stop bits indicate the start and end of data transmission. The Parity bit is sent by the transmitter and is used by the receiver to detect single bit errors. As the interface does not have a clock (asynchronous), the transmitter and receiver use their own clocks; also, they need to agree upon the period of a bit transfer. Three different serial interface protocols are supported: ■ Standard UART protocol ❐ Multi-Processor Mode ❐ Local Interconnect Network (LIN) ■ SmartCard, similar to UART, but with a possibility to send a negative acknowledgement ■ IrDA, modification to the UART with a modulation scheme By default, UART supports a data frame width of eight bits. However, this can be configured to any value in the range of 4 to 9. This does not include start, stop, and parity bits. The number of stop bits can be in the range of 1 to 4. The parity bit can be either enabled or disabled. If enabled, the type of parity can be set to either even parity or odd parity. The option of using the parity bit is available only in the Standard UART and SmartCard UART modes. For IrDA UART mode, UART Modes of Operation Standard Protocol A typical UART transfer consists of a start bit followed by multiple data bits, optionally followed by a parity bit and finally completed by one or more stop bits. The start bit value is always '0', the data bits values are dependent on the data transferred, the parity bit value is set to a value guaranteeing an even or odd parity over the data bits, and the stop bit value is '1'. The parity bit is generated by the transmitter and can be used by the receiver to detect single bit transmission errors. When not transmitting data, the TX line is '1' – the same value as the stop bits. Because the interface does not have a clock, the transmitter and receiver need to agree upon the period of a bit transfer. The transmitter and receiver have their own internal clocks. The receiver clock runs at a higher frequency than the bit transfer frequency, such that the receiver may oversample the incoming signal. The transition of a stop bit to a start bit is represented by a change from '1' to '0' on the TX line. This transition can be used by the receiver to synchronize with the transmitter clock. Synchronization at the start of each data transfer allows error-free transmission even in the presence of frequency drift between transmitter and receiver clocks. The required clock accuracy is dependent on the data transfer size. The stop period or the amount of stop bits between successive data transfers is typically agreed upon between transmitter and receiver, and is typically in the range of 1 to 3-bit transfer periods. Figure 15-8 illustrates the UART protocol. Figure 15-8. UART, Standard Protocol Example Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) TX / RX IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA LEGEND: TX / RX : Transmit or Receive line The receiver oversamples the incoming signal; the value of the sample point in the middle of the bit transfer period (on the receiver's clock) is used. Figure 15-9 illustrates this. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 107 Serial Communications Block (SCB) Figure 15-9. UART, Standard Protocol Example (Single Sample) TX clock TX / RX IDLE DATA START DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA RX clock Sample points Sample points Synchronisation Synchronisation LEGEND: TX / RX : Transmit or Receive line Alternatively, three samples around the middle of the bit transfer period (on the receiver's clock) are used for a majority vote to increase accuracy. Figure 15-10 illustrates this. Figure 15-10. UART, Standard Protocol (Multiple Samples) TX clock TX / RX IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA RX clock Sample points Sample points Synchronisation Synchronisation LEGEND: TX / RX : Transmit or Receive line UART Multi-Processor Mode The UART_MP (multi-processor) mode is defined with single-master-multi-slave topology, as Figure 15-11 shows. This mode is also known as UART 9-bit protocol because the data field is nine bits wide. UART_MP is part of Standard UART mode. Figure 15-11. UART MP Mode Bus Connections UART MP Master TX RX Master TX Master RX RX TX UART MP Slave 1 108 RX TX UART MP Slave 2 RX TX UART MP Slave 3 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) The main properties of UART_MP mode are: ■ Single master with multiple slave concept (multi-drop network). ■ Each slave is identified by a unique address. ■ Using 9-bit data field, with the ninth bit as address/data flag (MP bit). When set high, it indicates an address byte; when set low it indicates a data byte. A data frame is illustrated in Figure 15-12. ■ Parity bit is disabled. Figure 15-12. UART MP Data Frame DATA Field IDLE START DATA DATA DATA DATA DATA DATA DATA DATA STOP MP The SCB can be used as either master or slave device in UART_MP mode. Both SCB_TX_CTRL and SCB_RX_CTRL registers should be set to 9-bit data frame size. When the SCB works as UART_MP master device, the firmware changes the MP flag for every address or data frame. When it works as UART_MP slave device, the MP_MODE field of the SCB_UART_RX_CTRL register should be set to '1'. The SCB_RX_MATCH register should be set for the slave address and address mask. The matched address is written in the RX_FIFO when ADDR_ACCEPT field of the SCB_CTRL register is set to '1'. If received address does not match its own address, then the interface ignores the following data, until next address is received for compare. UART Local Interconnect Network (LIN) Mode The LIN protocol is supported by the SCB as part of the standard UART. LIN is designed with single-master-multi-slave topology. There is one master node and multiple slave nodes on the LIN bus. The SCB UART supports both LIN master and slave functionality. The LIN specification defines both physical layer (layer 1) and data link layer (layer 2). Figure 15-13 illustrates the UART_LIN and LIN Transceiver. Figure 15-13. UART_LIN and LIN Transceiver LIN Master 1 UART LIN TX RX LIN Transceiver LIN Slave 1 LIN Slave 2 UART LIN UART LIN TX RX TX RX LIN Transceiver LIN Transceiver LIN BUS LIN Frame Structure LIN protocol defines two tasks: ■ Master task: This task involves sending a header packet to initiate a LIN transfer. ■ Slave task: This task involves transmitting or receiving a response. LIN is based on the transmission of frames at predetermined moments of time. A frame is divided into header and response fields, as shown in Figure 15-15. ■ The master node supports master task and slave task; the slave node supports only slave task, as shown in Figure 15-14. The header field consists of: ❐ Break field (at least 13 bit periods with the value '0'). ❐ Sync field (a 0x55 byte frame). A sync field can be used to synchronize the clock of the slave task with that of the master task. ❐ Identifier field (a frame specifying a specific slave). Figure 15-14. LIN Bus Nodes and Tasks Master Node Slave Node Slave Node ■ The response field consists of data and checksum. Master Task Slave Task Slave Task Slave Task LIN bus PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 109 Serial Communications Block (SCB) Figure 15-15. LIN Frame Structure In LIN protocol communication, the least significant bit (LSB) of the data is sent first and the most significant bit (MSB) last. The start bit is encoded as zero and the stop bit is encoded as one. The following sections describe all the byte fields in the LIN frame. Break Field. Every new frame starts with a break field, which is always generated by the master. The break filed has logical zero with a minimum of 13 bit times and followed by a break delimiter. The break field structure is as shown in Figure 15-16. Figure 15-16. LIN Break Field Sync Field. This is the second field transmitted by the master in the header field; its value is 0x55. A sync field can be used to synchronize the clock of the slave task with that of the master task for automatic baud rate detection. Figure 15-17 shows the LIN sync field structure. Figure 15-17. LIN Sync Field Protected identifier (PID) Field. A protected identifier field consists of two sub-fields: the frame identifier (bits 0-5) and the parity (bit 6 and bit 7). The PID field structure is shown in Figure 15-18. ■ ■ Frame identifier: The frame identifiers are split into three categories ❐ Values 0 to 59 (0x3B) are used for signal carrying frames ❐ 60 (0x3C) and 61 (0x3D) are used to carry diagnostic and configuration data ❐ 62 (0x3E) and 63 (0x3F) are reserved for future protocol enhancements Parity: Frame identifier bits are used to calculate the parity Figure 15-18 shows the PID field structure. Figure 15-18. PID Field Data. In LIN, every frame can carry a minimum of one byte and maximum of 8 bytes of data. Here, the LSB of the data byte is sent first and the MSB of the data byte is sent last. Checksum. The checksum is the last byte field in the LIN frame. It is calculated by inverting the 8-bit sum along with carryover of all data bytes only or the 8-bit sum with the carryover of all data bytes and the PID field. There are two types of checksums in LIN frames. They are: ■ Classic checksum: the checksum calculated over all the data bytes only (used in LIN 1.x slaves). ■ Enhanced checksum: the checksum calculated over all the data bytes along with the protected identifier (used in LIN 2.x slaves). LIN Frame Types The type of frame refers to the conditions that need to be valid to transmit the frame. According to the LIN specification, there are five different types of LIN frames. A node or cluster does not have to support all frame types. Unconditional Frame. These frames carry the signals and their frame identifiers (of 0x00 to 0x3B range). The subscriber will receive the frames and make it available to the application; the publisher of the frame will provide the response to the header. Event-Triggered Frame. The purpose of an eventtriggered frame is to increase the responsiveness of the LIN cluster without assigning too much of the bus bandwidth to polling of multiple slave nodes with seldom occurring events. Event-triggered frames carry the response of one or more unconditional frames. The unconditional frames associated with an event triggered frame should: ■ Have equal length ■ Use the same checksum model (either classic or enhanced) ■ Reserve the first data field to its protected identifier ■ Be published by different slave nodes ■ Not be included directly in the same schedule table as the event-triggered frame Sporadic Frame. The purpose of the sporadic frames is to merge some dynamic behavior into the schedule table without affecting the rest of the schedule table. These 110 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) frames have a group of unconditional frames that share the frame slot. When the sporadic frame is due for transmission, the unconditional frames are checked if they have any updated signals. If no signals are updated, no frame will be transmitted and the frame slot will be empty. Diagnostic Frames. Diagnostic frames always transport layer, and contains eight data bytes. carry The frame identifier for diagnostic frame is: ■ Master request frame (0x3C), or ■ Slave response frame (0x3D) Before transmitting a master request frame, the master task queries its diagnostic module to see if it will be transmitted or if the bus will be silent. A slave response frame header will be sent unconditionally. The slave tasks publish and subscribe to the response according to their diagnostic modules. Reserved Frames. These frames are reserved for future use; their frame identifiers are 0x3E and 0x3F. LIN Go-To-Sleep and Wake-Up The LIN protocol has the feature of keeping the LIN bus in Sleep mode, if the master sends the go-to-sleep command. The go-to-sleep command is a master request frame (ID = 0x3C) with the first byte field is equal to 0x00 and rest set to 0xFF. The slave node application may still be active after the go-to-sleep command is received. This behavior is application specific. The LIN slave nodes automatically enter Sleep mode if the LIN bus inactivity is more than four seconds. Wake-up can be initiated by any node connected to the LIN bus - either LIN master or any of the LIN slaves by forcing the bus to be dominant for 250 µs to 5 ms. Each slave should detect the wakeup request and be ready to process headers within 100 ms. The master should also detect the wakeup request and start sending headers when the slave nodes are active. To support LIN, a dedicated (off-chip) line driver/receiver is required. Supply voltage range on the LIN bus is 7 V to 18 V. Typically, LIN line drivers will drive the LIN line with the value provided on the SCB TX line and present the value on the LIN line to the SCB RX line. By comparing TX and RX lines in the SCB, bus collisions can be detected (indicated by the SCB_UART_ARB_LOST field of the SCB_INTR_TX register). 2. Configure the UART interface to operate as a Standard protocol by writing '00' to the MODE field (bits [25:24]) of the SCB_UART_CTRL register. 3. To enable the UART MP Mode or UART LIN Mode, write '1' to the MP_MODE (bit 10) or LIN_MODE (bit 12) respectively of the SCB_UART_RX_CTRL register. 4. Follow steps 2 to 5 described in Enabling and Initializing UART on page 114. Note that PSoC Creator does all this automatically with the help of GUIs. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 15.3.3.2 SmartCard (ISO7816) ISO7816 is asynchronous serial interface, defined with single-master-single slave topology. ISO7816 defines both Reader (master) and Card (slave) functionality. For more information, refer to the ISO7816 Specification. Only master (reader) function is supported by the SCB. This block provides the basic physical layer support with asynchronous character transmission. UART_TX line is connected to SmartCard IO line, by internally multiplexing between UART_TX and UART_RX control modules. The SmartCard transfer is similar to a UART transfer, with the addition of a negative acknowledgement (NACK) that may be sent from the receiver to the transmitter. A NACK is always '0'. Both master and slave may drive the same line, although never at the same time. A SmartCard transfer has the transmitter drive the start bit and data bits (and optionally a parity bit). After these bits, it enters its stop period by releasing the bus. Releasing results in the line being '1' (the value of a stop bit). After one bit transfer period into the stop period, the receiver may drive a NACK on the line (a value of '0') for one bit transfer period. This NACK is observed by the transmitter, which reacts by extending its stop period by one bit transfer period. For this protocol to work, the stop period should be longer than one bit transfer period. Note that a data transfer with a NACK takes one bit transfer period longer, than a data transfer without a NACK. Typically, implementations use a tristate driver with a pull-up resistor, such that when the line is not transmitting data or transmitting the Stop bit, its value is '1'. Figure 15-19 illustrates the SmartCard protocol. Configuring the SCB as Standard UART Interface To configure the SCB as a standard UART interface, set various register bits in the following order: 1. Configure the SCB as UART interface by writing '10' to the MODE field (bits [25:24]) of the SCB_CTRL register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 111 Serial Communications Block (SCB) Figure 15-19. SmartCard Example Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) without NACK TX / RX IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA DATA DATA Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) with NACK TX / RX IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP NACK STOP START LEGEND: TX / RX : Transmit or Receive line The communication Baud rate for ISO7816 is given as: Baud rate= f7816 × (D/F) Where f7816 is the clock frequency, F is the clock rate conversion integer, and D is the baud rate adjustment integer. By default, F = 372, D = f1, and the maximum clock frequency is 5 MHz. Thus, maximum baud rate is 13.4 Kbps. Typically, a 3.57-MHz clock is selected. The typical value of the baud rate is 9.6 Kbps. Configuring SCB as UART SmartCard Interface '0' is signaled by a short '1' pulse on the line and a bit value of '1' is signaled by holding the line to '0'. For these data rates (<=115.2 Kbps), the RZI modulation scheme is used and the pulse duration is 3/16 of the bit period. The sampling clock frequency should be set 16 times the selected baud rate, by configuring the SCB_OVS field of the SCB_CTRL register. Different communication speeds under 115.2 Kbps can be achieved by configuring corresponding block clock frequency. Additional allowable rates are 2.4 Kbps, 9.6 Kbps, 19.2 Kbps, 38.4 Kbps, and 57.6 Kbps. An IrDA serial infrared interface operates at 9.6 Kbps. Figure 15-20 shows how a UART transfer is IrDA modulated. To configure the SCB as a UART SmartCard interface, set various register bits in the following order; note that PSoC Creator does all this automatically with the help of GUIs. For more information on these registers, see the PSoC 4100/ 4200 Family: PSoC 4 Registers TRM. 1. Configure the SCB as UART interface by writing '10' to the MODE (bits [25:24]) of the SCB_CTRL register. 2. Configure the UART interface to operate as a SmartCard protocol by writing '01' to the MODE (bits [25:24]) of the SCB_UART_CTRL register. 3. Follow steps 2 to 5 described in Enabling and Initializing UART on page 114. 15.3.3.3 IrDA The SCB supports the Infrared Data Association (IrDA) protocol for data rates of up to 115.2 Kbps using the UART interface. It supports only the basic physical layer of IrDA protocol with rates less than 115.2 Kbps. Hence, the system instantiating this block must consider how to implement a complete IrDA communication system with other available system resources. The IrDA protocol adds a modulation scheme to the UART signaling. At the transmitter, bits are modulated. At the receiver, bits are demodulated. The modulation scheme uses a Return-to-Zero-Inverted (RZI) format. A bit value of 112 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Figure 15-20. IrDA Example Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) TX / RX IDLE START ‘1' ‘0' ‘1' ‘1' ‘0' ‘0' ‘1' PAR STOP START ‘0' ‘1' ‘1' ‘1' IrDA TX / RX LEGEND: TX / RX : Transmit or Receive line Configuring the SCB as UART IrDA Interface To configure the SCB as a UART IrDA interface, set various register bits in the following order; note that PSoC Creator does all this automatically with the help of GUIs. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 1. Configure the SCB as UART interface by writing '10' to the MODE (bits [25:24]) of the SCB_CTRL register. 2. Configure the UART interface to operate as IrDA protocol by writing '10' to the MODE (bits [25:24]) of the SCB_UART_CTRL register. 3. Enable the Median filter on the input interface line by writing ‘1’ to MEDIAN (bit 9) of the SCB_RX_CTRL register. 4. Configure the SCB as described in Enabling and Initializing UART on page 114. 15.3.4 UART Registers The UART interface is controlled using a set of 32-bit registers listed in Table 15-8. For more information on these registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. Table 15-8. UART Registers Register Name Operation SCB_CTRL Enables the SCB; selects the type of serial interface (SPI, UART, I2C) SCB_UART_CTRL Used to select the sub-modes of UART (standard UART, SmartCard, IrDA), also used for local loop back control. SCB_UART_RX_STATUS Used to specify the BR_COUNTER value that determines the bit period. This is used to set the accuracy of the SCB clock. This value provides more granularity than the OVS bit in SCB_CTRL register. SCB_UART_TX_CTRL Used to specify the number of stop bits, enable parity, select the type of parity, and enable retransmission on NACK. SCB_UART_RX_CTRL Performs same function as SCB_UART_TX_CTRL but is also used for enabling multi processor mode, LIN mode drop on parity error, and drop on frame error. SCB_TX_CTRL Used to enable the transmitter; also to specify the data frame width and to specify whether MSB or LSB is the first bit in transmission. SCB_RX_CTRL Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. Also decides whether a median filter is to be used on the input interface lines. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 113 Serial Communications Block (SCB) 15.3.5 UART Interrupts ❐ Parity error in received data frame ❐ LIN baud rate detection is completed ❐ LIN break detection is successful The UART supports both internal and external interrupt requests. The internal interrupt events are listed in this section. PSoC Creator generates the necessary interrupt service routines (ISRs) for handling buffer management interrupts. Custom ISRs can also be used by connecting the external interrupt component to the interrupt output of the UART component (with external interrupts enabled). 15.3.6 The UART predefined interrupts can be classified as TX interrupts and RX interrupts. The TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal goes high when any of the enabled TX interrupt sources is true. The RX interrupt output is the logical OR of the group of all possible RX interrupt sources. This signal goes high when any of the enabled Rx interrupt sources is true. The UART provides interrupts on the following events: 2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 15-10. ■ TX ❐ ■ TX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL Enabling and Initializing UART The UART must be programmed in the following order: 1. Program protocol specific information using the SCB_UART_CTRL register, according to Table 15-9. This includes selecting the submodes of the protocol, transmitter-receiver functionality, and so on. a. Specify the data frame width. b. Specify whether MSB or LSB is the first bit to be transmitted or received. c. Enable the transmitter and receiver. 3. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respectively, as shown in Table 15-11. ❐ TX FIFO is not full ❐ TX FIFO is empty ❐ TX FIFO overflow a. Set the trigger level. ❐ TX FIFO underflow ❐ TX received a NACK in SmartCard mode b. Clear the transmitter and receiver FIFO and Shift registers. ❐ TX done ❐ Arbitration lost (in LIN or SmartCard modes) c. Freeze the TX and RX FIFOs. 4. Program the SCB_CTRL register to enable the SCB block. Also select the mode of operation, as shown in Table 15-12. RX ❐ RX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL ❐ RX FIFO is full ❐ RX FIFO is not empty ❐ RX FIFO overflow ❐ RX FIFO underflow ❐ Frame error in received data frame 5. Enable the block (write a '1' to the ENABLED bit of the SCB_CTRL register). After the block is enabled, control bits should not be changed. Changes should be made after disabling the block; for example, to modify the operation mode (from SmartCard to IrDA). The change takes effect only after the block is re-enabled. Note that reenabling the block causes re-initialization and the associated state is lost (for example FIFO content). Table 15-9. SCB_UART_CTRL Register Bits Name Value 00 [25:24] MODE 16 LOOP_BACK 114 Description Standard UART 01 SmartCard 10 IrDA 11 Reserved Loop back control. This allows a SCB UART transmitter to communicate with its receiver counterpart. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Table 15-10. SCB_TX_CTRL/SCB_RX_CTRL Registers Bits Name Description [3:0] DATA_ WIDTH 'DATA_WIDTH + 1' is the no. of bits in the transmitted or received data frame. The valid range is [3, 15]. This does not include start, stop, and parity bits. 8 MSB_FIRST 1= MSB first 0= LSB first MEDIAN This is for SCB_RX_CTRL only. Decides whether a digital three-tap median filter is applied on the input interface lines. This filter should reduce susceptibility to errors, but it requires higher oversampling values. For the UART IrDA mode, this should always be '1'. 1=Enabled 0=Disabled ENABLED In SCB_TX_CTRL register, this is the transmitter enable bit. This bit should be set for all protocols when transmitting. If not enabled, the transmit protocol may not function. In SCB_RX_CTRL register, this is the receiver enable bit. This bit should be set for all protocols when receiving. If not enabled, the receive protocol may not function. 9 31 Table 15-11. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL Registers Bits Name Description [2:0] Trigger level. When the transmitter FIFO has less entries or receiver FIFO has more entries than the TRIGGER_LEVEL value of this field, a transmitter or receiver trigger event is generated in the respective case. 16 CLEAR When '1', the transmitter or receiver FIFO and the shift registers are cleared/invalidated. 17 FREEZE When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze will not advance the TX or RX FIFO read/write pointer. Table 15-12. SCB_CTRL Register Bits Name Value 00 [25:24] 31 MODE ENABLED 15.4 Description I2C mode 01 SPI mode 10 UART mode 11 Reserved 0 SCB block disabled 1 SCB block enabled Inter Integrated Circuit (I2C) This section explains the I2C implementation in PSoC 4. For more information on the I2C protocol specification, refer to the I2C-bus specification available on the NXP website. 15.4.1 Features This block supports the following features: ■ Master, slave, and master/slave mode ■ Slow-mode (50 kbps), standard-mode (100 kbps), fastmode (400 kbps), and fast-mode plus (1000 kbps) datarates ■ 7- or 10-bit slave addressing (10-bit addressing requires firmware support) ■ Clock stretching and collision detection ■ Programmable oversampling of I2C clock signal (SCL) ■ Error reduction using an digital median filter on the input path of the I2C data signal (SDA) ■ Glitch-free signal transmission with an analog glitch filter ■ Interrupt or polling CPU interface 15.4.2 General Description Figure 15-21 illustrates communication network. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D an example of an I2C 115 Serial Communications Block (SCB) Figure 15-21. I2C Interface Block Diagram VDD Rp Rp SCL SDA I2C Master I2C Slave The standard I2C bus is a two wire interface with the following lines: ■ Serial Data (SDA) ■ Serial Clock (SCL) I2C devices are connected to these lines using open collector or open-drain output stages, with pull-up resistors (Rp). A simple master/slave relationship exists between devices. Masters and slaves can operate as either transmitter or receiver. Each slave device connected to the bus is software addressable by a unique 7-bit address. PSoC 4 also supports 10-bit address matching for I2C with firmware support. 15.4.3 Terms and Definitions Table 15-13 explains the commonly used terms in an I2C communication network. Table 15-13. Definition of I2C Bus Terminology Term Transmitter Description The device that sends data to the bus Receiver The device that receives data from the bus Master The device that initiates a transfer, generates clock signals, and terminates a transfer Slave The device addressed by a master Multi-master More than one master can attempt to control the bus at the same time without corrupting the message Arbitration Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Synchronization Procedure to synchronize the clock signals of two or more devices 116 I2C Slave I2C Slave 15.4.3.1 Clock Stretching When a slave device is not yet ready to process data, it may drive a ‘0’ on the SCL line to hold it down. Due to the implementation of the I/O signal interface, the SCL line value will be '0', independent of the values that any other master or slave may be driving on the SCL line. This is known as clock stretching and is the only situation in which a slave drives the SCL line. The master device monitors the SCL line and detects it when it cannot generate a positive clock pulse ('1') on the SCL line. It then reacts by delaying the generation of a positive edge on the SCL line, effectively synchronizing with the slave device that is stretching the clock. 15.4.3.2 Bus Arbitration The I2C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes an SDA line value that is not the same as the value it is driving on the SDA line. For example, when master 1 is driving the value '1' on the SDA line and master 2 is driving the value '0' on the SDA line, the actual line value will be '0' due to the implementation of the I/O signal interface. Master 1 detects the inconsistency and loses control of the bus. Master 2 does not detect any inconsistency and keeps control of the bus. 15.4.4 I2C Modes of Operation I2C is a synchronous single master, multi-master, multislave serial interface. Devices operate in either master mode, slave mode, or master/slave mode. In master/slave mode, the device switches from master to slave mode when it is addressed. Only a single master may be active during a data transfer. The active master is responsible for driving the clock on the SCL line. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Table 15-14 illustrates the I2C modes of operation. Table 15-14. I2C Modes Mode Description Slave Slave only operation (default) Master Master only operation Multi-master Supports more than one master on the bus Multi-masterslave Simultaneous slave and multi-master operation Data transfer through the I2C bus follows a specific format. Table 15-15 lists some common bus events that are part of an I2C data transfer. The Write Transfer and Read Transfer sections explain the I2C bus bit format during data transfer. Table 15-15. I2C Bus Events Terminology Bus Event Description START A HIGH to LOW transition on the SDA line while SCL is HIGH STOP A LOW to HIGH transition on the SDA line while SCL is HIGH ACK The receiver pulls the SDA line LOW and it remains LOW during the HIGH period of the clock pulse, after the transmitter transmits each byte. This indicates to the transmitter that the receiver received the byte properly. NACK The receiver does not pull the SDA line LOW and it remains HIGH during the HIGH period of clock pulse after the transmitter transmits each byte. This indicates to the transmitter that the receiver received the byte properly. Repeated START START condition generated by master at the end of a transfer instead of a STOP condition DATA SDA status change while SCL is low (data changing), and no change while SCL is high (data valid) When operating in multi-master mode, the bus should always be checked to see if it is busy; another master may already be communicating with a slave. In this case, the master must wait until the current operation is complete before issuing a START signal (see Table 15-15, Figure 15-22, and Figure 15-23). The master looks for a STOP signal as an indicator that it can start its data transmission. When operating in multi-master-slave mode, if the master loses arbitration during data transmission, the hardware reverts to slave mode and the received byte generates a slave address interrupt, so that the device is ready to respond to any other master on the bus. With all of these modes, there are two types of transfer read and write. In write transfer, the master sends data to slave; in read transfer, the master receives data from slave. Write and read transfer examples are available in Master Mode Transfer Examples on page 124, Slave Mode Transfer Examples on page 126, and Multi-Master Mode Transfer Example on page 128. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 117 Serial Communications Block (SCB) 15.4.4.1 Write Transfer Figure 15-22. Master Write Data Transfer Write data transfer(Master writes the data) SDA MSB LSB SCL START Write ACK Slave address (7 bits) Data(8 bits) ACK STOP LEGEND : SDA: Serial Data Line SCL: Serial Clock Line(always driven by the master) Slave Transmit / Master Receive ■ A typical write transfer begins with the master generating a START condition on the I2C bus. The master then writes a 7bit I2C slave address and a write indicator ('0') after the START condition. The addressed slave transmits an acknowledgement byte by pulling the data line low during the ninth bit time. ■ If the slave address does not match any of the slave devices or if the addressed device does not want to acknowledge the request, it transmits a no acknowledgement (NACK) by not pulling the SDA line low. The absence of an acknowledgement, results in an SDA line value of '1' due to the pull-up resistor implementation. ■ If no acknowledgement is transmitted by the slave, the master may end the write transfer with a STOP event. The master can also generate a repeated START condition for a retry attempt. ■ The master may transmit data to the bus if it receives an acknowledgement. The addressed slave transmits an acknowledgement to confirm the receipt of every byte of data written. Upon receipt of this acknowledgement, the master may transmit another data byte. ■ When the transfer is complete, the master generates a STOP condition. 15.4.4.2 Read Transfer Figure 15-23. Master Read Data Transfer Read data transfer(Master reads the data) SDA MSB LSB SCL START Slave address (7 bits) Read ACK Data(8 bits) ACK STOP LEGEND : SDA: Serial Data Line SCL: Serial Clock Line(always driven by the master) Slave Transmit / Master Receive ■ ■ ■ A typical read transfer begins with the master generating a START condition on the I2C bus. The master then writes a 7-bit I2C slave address and a read indicator ('1') after the START condition. The addressed slave transmits an acknowledgement by pulling the data line low during the ninth bit time. If the slave address does not match with that of the connected slave device or if the addressed device does not want to acknowledge the request, a no acknowledgement (NACK) is transmitted by not pulling the SDA line low. The absence of an acknowledgement, results in an SDA line value of '1' due to the pull-up resistor implementation. If no acknowledgement is transmitted by the slave, the master may end the read transfer with a STOP event. 118 The master can also generate a repeated START condition for a retry attempt. ■ If the slave acknowledges the address, it starts transmitting data after the acknowledgement signal. The master transmits an acknowledgement to confirm the receipt of each data byte sent by the slave. Upon receipt of this acknowledgement, the addressed slave may transmit another data byte. ■ The master can send a NACK signal to the slave to stop the slave from sending data bytes. This completes the read transfer. ■ When the transfer is complete, the master generates a STOP condition. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) 15.4.5 I2C Registers The I2C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed in Table 15-16. Table 15-16. I2C Registers Register Function SCB_CTRL Enables the SCBI2C block and selects the type of serial interface (SPI, UART, I2C). Also used to select internally and externally clocked operation. SCB_I2C_CTRL Selects the mode (master, slave) and sends an ACK or NACK signal based on receiver FIFO status. SCB_I2C_STATUS Indicates bus busy status detection, read/write transfer status of the slave/master. SCB_I2C_M_CMD Enables the master to generate START, STOP, and ACK/NACK signals. SCB_I2C_S_CMD Enables the slave to generate ACK/NACK signals. SCB_I2C_CFG Configures filters, which remove glitches from the SDA and SCL lines. SCB_TX_CTRL Enables the transmitter and specifies the data frame width; also used to specify whether MSB or LSB is the first bit in transmission. SCB_TX_FIFO_CTRL Specifies the trigger level, clearing of the transmitter FIFO and shift registers, and FREEZE operation of the transmitter FIFO. SCB_TX_FIFO_STATUS Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides if the transmitter FIFO holds the valid data. SCB_TX_FIFO_WR Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. SCB_RX_CTRL Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. Also decides whether a median filter is to be used on the input interface lines. SCB_RX_FIFO_CTRL Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver. SCB_RX_FIFO_STATUS Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver. SCB_RX_FIFO_RD Holds the data read from the receiver FIFO. Reading a data frame removes the data frame from the FIFO; behavior is similar to that of a POP operation. This register has a side effect when read by software: a data frame is removed from the FIFO. SCB_RX_FIFO_RD_SILENT Holds the data read from the receiver FIFO. Reading a data frame does not remove the data frame from the FIFO; behavior is similar to that of a PEEK operation. SCB_RX_MATCH Stores slave device address and is also used as slave device address MASK. Note Detailed descriptions of the I2C register bits are available in the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 15.4.6 I2C Interrupts The fixed-function I2C block generates interrupts for the following conditions. ■ ■ I2C Master ❐ I2C master lost arbitration ❐ I2C master received NACK ❐ I2C master received ACK ❐ I2C master sent STOP ❐ I2C bus error (unexpected stop/start condition detected) I2C Slave ❐ I2C slave lost arbitration ❐ I2C slave received NACK ❐ I2C slave received ACK ❐ I2C slave received STOP ■ ■ ❐ I2C slave received START ❐ I2C slave address matched ❐ I2C bus error (unexpected stop/start condition detected) TX ❐ TX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL ❐ TX FIFO is not full ❐ TX FIFO is empty ❐ TX FIFO overflow ❐ TX FIFO underflow RX ❐ RX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL ❐ RX FIFO is full ❐ RX FIFO is not empty PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 119 Serial Communications Block (SCB) ■ ❐ RX FIFO overflow ❐ RX FIFO underflow 15.4.7 Enabling and Initializing the I2C The following section describes the method to configure the I2C blockThe I2C interface must be programmed in the following order. I2C Externally Clocked ❐ Wake up request on address match ❐ I2C STOP detection at the end of each transfer ❐ I2C STOP detection at the end of a write transfer ❐ I2C STOP detection at the end of a read transfer 1. Program protocol specific information using the SCB_I2C_CTRL register according to Table 15-17. This includes selecting master - slave functionality. The I2C interrupt signal is hard-wired to the Cortex-M0 NVIC and cannot be routed to external pins. The interrupt output is the logical OR of the group of all possible interrupt sources. The interrupt is triggered when any of the enabled interrupt conditions are met. Interrupt status registers are used to determine the actual source of the interrupt. For more information on interrupt registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. 2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers, as shown in Table 15-18. a. Specify the data frame width. b. Specify that MSB is the first bit to be transmitted/ received. c. Enable the transmitter and receiver. 3. Program transmitter and receiver FIFO using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers, respectively, as shown in Table 15-19. a. Set the trigger level. b. Clear the transmitter and receiver FIFO and Shift registers. 4. Program the SCB_CTRL register to enable the I2C block and select the I2C mode. These register bits are shown in Table 15-20. For a complete description of the I2C registers, see the PSoC 4100/4200 Family: PSoC 4 Registers TRM. Table 15-17. SCB_I2C_CTRL Register Bits 30 31 Name SLAVE_MODE MASTER_MODE Value 1 1 Description Slave mode Master mode Table 15-18. SCB_TX_CTRL/SCB_RX_CTRL Register Bits Name [3:0] DATA_ WIDTH 8 MSB_FIRST 9 MEDIAN Description 'DATA_WIDTH + 1' is the number of bits in the transmitted or received data frame. For I2C, this is always 7. 1= MSB first (this should always be true for I2C) 0= LSB first This is for SCB_RX_CTRL only. Decides whether a digital three-tap median filter is applied on the input interface lines. This filter should reduce susceptibility to errors, but it requires higher oversampling values. 1=Enabled 31 120 ENABLED 0=Disabled In SCB_TX_CTRL register, this is the transmitter enable bit This bit should be set for all protocols when transmitting. If not enabled, the transmit protocol may not function. In SCB_RX_CTRL register, this is the receiver enable bit. This bit should be set for all protocols when receiving. If not enabled, the receive protocol may not function. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) Table 15-19. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL Bits Name [2:0] TRIGGER_LEVEL 16 CLEAR 17 FREEZE Description Trigger level. When the transmitter FIFO has less entries or the receiver FIFO has more entries than the value of this field, a transmitter or receiver trigger event is generated in the respective case. When '1', the transmitter or receiver FIFO and the shift registers are cleared. When '1', hardware reads/writes to the transmitter or receiver FIFO have no effect. Freeze does not advance the TX or RX FIFO read/write pointer. Table 15-20. SCB_CTRL Registers Bits Name [25:24] MODE 31 ENABLED 15.4.8 Value 00 01 10 11 0 1 Description I2C mode SPI mode UART mode Reserved SCB block disabled SCB block enabled Internal and External Clock Operation in I2C The I2C block supports both internally and externally clocked operation for data-rate generation. Internally clocked operations use a clock signal derived from the PSoC system bus clock. Externally clocked operations use a clock provided by the user. Externally clocked operation allows limited functionality in the Deep-Sleep power mode, in which on-chip clocks are not active. For more information on system clocking, see the Clocking System chapter on page 61. Externally clocked operation is limited to slave functionality.Internally and externally clocked operations are determined by two register fields of the SCB_CTRL register: ■ EC_AM_MODE (Externally Clocked Address Matching Mode): Indicates whether I2C address matching is internally ('0') or externally ('1') clocked. ■ EC_OP_MODE (Externally Clocked Operation Mode): Indicates whether the rest of the protocol operation (besides I2C address match) is internally ('0') or externally ('1') clocked. required behavior in Active, Sleep, and Deep-Sleep system power modes. Improper setting may result in faulty behavior in certain power modes. Table 15-21 describes these settings. EC_OP_MODE should always be set to '0'. However, EC_AM_MODE can be set to '0' or '1'.The combination EC_AM_MODE = 0 and EC_OP_MODE = 1 is invalid and the block will not respond. EC_AM_MODE is '0' and EC_OP_MODE is '0'. This setting only works in Active and Sleep system power modes. All the functionality of the I2C is provided in the internally clocked domain. EC_AM_MODE is '1' and EC_OP_MODE is '0'. This setting works in Active, Sleep, and Deep-Sleep system power modes. I2C address matching is performed by the externally clocked logic in Active, Sleep, and Deep-Sleep system power modes. When the externally clocked logic matches the address, it sets a wakeup interrupt cause bit, which can be used to generate an interrupt to wakeup the CPU. These two register fields determine the functional behavior of I2C. The register fields should be set based on the Table 15-21. I2C Operation I2C Mode System Power Mode EC_OP_MODE = 0 EC_AM_MODE = 0 EC_AM_MODE = 1 Active and Sleep Address match using internal clock. Address match using external clock. Operation using internal clock. Operation using internal clock. Deep-Sleep Not supported Hibernate Stop EC_OP_MODE = 1 EC_AM_MODE = 0 Address match using external clock. Operation using internal clock. EC_AM_MODE = 1 Not supported The SCB is not available in these modes (see the Power Modes chapter on page 75). PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 121 Serial Communications Block (SCB) ■ In Active system power mode, the CPU is active and the wakeup interrupt cause is disabled (associated MASK bit is '0'). The externally clocked logic takes care of the address matching and the internally locked logic takes care of the rest of the I2C transfer. ■ In the Sleep mode, wakeup interrupt cause can be either enabled or disabled based on the application. The remaining operations are similar to the Active mode. ■ In the Deep-Sleep mode, the CPU is shut down and will wake up on I2C activity if the wakeup interrupt cause is enabled. CPU wakeup up takes time and the ongoing I2C transfer is either negatively acknowledged (NACK) or the clock is stretched. In the case of a NACK, the internally clocked logic takes care of the first I2C transfer after it wakes up. For clock stretching, the internally clocked logic takes care of the ongoing/stretched transfer when it wakes up. The register bit S_NOT_READY_ADDR_NACK (bit 14) of the SCB_I2C_CTRL register determines whether the externally clocked logic performs a negative acknowledge ('1') or clock stretch ('0'). 122 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) 15.4.9 Wake up from Sleep The system wakes up from Sleep or Deep-Sleep system power modes when an I2C address match occurs. The fixed-function I2C block performs either of two actions after address match: Address ACK or Address NACK. Address ACK - The I2C slave executes clock stretching and waits until the device wakes up and ACKs the address. Address NACK - The I2C slave NACKs the address immediately. The master must poll the slave again after the device wakeup time is passed. This option is only valid in the slave or multi-master-slave modes. Note The interrupt bit WAKE_UP (bit 0) of the SCB_INTR_I2C_EC register must be enabled for the I2C to wake up the device on slave address match while switching to the Sleep mode. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 123 Serial Communications Block (SCB) 15.4.10 Master Mode Transfer Examples Master mode transmits or receives data. 15.4.10.1 Master Transmit Figure 15-24. Single Master Mode Write Operation Flow Chart Begin TX FIFO Empty? Disable Fixed Function I2C block Yes E No No (stretch) Select Master mode Transmission of one byte data complete? Error E Yes Enable TX FIFO Byte ACK’ed or NACK’ed? NACK STOP/ RESTART ACK Enable SCB I2C block No Data transfer complete? Yes Send START signal RESTART No (stretch) Transmission of one byte slave address complete? Send STOP signal STOP Error E End Yes Address ACK’ed or NACK’ed? ACK Set Fixed Function I2C block to transmit mode 124 NACK STOP/ RESTART E Report and handle error PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) 15.4.10.2 Master Receive Figure 15-25. Single Master Mode Read Operation Flow Chart Begin RX FIFO full? Yes E No Disable Fixed Function I2C block No Receiving one byte data complete? Select Master mode Error E Yes Enable RX FIFO Send ACK No Data transfer complete? Yes Enable Fixed Function I2C block Send NACK STOP Send START signal RESTART No (stretch) Transmission of one byte slave address complete? Send STOP signal Error E End Yes Address ACK’ed or NACK’ed? NACK STOP/ RESTART E ACK Set Fixed Function I2C block to receive mode PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Report and handle error 125 Serial Communications Block (SCB) 15.4.11 Slave Mode Transfer Examples Slave mode transmits or receives data. 15.4.11.1 Slave Transmit Figure 15-26. Slave Mode Write Operation Flow Chart Begin Yes TX FIFO empty? Disable Fixed Function I2C block E No No Select Slave mode Transmitting one byte data complete? Error E Yes Enable TX FIFO Byte ACK’ed or NACK’ed? NACK Begin ACK Enable Fixed Function I2C block No Data transfer complete? START detected Yes No (stretch) Receiving one byte slave address complete? Error E End Wake up Yes Address ACK’ed or NACK’ed? NACK ACK E Set Fixed Function I2C block to transmit mode Report and handle error 126 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) 15.4.11.2 Slave Receive Figure 15-27. Slave Mode Read Operation Flow Chart Begin Disable Fixed Function I2C block RX FIFO full? Select Slave mode Yes E No No (stretch) Receiving one byte data complete? Enable RX FIFO Error E Yes Enable Fixed Function I2C block Send ACK No Data transfer complete? Yes Enable Fixed Function I2C block Send NACK START detected End No (stretch) Receiving one byte slave address complete? Error E Wake up Yes Address ACK’ed or NACK’ed? NACK ACK Set Fixed Function I2C block to receive mode PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D E Report and handle error 127 Serial Communications Block (SCB) 15.4.12 Multi-Master Mode Transfer Example In multi-master mode, data can be transferred with the slave mode enabled or not enabled. 15.4.12.1 Multi-Master - Slave Not Enabled Figure 15-28. Multi-Master, Slave Not Enabled Flow Chart B e g in D is a b le F ixe d F u n c tio n I2C b lo ck S e le ct M a ste r m ode No (stre tc h ) T ra n s m iss io n o f o n e b y te s la ve a d d re ss c o m p le te? E n a b le T X F IF O E E rro r Yes L o st a rb itra tio n? B e g in Yes E n a b le F ixe d F u n c tio n I2C b lo ck No C o n tin u e w ith d a ta tra n sfe r a s in sin g le m a ste r B u s b u sy? Yes End No Send START sig n a l E B u s b u sy? Yes R e p o rt a n d h a n d le e rro r No 128 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Serial Communications Block (SCB) 15.4.12.2 Multi-Master - Slave Enabled Figure 15-29. Multi-Master, Slave Enabled Flow Chart B eg in D isab le F ixed F u nctio n I2C b lock S elect M a ster a nd S lave m od e No (stretch ) T ran sm issio n of o ne b yte sla ve a dd ress co m ple te? En ab le T X F IF O E rror E Yes Bu s bu sy or lost arbitra tio n? Yes E n able F ixed F u nctio n I2C b lock No B u s bu sy? Y es C o ntinu e w ith da ta tra nsfe r as in sing le m aste r C on tin ue w ith a dd ress re co gnition a s a slave No E nd E S en d S T A R T sign al R e po rt a nd ha ndle e rror PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 129 Serial Communications Block (SCB) 130 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 16. Universal Digital Blocks (UDB) This chapter shows the design details of the PSoC® 4 universal digital blocks (UDBs). The UDB architecture implements a balanced approach between configuration granularity and efficiency; UDBs have a combination of programmable logic devices (PLDs), structured logic (datapaths), and a flexible routing scheme. Note: Some PSoC 4 device families do not support UDBs. See the device datasheet for details. 16.1 Features ■ PSoC 4 contains an array of four UDBs ■ For optimal flexibility, each UDB contains several components: ❐ An ALU-based 8-bit datapath (DP) with multiple registers, FIFOs, and an 8-word instruction store ❐ Two PLDs, each with 12 inputs, eight product terms, and four macrocell outputs ❐ Control and status modules ❐ Clock and reset modules ■ Flexible routing through the UDB array ■ Portions of UDBs can be shared or chained to enable larger functions ■ Flexible implementations of multiple digital functions, including timers, counters, PWM (with dead band generator), UART, SPI, and CRC generation/checking ■ Register-based interface to CPU Figure 16-1 shows the components of a single UDB: two PLDs, a datapath, and control, status, clock and reset functions. Figure 16-1. Single UDB Block Diagram PLD Chaining Clock and Reset Control Status and Control PLD 12C4 (8 PTs) PLD 12C4 (8 PTs) Datapath Datapath Chaining Routing Channel PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 131 Universal Digital Blocks (UDB) Figure 16-2 shows how the array of four UDBs interfaces with the rest of the PSoC 4. Figure 16-2. UDBs Array in PSoC 4 System Interconnect (Single Layer AHB) CPUSS (CPU Subsystem) 8 to 32 Dig. CLKs 4 to 8 BUS IF IRQ IF CLK IF Other Digital Signals in Chip DSI Port IFIF Port Port IF DSI UDB UDB UDB UDB High-Speed I/O Matrix UDBIF Routing Channels DSI DSI Programmable Digital Subsystem 16.2 How It Works 16.2.1 The major components of a UDB are: ■ PLDs (2) – These blocks take inputs from the routing channel and form registered or combinational sum-ofproducts logic to implement state machines, control for datapath operations, conditioning inputs, and driving outputs. ■ Datapath – This block contains a dynamically programmable ALU, four registers, two FIFOs, comparators, and condition generation. ■ Control and Status – These modules provide a way for CPU firmware to interact and synchronize with UDB operation. ■ Reset and Clock Control – These modules provide clock selection and enabling, and reset selection, for the other blocks in the UDB. ■ Chaining Signals – The PLDs and datapath have chaining signals that enable neighboring UDBs to be linked, to create higher precision functions. ■ Routing Channel – UDBs are connected to the routing channel through a programmable switch matrix for connections between blocks in one UDB, and to all other UDBs in the array. ■ System Bus Interface – All registers and RAM in each UDB are mapped into the system address space and are accessible by the CPU as 8, 16 and 32-bit accesses. 132 PLDs Each UDB has two “12C4” PLDs. The PLD blocks, shown in Figure 16-3, can be used to implement state machines, perform input or output data conditioning, and to create lookup tables (LUTs). PLDs may also be configured to perform arithmetic functions, sequence the datapath, and generate status. General-purpose RTL can be synthesized and mapped to the PLD blocks. This section presents an overview of the PLD design. A PLD has 12 inputs, which feed across eight product terms (PT) in the AND array. In a given product term, the true (T) or complement (C) of the input can be selected. The outputs of the PTs are inputs into the OR array. The 'C' in 12C4 indicates that the OR terms are constant across all inputs, and each OR input can programmatically access any or all of the PTs. This structure gives maximum flexibility and ensures that all inputs and outputs are permutable. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Figure 16-3. PLD 12C4 Structure PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 IN0 TC TC TC TC TC TC TC TC IN1 TC TC TC TC TC TC TC TC IN2 TC TC TC TC TC TC TC TC IN3 TC TC TC TC TC TC TC TC IN4 TC TC TC TC TC TC TC TC IN5 TC TC TC TC TC TC TC TC IN6 TC TC TC TC TC TC TC TC IN7 TC TC TC TC TC TC TC TC IN8 TC TC TC TC TC TC TC TC IN9 TC TC TC TC TC TC TC TC IN10 TC TC TC TC TC TC TC TC IN11 TC TC TC TC TC TC TC TC AND Array Carry In T T T T T T T T MC0 OUT0 T T T T T T T T MC1 OUT1 T T T T T T T T MC2 OUT2 T T T T T T T T MC3 OUT3 Carry Out OR Array 16.2.1.1 PLD Macrocells Figure 16-4 shows the macrocell architecture. The output drives the routing array and can be registered or combinational. The registered modes are D Flip-Flop (DFF) with true or inverted input and Toggle Flip-Flop (TFF) on input high or low. The output register can be set or reset for purposes of initialization, or asynchronously during operation under control of a routed signal. Figure 16-4. PLD Macrocell Architecture XOR Feedback (XORFB) 00: D FF 01: Arithmetic (Carry) 10: T FF on high 11: T FF on low (from prev MC) XORFB[1:0] SSEL selin cpt1 cpt0 CONST 1 3 2 1 0 1 0 To macrocell read-only register Constant (CONST) 0: D FF true in 1: D FF inverted in 0 Set Select (SSEL) 0: Set not used 1: Set from input 1 set D Q From OR gate clk out 0 QB res pld_en reset 1 COEN Carry Out Enable (COEN) 0:Carry Out disabled 1: Carry Out enabled selout BYP 0 RSEL Output Bypass (BYP) 0: Registered 1: Combinational Reset Select (RSEL) 0: Set not used 1: Set from input (to next MC) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 133 Universal Digital Blocks (UDB) PLD Macrocell Read-Only Registers The outputs of the eight macrocells in the two PLDs can be accessed by the CPU as an 8-bit read-only register. Macrocells across multiple UDBs can be accessed as 16 or 32-bit read-only registers. See UDB Addressing on page 164. 16.2.1.2 PLD Carry Chain PLDs are chained together in UDB address order. As shown in Figure 16-5, the carry chain input “selin” is routed from the previous UDB in the chain through each macrocell in both PLDs, and then to the next UDB as the carry chain out “selout”. To support the efficient mapping of arithmetic functions, special product terms are generated and used in the macrocell in conjunction with the carry chain. Figure 16-5. PLD Carry Chain and Special Product Term Inputs PLD1 {PT7,PT6} {PT5,PT4} {PT3,PT2} {PT1,PT0} {PT7,PT6} {PT5,PT4} {PT3,PT2} {PT1,PT0} selout PLD0 cpt1,cpt0 MC3 cpt1,cpt0 MC2 cpt1,cpt0 MC1 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 cpt1,cpt0 MC0 MC3 MC2 MC1 MC0 selin To the next PLD block in the chain 16.2.1.3 From the previous PLD block in the chain PLD Configuration The PLDs can be configured by accessing a set of 16 or 32-bit registers; see UDB Addressing on page 164. 16.2.2 Datapath The datapath, shown in Figure 16-6, contains an 8-bit single-cycle ALU, with associated compare and condition generation circuits. A datapath may be chained with datapaths in neighboring UDBs to achieve higher precision functions. The datapath includes a small dynamic configuration RAM, which can dynamically select the operation to perform in a given cycle. The datapath is optimized to implement typical embedded functions such as timers, counters, PWMs, PRS, CRC, shifters, and dead band generators. The add and subtract functions allow support for digital delta-sigma operations. Figure 16-6. Datapath Top Level System Bus R/W Access to all registers F1 FIFOs F0 D1 Data Registers D0 To/From Prev Datapath A1 Output Muxes Conditions A0 A1 D0 D1 2 Compares 2 Zero Detect, 2 Ones Detect Overflow Detect Datapath Control 6 Dynamic Configuration RAM 8 Word X 16 bit Input from Programmable Routing Input Muxes Chaining 6 Output to Programmable Routing To/From Next Datapath Accumulators A0 Parallel Input/Output (to/from Programmable Routing) PI SRC A SRC B PO ALU ALU Shift Mask 134 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.2.1 Overview cision arithmetic, shift, and CRC/PRS functions. The following are key datapath features: Time Multiplexing Dynamic Configuration In applications that are oversampled or do not need the highest clock rates, the single ALU block in the datapath can be efficiently shared between two sets of registers and condition generators. ALU and shift outputs are registered and can be used as inputs in subsequent cycles. Usage examples include support for 16-bit functions in one (8-bit) datapath, or interleaving a CRC generation operation with a data shift operation. Dynamic configuration is the ability to change the datapath function and interconnect on a cycle-by-cycle basis, under sequencer control. This is implemented using the configuration RAM, which stores eight unique configurations. The address input to this RAM can be routed from any block connected to the routing fabric, typically PLD logic, I/O pins, or other datapaths. ALU Datapath Inputs The ALU can perform eight general-purpose functions: increment, decrement, add, subtract, AND, OR, XOR, and PASS. Function selection is controlled by the configuration RAM on a cycle-by-cycle basis. Independent shift (left, right, nibble swap) and masking operations are available at the output of the ALU. The datapath has three types of inputs: configuration, control, and serial and parallel data. The configuration inputs select the dynamic configuration RAM address. The control inputs load the data registers from the FIFOs and capture accumulator outputs into the FIFOs. Serial data inputs include shift in and carry in. A parallel data input port allows up to eight bits of data to be brought in from routing. Conditionals Datapath Outputs Each datapath has two comparators with bit masking options, which can be configured to select a variety of datapath register inputs for comparison. Other detectable conditions include all zeros, all ones, and overflow. These conditions form the primary datapath output selects to be routed to the digital routing fabric as inputs to other functions. A total of 16 signals are generated in the datapath. Some of these signals are conditional signals (for example, compares), some are status signals (for example, FIFO status), and the rest are data signals (for example, shift out). These 16 signals are multiplexed into the six datapath outputs and then driven to the routing matrix. By default, the outputs are single synchronized (pipelined). A combinational output option is also available for these outputs. Built-in CRC/PRS The datapath has built-in support for single-cycle cyclic redundancy check (CRC) computation and pseudo random sequence (PRS) generation of arbitrary width and arbitrary polynomial specification. To achieve longer than 8-bit CRC/ PRS widths, signals may be chained between datapaths. This feature is controlled dynamically and therefore, can be interleaved with other functions. Datapath Working Registers Each datapath module has six 8-bit working registers. All registers are readable and writable by CPU. Variable MSB The most significant bit of an arithmetic and shift function can be programmatically specified. This supports variable width CRC/PRS functions and, in conjunction with ALU output masking, can implement arbitrary width timers, counters, and shift blocks. Input/Output FIFOs Each datapath contains two 4-byte FIFOs, which can be individually configured for direction as an input buffer (CPU writes to the FIFO, datapath internals read the FIFO), or an output buffer (datapath internals write to the FIFO, the CPU reads from the FIFO). These FIFOs generate full or empty status signals that can be routed to interact with sequencers or interrupts. Chaining The datapath can be configured to chain conditions and signals with neighboring datapaths. Shift, carry, capture, and other conditional signals can be chained to form higher pre- PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 135 Universal Digital Blocks (UDB) Table 16-1. Datapath Working Registers Type Name Description Accumulator A0, A1 The accumulators may be both a source and a destination for the ALU. They may also be loaded from a Data register or a FIFO. The accumulators typically contain the current value of a function, such as a count, CRC, or shift. These registers are non-retention; they lose their values in sleep and are reset to 0x00 on wakeup. Data D0, D1 The Data registers typically contain constant data for a function, such as a PWM compare value, timer period, or CRC polynomial. These registers retain their values across sleep intervals. F0, F1 The two 4-byte FIFOs provide both a source and a destination for buffered data. The FIFOs can be configured as both input buffers, both output buffers, or as one input buffer and one output buffer. Status signals indicate the full/empty status of these registers. Usage examples include buffered TX and RX data in the SPI or UART and buffered PWM compare and buffered timer period data. These registers are non-retention; they lose their values in sleep and are reset to 0x00 on wakeup. FIFOs 16.2.2.2 Datapath FIFOs FIFO Modes and Configurations Each FIFO has a variety of operation modes and configurations. Table 16-2. FIFO Modes and Configurations Mode Description Input/Output In input mode, the CPU writes to the FIFO and the data is read and consumed by the datapath internals. In output mode, the FIFO is written to by the datapath internals and is read and consumed by the CPU. Single Buffer The FIFO operates as a single-byte buffer with no status. Data written to the FIFO is immediately available for reading, and can be overwritten at anytime. Level/Edge The control to load the FIFO from the datapath internals can be either level or edge triggered. Normal/Fast The control to load the FIFO from the datapath source is sampled on the currently selected datapath clock (normal) or the HFCLK (fast). This allows captures to occur at the highest rate in the system (HFCLK), independent of the datapath clock. Software Capture When this mode is enabled and the FIFO is in output mode, a read by the CPU of the associated accumulator (A0 for F0, A1 for F1) initiates a synchronous transfer of the accumulator value into the FIFO. The captured value may then be immediately read from the FIFO. If chaining is enabled, the operation follows the chain to the MS block for atomic reads by datapaths of multi-byte values. Asynch When the datapath is being clocked asynchronously to the HFCLK, the FIFO status signals can be routed to the rest of the datapath either directly, single sampled to the datapath clock, or double sampled in the case of an asynchronous datapath clock Independent Clock Polarity Each FIFO has a control bit to invert polarity of the FIFO clock with respect to the datapath clock. Figure 16-7 shows the possible FIFO configurations controlled by the input/output modes. The TX/RX mode has one FIFO in input mode and the other in output mode. The primary example of this configuration is SPI. The dual capture configuration provides independent capture of A0 and A1, or two separately controlled captures of either A0 or A1. Finally, the dual buffer mode can provide buffered periods and compares, or two independent periods/compares. 136 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Figure 16-7. FIFO Configurations System Bus System Bus F0 D0/D1 A0/A1/ALU A0/A1/ALU A0/A1/ALU F1 F0 F1 System Bus System Bus TX/RX Dual Capture F0 F1 D0 D1 A0 A1 Dual Buffer Figure 16-8 shows a detailed view of FIFO sources and sinks. UDB Local Data Bus FIFO F0 ALU A1 A0 ALU A1 A0 Figure 16-8. FIFO Sources and Sinks FIFO F1 D0 D1 A0 A1 When the FIFO is in input mode, the source is the system bus and the sinks are the Dx and Ax registers. When in output mode, the sources include the Ax registers and the ALU, and the sink is the system bus. The multiplexer selection is statically set in UDB configuration register CFG15, as shown in Table 16-3 for the F0_INSEL[1:0] or F1_INSEL[1:0]. Table 16-3. FIFO Multiplexer Set in UDB CFG15 Register Fx_INSEL[1:0] Description 00 Input mode - System bus writes the FIFO, FIFO output destination is Ax or Dx. 01 Output A0 Mode - FIFO input source is A0, FIFO output destination is the system bus. 10 Output A1 Mode - FIFO input source is A1, FIFO output destination is the system bus. 11 Output ALU Mode - FIFO input source is the ALU output, FIFO output destination is the system bus. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 137 Universal Digital Blocks (UDB) FIFO Status Each FIFO generates two status signals, “bus” and “block,” which are sent to the UDB routing through the datapath output multiplexer. The “bus” status can be used to assert an interrupt request to read/write the FIFO. The “block” status is primarily intended to provide the FIFO state to the UDB internals. The meanings of the status bits depend on the configured direction (Fx_INSEL[1:0] in the UDB CFG15 register) and the FIFO level bits. The FIFO level bits (Fx_LVL) are set in the Auxiliary Control Working register (ACTL) in working register space. Table 16-4 shows the options. Table 16-4. FIFO Status Options Fx_INSEL[1:0] Input Fx_LVL FIFO Status Signal FIFO Status Description 0 Not Full Bus Status Asserted when there is room for at least 1 byte in the FIFO. Input 1 At Least Half Empty Bus Status Asserted when there is room for at least 2 bytes in the FIFO. Input NA Empty Block Status Asserted when there are no bytes left in the FIFO. When not empty, the datapath internals may consume bytes. When empty the datapath may idle or generate an underrun condition. Output 0 Not Empty Bus Status Asserted when there is at least 1 byte available to be read from the FIFO. Output 1 At Least Half Empty Bus Status Asserted when there are at least 2 bytes available to be read from the FIFO. Output NA Full Block Status Asserted when the FIFO is full. When not full, the datapath internals may write bytes to the FIFO. When full, the datapath may idle or generate an overrun condition. FIFO Operation Figure 16-9 illustrates a typical sequence of reads and writes and the associated status generation. Although the figure shows reads and writes occurring at different times, a read and write can also occur simultaneously. Figure 16-9. Detailed FIFO Operation Sinks Reset Write 2 bytes Write 2 more bytes Empty = 1 Empty = 0 Empty = 0 Empty = 0 At Least Half Empty = 1 At Least Half Empty = 1 At Least Half Empty = 0 At Least Half Empty = 1 Full = 0 Full = 0 Full = 1 Full = 0 At Least Half Full = 0 At Least Half Full = 1 At Least Half Full = 1 At Least Half Full = 0 WR_PTR RD_PTR RD_PTR D0 WR_PTR RD_PTR D1 WR_PTR D0 WR_PTR Write 2 bytes X D2 X Empty = 0 Empty = 0 Empty = 1 At Least Half Empty = 1 At Least Half Empty = 1 Full = 0 Full = 0 Full = 0 At Least Half Full = 1 At Least Half Full = 0 At Least Half Full = 0 D4 X X D5 X 138 X D3 RD_PTR WR_PTR X X RD_PTR D3 Read 1 bytes At Least Half Empty = 0 D5 RD_PTR Read 2 bytes X D1 D3 WR_PTR Read 3 bytes WR_PTR RD_PTR X X PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) FIFO Fast Mode (FIFO FAST) When the FIFO is configured for output, the FIFO load operation normally uses the currently selected datapath clock for sampling the write signal. As shown in Figure 16-10, with the FIFO fast mode set, the HFCLK can be optionally selected for this operation. Used in conjunction with edge sensitive mode, this operation reduces the latency of accumulator-to-FIFO transfer from the resolution of the datapath clock to the resolution of the HFCLK, which can be much higher. This allows the CPU to read the captured result in the FIFO with minimal latency. Figure 16-10 illustrates that the fast load operation is independent of the currently selected datapath clock; however, using the HFCLK may cause higher power consumption. Note that the incoming fx_ld signal must be able to meet HFCLK timing, which can require local resynchronization. Figure 16-10. FIFO Fast Configuration Sinks UDB DP Clock Mux digital clocks DP clk DP Operation HFCLK fx_ld Write FIFO (In Output Mode) 0 HFCLK 1 FIFO Fast FIFO Level/Edge Write Mode FIFO Software Capture Mode Two modes are available for writing the FIFO from the datapath. In the first mode, data is synchronously transferred from the accumulators to the FIFOs. The control for that write (fx_ld) is typically generated from a state machine or condition that is synchronous to the datapath clock. The FIFO is written in any cycle where the input load control is a '1'. A common and important requirement is to allow the CPU the ability to reliably read the contents of an accumulator during normal operation. This is done with software capture and is enabled by setting the FIFO Cap configuration bit (FIFO_CAP bit in the UDB CFG16 register). This bit applies to both FIFOs in a UDB, but is only operational when a FIFO is in output mode. When using software capture, F0 should be set to load from A0 and F1 from A1. In the second mode, the FIFO is used to capture the value of the accumulator in response to a positive edge of the fx_ld signal. In this mode the duty cycle of the waveform is arbitrary (however, it must be at least one datapath clock cycle in width). An example of this mode is capturing the value of the accumulator using an external pin input as a trigger. The limitation of this mode is that the input control must revert to '0' for at least one cycle before another positive edge is detected. Figure 16-11 shows the edge detect option on the fx_ld control input. One bit for this option sets the mode for both FIFOs in a UDB. Note that edge detection is sampled at the rate of the selected FIFO clock. Figure 16-11. Edge Detect Option for Internal FIFO Write 0 fx_ld (from Routing) 1 FF dp_clk 0 HFCLK 1 FIFO Fast FIFO Edge fx_write As shown in Figure 16-12, reading the accumulator triggers a write to the FIFO from that accumulator. This signal is chained so that a read of a given byte simultaneously captures accumulators in all chained UDBs. This allows the CPU to reliably read 16 bits or more simultaneously. The data returned in the read of the accumulator should be ignored; the captured value may be read from the FIFOs immediately. The fx_ld signal, which generates a FIFO load, is ORed with the software capture signal; the results can be unpredictable when both hardware and software capture are used at the same time. As a general rule, these functions should be mutually exclusive; however, hardware and software capture can be used simultaneously with the following settings: ■ FIFO capture clocking mode is set to FIFO FAST ■ FIFO write mode is set to FIFO EDGE With these settings, hardware and software capture work essentially the same and in any given HFCLK cycle, either signal asserted initiates a capture. It is also recommended to clear the target FIFO in firmware (UDB ACTL register) before initiating a software capture. This initializes the FIFO read and write pointers to a known state. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 139 Universal Digital Blocks (UDB) Figure 16-12. Software Capture Configuration Chain X capxi (chaining in) capx (chaining out) read ax FIFO Cap fx_write 0 1 fx_ld FIFO EDGE HFCLK (FIFO FAST) FIFO Control Bits The Auxiliary Control register (ACTL) has four bits that may be used by the CPU firmware to control the FIFO during normal operation. The FIFO0 CLR and FIFO1 CLR bits are used to reset or flush the FIFO. When a '1' is written to one of these bits, the associated FIFO is reset. The bit must be written back to '0' for FIFO operation to continue. If the bit is left asserted, the given FIFO is disabled and operates as a one byte buffer without status. Data can be written to the FIFO; the data is immediately available for reading and can be overwritten at anytime. Data direction using the Fx INSEL[1:0] (UDB CFG15 register) configuration bits is still valid. The FIFO0 LVL and FIFO1 LVL bits control the level at which the 4-byte FIFO asserts bus status (when the bus is either reading or writing to the FIFO) to be asserted. The meaning of FIFO bus status depends on the configured direction, as shown in Table 16-5. Table 16-5. FIFO Level Control Bits in UDB ACTL Register FIFOxLVL 0 1 Input Mode (Bus is Writing FIFO) Output Mode (Bus is Reading FIFO) Not Full Not Empty At least 1 byte can be written At least 1 byte can be read At least Half Empty At least Half Full At least 2 bytes can be written At least 2 bytes can be read FIFO Asynchronous Operation Figure 16-13 illustrates the concept of asynchronous FIFO operation. As an example, assume F0 is set for input mode and F1 is set for output mode, which is a typical configuration for TX and RX registers. On the TX side, the datapath state machine uses "empty" to determine if there are any bytes available to consume. Empty is set synchronously to the DP state machine, but is cleared asynchronously due to a bus write. When cleared, the status is synchronized back to the DP state machine. On the RX side, the datapath state machine uses “full” to determine whether there is a space left to write to the FIFO. Full is set synchronously to the DP state machine, but is cleared asynchronously due to a bus read. When cleared, the status is synchronized back to the DP state machine. A single FIFO ASYNCH bit of the UDB CFG16 register is used to enable this synchronization method; when set it applies to both FIFOs. It is only applied to the block status, as it is assumed that bus status is naturally synchronized by the interrupt process. 140 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Figure 16-13. FIFO Asynchronous Operation System Bus async F0 (TX) blk_stat empty Synch to DP empty Asynchronously cleared by bus write, sycnhyronously set by DP read 0 d set 1 q DP clk Datapath Process (Asynch) async Synch to DP FIFO Overflow Operation Use FIFO status signaling to safely implement both internal (datapath) and external (CPU) reads and writes. There is no built-in protection from underflow and overflow conditions. If the FIFO is full and subsequent writes occur (overflow), the new data overwrites the front of the FIFO (the data currently being output, the next data to read). If the FIFO is empty and subsequent reads occur (underflow), the read value is undefined. FIFO pointers remain accurate regardless of underflow and overflow. d set 1 Full to DP state machine q DP clk Figure 16-14. FIFO Dynamic Mode ALU System Bus 0 A1 F1 (RX) full Asynchronously cleared by bus read, sycnhyronously set by DP write A0 full blk_stat Empty to DP state machine INSEL FIFO Fx UDB Local Data Bus FIFO Fx FIFO Clock Inversion Option Each FIFO has a control bit called Fx CK INV in the UDB CFG16 register that controls the polarity of the FIFO clock, with respect to the polarity of the DP clock. By default, the FIFO operates at the same polarity as the DP clock. When this bit is set, the FIFO operates at the opposite polarity as the DP clock. This provides support for “both clock edge” communication protocols, such as SPI. FIFO Dynamic Control Normally, the FIFOs are configured statically in either input or output mode. As an alternative, each FIFO can be configured into a mode where the direction is controlled dynamically, that is, by routed signals. One configuration bit per FIFO (Fx DYN bit in the UDB CFG17 register) enables the mode. Figure 16-14 shows the configurations available in dynamic FIFO mode. Ax UDB Local Data Bus Internal Access External Access (Fx DYN = 1, dx_load = 0) (Fx DYN = 1, dx_load = 1) In internal access mode, the datapath can read and write the FIFO. In this configuration, the Fx INSEL bits must be configured to select the source for the FIFO writes. Fx INSEL = 00 (CPU bus source) is invalid in this mode; they can only be 01, 10, or 11 (A0, A1, or ALU). Note that the only read access is to the associated accumulator; the data register destination is not available in this mode. In external access mode, the CPU can both read and write the FIFO. The configuration between internal and external access is dynamically switchable using datapath routing signals. The datapath input signals d0_load and d1_load are used for this control. Note that in the dynamic control mode, d0_load and d1_load are not available for their normal use in loading the D0/D1 registers from F0/F1. The dx_load signals can be driven by any routed signal, including constants. In one usage example, starting with external access (dx_load == 1), the CPU can write one or more bytes of data to the FIFO. Then toggling to internal access (dx_load == 0), the datapath can perform operations on the data. Then toggling back to external access, the CPU can read the result of the computation. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 141 Universal Digital Blocks (UDB) Because the Fx INSEL must always be set to 01, 10, or 11 (A0, A1, or ALU), which is “output mode” in normal operation, the FIFO status signals have the following definitions (also dependent on Fx LVL control). Carry In The carry in is used in arithmetic operations. Table 16-8 shows the default carry in value for certain functions. Table 16-6. FIFO Status Status Signal Meaning Fx LVL = 0 Fx LVL = 1 Table 16-8. Carry In Functions fx_blk_stat Write Status FIFO full FIFO full Function fx_bus_stat Read Status FIFO not empty At least half full INC ++srca srca + 00h + ci, where ci is forced to 1 DEC --srca srca + ffh + ci, where ci is forced to 0 Because the datapath and CPU may both write and read the FIFO, these signals are no longer considered “block” and “bus” status. The blk_stat signal is used for write status and the bus_stat signal is used for read status. 16.2.2.3 FIFO Status There are four FIFO status signals, two for each FIFO: fifo0_bus_stat, fifo0_blk_stat, fifo1_bus_stat, and fifo1_blk_stat. The meaning of these signals depends on the direction of the given FIFO, which is determined by static configuration. 16.2.2.4 The ALU core consists of three independent 8-bit programmable functions, which include an arithmetic/logic unit, a shifter unit, and a mask unit. See the UDB datapath architecture block diagram (Figure 16-6) for more details. Arithmetic and Logic Operation srca + srcb srca + srcb + ci, where ci is forced to 0 SUB srca – srcb Table 16-9. Additional Carry In Functions in UDB CFG13 Carry Mode Function srca 001 INC ++srca 010 DEC --srca 011 ADD srca +srcb 100 SUB srca – srcb 101 XOR srca ^ srcb 110 AND srca and srcb 111 OR srca | srcb srca = ‘A’ input source to the ALU, srcb = ‘B’ input source to the ALU. See Figure 16-6. 142 Default arithmetic mode as described in Table 16-8. Default 01 Carry Flag, result of the carry from the previous cycle. This mode is used to implement add with carry and subtract with Registered borrow operations. It can be used in successive cycles to emulate a double precision operation. 10 Routed Carry is generated elsewhere and routed to this input. This mode can be used to implement controllable counters. 11 Chained Carry is chained from the previous datapath. This mode can be used to implement single cycle operations of higher precision involving two or more datapaths. Operation PASS Description 00 Table 16-7. ALU Functions in UDB DCFG Register Func[2:0] srca + ~srcb + ci, where ci is forced to 1 In addition to this default arithmetic mode for carry operation, there are three additional carry options. The CI SELA and CI SELB configuration bits in the CFG13 register determine the carry in for a given cycle. Dynamic configuration RAM selects either the A or B configuration on a cycle-bycycle basis. The options are defined in Table 16-9. The ALU functions, which are configured dynamically by the configuration RAM, are shown in Table 16-7. 000 Default Carry In Implementation ADD CI SEL A CI SEL B Datapath ALU Operation When a routed carry is used, the meaning with respect to each arithmetic function is shown in Table 16-10. Note that in the case of the decrement and subtract functions, the carry is active low (inverted). Table 16-10. Routed Carry In Functions Function Carry In Polarity Carry In Active Carry In Inactive INC True ++srca srca DEC Inverted --srca srca ADD True (srca + srcb) + 1 srca + srcb SUB Inverted (srca – srcb) – 1 (srca – srcb) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Carry Out The carry out is a selectable datapath output and is derived from the currently defined MSB position, which is statically programmable. This value is also chained to the next most significant block as an optional carry in. Note that in the case of decrement and subtract functions, the carry out is inverted. Table 16-11. Carry Out Functions Function Carry Out Polarity INC True Carry Out Active ++srca == 0 Carry Out Inactive srca DEC Inverted --srca == –1 srca ADD True srca + srcb > 255 srca + srcb SUB Inverted srca – srcb < 0 (srca – srcb) Carry Structure Figure 16-15 shows the options for carry in, and for MSB selection for carry out generation. The registered carry out value may be selected as the carry in for a subsequent arithmetic operation. This feature can be used to implement higher precision functions in multiple cycles. Figure 16-15. Carry Operation Selected MSB Arithmetic ALU Function (inc, dec, add, sub) Default function value ALU Bit 7 ALU Bit 6 ALU Bit 5 ALU Bit 4 ALU Bit 3 ALU Bit 2 ALU Bit 1 ALU Bit 0 ci Chained (from prev datapath) Registered (from co_msb_reg) Routed (from interconnect) co_msb (to DP output mux) co_msb_reg Shift Operation The shift operation occurs independent of the ALU operation, according to Table 16-12. Table 16-12. Shift Operation Functions in UDB DCFG Register Shift[1:0] Function 00 Pass 01 Shift Left 10 Shift Right 11 Nibble Swap A shift out value is available as a datapath output. Both shift out right (sor) and shift out left (sol_msb) share that output selection. A static configuration bit (SHIFT SEL in the UDB CFG15 register) determines which shift output is used as a datapath output. When no shift is occurring, the sor and sol_msb signal is defined as the LSB or MSB of the ALU function, respectively. The SI SELA and SI SELB configuration bits determine the shift in data for a given operation. Dynamic configuration RAM selects the A or B configuration on a cycle-by-cycle basis. Shift in data is only valid for left and right shift; it is not used for pass and nibble swap. Table 16-13 shows the selections and usage that apply to both left and right shift directions. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 143 Universal Digital Blocks (UDB) Table 16-13. Shift In Functions in UDB CFG15 Register SI SEL A/ SI SEL B Shift In Source Description 00 Default/Arithmetic The default input is the value of the DEF SI configuration bit (fixed 1 or 0). However, if the MSB SI bit is set, then the default input is the currently defined MSB (for right shift only). 01 Registered The shift in value is driven by the current registered shift out value (from the previous cycle). The shift left operation uses the last shift out left value. The shift right operation uses the last shift out right value. 10 Routed Shift in is selected from the routing channel (the SI input). 11 Chained Shift in left is routed from the right datapath neighbor and shift in right is routed from the left datapath neighbor. The shift out left data comes from the currently defined MSB position (MSB_EN and MSB_SEL bits in the CFG14 register), and the data that is shifted in from the left (in a shift right operation) goes into the currently defined MSB position. Both shift out data (left or right) are registered and can be used in a subsequent cycle. This feature can be used to implement a higher precision shift in multiple cycles. Figure 16-16. Shift Operation Select default value or arithmetic shift Default (tie value) sor_reg shift in left (sil) Registered (sor_reg) Selected MSB Routed (from interconnect) Chained (from next Datapath) sil 7 6 shift out right (sor) (to DP output mux) Shift right or shift left 5 4 3 2 1 0 Default (tie value) shift out left (sol_msb) (to DP output mux) sol_msb_reg Registered (from sol_msb_reg) shift in right (sir) Routed (from interconnect) Chained (from prev Datapath) Note that the bits that are isolated by the MSB selection are still shifted. In the example shown, bit 7 still shifts in the sil value on a right shift and bit 5 shifts in bit 4 on a left shift. The shift out either right or left from the isolated bits is lost. ALU Masking Operation An 8-bit mask register (AMASK) in the UDB static configuration register space (CFG9) defines the masking operation. In this operation, the output of the ALU is masked (ANDed) with the value in the mask register. A typical use for the ALU mask function is to implement free-running timers and counters in power of two resolutions. 144 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.2.5 Datapath Inputs and Multiplexing The datapath has a total of nine inputs, as shown in Table 16-14, including six inputs from the channel routing. These consist of the configuration RAM address, FIFO and data register load control signals, and the data inputs shift in and carry in. Table 16-14. Datapath Inputs Input RAD2 RAD1 RAD0 F0 LD F1 LD D0 LD Description Asynchronous dynamic configuration RAM address. There are eight 16-bit words, which are user-programmable. Each word contains the datapath control bits for the current cycle. Sequences of instructions can be controlled by these address inputs. When asserted in a given cycle, the selected FIFO is loaded with data from one of the A0 or A1 accumulators or from the output of the ALU. The source is selected by the Fx INSEL[1:0] configuration bits. This input is edge sensitive. It is sampled at the datapath clock; when a '0' to '1' transition is detected, a load occurs at the subsequent clock edge. D1 LD When asserted in a given cycle, the Dx register is loaded from associated FIFO Fx. This input is edge sensitive. It is sampled at the datapath clock; when a '0' to '1' transition is detected, a load occurs at the subsequent clock edge. SI This is a data input value that can be used for either shift in left or shift in right. CI This is the carry in value used when the carry in select control is set to "routed carry." As shown in Figure 16-17, each input has a 6-to-1 multiplexer, therefore, all inputs are permutable. Inputs are handled in one of two ways, either level sensitive or edge sensitive. RAM address, shift in and data in values are level sensitive; FIFO and data register load signals are edge sensitive. Figure 16-17. Datapath Input Selection rad0 (similar for rad1, rad2, si, ci) {0, dp_in[5:0], 0} CFGx RAD0 MUX[2:0] These inputs are edge sensitive f0_ld (similar for f1_ld, d0_ld, d1_ld) {0, dp_in[5:0], 0} CFGx F0 LD MUX[2:0] 16.2.2.6 CRC/PRS Support The datapath can support cyclic redundancy checking (CRC) and pseudo random sequence (PRS) generation. Chaining signals are routed between datapath blocks to support CRC/PRS bit lengths of longer than eight bits. The most significant bit (MSB) of the most significant block in the CRC/PRS computation is selected and routed (and chained across blocks) to the least significant block. The MSB is then XORed with the data input (SI data) to provide the feedback (FB) signal. The FB signal is then routed (and chained across blocks) to the most significant block. This feedback value is used in all blocks to gate the XOR of the polynomial (from the Data0 or Data1 register) with the current accumulator value. to zero, the feedback signal is driven to '1', which allows for normal arithmetic operation. Dynamic control of this bit on a cycle-by-cycle basis gives the capability to interleave a CRC/PRS operation with other arithmetic operations. Figure 16-18. CRC Functional Structure D0/D1 (POLY) A0/A1 (CRC) MSB (most significant bit) Figure 16-18 shows the structural configuration for the CRC operation. The PRS configuration is identical except that the shift in (SI) is tied to '0'. In the PRS configuration, D0 or D1 contain the polynomial value, while A0 or A1 contain the initial (seed) value and the CRC residual value at the end of the computation. FB (feedback) srcb srca ALU (XOR) SI (shift in) Tie input to zero for PRS operation SHIFTER (LEFT) To enable CRC operation, the CFB_EN bit in the dynamic configuration RAM must be set to '1'. This enables the AND of SRCB ALU input with the CRC feedback signal. When set PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 145 Universal Digital Blocks (UDB) CRC/PRS Chaining Figure 16-19 illustrates an example of CRC/PRS chaining across three UDBs. This scenario can support a 17- to 24-bit operation. The chaining control bits are set according to the position of the datapath in the chain as shown in the figure. Figure 16-19. CRC/PRS Chaining Configuration Set msb_sel CHAIN MSB = 1 CHAIN FB = 1 CHAIN FB = 1 cmsbi cmsbo cmsbi CHAIN MSB = 1 cmsbo UDB 2 cmsbi UDB 0 UDB 1 cfbo cfbi cmsbo sir cfbo cfbi cfbo CRC data in cfbi The CRC/PRS feedback signal (cfbo, cfbi) is chained as follows: ■ If a given block is the least significant block, then the feedback signal is generated in that block from the built-in logic that takes the shift in from the right (sir) and XORs it with the MSB signal. (For PRS, the "sir" signal is tied to '0'.) ■ If a given block is not the least significant block, the CHAIN FB configuration bit must be set and the feedback is chained from the previous block in the chain. The CRC/PRS MSB signal (cmsbo, cmsbi) is chained as follows: ■ If a given block is the most significant block, the MSB bit (according to the polynomial selected) is configured using the MSB_SEL configuration bits in the UDB CFG14 register. ■ If a given block is not the most significant block, the CHAIN CMSB configuration bit in the UDB CFG14 register must be set and the MSB signal is chained from the next block in the chain. CRC/PRS Polynomial Specification As an example of how to configure the polynomial for programming into the associated D0/D1 register, consider the CCITT CRC-16 polynomial, which is defined as x16 + x12 +x5 + 1. The method for deriving the data format from the polynomial is shown in Figure 16-20. The X0 term is inherently always '1' and therefore does not need to be programmed. For each of the remaining terms in the polynomial, a '1' is set in the appropriate position in the alignment shown. Note This polynomial format is slightly different from the format normally specified in Hex. For example, the CCITT CRC16 polynomial is typically denoted as 1021H. To convert to the format required for datapath operation, shift right by one and add a '1' in the MSB bit. In this case, the correct polynomial value to load into the D0 or D1 register is 8810H. Figure 16-20. CCITT CRC16 Polynomial Format X16 X15 X16 1 X14 X13 0 X11 X10 X9 X12 + 0 X12 0 1 X8 X7 X6 0 0 X4 X3 X5 + 0 X5 0 0 0 1 X2 X1 + 0 0 X0 1 0 0 CCITT 16-Bit Polynomial is 0x8810 146 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Example CRC/PRS Configuration The following is a summary of CRC/PRS configuration requirements, assuming that D0 is the polynomial and the CRC/PRS is computed in A0: 1. Select a suitable polynomial and write it into D0. 2. Select a suitable seed value (for example, all zeros for CRC, all ones for PRS) and write it into A0. 3. Configure chaining if necessary. 4. Select the MSB position as defined in the polynomial from the MSB_SEL static configuration register bits and set the MSB_EN register bit in the UDB CFG14 register. 5. Configure the dynamic configuration RAM word fields: a. Select D0 as the ALU "SRCB" (ALU B Input Source) b. Select A0 as the ALU "SRCA" (ALU A Input Source) c. Select "XOR" for the ALU function d. Select "SHIFT LEFT" for the SHIFT function e. Select "CFB_EN" to enable the support for CRC/PRS f. Select ALU as the A0 write source If a CRC operation, configure "shift in right" for input data from routing and supply input on each clock. If a PRS operation, tie "shift in right" to '0'. Clocking the UDB with this configuration generates the required CRC or outputs the MSB, which may be output to the routing for the PRS sequence. External CRC/PRS Mode A static configuration bit may be set (EXT CRCPRS in the UDB CFG16 register) to enable support for external computation of a CRC or PRS. As shown in Figure 16-21, computation of the CRC feedback is done in a PLD block. When the bit is set, the CRC feedback signal is driven directly from the CI (Carry In) datapath input selection mux, bypassing the internal computation. The figure shows a simple configuration that supports up to an 8-bit CRC or PRS. Normally the built-in circuitry is used, but this feature gives the capability for more elaborate configurations, such as up to a 16-bit CRC/PRS function in one UDB using time division multiplexing. In this mode, the dynamic configuration RAM bit CFB_EN in the UDB DCFG0 register still controls whether the CRC feedback signal is ANDed with the SRCB ALU input. Therefore, as with the built-in CRC/PRS operation, the function can be interleaved with other functions if required. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 147 Universal Digital Blocks (UDB) Figure 16-21. External CRC/PRS Mode PLD Tie shift in to zero for PRS operation SI (shift in) Routing Routing D0/D1 (POLY) When the EXT_CRCPRS bit is set, the CI selection drives the CRC feedback line. A0/A1 (CRC) FB (feedback) srcb srca CI Mux ALU (XOR) SHIFTER (LEFT) 16.2.2.7 DP Inputs MSB (Most Significant Bit) SI Mux Datapath Outputs and Multiplexing Conditions are generated from the registered accumulator values, ALU outputs, and FIFO status. These conditions can be driven to the digital routing for use in other UDB blocks, for use as interrupts, or to I/O pins. The 16 possible conditions are shown in Table 16-15. Table 16-15. Datapath Condition Generation Name Condition Chain Description ce0 Compare Equal Y A0 == D0 cl0 Compare Less Than Y A0 < D0 z0 Zero Detect Y A0 == 00h ff0 Ones Detect Y A0 == FFh ce1 Compare Equal Y A1 or A0 == D1 or A0 (dynamic selection) cl1 Compare Less Than Y A1 or A0 < D1 or A0 (dynamic selection) z1 Zero Detect Y A1 == 00h ff1 Ones Detect Y A1 == FFh ov_msb Overflow N Carry(msb) ^ Carry(msb–1) co_msb Carry Out Y Carry out of MSB defined bit cmsb CRC MSB Y MSB of CRC/PRS function So Shift Out Y Selection of shift output f0_blk_stat FIFO0 Block Status N Definition depends on FIFO configuration f1_blk_stat FIFO1 Block Status N Definition depends on FIFO configuration f0_bus_stat FIFO0 Bus Status N Definition depends on FIFO configuration f1_bus_stat FIFO1 Bus Status N Definition depends on FIFO configuration There are a total of six datapath outputs. As shown in Figure 16-22, each output has a 16-1 multiplexer that allows any of these 16 signals to be routed to any of the datapath outputs. 148 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Figure 16-22. Output Mux Connections Figure 16-23. Compare Equal Chaining CFG14 CCHAIN0 3 5 6 7 ov_msb 8 z1 ff1 co_msb 14 13 12 11 10 9 cl1 cmsb f0_blk_stat f1_blk_stat f0_bus_stat f1_bus_stat ce0i (from chaining) Compare Equal 6 dp_out[5:0] 15 sol_ msb ce1 Output Mux (6 - 16 to 1) sor ff0 4 z0 ce0 (to routing and chaining) 1 cl0 2 ce0 0 Output Mux Figure 16-24 illustrates compare less than chaining. In this case, the “less than” is formed by the compare less than output in this block, which is unconditional. This is ORed with the condition where this block is equal, and the chained input from the previous block is asserted as less than. Figure 16-24. Compare Less Than Chaining CFG14 CCHAIN0 cl0i (from chaining) cl0 (to routing and chaining) Compare Less Than Compares There are two compares, one of which has fixed sources (Compare 0) and the other has dynamically selectable sources (Compare 1). Each compare has an 8-bit statically programmed mask register, which enables the compare to occur in a specified bit field. By default, the masking is off (all bits are compared) and must be enabled. Comparator 1 inputs are dynamically configurable. As shown in Table 16-16, there are four options for Comparator 1, which applies to both the "less than" and the "equal" conditions. The CMP SELA and CMP SELB configuration bits in the UDB CFG12 register determine the possible compare configurations. A dynamic configuration RAM bit CMP SEL in the UDB DCFG0 register selects one of the A or B configurations on a cycle-by-cycle basis. Table 16-16. Compare Configuration CMP SEL A CMP SEL B Comparator 1 Compare Configuration 00 A1 Compare to D1 01 A1 Compare to A0 10 A0 Compare to D1 11 A0 Compare to A0 Compare 0 and Compare 1 are independently chainable to the conditions generated in the previous datapath (in addressing order). The decision to chain compares is statically specified by CHAIN0 and CHAIN1 bits of the UDB CFG14 registers. Figure 16-23 illustrates compare equal chaining, which is just an ANDing of the compare equal in this block with the chained input from the previous block. Compare Equal All Zeros and All Ones Detect Each accumulator has dedicated all zeros detect and all ones detect. These conditions are statically chainable as specified in the UDB configuration registers. The decision to chain these conditions is statically specified in the UDB configuration registers. Chaining of zero detect is the same concept as the compare equal. Successive chained data is ANDed if the chaining is enabled. Overflow Overflow is defined as the XOR of the carry into the MSB and the carry out of the MSB. The computation is done on the currently defined MSB as specified by the MSB_SEL bits. This condition is not chainable, however the computation is valid when done in the most significant datapath of a multi-precision function as long as the carry is chained between blocks. 16.2.2.8 Datapath Parallel Inputs and Outputs As shown in Figure 16-25, the datapath Parallel In (PI) and Parallel Out (PO) signals give limited capability to bring routed data directly into and out of the Datapath. Parallel Out signals are always available for routing as the ALU asrc selection between A0 and A1. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 149 Universal Digital Blocks (UDB) PI multiplexer may then be controlled by the CFB_EN (UDB DCFG0 register) dynamic control bit. The primary function of CFB_EN is to enable PRS/CRC functionality. Figure 16-25. Datapath Parallel In/Out PI[7:0] A0[7:0] A1[7:0] 16.2.2.9 CFB_EN 1 PI DYN (static config bit in CFG15 register) 0 ASRC[7:0] PI SEL (static config bit in CFG15 register) Alu PO[7:0] Parallel In needs to be selected for input to the ALU. The two options available are static operation or dynamic operation. For static operation, the PI SEL bit of the UDB CFG15 register forces the ALU asrc to be PI. The PI DYN bit of the UDB CFG15 register is used to enable the PI dynamic operation. When it is enabled, and assuming the PI SEL is 0, the Datapath Chaining Each datapath block contains an 8-bit ALU, which is designed to chain carries, shifted data, capture triggers, and conditional signals to the nearest neighbor datapaths, to create higher precision arithmetic functions and shifters. These chaining signals, which are dedicated signals, allow singlecycle 16-, 24- and 32-bit functions to be efficiently implemented without the timing uncertainty of channel routing resources. In addition, the capture chaining supports the ability to perform an atomic read of the accumulators in chained blocks. As shown in Figure 16-26, all generated conditional and capture signals chain in the direction of least significant to most significant blocks. Shift left also chains from least to most significant. Shift right chains from most to least significant. The CRC/PRS chaining signal for feedback chains least to most significant; the MSB output chains from most to least significant. Figure 16-26. Datapath Chaining Flow CE0 CL0 CE1 CL1 CE0i CL0i CE1i CL1i Z0 Z0 Z0i Z1 Z1i Z1 Z1i FF0i FF0 FF0i CAP1 150 CE0i CL0i CE1i CL1i FF0 FF1 CAP0 0 0 Z0i CE0 CL0 CE1 CL1 UDB2 FF1i CAP0i CAP1i FF1 CAP0 CAP1 UDB1 FF1i CAP0i CAP1i CE0 CL0 CE1 CL1 CE0i CL0i CE1i CL1i Z0 Z0i Z1 Z1i FF0 FF1 CAP0 CAP1 UDB0 0 0 0 0 0 FF0i 0 0 FF1i CAP0i 0 0 CAP1i 0 CO_MSB CI CO_MSB CI CO_MSB CI SOL_MSB SIR SOL_MSB SIR SOL_MSB SIR 0 0 0 CFBO CFBI CFBO CFBI CFBO CFBI SIL SOR SIL SOR SIL SOR CMSBI CMSBO CMSBI CMSBO CMSBI CMSBO PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.2.10 Dynamic Configuration RAM Each datapath contains a 16 bit-by-8 word dynamic configuration RAM, which is shown in Figure 16-27. The purpose of this RAM is to control the datapath configuration bits on a cycle-by-cycle basis, based on the clock selected for that datapath. This RAM has synchronous read and write ports for purposes of loading the configuration via the system bus. An additional asynchronous read port is provided as a fast path to output these 16-bit words as control bits to the datapath. The asynchronous address inputs are selected from datapath inputs and can be generated from any of the possible signals on the channel routing, including I/O pins, PLD outputs, control block outputs, or other datapath outputs. The primary purpose of the asynchronous read path is to provide a fast single-cycle decode of datapath control bits. Figure 16-27. Configuration RAM I/O Read Only bus_data[15:0] wrl UDBLocal Bus R/W Read 16 bus_addr [2:0] Wr Ctrl RO Read Address 16 Bit-by-8 Word RAM Array Read/Write Decoder rad[2:0] Address Decoder 16 Datapath Control Inputs wrh 16 Config RAM dyn_cfg_ram [15:0] rd dpram The fields of this dynamic configuration RAM word are shown here. A description of the usage of each field follows. Register Address CFGRAM 61h - 6Fh (odd) Register Address CFGRAM 60h - 6Eh (even) 15 14 13 12 FUNC[2:0] 7 6 11 SRCA 5 A0 WR SRC[1:0] 9 SRCB[1:0] 4 A1 WR SRC[1:0] 10 8 SHIFT[1:0] 3 2 1 0 CFB EN CI SEL SI SEL CMP SEL Table 16-17. Dynamic Configuration Quick Reference Table 16-17. Dynamic Configuration Quick Reference Field Bits Parameter Field Values 000 PASS A0 WR 001 INC SRCA SRC[1:0] Bits 2 Parameter A0 Write Source 010 DEC SRCA FUNC[2:0] 3 ALU Function SRCB 1 2 ALU A Input Source ALU B Input Source 100 SUB A1 WR 101 XOR SRC[1:0] 2 A1 Write Source 111 OR 0 A0 CFB EN 1 CRC Feedback Enable 1 A1 00 D0 CI SEL 1 Carry In Configuration Select SI SEL 1 Shift In Configuration Select CMP SEL 1 Compare Configuration Select 01 D1 10 A0 11 A1 00 PASS SHIFT[1:0] 2 SHIFT Function 01 Left Shift 10 Right Shift 01 ALU 10 D0 11 F0 00 None 011 ADD 110 AND SRCA Values 00 None 01 ALU 10 D1 11 F1 0 Enable 1 Disable 0 ConfigA 1 ConfigBa 0 ConfigA 1 ConfigBa 0 ConfigA 1 ConfigBa a. For CI, SI, and CMP, the RAM fields select between two predefined static settings. See Static Register Configuration. 11 Nibble Swap PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 151 Universal Digital Blocks (UDB) 16.2.3 Status and Control Module Figure 16-28 shows a high-level view of the Status and Control module. The Control register drives into the routing to provide firmware control inputs to UDB operation. The Status register read from routing provides firmware a method of monitoring the state of UDB operation. Figure 16-29 shows a more detailed view of the Status and Control module. The primary purpose of this block is to coordinate CPU firmware interaction with internal UDB operation. However, due to its rich connectivity to the routing matrix, this block may be configured to perform other functions. Figure 16-28. Status and Control Registers System Bus 8-Bit Status Register (Read Only) 8-Bit Control Register (Write/Read) Routing Channel Figure 16-29. Status and Control Module Status and Control Module 7-Bit Period Register (same as Mask) 8-Bit Control Register From Datapath Parallel Output (po[7:0]) TC 8 Interrupt Gen EN/LD CTL 7-Bit Down Count CNT 7 8 8-Bit Status Register INT 8 sc_in[3:0] 7-Bit Mask Register (same as Period) 8 8 To Datapath Parallel Input (pi[7:0]) 4 4-Bit Sync 8 CFGx SC OUT CTL[1:0] 3 CFGx INT MD CFGx SYNC MD 8 sc_out[7:0] sc_io_out[3] 8 sc_io_out[2:0] {sc_io_in[3:0],sc_in[3:0]} Horizontal Channel Routing Modes of operation include: ■ Status Input – The state of routing signals can be input and captured as status and read by the CPU. ■ Control Output – The CPU can write to the control register to drive the state of the routing. ■ Parallel Input – To datapath parallel input. ■ Parallel Output – From datapath parallel output. ■ Counter Mode – In this mode, the control register operates as a 7-bit down counter with programmable period and automatic reload. Routing inputs can be configured to control both the enable and reload of the counter. When this mode is enabled, control register operation is not available. ■ Sync Mode – In this mode, the status register operates as a 4-bit double synchronizer. When this mode is enabled, status register operation is not available. 152 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.3.1 Status and Control Mode When operating in status and control mode, this module functions as a status register, interrupt mask register, and control register in the configuration shown in Figure 16-30. Figure 16-30. Status and Control Operation 00: Read Transparently 01: Sticky, Clear on Read CFGx STAT MD[7:0] System Bus Read Write Reset (Routed Reset Read Only 8-Bit Control Register Read Write 8-Bit Status Register 7 7 7-Bit Mask Register from Reset and Clock Control Block 7 ACTL INT EN CFGx SC OUT CTL[1:0] INT SC OUT CTL bits must be set to select Control register bits for output 8 sc_out[7:0] CFGx INT MD 8 {sc_io_in[3:0],sc_in[3:0] sc_io_out[3] Status Register Operation Sticky Status, with Clear on Read One 8-bit, read-only status register is available for each UDB. Inputs to this register come from any signal in the digital routing fabric. The status register is nonretention; it loses its state across sleep intervals and is reset to 0x00 on wakeup. Each bit can be independently programmed to operate in one of two ways, as shown in Table 16-18. In this mode, the status register inputs are sampled on each cycle of the status and control clock. If the signal is high in a given sample, it is captured in the status bit and remains high, regardless of the subsequent state of the input. When the CPU reads the status register the bit is cleared. The status register clearing is independent of mode and occurs even if the UDB clock is disabled; it is based on the HFCLK and occurs as part of the read operation. Table 16-18. Status Register Mode Selection in UDB CFG20 Register STAT MD Description 0 Transparent read. A read returns the current value of the routed signal 1 Sticky, clear on read. A high on the input is sampled and captured. It is cleared when the register is read. Status Latching During Read Figure 16-31 shows the structure of the status read logic. The sticky status register is followed by a latch, which latches the status register data and holds it stable during the duration of the read cycle, regardless of the number of wait states in a given read. An important feature of the status register clearing operation is to note that the clear of status is only applied to the bits that are set. This allows other bits that are not set to continue to capture status, so that a coherent view of the process can be maintained. Transparent Status Read By default, a CPU read of this register transparently reads the state of the associated routing. This mode can be used for a transient state that is computed and registered internally in the UDB. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 153 Universal Digital Blocks (UDB) Figure 16-31. Status Read Logic Sticky/!Transparent Read Latch 0 D D from Routing AR Status and Control Clock UDB Local Bus Q EN 1 Q Sticky Status Register Status Register Read End of Status Register Read Interrupt Generation Control Register Direct Mode In most functions, interrupt generation is tied to the setting of status bits. As shown in Figure 16-31, this feature is built into the status register logic as the masking and OR reduction of status. Only the lower seven bits of status input can be used with the built-in interrupt generation circuitry. The most significant bit is typically used as the interrupt output and may be routed to the interrupt controller through the digital routing. In this configuration, the MSB of the status register is read as the state of the interrupt bit. The default mode is Direct mode. As shown in Figure 16-32, when the Control Register is written by the CPU the output of the control register is driven directly to the routing on that write cycle. 16.2.3.2 Figure 16-32. Control Register Direct Mode Control Register Operation One 8-bit control register is available for each UDB. This operates as a standard read/write register on the system bus, where the output of these register bits are selectable as drivers into the digital routing fabric. The Control register is nonretention; it loses its contents across sleep intervals and is reset to 0x00 on wakeup. Control Register Operating Modes Three modes are available that may be configured on a bitby-bit basis. The configuration is controlled by the concatenation of the bits of the two 8-bit registers CTL_MD1[7:0] and CTL_MD0[7:0] of the UDB CFG18 and CFG19 registers. For example, {CTL_MD1[0],CTL_MD0[0]} controls the mode for Control Register bit 0, as shown in Table 16-19. Table 16-19. Mode for Control Register Bit 0 in the UDB CFG18 and CFG19 Registers CTL MD Description 00 Direct mode 01 Sync mode 10 Double sync mode 11 Pulse mode To Routing Data Bus HFCLK Control Register Sync Mode In Sync mode, as shown in Figure 16-33, the control register output is driven by a re-sampling register clocked by the currently selected Status and Control (SC) clock. This allows the timing of the output to be controlled by the selected SC clock, rather than the HFCLK. Figure 16-33. Control Register Sync Mode To Routing Data Bus SC CLK HFCLK Control Register Double Sync Mode In Double Sync mode, as shown in Figure 16-34, a second register clocked by the selected SC clock is added after the re-sampling register. This allows the circuit to perform robustly when the HFCLK and SC clock are asynchronous. Figure 16-34. Control Register Double Sync Mode To Routing Data Bus HFCLK 154 SC CLK SC CLK PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Control Register Pulse Mode Pulse mode is similar to Sync mode in that the control bit is re-sampled by the SC clock; the pulse starts on the first SC clock cycle following the bus write cycle. The output of the control bit is asserted for one full SC clock cycle. At the end of this clock cycle, the control bit is automatically reset. With this mode of operation, firmware can write a ‘1’ to a control register bit to generate a pulse. After it is written as a ‘1’, it is read back by firmware as a ‘1’ until the completion of the pulse, after which it is read back as a ‘0’. The firmware can then write another ‘1’ to start another pulse. A new pulse cannot be generated until the previous one is completed. Therefore, the maximum frequency of pulse generation is every other SC clock cycle. Control Register Reset The control register has two reset modes, controlled by the EXT RES configuration bit, as shown in Figure 16-35. When EXT RES is 0 (the default) then in sync or pulse mode the routed reset input resets the synced output but not the actual control bit. When EXT RES is 1 then the routed reset input resets both the control bit and the synced output. Figure 16-35. Control Register Reset Routed Reset 0 EXT RES 1 Data Bus Static configuration bit res To Routing res Bit by Bit CFG SC CLK HFCLK 16.2.3.3 Parallel Input/Output Mode In this mode, as Figure 16-36 shows, the status and control routing is connected to the datapath parallel in and parallel out signals. To enable this mode, the SC OUT configuration bits in the UDB CFG22 registers are set to select datapath parallel out. The parallel input connection is always available, but these routing connections are shared with the status register inputs, counter control inputs, and the interrupt output. Figure 16-36. Parallel Input/Output Mode Datapath SC OUT CTL bits must be set to select datapath parallel out bits for output to routing. po[7:0] Datapath Parallel Out 8 sc_out[7:0] pi[7:0] Datapath Parallel In 8 The INT MD and SYNC MD control bits should be cleared to enable SC_IO bits to input mode. {sc_io_in[3:0], sc_in[3:0]} PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 155 Universal Digital Blocks (UDB) 16.2.3.4 Counter Mode As shown in Figure 16-37, when the block is in counter mode, a 7-bit down counter is exposed for use by UDB internal operation or firmware applications. This counter has the following features: ■ A 7-bit read/write period register. ■ A 7-bit read/write count register. It can be accessed only when the counter is disabled. ■ Automatic reload of the period to the count register on terminal count (0). ■ A firmware control bit in the Auxiliary Control Working register (ACTL0) called CNT START, to start and stop the counter. (This is an overriding enable and must be set for optional routed enable to be operational.) ■ Selectable bits from the routing for optional dynamic control of the counter enable and load functions: ❐ EN, routed enable to start or stop counting. ❐ LD, routed load signal to force the reload of period. When this signal is asserted, it overrides a pending terminal count. It is level sensitive and continues to load the period while asserted. ■ The 7-bit count may be driven to the routing fabric as sc_out[6:0]. ■ The terminal count may be driven to the routing fabric as sc_out[7]. ■ In default mode, the terminal count is registered. In alternate mode the terminal count is combinational. ■ In default mode, the routed enable, if used, must be asserted for routed load to operate. In alternate mode the routed enable and routed load signals operate independently. To enable the counter mode, the SC_OUT_CTL[1:0] bits of the UDB CFG22 register must be set to counter output. In this mode the normal operation of the control register is not available. The status register can still be used for read operations, but should not be used to generate an interrupt because the mask register is reused as the counter period register. The Period register is implemented as a retention register and maintains its state across sleep intervals. For a period of N clocks, the period value of N–1 should be loaded. N = 1 (period of 0) is not supported as a clock divide value, and results in the terminal count output of a constant 1.The use of SYNC mode depends on whether the dynamic control inputs (LD/EN) are used. If they are not used, SYNC mode is unaffected. If they are used, SYNC mode is unavailable. Figure 16-37. Counter Mode System Bus Read Only* Read Write *Current count value is only readable when not enabled. 7-Bit Period Register 0: Reload is only controlled by terminal count 1: Reload is also controlled by routing Routed Reset from Reset and Clock Control Block CFGx ROUTE LD CFGx ROUTE EN LD RES 7-Bit Counter EN Zero Detect Terminal Count (TC) SC OUT CTL bits must be set to select the counter output as the selected output to routing. sc_out[7] 0: Enable is only controlled by firmware 1: Enable is also controlled by routing ACTL CNT START CFGx EN SEL[1:0] 7 sc_out[6:0] The INT MD and SYNC MD bits should be cleared to configure the SC_IO bits to input mode. CFGx LD SEL[1:0] 4 4 [7:4] [3:0] 8 {sc_io_in[3:0], sc_in[3:0]} 156 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.3.5 Sync Mode As shown in Figure 16-38, the status register can operate as a 4-bit double synchronizer, clocked by the current SC_CLK, when the SYNC MD bit in the UDB CFG22 register is set. This mode may be used to implement local synchronization of asynchronous signals, such as GPIO inputs. When enabled, the signals to be synchronized are selected from SC_IN[3:0], the outputs are driven to the SC_IO_OUT[3:0] pins, and SYNC MD automatically puts the SC_IO pins into output mode. When in this mode, the normal operation of the status register is not available, and the status sticky bit mode is forced off, regardless of the control settings for this mode. The control register is not affected by the mode. The counter can still be used with limitations. No dynamic inputs (LD/EN) to the counter can be enabled in this mode. 5 5 CNT START 4 INT EN 3 2 1 0 FIFO1 LVL FIFO0 LVL FIFO1 CLR FIFO0 CLR FIFO0 Clear, FIFO1 Clear The FIFO0 CLR and FIFO1 CLR bits are used to reset the state of the associated FIFO. When a '1' is written to these bits, the state of the associated FIFO is cleared. These bits must be written back to '0' to allow FIFO operation to continue. When these bits are left asserted, the FIFOs operate as simple one-byte buffers, without status. 4 3 2 1 0 Table 16-20. FIFO Level Control Bits FIFOx LVL 0 4 4 CFGx SYNC MD 1 sc_io_out[3:0] sc_in[3:0] Digital Routing 16.2.3.6 6 The FIFO0 LVL and FIFO1 LVL bits control the level at which the 4-byte FIFO asserts bus status (when the bus is either reading or writing to the FIFO) to be asserted. The meaning of FIFO bus status depends on the configured direction, as shown in Table 16-20. Sync Module (Status Register) 6 7 FIFO0 Level, FIFO1 Level Figure 16-38. Sync Mode 7 Auxiliary Control Registers Status and Control Clocking The status and control registers require a clock selection for any of the following operating modes: ■ Status register with any bit set to sticky, clear on read mode. ■ Control register in counter mode. ■ Sync mode. Input Mode (Bus is Writing FIFO) Output Mode (Bus is Reading FIFO) Not Full Not Empty At least 1 byte can be written At least 1 byte can be read At Least Half Empty At Least Half Full At least 2 bytes can be writ- At least 2 bytes can be ten read Interrupt Enable When the status register’s interrupt generation logic is enabled, the INT EN bit gates the resulting interrupt signal. Count Start The CNT START bit may be used to enable and disable the counter (only valid when the SC_OUT_CTL[1:0] bits are configured for counter output mode). The clock for this is allocated in the reset and clock control module. See Reset and Clock Control Module on page 158. 16.2.3.7 Auxiliary Control Register The read-write Auxiliary Control register is a special register that controls fixed function hardware in the UDB. This register allows CPU to dynamically control the interrupt, FIFO, and counter operation. The register bits and descriptions are as follows. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 157 Universal Digital Blocks (UDB) 16.2.3.8 16.2.4 Status and Control Register Summary Table 16-21 summarizes the function of the status and control registers. Note that the control and mask registers are shared with the count and period registers and the meaning of these registers is mode dependent. Table 16-21. Status, Control Register Function Summary Mode Control/Count Status/SYNC Control Control Out Count Count Out Status Control Out or Count Out SYNC Mask/Period Status In or SYNC Status Mask Status In Status Mask SYNC NAb Count Perioda a. Note that in counter mode, the mask register is operating as a period register and cannot function as a mask register. Therefore, interrupt output is not available when counter mode is enabled. b. Note that in SYNC mode, the status register function is not available, and therefore, the mask register is unusable. However, it can be used as a period register for count mode. Reset and Clock Control Module The primary function of the reset and clock block is to select a clock from the available global system clocks or HFCLK for each of the PLDs, the datapath, and the status and control block. It also supplies dynamic and firmware-based resets to the UDB blocks. As shown in Figure 16-39, there are four clock control blocks, and one reset block. Four inputs are available for use from the routing matrix (RC_IN[3:0]). Each clock control block can select a clock enable source from these routing inputs, and there is also a multiplexer to select one of the routing inputs to be used as an external clock source. As shown, the external clock source selection can be optionally synchronized. There are a total of six clocks that can be selected for each UDB component: four UDB peripheral clocks, HFCLK, and the selected external clock (ext clk). Any of the routed input signals (rc_in) can be used as either a level sensitive or edge sensitive enable. The reset function of this block provides a routed reset for the PLD blocks and SC counter, and a firmware reset capability to each block to support reconfiguration. The HFCLK input to the reset and clock control is distinct from the system HFCLK. This clock is called “hf_clk_app” because it is gated similar to the other UDB peripheral clocks and used for UDB applications. The system HFCLK is only used for I/O access and is automatically gated, per access. The datapath clock generator produces three clocks: one for the datapath in general, and one for each of the FIFOs. Figure 16-39. Reset and Clock Control global_enable From channel routing rc_in[3:0] hf_clk_app, gclks[7:0] rc_in_gated[3:0] PLD0 Clock Select/Enable pld0_clk (to PLD0) PLD1 Clock Select/Enable pld1_clk (to PLD1) ext_clk 2 CFGx EXT CLK SEL[1:0] HFCLK CFGx EXT SYNC dp_clk (to Datapath) DP Clock Select/Enable f0_clk (to FIFO0) f1_clk (to FIFO1) SC Clock Select/Enable sc_clk (to Status and Control) mf rc_in_gated[3:0] cnt_routed_ reset (to SC counter) sysreset Reset Select/Enable pld0_reset (firmware/system reset) pld1_reset (firmware/system reset) sc_reset (firmware/system reset) dp_reset (firmware/system reset) 158 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.4.1 Clock Control Figure 16-40 illustrates one instance of the clock selection and enable circuit. Each UDB has four of these circuits: one for each of the PLD blocks, one for the datapath, and one for the status and control block. The main components of this circuit are a global clock selection multiplexer, clock inversion, clock enable selection multiplexer, clock enable inversion, and edge detect logic. Figure 16-40. Clock Select/Enable Control 3 1 rc_in_gated[3:0] 2 0 2 1 1 0 0 2 CFGx EN SEL[1:0] Enable Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] FF clk Latch 2 CFGx EN INV CFGx EN MODE[1:0] Enable Invert 0: true 1: inverted Enable Mode 00: off 01: on 10: positive edge 11: level 1 {hf_clk_app,ext_clk, gclk[7:0]} Clock Select 0000: gclk[0] 0100: gclk[4] 0001: gclk[1] 0101: gclk[5] 0010: gclk[2] 0110: gclk[6] 0011: gclk[3] 0111: gclk[7] 1000: ext_clk 1001: hf_clk_app 0 4 CFGx CK SEL[3:0] 2 CFGx CK INV Clock Invert 0: true 1: inverted Clock Selection the routing matrix that are available to this block. Four UDB peripheral clocks (see Clocking System chapter on page 63), gclk[0] to gclk[3], are routed to all UDBs; the remaining four clock configurations, gclk[4] to gclk[7], are not supported in the PSoC 4 family of devices. Any of these clocks may be selected. UDB peripheral clocks are the output of user-selectable clock dividers. Another selection is HFCLK, which is the highest frequency in the system. Called “hf_clk_app,” this signal is routed separately from the system HFCLK. In addition, an external routing signal can be selected as a clock input to support direct-clocked functions such as SPI. Because application functions are mapped to arbitrary boundaries across UDBs, individual clock selection for each UDB subcomponent block supports a fine granularity of programming. Clock Enable Inversion Clock Inversion The clock enable signal may be optionally inverted. This feature allows the clock enable to be generated in any polarity. Clock Enable Mode By default, the clock enable is OFF. After configuring the target block operation, software can set the mode to one of the following using the EN MODE[1:0] bits of the UDB CFG24 register shown in Figure 16-40. Table 16-22. Clock Enable Mode in UDB CFG24 Register Clock Enable Mode Description The selected clock may be optionally inverted. This limits the maximum frequency of operation due to the existence of one half cycle timing paths. Simultaneous bus writes and internal writes (for example writing a new count value while a counter is counting) are not supported when the internal clock is inverted and the same frequency as HFCLK. This limitation affects A0, A1, D0, D1, and the Control register in counter mode. OFF Clock is OFF. ON Clock is ON. The selected global clock is free running. Positive Edge A gated clock is generated on each positive edge detect of the clock enable input. Maximum frequency of enable input is the selected global clock divided by two. Clock Enable Selection Level Clocks are generated while the clock enable input is high ('1'). The clock enable signal may be routed to any synchronous signal and can be selected from any of the four inputs from PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 159 Universal Digital Blocks (UDB) Clock Enable Usage bits that alter the clock configuration: The two general usage scenarios for the clock enable are: ■ Each FIFO clock can be inverted with respect to the selected datapath clock polarity. ■ When FIFO FAST mode is set in the UDB CFG16 register, the HFCLK overrides the datapath clock selection normally in use by the FIFO. Firmware Enable – It is assumed that most functions require a firmware clock enable to start and stop the function. Because the boundary of a function mapped into the UDB array is arbitrary–it may span multiple UDBs and/or portions of UDBs–there must be a way to enable a given function atomically. This is typically implemented from a bit in a control register routed to one or more clock enable inputs. This scenario also supports the case where applications require multiple, unrelated blocks to be enabled simultaneously. Emulated Local Clock Generation – This feature allows local clocks to be generated by UDBs, and distributed to other UDBs in the array by using a synchronous clock enable implementation scheme, rather than directly clocking from one UDB to another. Using the positive edge feature of the clock enable mode eliminates restrictions on the duty cycle of the clock enable waveform. 16.2.4.2 Reset Control The two modes of reset control are: compatible mode and alternate mode. The modes are controlled by the ALT RES bit in each UDB CFG31 register. When this bit is ‘0’, the compatible scheme is implemented. When this bit is ‘1’, the alternate scheme is implemented. Compatible Reset Scheme This scheme features a routed reset, for dynamically resetting the embedded state of block, which can be applied to each PLD macrocell and the SC counter. Special FIFO Clocking Compatible PLD Reset Control The datapath FIFOs have special clocking considerations. By default, the FIFO clocks follow the same configuration as the datapath clock. However, the FIFOs have special control Figure 16-41 shows the compatible PLD reset system, using routed dynamic resets. Figure 16-41. Compatible PLD Reset Structure PLD0 pld_routed_reset rc_in[3:0] M C sysreset 2 CFGx PLD0 RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] M C CFGx PLD0 RES POL Reset Invert 0: true 1: inverted SSEL routed reset 1 M C 0 SSEL M C set D Q QB res 1 0 PLD1 M C System Reset RSEL PLD Macrocell M C M C M C Compatible Datapath Reset Control Figure 16-42 shows the compatible datapath reset system, using firmware reset. The firmware reset asynchronously clears the DP output registers, the carry and shift out flags, the FIFO state, accumulators, and data registers. Note that the DO and D1 registers are implemented as retention registers that maintain their state across sleep intervals. The FIFO data is unknown because it is RAM-based. 160 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Figure 16-42. Compatible Datapath Reset Structure res res OUT res OUT res OUT res OUT res OUT OUT SYNC ACTL F0 CLR res res res CO REG SOL MSB REG SOR REG RES F0 Status ACTL F1 CLR RES CFGx DP FRES F1 Status dp_reset RES sysreset A0/A1 dp_reset_ret RES D0/D1 sysreset _ret Compatible Status and Control Reset Control Figure 16-43 shows the compatible status and control block reset. The mask/period and auxiliary control registers are retention registers. Figure 16-43. Compatible Status and Control Reset Control RES Aux Control (retention) sc_reset_ret sysreset_ret CFGx SC FRES RES Mask/Period (retention) sc_reset sysreset RES Status Control register is enabled for routed reset, either in Counter mode, OR with the EXT RES bit explicitly. CGFx SC OUT CTL[1:0] RES Control Write Register And Counter CFGx EXT RES rc_in[3:0] sc_routed_reset RES Control Sampling Register (embedded) 2 CFGx RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] CFGx RES INV Reset Invert 0: true 1: inverted CFGx EN RES CNTCTL PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 161 Universal Digital Blocks (UDB) Alternate Reset Scheme Table 16-23 shows a summary of the differences between the compatible reset scheme and the alternate reset scheme. Table 16-23. Reset Schemes Feature Compatible Alternate Granularity One routed reset is shared by all blocks in the UDB Each UDB component block can select an individual reset Status register No routed reset capability Optionally can use the selected SC routed reset Datapath No routed reset capability Optionally can use the selected DP routed reset Alternate PLD Reset Control Figure 16-44 shows the alternate PLD reset system. Although there are provisions for individual resets for each PLD, this is not supported in the PLD block. Therefore, in the alternate reset scheme, the PLD0 reset control settings applies to both PLDs. Figure 16-44. Alternate PLD Reset Structure PLD0 pld_routed_reset rc_in[3:0] MC sysreset 2 CFGx PLD0 RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] pld0_reset MC CFGx PLD0 RES POL Reset Invert 0: true 1: inverted SSEL routed reset 1 0 MC SSEL MC NOTE: The current PLD only supports 1 routed reset. Both are controlled by PLD0 routed reset. rc_in[3:0] set D Q QB res 1 0 PLD1 system/ firmware reset RSEL MC PLD Macrocell 2 CFGx PLD1 RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] 162 MC CFGx PLD1 RES POL Reset Invert 0: true 1: inverted sysreset pld1_reset MC MC PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) Alternate Datapath Reset Control Figure 16-45 shows the alternate datapath reset system. The datapath routed reset applies to all datapath states, except the Data Registers, which are implemented as retention registers. Figure 16-45. Alternate Datapath Reset Structure sysreset_ret RES Accumulator Data Registers All elements of the Datapath are reset by the selected DP routed reset signal, EXCEPT the Data Registers RES Accumulator Accumulators RES Carry Out Register RES Shift Out Left Register RES Shift Out Right Register Output Sync Registers sysreset RES rc_in[3:0] 2 CFGx DP RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] CFGx DP RES POL Reset Invert 0: true 1: inverted CFGx EN RES DP ACTL F0 CLR RES FIFO0 Status ACTL F1 CLR RES FIFO1 Status PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 163 Universal Digital Blocks (UDB) Alternate Status and Control Reset Control Figure 16-46 shows the alternate status and control block reset. The mask/period and auxiliary control registers are retention registers. Figure 16-46. Alternate Status and Control Reset Control sysreset_ret RES Aux Control RES Mask/Period sysreset RES Status CFGx EN RES STAT Control register is enabled for routed reset, either in Counter mode, OR with the EXT RES bit explicitly. CGFx SC OUT CTL[1:0] RES Control Write Register and Counter CFGx EXT RES rc_in[3:0] RES Control Sampling Register (embedded) 2 CFGx SC RES SEL[1:0] Reset Select 00: rc_in[0] 01: rc_in[1] 10: rc_in[2] 11: rc_in[3] 16.2.4.3 CFGx EN RES CNTCTL CFGx SC RES POL Reset Invert 0: true 1: inverted 16.2.5 UDB POR Initialization The UDBs can be accessed through a number of address spaces, for 8, 16, and 32-bit accesses of both the working registers (A0, A1, D0, D1, FIFOs, and so on) and the configuration registers. Register and State Initialization Table 16-24. UDB POR State Initialization State Element State Element UDB Addressing POR State Configuration Latches CFG 0 – 31 0 Ax, Dx, CTL, ACTL, MASK Accumulators, data registers, auxiliary control register, mask register 0 ST, Macrocell Status and macrocell read only registers 0 DP CFG RAM and Fx (FIFOs) Datapath configuration RAM and FIFO RAM Unknown PLD RAM PLD configuration RAM Unknown ■ 8-bit working registers – This address space allows access to individual working registers in a single UDB. ■ 16-bit working registers consecutive – This address space allows access to the same working register in two consecutive UDBs, for example D0 of UDB n and D0 of UDB n + 1 ■ 16-bit working registers paired – This address space allows access to two working registers, for example A0 and A1, from the same UDB. ■ 32-bit working registers – This address space allows access to the same working register, for example A1, in all four UDBs. ■ 8, 16 or 32-bit configuration registers – This address space allows access to the configuration registers for a single UDB. Routing Initialization On POR, the state of input and output routing is as follows: ■ All outputs from the UDB that drive into the routing matrix are held at '0'. ■ All drivers out of the routing and into UDB inputs are initially gated to '0'. As a result of this initialization, conflicting drive states on the routing are avoided and initial configuration occurs in an order-independent sequence. 164 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.2.6 System Bus Access Coherency UDB registers have dual access modes: ■ System bus access, where the CPU is reading or writing a UDB register. ■ UDB internal access, where the UDB function is updating or using the contents of a register. 16.2.6.1 Simultaneous System Bus Access Table 16-25 lists the possible simultaneous access events and required behavior: Table 16-25. Simultaneous System Bus Access Register Ax UDB Write UDB Write UDB Read UDB Read Bus Write Bus Read Bus Write Bus Read Undefined result Not allowed directlya, b Fx Not supported (UDB and bus must be opposite access) If FIFO status flags are used, no simultaneous read/ write at the same location is possible ST NA, bus does not write Bus reads previous value CTL NA, UDB does not write CNT Undefined result Dx Current value is read by both Not supported (UDB and bus must be opposite access) NA, UDB does not read Not allowed directlyc UDB reads previous value ACTL MASK UDB reads previous value Current value is read by both NA, UDB does not write PER Macrocell (RO) NA, bus does not write Not allowed directlyd NA, bus does not write a. The Ax registers can be safely read by using the software capture feature of the FIFOs. b. The Dx registers can only be written dynamically by the FIFOs. When this mode is programmed, direct read of the Dx registers is not allowed. c. The CNT register can only be safely read when it is disabled. An alternative for dynamically reading the CNT value is to route the output to the SC register (in transparent mode). d. Macrocell register bits can also be routed to the status register (in transparent mode) inputs for safe reading. 16.2.6.2 Coherent Accumulator Access (Atomic Reads and Writes) The UDB accumulators are the primary target of data computation. Therefore, reading these registers directly during normal operation gives an undefined result, as indicated in Table 16-25. However, there is built-in support for atomic reads in the form of software capture, which is implemented across chained blocks. In this usage model, a read of the least significant accumulator transfers the data from all chained blocks to their associated FIFOs. Atomic writes to the accumulator can be implemented programmatically. Individual writes can be performed to the input FIFOs, and then the status signal of the last FIFO written can be routed to all associated blocks and simultaneously transfer the FIFO data into the Dx or Ax registers. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 165 Universal Digital Blocks (UDB) 16.3 Port Adapter Block The Port Adaptor block extends the UDBs to provide an interface to the GPIOs through the High-Speed I/O Matrix (HSIOM), described in High-Speed I/O Matrix on page 57. The HSIOM places registers for faster routing of DSI signals to GPIO outputs and output enables. The HSIOM also allows GPIOs to be shared amongst multiple blocks, for example port data registers and peripherals such as I2C. Figure 16-47 shows a high-level view. Figure 16-47. Port Adapter Block Diagram GPIO Port 8 8 HSIOM 8 Port Input Clock Multiplexer 8 8 To Clock Tree 8 8 4 Input Synch Regs Output Synch Regs 9 Global Clocks 3 DSI Signals 3 4 [0] 8 4 8 [0] [1] 2 Reset Selectors reset [1] 2 Clock Selectors Output Enables reset reset To DSI From DSI From DSI Each 8-bit GPIO port has one port adaptor (PA). There are eight inputs from the GPIO data in, eight outputs to the GPIO data out, and eight output enable (OE) connections. The registers in the PA are used for synchronizing inputs, outputs, and output enables. Another feature is the port input clock multiplexer. This multiplexer selects one of the port inputs to be used as a clock. The clock can be used locally in the PA and routed to the global clocks (see Clocking System chapter on page 63). Two programmable clock selectors are available, to supply separate clocks for the input and output synchronization registers. The OE register uses the same clock as the output register. Also, two programmable reset selectors are available, in the same manner as for the clock selectors. 16.3.1 PA Data Input Logic Figure 16-48 shows the structure for the data input logic. Inputs are from each pin of an I/O port. The signal can be either single synchronized or double synchronized, or synchronization can be bypassed for asynchronous inputs. Synchronization is to the selected port input clock. The output of this circuit connects to the DSI routing. Figure 16-48. Detail of GPIO Input Logic 8 Instances (one per port pin) in each Port Adapter Selected Input Reset dsi_from_pin[j] (to DSI routing) From Port Pin[j] where j = 0-7 2 Selected Input Clock 166 PACFGx IN SYNC[1:0] 00: transparent 01: single sync 10: double sync 11: reserved PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.3.2 PA Port Pin Clock Multiplexer Logic Figure 16-49 shows the port pin multiplexer. Each port has eight data input signals, one of which is selected for use as a clock. This selection is routed for use as: ■ Programmable clock in the port adapter ■ Source for the UDB clock tree ■ Programmable reset in the port adapter ■ For use as a clock enable in the port adapter. Note that the selected signal does not pass through synchronizers and is asynchronous to other clock domains within the block. It should be used carefully for selected functions. Figure 16-49. Detail of GPIO Pin Selection PIN CLK MUX dsi_from_pin[0] dsi_from_pin[1] dsi_from_pin[2] dsi_from_pin[3] To PA CLK/ Reset Select dsi_from_pin[4] dsi_from_pin[5] dsi_from_pin[6] dsi_from_pin[7] (From Port Pins) 3 PACFGx PIN SEL[2:0] Pin Clk Sel 000: sel pin 0 001: sel pin 1 010: sel pin 2 011: sel pin 3 100: sel pin 4 101: sel pin 5 110: sel pin 6 111: sel pin 7 16.3.3 PA Data Output Logic Figure 16-50 shows the structure for the data output logic. Outputs go to each pin of an I/O port (through HSIOM). The signal can be single synchronized or synchronization can be bypassed for asynchronous outputs. Other options include the ability to output either the selected clock or an inverted version of the clock. Figure 16-50. Detail of GPIO Output Data Logic 8 Instances (one per port pin) in each Port Adapter Selected Output Reset Data Mux dsi_to_pin[i+0] dsi_to_pin[i+1] To Port Pin[j] where j = i+ 0,1,2,3 dsi_to_pin[i+2] dsi_to_pin[i+3] (From DSI routing) 2 PACFGx DATA SEL[1:0] 00: Sel i+0 01: Sel i+1 10: Sel i+2 11: Sel i+3 where i = 0, 4 2 Selected Outout Clock PACFGx OUT SYNC[1:0] 00: transparent 01: single sync 10: clock 11: clock inverted PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 167 Universal Digital Blocks (UDB) 16.3.4 PA Output Enable Logic Figure 16-51 shows the output enable (OE) logic. This circuit shares the clock and reset associated with data output. This connection is unique in that there are four DSI outputs associated with the OE, but these are muxed to a total of four OE connections to the I/O port pins, as Figure 16-52 shows. Figure 16-51. GPIO Output Enable (OE) Sync Logic 4 Instances (one per DSI OE connection) in each Port Adapter Selected Output Reset dsi_to_oe[j] ( j=0 to 3) To OE Muxes 0 1 2 Selected Outout Clock PACFGx OE SNYC[1:0] 00: transparent 01: single sync 10: 1 11: 0 Figure 16-52. GPIO Output Enable (OE) Multiplexers 8 Instances (one per OE port pin input) in each Port Adapter dsi_to_oe[0] OE Sync OE selected[0] OE selected[1] To Port Pin OE[j] j = 0 to 7 OE selected[2] OE selected[3] dsi_to_oe[1] OE MUXes OE Sync 2 dsi_to_oe[2] dsi_to_oe[3] OE Sync OE Sync PACFGx OE SEL[1:0] 00: Sel 0 01: Sel 1 10: Sel 2 11: Sel 3 Note that due to the active low sense of the OE signals at the ports, there is an additional inversion in the path between the OE sync logic and the OE multiplexers. 168 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Universal Digital Blocks (UDB) 16.3.5 PA Clock Multiplexer Figure 16-53 shows the structure of the PA clock multiplexer. As noted previously, each PA has two programmable clock selectors, to supply separate clocks for port inputs and outputs and output enables (OEs). Figure 16-53. PA Clock Multiplexer Detail 3 1 {dsi_xx_rc[2:0],port_xx_rc} 2 0 2 FF 1 1 0 0 2 PACFGx EN SEL[1:0] Input/Output clk 2 PACFGx EN INV PACFGx EN MODE[1:0] 0: true 1: inverted 00: port_xx_rc 01: dsi_xx_rc[0] 10: dsi_xx_rc[1] 11: dsi_xx_rc[2] Latch 00: off 01: on 10: pos edge 11: level 1 {dsi_xx_rc[2:0],port_xx_rc,bus_clk_app, gclk[7:0]} 0000: gclk[0] 0001: gclk[4] 0010: gclk[1] 0011: gclk[5] 0100: gclk[2] 0101: gclk[6] 0110: gclk[3] 0111: gclk[7] 16.3.6 0 1000: res 1001: hf_clk_app 1010: res 1011: res 1100: port_xx_rc 1101: dsi_xx_rc[0] 1110: dsi_xx_rc[1] 1111: dsi_xx_rc[2] 4 2 PACFGx CK SEL[3:0] PACFGx CK INV 0: true 1: inverted PA Reset Multiplexer The structure of the PA reset multiplexer is shown in Figure 16-54. Figure 16-54. PA Reset Multiplexer Detail To Input/Output reset {dsi_xx_rc[2:0],port_xx_rc} 2 PACFGx RES SEL[1:0] 00: port_xx_rc 01: dsi_xx_rc[0] 10: dsi_xx_rc[1] 11: dsi_xx_rc[2] PACFGx RES INV 0: true 1: inverted As shown in Figure 16-55, the reset selection logic is duplicated, one for input, and one that serves both output and output enable. Each of these resets has an individual enable, which applies to all eight bits in the associated category. Figure 16-55. PA Reset System To Input/Output reset {dsi_xx_rc[2:0],port_xx_rc} Input Reset Select To Input Sync Register Resets 0 PACFGx RES IN EN Output Reset Select To Output Sync Registers Resets 0 PACFGx RES OUT EN To OE Sync Registers Resets 0 PACFGx RES OE EN PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 169 Universal Digital Blocks (UDB) 170 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 17. Timer, Counter, and PWM The Timer, Counter, and Pulse Width Modulator (TCPWM) block in PSoC® 4 implements the 16-bit timer, counter, pulse width modulator (PWM), and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode quadrature signals. This chapter explains the features, implementation, and operational modes of the TCPWM block. 17.1 Features ■ Four 16-bit timers, counters, or pulse width modulators (PWM) ■ The TCPWM block supports the following operational modes: ❐ Timer ❐ Capture ❐ Quadrature decoding ❐ Pulse width modulation ❐ Pseudo-random PWM ❐ PWM with dead time ■ Multiple counting modes – up, down, and up/down ■ Clock prescaling (division by 1, 2, 4, ... 64, 128) ■ Double buffering of compare/capture and period values ■ Supports interrupt on: ❐ Terminal Count – The final value in the counter register is reached ❐ Capture/Compare – The count is captured to the capture/compare register or the counter value equals the compare value ■ Synchronized counters – The counters can reload, start, stop, and count at the same time ■ DSI output signals for each counter to indicate underflow, overflow, and capture/compare condition ■ Complementary line output for PWMs ■ Selectable start, reload, stop, count, and capture event signals for each TCPWM from up to 14 DSI signals with rising edge, falling edge, both edges, and level trigger options PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 171 Timer, Counter, and PWM 17.2 Block Diagram Figure 17-1. TCPWM Block Diagram CPU Subsystem Bus Interface System Interface Configuration Registers 14 Trigger Synchronization DSI: Trigger_in Bus Interface Logic Counter 0 Counter 1 Counter 2 Counter 3 DSI: 12 underflow[3:0], overflow[3:0], cc[3:0] 5 8 Interrupts[3:0], Interrupt line_out[3:0], line_compl_out[3:0] 17.2.2 The block has these interfaces: ■ Bus interface: Connects the block to the CPU subsystem. ■ I/O signal interface with DSI: Routes signals to or from the universal digital block (UDB) and TCPWM block. It consists of input triggers (such as reload, start, stop, count, and capture) and output signals (such as overflow (OV), underflow (UN), and capture/compare (CC)). Any GPIO can be used as the input trigger signal. ■ Interrupts: Provides interrupt request signals from each counter, based on terminal count (TC) or CC conditions, and a combined interrupt signal generated by the logical OR of all four interrupt request signals. ■ System interface: Consists of control signals such as clock and reset from the system resources subsystem. Clocking The TCPWM receives the HFCLK through the system interface to synchronize all events in the block. The counter enable signal (counter_en), which is generated when the counter is enabled, gates the HFCLK to provide a counterspecific clock (counter_clock). Output triggers (explained later in this chapter) are also synchronized with the HFCLK. Clock Prescaling: counter_clock can be prescaled, with divider values of 1, 2, 4… 64, 128. This is done by modifying the GENERIC field of the counter control (TCPWM_CNT_CTRL) register, as shown in Table 17-1. Table 17-1. Bit-Field Setting to Prescale Counter Clock GENERIC[10:8] Description This TCPWM block can be configured by writing to the TCPWM registers. See TCPWM Registers on page 193 for more information on all registers required for this block. 0 Divide by 1 1 Divide by 2 2 Divide by 4 17.2.1 3 Divide by 8 4 Divide by 16 5 Divide by 32 6 Divide by 64 7 Divide by 128 Enabling and Disabling Counter in TCPWM Block The counter can be enabled by setting the COUNTER_ENABLED field (bit 0) of the control register TCPWM_CTRL. Note The counter must be configured before enabling it. If the counter is enabled after being configured, registers are updated with the new configuration values. Disabling the counter retains the values in the registers until it is enabled again (or reconfigured). Status registers are cleared after the counter is disabled. 172 Note Clock prescaling cannot be done in quadrature mode and pulse width modulation mode with dead time (PWMDT). PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM 17.2.3 Events Based on Trigger Inputs These are the events triggered by hardware or software. ■ Reload ■ Start ■ Stop ■ Count ■ Capture/switch Hardware triggers can be level signal, rising edge, falling edge, or both edges. Figure 17-2 shows the trigger selection and event detection in the TCPWM block. The trigger control register 0 (TCPWM_CNT_TR_CTRL0) selects one of the 14 trigger inputs as the event signal. Additionally, a constant '0' and '1' signals are available to be used as the event signal. Any edge (rising, falling, or both) or level (high or low) can be selected for the occurrence of an event by configuring the trigger control register 1 (TCPWM_CNT_TR_CTRL1). This edge/level configuration can be selected for each trigger event separately. Alternatively, firmware can generate an event by writing to the counter command register (TCPWM_CMD), as shown in Figure 17-2. Figure 17-2. TCPWM Trigger Selection and Event Detection rising edge System bus clock Trigger_in [13:0] 14 Trigger Synchronisation 1 Trigger signal Edge Detector Circuit counter command register (SW generated) trigger control register 1 2 4 trigger control register 0 The events derived from these triggers can have different definitions in different modes of the TCPWM block. ❐ ■ ❐ In quadrature mode, the reload event acts as a quadrature index event. An index/reload event indicates a completed rotation and can be used to synchronize quadrature decoding. Start: A start event is used to start counting; it can be used after a stop event or after re-initialization of the counter register to any value by software. Note that the count register is not initialized on this event. Notes ■ All trigger inputs are synchronized to the HFCLK. ■ When more than one event occurs in the same counter clock period, one or more events may be missed. This can happen for high-frequency events (frequencies close to the counter frequency) and a timer configuration in which a pre-scaled (divided) counter clock is used.In the Quadrature mode, edge detection is performed with the counter clock. In the other five modes, the edge detection is done using the gated version of the HFCLK. 17.2.4 Output Signals The TCPWM block generates several output signals, as shown in Figure 17-3. In quadrature mode, the start event acts as quadrature phase input phiB, which is explained in detail in Quadrature Decoder Mode on page 181. Count: A count event causes the counter to increment or decrement, depending on its configuration. In quadrature mode, the count event acts as quadrature phase input phiA. Stop: A stop event stops the counter from incrementing or decrementing. A start event will start the counting again. ❐ ■ In down counting mode, the counter is initialized with the period value stored in the TCPWM_CNT_PERIOD register. In up/down counting mode, the count register is initialized with ‘0’. ❐ ■ In up counting mode, the count register (TCPWM_CNT_COUNTER) is initialized with ‘0’. ❐ ❐ ■ capture event acts as a switch event. It switches the values of the capture/compare and period registers with their buffer counterparts. This feature can be used to modulate the pulse width and frequency. Reload: A reload event initializes and starts the counter. ❐ event both pass through 0 ■ falling edge In the PWM modes, the stop event acts as a kill event. A kill event disables all the PWM output lines. Capture: A capture event copies the counter register value to the capture register and capture register value to the buffer capture register. In the PWM modes, the PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 173 Timer, Counter, and PWM Figure 17-3. TCPWM Output Signals In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t T C P W M b lo c k 0 1 2 3 4 5 6 7 In te rru p t 8 8 8 U n d e rflo w O v e rflo w CC 8 8 lin e _ o u t lin e _ c o m p l_ o u t ❐ The counter value equals the compare value. ❐ A capture event occurs - When a capture event occurs, the TCPWM_CNT_COUNTER register value is copied to the capture register and the capture register value is copied to the buffer capture register. Note These signals, when they occur, remain at logic high for one cycle of the HFCLK. For reliable operation, the condition that causes this trigger should be less than a quarter of the HFCLK. For example, if the HFCLK is running at 24 MHz, the condition causing the trigger should occur at a frequency less than 6 MHz. 17.2.4.2 17.2.4.1 Signals upon Trigger Conditions ■ Counter generates an internal overflow (OV) condition when counting up and the count register reaches the period value. ■ Counter generates an internal underflow (UN) condition when counting down and the count register reaches zero. ■ Interrupts The TCPWM block provides a dedicated interrupt output signal from the counter. An interrupt can be generated for a TC condition or a CC condition. The exact definition of these conditions is mode-specific. All four interrupt output signals from the four TCPWMs are also OR’ed together to produce a single interrupt output signal. Four registers are used for interrupt handling in this block, as shown in Table 17-2. The capture/compare (CC) condition is generated by the TCPWM when the counter is running and one of the following conditions occur: Table 17-2. Interrupt Register Interrupt Registers Bits Name Description 0 TC This bit is set to '1', when a terminal count is detected. Write '1' to clear this bit. 1 CC_MATCH This bit is set to ‘1’ when the counter value matches capture/compare register value. Write '1' to clear this bit. 0 TC Write '1' to set the corresponding bit in the interrupt request register. When read, this register reflects the interrupt request register status. 1 CC_MATCH Write '1' to set the corresponding bit in the interrupt request register. When read, this register reflects the interrupt request register status. TCPWM_CNT_INTR_MASK (Interrupt mask register) 0 TC Mask bit for the corresponding TC bit in the interrupt request register. 1 CC_MATCH Mask bit for the corresponding CC_MATCH bit in the interrupt request register. TCPWM_CNT_INTR_MASKED (Interrupt masked request register) 0 TC Logical AND of the corresponding TC request and mask bits. 1 CC_MATCH Logical AND of the corresponding CC_MATCH request and mask bits. TCPWM_CNT_INTR (Interrupt request register) TCPWM_CNT_INTR_SET (Interrupt set request register) 17.2.4.3 Outputs The TCPWM has two outputs, line_out and line_compl_out (complementary of line_out). Note that the OV, UN, and CC conditions can be used to drive line_out and line_compl_out if needed, by configuring the TCPWM_CNT_TR_CTRL2 register (Table 17-3). Table 17-3. Configuring Output Line for OV, UN, and CC Conditions Field CC_MATCH_MODE Default Value = 3 174 Bit 1:0 Value Event 0 Set line_out to '1 1 Clear line_out to '0 2 Invert line_out 3 No change Description Configures output line on a compare match (CC) event PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Table 17-3. Configuring Output Line for OV, UN, and CC Conditions Field OVERFLOW_MODE Default Value = 3 UNDERFLOW_MODE Default Value = 3 Bit 3:2 5:4 Value Event 0 Set line_out to '1 1 Clear line_out to '0 2 Invert line_out 3 No change 0 Set line_out to '1 1 Clear line_out to '0 2 Invert line_out 3 No change PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Description Configures output line on a overflow (OV) event Configures output line on a underflow (UN) event 175 Timer, Counter, and PWM 17.2.5 Power Modes The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from VCCD. The configuration registers and other logic are powered in Deep-Sleep mode to keep the states of configuration registers. See Table 17-4 for details. Table 17-4. Power Modes in TCPWM Block Power Mode Block Status Active This block is fully operational in this mode with clock running and power switched on. Sleep All counter clocks are on, but bus interface cannot be accessed. Deep-Sleep In this mode, the power to this block is still on but no bus clock is provided; hence, the logic is not functional. All the configuration registers will keep their state. Hibernate In this mode, the power to this block is switched off. Configuration registers will lose their state. Stop In this mode, the power to this block is switched off. Configuration registers will lose their state. 17.3 Modes of Operation The counter block can function in six operational modes, as shown in Table 17-5. The MODE [26:24] field of the counter control register (TCPWM_CNTx_CTRL) configures the counter in the specific operational mode. Table 17-5. Operational Mode Configuration Mode MODE Field [26:24] Description Timer 000 Implements a timer or counter. The counter increments or decrements by '1' at every counter clock cycle in which a count event is detected. Capture 010 Implements a timer or counter with capture input. The counter increments or decrements by '1' at every counter clock cycle in which a count event is detected. When a capture event occurs, the counter value copies into the capture register. Quadrature Decoder 011 Implements a quadrature decoder, where the counter is decremented or incremented, based on two phase inputs according to the selected (X1, X2 or X4) encoding scheme. PWM 100 Implements edge/center-aligned PWMs with an 8-bit clock prescaler and buffered compare/period registers. PWM-DT 101 Implements edge/center-aligned PWMs with configurable 8-bit dead time (on both outputs) and buffered compare/period registers. PWM-PR 110 Implements a pseudo-random PWM using a 16-bit linear feedback shift register (LFSR). The counter can be configured to count up, down, and up/down by setting the UP_DOWN_MODE[17:16] field in the TCPWM_CNT_CTRL register, as shown in Table 17-6. Table 17-6. Counting Mode Configuration UP_DOWN_ MODE[17:16] Description UP Counting Mode 00 Increments the counter until the period value is reached. A Terminal Count (TC) condition is generated when the counter reaches the period value. DOWN Counting Mode 01 Decrements the counter from the period value until 0 is reached. A TC condition is generated when the counter reaches ‘0’. UP/DOWN Counting Mode 0 10 Increments the counter until the period value is reached, and then decrements the counter until ‘0’ is reached. A TC condition is generated only when ‘0’ is reached. UP/DOWN Counting Mode 1 11 Similar to up/down counting mode 0 but a TC condition is generated when the counter reaches ‘0’ and when the counter value reaches the period value. Counting Modes 176 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM 17.3.1 Timer Mode The timer mode is commonly used to measure the time of occurrence of an event or to measure the time difference between two events. 17.3.1.1 Block Diagram Figure 17-4. Timer Mode Block Diagram Reload PERIOD Start Stop UN == CC COUNTER Count OV == TC Capture COMPARE counter_clock 17.3.1.2 BUFFER COMPARE How It Works The timer can be configured to count in up, down, and up/down counting modes. It can also be configured to run in either continuous mode or one-shot mode. The following explains the working of the timer: ■ ■ ■ The timer is an up, down, and up/down counter. ❐ The current count value is stored in the count register (TCPWM_CNTx_COUNTER). Note It is not recommended to write values to this register while the counter is running. ❐ The period value for the timer is stored in the period register. The counter is re-initialized in different counting modes as follows: ❐ In the up counting mode, after the count reaches the period value, the count register is automatically reloaded with 0. ❐ In the down counting mode, after the count register reaches zero, the count register is reloaded with the value in the period register. ❐ In the up/down counting modes, the count register value is not updated upon reaching the terminal values. Instead the direction of counting changes when the count value reaches 0 or the period value. The CC condition is generated when the count register value equals the compare register value. Upon this condition, the compare register and buffer compare register switch their values if enabled by the AUTO_RELOAD_CC bit-field of the counter control (TCPWM_CNT_CTRL) register. This condition can be used to generate an interrupt request. Figure 17-5 shows the timer operational mode of the counter in four different counting modes. The period register contains the maximum counter value. ■ In the up counting mode, a period value of A results in A+1 counter cycles (0 to A). ■ In the down counting mode, a period value of A results in A+1 counter cycles (A to 0). ■ In the two up/down counting modes (0 and 1), a period value of A results in 2*A counter cycles (0 to A and back to 0). PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 177 Timer, Counter, and PWM Figure 17-5. Timing Diagram for Timer in Multiple Counting Modes Timer, down counting mode counter_clock Period 0xFF 0xFF 0xFF 0xFE 0xFD Counter 0xFF 0xFF 0xFE 0xFE 0xFD 0xFC 0x03 0xFC 0x02 0x01 0x01 0x00 0x00 OV UN TC Timer, up counting mode counter_clock 0xFF Period 0xFF 0xFF 0xFE 0xFE Counter 0xFE 0x03 0x03 0x02 0x02 0x02 0x01 0x01 0x01 0x00 0x00 0x00 OV UN TC Timer, up/down counting mode 1 counter_clock 0xFF Period 0xFF 0xFF 0xFE 0x03 Counter 0x02 0x01 0x00 0xFE 0xFE 0xFD 0x03 0xFC 0x02 0x01 0x01 0x00 OV UN TC 178 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Timer, up/down counting mode 0 counter_clock 0xFF Period 0xFF 0xFF 0xFE 0x03 Counter 0xFE 0xFE 0xFD 0x03 0xFC 0x02 0x02 0x01 0x01 0x01 0x00 0x00 OV UN TC Note The OV and UN signals remain at logic high for one cycle of the HFCLK, as explained in Signals upon Trigger Conditions on page 174. The figures in this chapter assume that HFCLK and counter clock are the same. 17.3.1.3 Configuring Counter for Timer Mode The steps to configure the counter for Timer mode of operation and the affected register bits are as follows. 12. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled. 17.3.2 Capture Mode 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. In the capture mode, the counter value can be captured at any time either through a firmware write to command register (TCPWM_CMD) or a capture trigger input. This mode is used for period and pulse width measurement. 2. Select Timer mode by writing '000' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 17.3.2.1 3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register. Block Diagram Figure 17-6. Capture Mode Block Diagram 4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register. Reload 5. Set AUTO_RELOAD_CC field of the TCPWM_CNT_CTRL register, if required to switch values at every CC condition. Count Capture 6. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 17-1. counter_clock 7. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register, as shown in Table 17-6. 8. The timer can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the ONE_SHOT[18] field of the TCPWM_CNT_CTRL register. 9. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Stop, Capture, and Count). 10. Set the TCPWM_CNT_TR_CTRL1 register to select the edge of the trigger that causes the event (Reload, Start, Stop, Capture, and Count). 11. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. PERIOD Start UN == Stop COUNTER OV CC TC CAPTURE 17.3.2.2 CAPTURE BUFFER How it Works The counter can be set to count in up, down, and up/down counting modes by configuring the UP_DOWN_MODE[17:16] bit-field of the counter control register (TCPWM_CNT_CTRL). Operation in capture mode occurs as follows: ■ During a capture event, generated either by hardware or software, the current count register value is copied to the capture register (TCPWM_CNT_CC) and the capture register value is copied to the buffer capture register (TCPWM_CNT_CC_BUFF). ■ A pulse on the CC output signal is generated when the counter value is copied to the capture register. This condition can also be used to generate an interrupt request. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 179 Timer, Counter, and PWM Figure 17-7 illustrates the capture behavior in the up counting mode. Figure 17-7. Timing Diagram of Counter in Capture Mode, Up Counting Mode Capture, up counting mode counter_clock 0xFF Period Capture trigger 0xFE 0xFE 0x03 Counter 0x03 0x02 0x02 0x01 0x00 capture 0x02 0x01 0x01 0x00 0x02 capture buffer 0x00 0xFE 0x02 0x03 0xFE OV UN TC CC Table 17-1. In the figure, observe that: ■ The period register contains the maximum count value. ■ Internal overflow (OV) and TC conditions are generated when the counter reaches the period value. ■ A capture event is only possible at the edges or through software. Use trigger control register 1 to configure the edge detection. ■ Multiple capture events in a single clock cycle are handled as: 5. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register, as shown in Table 17-6. 6. Counter can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the ONE_SHOT[18] field of the TCPWM_CNT_CTRL register. 7. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Stop, Capture, and Count). ❐ Even number of capture events - no event is observed ❐ Odd number of capture events - single event is observed 8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Stop, Capture, and Count). This happens when the capture signal frequency is greater than the counter_clock frequency. 9. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. 17.3.2.3 10. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled. Configuring Counter for Capture Mode The steps to configure the counter for Capture mode operation and the affected register bits are as follows. 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. 2. Select Capture mode by writing '010' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register. 4. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in 180 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM 17.3.3 Quadrature Decoder Mode Quadrature decoders are used to determine speed and position of a rotary device (such as servo motors, volume control wheels, and PC mice). The quadrature encoder signals are used as phiA and phiB inputs to the decoder. 17.3.3.1 Block Diagram Figure 17-8. Quadrature Mode Block Diagram index 0x0000 0xFFFF PERIOD phiA Stop == CC COUNTER phiB TC CAPTURE counter_clock 17.3.3.2 BUFFER CAPTURE ❐ How It Works Quadrature decoding only runs on counter_clock. It can operate in three sub-modes: X1, X2, and X4 modes. These encoding modes can be controlled by the QUADRATURE_MODE[21:20] field of the counter control register (TCPWM_CNT_CTRL). This mode uses double buffered capture registers. ■ The Quadrature mode operation occurs as follows: ■ Quadrature phases phiA and phiB: Counting direction is determined by the phase relationship between phiA and phiB. These phases are connected to the count and the start trigger inputs, respectively as hardware input to the decoder. ■ Quadrature index signal: This is connected to the reload signal as a hardware input. This event generates a TC condition, as shown in Figure 17-9. ■ ■ ■ This condition can be used to generate an interrupt request The value in the capture register can be used to determine which condition caused the event and whether: ❐ A counter underflow occurred (value 0) ❐ A counter overflow occurred (value 0xFFFF) ❐ An index/TC event occurred (value is not equal to either 0 or 0xFFFF) The DOWN bit field of counter status (TCPWM_CNTx_STATUS) register can be read to determine the current counting direction. Value '0' indicates a previous increment operation and value '1' indicates previous decrement operation. Figure 17-9 illustrates quadrature behavior in the X1 encoding mode. ❐ On TC, the counter is set to 0x0000 (in the up counting mode) or to the period value (in the down counting mode). A positive edge on phiA increments the counter when phiB is '0' and decrements the counter when phiB is '1'. ❐ Note The down counting mode is recommended to be used with a period value of 0x8000 (the mid-point value). The count register is initialized with the period value on an index/reload event. ❐ A pulse on CC output signal is generated when the count register value reaches 0x0000 or 0xFFFF. On a CC condition, the count register is set to the period value (0x8000 in this case). Terminal count is generated when the counter is initialized by index event. This event can be used to generate an interrupt. ❐ When the count register reaches 0xFFFF (the maximum count register value), the count register value is copied to the capture register and the count register is initialized with period value (0x8000 in this case). On TC or CC condition: ❐ Count register value is copied to the capture register ❐ Capture register value is copied to the buffer capture register PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 181 Timer, Counter, and PWM Figure 17-9. Timing Diagram for Quadrature Mode, X1 Encoding Quadrature, X1 encoding counter_clock index/reload event phiA phiB Period counter capture buffer capture 0x8000 0x8000 0x8001 0x8002 0x8003 0xFFFF 0x7FFF 0x8000 Y 0xFFFF X Y TC CC The quadrature phases are detected on the counter_clock. Within a single counter_clock period, the phases should not change value more than once. The X2 and X4 quadrature encoding modes count twice and four times as fast as the X1 encoding mode. Figure 17-10 illustrates the quadrature mode behavior in the X2 and X4 encoding modes. 182 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Figure 17-10. Timing Diagram for Quadrature Mode, X2 and X4 Encoding Quadrature, X2 encoding counter_clock index/reload event phiA phiB Period counter 4 4 6 5 7 8 7 6 TC Quadrature, X4 encoding counter_clock index/reload event phiA phiB Period counter 4 4 5 6 7 8 9 10 11 12 11 10 9 8 TC 17.3.3.3 Configuring Counter for Quadrature Mode The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows. 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. 2. Select Quadrature mode by writing '011' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register. 4. Set the required encoding mode by writing to the QUADRATURE_MODE[21:20] field of the TCPWM_CNT_CTRL register. 5. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Index and Stop). 6. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Index and Stop). 7. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. 8. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 183 Timer, Counter, and PWM 17.3.4 Pulse Width Modulation Mode The PWM mode is also called the Digital Comparator mode. The comparison output is a PWM signal whose period depends on the period register value and duty cycle depends on the compare and period register values. PWM period = (period value/counter clock frequency) in left- and right-aligned modes PWM period = (2 × (period value/counter clock frequency)) in center-aligned mode Duty cycle = (compare value/period value) in left- and right-aligned modes Duty cycle = ((period value-compare value)/period value) in center-aligned mode 17.3.4.1 Block Diagram Figure 17-11. PWM Mode Block Diagram UN BUFFER PERIOD OV CC reload PERIOD TC start == stop COUNTER line_out switch PWM count line_out_compl COMPARE counter_clock 17.3.4.2 BUFFER COMPARE ■ How It Works The PWM mode can output left, right, center, or asymmetrically aligned PWM signals. The desired output alignment is achieved by using the counter's up, down, and up/down counting modes selected using UP_DOWN_MODE [17:16] bits in the TCPWM_CNT_CTRL register, as shown in Table 17-6. This CC signal along with OV and UN signals control the PWM output line. The signals can toggle the output line or set it to a logic '0' or '1' by configuring the TCPWM_CNT_TR_CTRL2 register. By configuring how the signals impact the output line, the desired PWM output alignment can be obtained. Updates to the buffer period register and buffer compare register should be completed before the next TC with an active switch event; otherwise, switching does not reflect the register update, as shown in Figure 17-13. In the center-aligned mode, the output line is set to '0' at Terminal Count and toggled at the CC condition At the reload event, the count register is initialized and starts counting in the appropriate mode. At every count, the count register value is compared with compare register value to generate the CC signal on match. Figure 17-12 illustrates center-aligned PWM with buffered period and compare registers (up/down counting mode 0). The recommended way to modify the duty cycle is: ■ The buffer period register and buffer compare register are updated with new values. ■ On TC, the period and compare registers are automatically updated with the buffer period and buffer compare registers when there is an active switch event. The AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD fields of the counter control register are set to ‘1’. When a switch event is detected, it is remembered until the next TC event. Pass through signal (selected during event detection setting) cannot trigger a switch event. 184 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Figure 17-12. Timing Diagram for Center Aligned PWM PWM center aligned buffered counter_clock SW update of buffers new period value B, new compare value N reload event period buffer A period B A A compare buffer M compare M B N B M N A N Switch at TC condition B N Counter M 0 TC CC line_out Figure 17-12 illustrates center-aligned PWM with software generated switch events: ■ Software generates a switch event only after both the period buffer and compare buffer registers are updated. ■ Because the updates of the second PWM pulse come late (after the terminal count), the first PWM pulse is repeated. ■ Note that the switch event is automatically cleared by hardware at TC after the event takes effect. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 185 Timer, Counter, and PWM Figure 17-13. Timing Diagram for Center Aligned PWM (software switch event) PWM, center aligned, buffered (software switch event) counter_clock Switch event reload event period buffer period A B A B A compare buffer N M compare M M N A Switch at TC condition B N Counter M 0 TC CC line_out 17.3.4.3 ■ ■ ■ Other Configurations For asymmetric PWM, the up/down counting mode 1 should be used. This causes a TC when the counter reaches either ‘0’ or the period value. To create an asymmetric PWM, the compare register is changed at every TC (when the counter reaches either ‘0’ or the period value), whereas the period register is only changed at every other TC (only when the counter reaches ‘0’). For left-aligned PWM, use the up counting mode; configure the OV condition to set output line to '1' and CC condition to reset the output line to '0'. See Table 17-3. For right-aligned PWM, use the down counting mode; configure UN condition to reset output line to '0' and CC condition to set the output line to '1'. See Table 17-3. 17.3.4.4 Table 17-7. Field Setting for Stop on Kill Feature PWM_STOP_ON_KI LL Field 0 The kill trigger temporarily blocks the PWM output line but the counter is still running. 1 The kill trigger temporarily blocks the PWM output line and the counter is also stopped. A kill event can be programmed to be asynchronous or synchronous, as shown in Table 17-8. Table 17-8. Field Setting for Synchronous/Asynchronous Kill PWM_SYNC_KILL Field Kill Feature The kill feature gives the ability to disable both output lines immediately. This event can be programmed to stop the counter by modifying the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the counter control register, as shown in Table 17-7. Comments Comments 0 An asynchronous kill event lasts as long as it is present. This event requires pass through mode. 1 A synchronous kill event disables the output lines until the next TC event. This event requires rising edge mode. In the synchronous kill, PWM cannot be started before the next TC. To restart the PWM immediately after kill input is removed, kill event should be asynchronous (see 186 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Table 17-8). The generated stop event disables both output lines. In this case, the reload event can use the same trigger input signal but should be used in falling edge detection mode. 17.3.4.5 Configuring Counter for PWM Mode The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows. 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. 2. Select PWM mode by writing '100' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 3. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 17-1. 4. Set the required 16-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required. 5. Set the 16-bit compare value in the TCPWM_CNT_CC register and buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values, if required. 6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to configure left-aligned, right-aligned, or center-aligned PWM, as shown in Table 17-6. 7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required. 8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, Switch, and Count). 9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, Switch, and Count). 10. line_out and line_out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions. 11. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. 12. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 187 Timer, Counter, and PWM 17.3.5 Pulse Width Modulation with Dead Time Mode Dead time is used to delay the transitions of both ‘line_out’ and ‘line_out_compl’ signals. It separates the transition edges of these two signals by a specified time interval. Two complementary output lines 'dt_line' and 'dt_line_compl' are derived from these two lines. During the dead band period, both compare output and complement compare output are at logic ‘0’ for a fixed period. The dead band feature allows the generation of two non-overlapping PWM pulses. A maximum dead time of 255 clocks can be generated using this feature. 17.3.5.1 Block Diagram Figure 17-14. PWM-DT Mode Block Diagram BUFFER PERIOD CC Reload PERIOD TC Start Stop == COUNTER dt_line Switch PWM Count Dead Time dt_line_compl COMPARE counter_clock 17.3.5.2 BUFFER COMPARE How It Works The PWM operation with Dead Time mode occurs as follows: ■ Various output alignment modes ■ Two complementary output lines, dt_line and dt_line_compl, derived from PWM "line_out" and "line _out_compl", respectively ■ On the rising edge of the PWM line_out, depending upon UN, OV, and CC conditions, the dead time block sets the dt_line and dt_line_compl to '0'. ■ The dead band period is loaded and counted for the period configured in the register. ■ When the dead band period is complete, dt_line is set to '1'. This mode does not support clock prescaling. ■ On the falling edge of the PWM line_out depending upon UN, OV, and CC conditions, the dead time block sets the dt_line and dt_line_compl to '0'. Figure 17-15 illustrates how the complementary output lines "dt_line" and "dt_line_compl" are generated from the PWM output line, "line_out". ■ The dead band period is loaded and counted for the period configured in the register. ■ When the dead band period has completed, dt_line_compl is set to '1'. ■ A dead band period of zero has no effect on the dt_line and is the same as line_out. ■ When the duration of the dead time equals or exceeds the width of a pulse, the pulse is removed. ❐ Stop/kill event with synchronous and asynchronous modes ❐ Conditional switch event for compare and buffer compare registers and period and buffer period registers This mode follows PWM mode and supports the following features available with that mode: 188 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM Figure 17-15. Timing Diagram for PWM, with and without Dead Time PWM, Deadtime insertion line_out Dead time duration : 0 dt_line dt_line_compl Deadtime duration : dt_line dt_line_compl 17.3.5.3 Configuring Counter for PWM with Dead Time Mode The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows: 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. 2. Select PWM with Dead Time mode by writing '101' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 10. dt_line and dt_line_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions. 11. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. 12. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be provided through firmware (TCPWM_CMD register) to start the counter if hardware start signal is not enabled. 3. Set the required dead time by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 17-1. 4. Set the required 16-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required. 5. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values, if required. 6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to configure left-aligned, right-aligned, or center-aligned PWM, as shown in Table 17-6. 7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required, as shown in the Pulse Width Modulation Mode on page 184. 8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, Switch, and Count). 9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, Switch, and Count). PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 189 Timer, Counter, and PWM 17.3.6 Pulse Width Modulation Pseudo-Random Mode This mode uses the linear feedback shift register (LFSR). LFSR is a shift register whose input bit is a linear function of its previous state. 17.3.6.1 Block Diagram Figure 17-16. PWM-PR Mode Block Diagram BUFFER PERIOD CC reload PERIOD TC start == stop LFSR / COUNTER line_out switch < COMPARE counter_clock 17.3.6.2 BUFFER COMPARE How It Works The counter register is used to implement LFSR with the polynomial: x16+x14+x13+x11+1, as shown in Figure 17-17. It generates all the numbers in the range [1, 0xFFFF] in a pseudo-random sequence. Note that the counter register should be initialized with a non-zero value. Figure 17-17. Pseudo-Random Sequence Generation using Counter Register 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 190 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM The following steps describe the process: ■ The PWM output line, ‘line_out’, is driven with '1' when the lower 15-bit value of the counter register is smaller than the value in the compare register (when counter[14:0] < compare[15:0]). A compare value of ‘0x8000’ or higher always results in a '1' on the PWM output line. A compare value of ‘0’ always results in a '0' on the PWM output line. ■ A reload event behaves similar to a start event; however, it does not initialize the counter. ■ Terminal count is generated when the counter value equals the period value. LFSR generates a predictable pattern of counter values for a certain initial value. This predictability can be used to calculate the counter value after a certain amount of LFSR iterations ‘n’. This calculated counter value can be used as a period value and the TC is generated after ‘n’ iterations. ■ At TC, a switch/capture event conditionally switches the compare and period register pairs (based on the AUTO_RELOAD_CC and AUTO_RELOAD_PERIOD fields of the counter control register). ■ A kill event can be programmed to stop the counter as described in previous sections. ■ One shot mode can be configured by setting the ONE_SHOT field of the counter control register. At terminal count, the counter is stopped by hardware. ■ In this mode, underflow, overflow, and trigger condition events do not occur. ■ CC condition occurs when the counter is running and its value equals compare value. Figure 17-18 illustrates pseudo-random noise behavior. ■ A compare value of 0x4000 results in 50 percent duty cycle (only the lower 15 bits of the 16- bit counter are used to compare with the compare register value). Figure 17-18. Timing Diagram for Pseudo-Random PWM Pseudo Random PWM counter_clock reload event compare 0x4000 period 0xACE1 counter 0xACE1 0x5670 0xAB38 0x559C 0x2ACE 0x1567 line_out A capture/switch input signal may switch the values between the compare and compare buffer registers and the period and period buffer registers. This functionality can be used to modulate between two different compare values using a trigger input signal to control the modulation. Note Capture/switch input signal can only be triggered by an edge (rising, falling, or both). This input signal is remembered until the next terminal count. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 191 Timer, Counter, and PWM 17.3.6.3 Configuring Counter for PseudoRandom PWM Mode 5. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required. The steps to configure the counter for pseudo-random PWM mode of operation and the affected register bits are as follows. 6. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, and Switch). 1. Disable the counter by writing '0' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. 7. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, and Switch). 2. Select pseudo-random PWM mode by writing '110' to the MODE[26:24] field of the TCPWM_CNT_CTRL register. 8. line_out and line_out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and UN conditions. 3. Set the required period (16 bit) in the TCPWM_CNT_PERIOD register and buffer period value in the TCPWM_CNT_PERIOD_BUFF register to switch values, if required. 4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values. 192 9. If required, set the interrupt upon TC or CC condition, as shown in Interrupts on page 174. 10. Enable the counter by writing '1' to the corresponding bit in the COUNTER_ENABLED field of the TCPWM_CTRL register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Timer, Counter, and PWM 17.4 TCPWM Registers Table 17-9. List of TCPWM Registers Register Comment Features TCPWM_CTRL TCPWM control register Enables the counter block TCPWM_CMD TCPWM command register Generates software events TCPWM_INTR_CAUSE TCPWM counter interrupt cause register Determines the source of the combined interrupt signal TCPWM_CNTx_CTRL Counter control register Configures counter mode, encoding modes, one shot mode, switching, kill feature, dead time, clock prescaling, and counting direction TCPWM_CNTx_STATUS Counter status register Reads the direction of counting, dead time duration, and clock prescaling; checks if counter is running TCPWM_CNTx_COUNTER Count register Contains the 16-bit counter value TCPWM_CNTx_CC Counter compare/capture register Captures the counter value or compares the value with the counter value TCPWM_CNTx_CC_BUFF Counter buffered compare/capture register Buffer register for counter CC register; switches compare value TCPWM_CNTx_PERIOD Counter period register Contains upper value of the counter TCPWM_CNTx_PERIOD_BUFF Counter buffered period register Buffer register for counter period register; switches period value TCPWM_CNTx_TR_CTRL0 Counter trigger control register 0 Selects trigger for specific counter events TCPWM_CNTx_TR_CTRL1 Counter trigger control register 1 Determines edge detection for specific counter input signals TCPWM_CNTx_TR_CTRL2 Counter trigger control register 2 Controls counter output lines upon CC, OV, and UN conditions TCPWM_CNTx_INTR Interrupt request register Sets the register bit when TC or CC condition is detected TCPWM_CNTx_INTR_SET Interrupt set request register Sets the corresponding bits in the interrupt request register TCPWM_CNTx_INTR_MASK Interrupt mask register Mask for interrupt request register TCPWM_CNTx_INTR_MASKED Interrupt masked request register Bit-wise AND of interrupt request and mask registers Note 'x' in the register name denotes the number of TCPWM. For example, the interrupt mask register for TCPWM0 is TCPWM_CNT0_INTR_MASK. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 193 Timer, Counter, and PWM 194 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section F: Analog System This section encompasses the following chapter: ■ Precision Reference chapter on page 197 ■ SAR ADC chapter on page 201 ■ Low-Power Comparator chapter on page 229 ■ Continuous Time Block mini (CTBm) chapter on page 235 ■ LCD Direct Drive chapter on page 243 ■ CapSense chapter on page 255 ■ Temperature Sensor chapter on page 265 Top Level Architecture Analog System Block Diagram x1 SAR (12-bit) LCD 2x LP Comparator Programmable Analog CapSense Peripheral Interconnect (MMIO) Port Interface and Digital System Interconnect (DSI) SMX CTBm 2x OpAmp x1 I/O Pins (Analog, Digital, Special, ESD) PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 195 CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Analog Routing Diagram P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus vminus sarbus0 sarbus1 vplus CSD0 source shield csh cmod CSIDAC1 iout - + - + CAP SENSE CSIDAC0 iout OA1 OA0 TEMP0 10x ~ 1x ~ 1x Firmware Only DSI Only Firmware + DSI 10x Switch Control Legend SARADC0 vplus vminus ext_vref Firmware + DSI + SAR-Sequencer Comp out to DSI 196 temp Vssa_kelvin SAR Comp out to DSI PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 18. Precision Reference PSoC® 4 has a precision reference block, which creates multiple reference bias voltages and currents for the whole chip. This block is also responsible to provide temperature dependent references to the internal main oscillator (IMO) circuit and the flash memory block for accurate IMO output frequency and error free flash read/write operations respectively, across temperature range of the device. 18.1 Features The precision reference block has following features: ■ Bandgap circuit to generate 1.024 V and 2.4 µA references ■ Trim buffer to generate different output voltage levels - 1.2 V, 1.024 V, and 0.8 V with input from the bandgap circuit ■ Multiple fast and slow low-power buffers, which not only enhance the drive capability of various reference outputs, but also isolate noise from one another ■ Multiple fast and slow current mirror circuits ■ Temperature-dependent voltage reference for flash memory ■ Temperature-dependent current reference for the IMO 18.2 Block Diagram Figure 18-1 illustrates the block diagram. The precision reference is mainly composed of these blocks: ■ A precision bandgap block, which generates the precision voltage and current references ■ A trim buffer, which generates different output voltage references for various applications and trims the voltage magnitude of 1.024-V output ■ A group of fast low-power buffers and slow low-power buffers, which not only enhance the drive capability of various reference outputs, but also isolate the noise from one another ■ A group of fast leaf cells and slow leaf cells, which create multiple copies of current references in fast and slow domains, respectively ■ A temperature-controlled voltage generator block for the flash system ■ A temperature-controlled current source for the IMO PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 197 Precision Reference Figure 18-1. Voltage Reference Block Diagram Voltage Buffers LVD Voltage Generator Resistor Divider 1.024 V Trim Buffer Precision BandGap CSD 1.2 V Current Generator 1.024 V BOD, Flash SAR 0.8 V 2.4 uA Current Mirrors - fast IMO, LDO GND … MIRROR 2.4 uA Current Mirrors - slow Temperature depended Voltage and Current sources … MIRROR 2.4 uA Temperature Controlled Current Generator 2.4 uA 9.6 uA (Trimmable) Temperature Controlled Voltage Generator To Analog Blocks IMO Flash (V CTAT ) Slow Voltage Buffer/ Current Mirror Fast Voltage Buffer/ Current Mirror 18.3 How it Works 18.3.3 The work principles of the main components are detailed in this section. 18.3.1 Precision Bandgap This circuit is the source of all the references generated by the precision reference block. It provides the second order curvature corrected 1.024-V voltage reference and 2.4-µA current reference. The voltage reference is routed to the trim buffer and the current reference is routed to the current mirror circuits. 18.3.2 Trim Buffer The trim buffer is an opamp network, which takes input from the bandgap circuit and generates three different references (1.2 V, 1.024 V, and 0.8 V). The references are tapped at the resistor array in the feedback network, resulting in high output impedance. This necessitates use of buffers to drive the references. 198 Low-Power Buffers PSoC 4 has multiple low-power buffers divided into two groups - fast and slow. These buffers take input from the trim buffer circuit and drive the destination blocks. The fast buffer has the capability to reach within 1 percent of the final value in 9 us. The slow buffer can reach within 40 us. Multiple buffers ensure low reference-line capacitances, which in turn reduces the settling time. Fast voltage buffers are used for the references driven to the blocks that are crucial for system startup. These include the IMO, flash, low dropout (LDO) regulator, low voltage detect (LVD), and brownout detect (BOD) circuit. The output of the fast buffer is driven to the slow buffer. This ensures that the extra loading due to the non-startup related blocks are isolated from those driven by fast buffers. Slow buffers drive function blocks, such as SAR ADC and CapSense CSD. Fast buffers are always enabled along with the bandgap block; slow buffers can be individually enabled or disabled by the user using the VREF_EN bits of the PWR_BG_CONFIG register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Precision Reference 18.3.4 Current Mirrors 18.3.5 Current mirror circuits are used to generate multiple copies of 2.4 µA reference from the bandgap circuit. Similar to voltage buffers, there are two types of current mirrors - fast and slow current mirrors. The fast current mirror circuit has a settling time of 9 us to reach within 1 percent of the final value and slow current mirror can settle in 40 µs. The fast current mirrors are used to provide bias to the fast voltage buffers. The slow current mirror outputs are used to drive the analog blocks such as SAR, CTBm, CSD, and LPCOMP. Besides the 2.4-µA source current, a 3-µA sink current (fast), required by the flash block, is also generated. Temperature-Controlled Voltage Generator The bias signal generated by this block controls the reference for flash memory, depending on the temperature. It receives input from the precision bandgap block. The temperature-dependent voltage reference (VCTAT) compensates the pump voltage generated in the flash memory block required for proper read and write operations across the temperature range of the device. 18.3.6 Temperature-Controlled Current Generator This block generates the temperature dependent current reference for the IMO to maintain its clock frequency within ±2% across the device operating temperature. Table 18-1. Voltage References Voltage References Buffer Speed Description 1.2 V Fast Reference to the LVD block 1.2 V Slow Reference to the CapSense block 1.024 V Fast Reference to the BOD block 1.024 V Fast Bias reference voltage to the flash block for flash read-out 1.024 V Slow Reference to the SAR ADC block 0.8 V Fast Comparator threshold for relaxation oscillator in the IMO 0.8 V Fast Reference to VCCD and VCCA regulators in the LDO block VCTAT Fast Temperature dependent voltage reference for flash positive voltage (VPOS) pump Table 18-2. Current References Current References Buffer Speed 2.4 µA Fast Current reference for LCD drive, BOD, and blocks, and bias for fast voltage buffers 2.4 µA Slow Current reference for analog blocks (SAR, CapSense, IDAC, LPCOMP, and CTBm) and bias for slow voltage buffers 3.0 µA Fast Current reference for flash block 9.6 µA Fast Current reference for the IMO block with programmable temperature compensation 18.4 Description Configuration During power-up, the precision reference block is initialized with default trim settings saved in the nonvolatile latch (NVL) and SFLASH. These settings are programmed during manufacturing and no field adjustment is needed. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 199 Precision Reference 200 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 19. SAR ADC The PSoC® 4 has one successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC is designed for applications that require moderate resolution and high data rate. It consists of the following blocks (see Figure 19-1): ■ SARMUX ■ SAR ADC core ■ SARREF ■ SARSEQ The SAR ADC core is a fast 12-bit ADC with sampling rate of 1 Msps in PSoC 4200 and 806 Msps in PSoC 4100. Preceding the SAR ADC is the SARMUX, which can route external pins and internal signals (AMUXBUS-A/-B, CTBm, temperature sensor output) to the eight internal channels of SAR ADC. SARREF is used for multiple reference selection. The sequencer controller SARSEQ is used to control SARMUX and SAR ADC to do an automatic scan on all enabled channels without CPU intervention and for pre-processing, such as averaging the output data. The ninth channel is an injection channel that is used for infrequent and incidental sampling of pins and signals, for example, the internal temperature sensor. The result from each channel is double-buffered and a complete scan may be configured to generate an interrupt at the end of the scan. Alternatively, the data can be routed to programmable digital blocks (UDBs) for further processing without CPU intervention. The sequencer may also be configured to flag overflow, collision, and saturation errors that can be configured to assert an interrupt. For more flexibility, it is also possible to control most analog switches, including those in the SARMUX with the UDBs. This makes it possible to implement an alternative sequencer with the UDBs. 19.1 Features ■ Operates across the entire device power supply range ■ Maximum 1 Msps sample rate ■ Eight individually configurable channels and one injection channel ■ Each channel has the following features: ■ ❐ Input from external pin or internal signal (AMUXBUS/CTBm/temperature sensor) ❐ Programmable acquisition times ❐ Selectable 8-, 10-, and 12-bit resolution ❐ Single-ended or differential measurement ❐ Averaging ❐ Results are double-buffered ❐ Result may be left or right aligned Scan triggered by timer, pin, or UDB ❐ ■ One shot–periodic or continuous mode Hardware averaging support ❐ First order accumulate ❐ Samples averaging from 2 to 256 (powers of 2) ■ Results represented in 16-bit sign extended values ■ Selectable voltage references PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 201 SAR ADC ■ ■ ❐ Internal VDDA and VDDA/2 references ❐ Internal 1.024-V reference with buffer ❐ External reference Interrupt generation ❐ Finished scan conversion ❐ Saturation detect and over-range (configurable) detect for every channel ❐ Scan results overflow ❐ Collision detect Configurable injection channel ❐ Can be interleaved between two scan sequences (tailgating) ❐ Selectable sample time, resolution, single-ended or differential, averaging ■ Option to process data in programmable digital blocks to off-load CPU ■ Option to control switches from programmable digital blocks ■ Option to control SAR ADC and switches from programmable digital blocks ■ ❐ Implement an alternative SAR sequencer ❐ Able to achieve 1 Msps Low-power modes ❐ 19.2 ADC core and reference voltage have dedicated low power modes Block Diagram Figure 19-1. Block Diagram Control Configure Registers AHB, DSI SARSEQ Port with SARMUX connectivity VPLUS SARMUX and Temp SARADC Data Sequencer VMINUS SARREF CTBm, AMUXBUS 19.3 How it Works Ref-bypass 19.3.1 This section includes the following contents: ■ Introduction of each block: SAR ADC core, SARMUX, SARREF, and SARSEQ ■ SAR ADC system resource: Interrupt, low-power mode, and SAR ADC status ■ System operation modes ■ Vrefs SAR ADC Core PSoC 4 SAR ADC core is a 12-bit SAR ADC. The maximum sample rate for this ADC is 1 Msps. The SAR ADC core has the following features: ■ Fully differential architecture; also supports single-ended mode ■ 12-bit resolution and a selectable alternate resolution: either 8-bit or 10-bit ❐ Register mode ■ Programmable acquisition time ❐ DSI mode ■ Programmable power mode (full, one-half, one-quarter) ■ Supports single and continuous conversion mode Configuration examples 202 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.1.1 Single-ended and Differential Mode input is Vn and the ADC reference is VREF, the range on the positive input is Vn ± VREF. This criteria applies for both single-ended and differential modes. In single-ended mode, Vn is connected to VSSA, VREF or an external input. PSoC 4 SAR ADC can operate in single-ended and differential mode. It is designed in a fully differential architecture, optimized to provide 12-bit accuracy in the differential mode of operation. It gives full range output (0 to 4095) for differential inputs in the range of –VREF to +VREF. SAR ADC can be configured in single-ended mode by fixing the negative input. Differential or single-ended mode can be configured by channel configuration register, SAR_CHANx_CONFIG. Note that Vn ± VREF should be in the range of VSSA to VDDA. For example, if negative input is connected to VSSA, the range on the positive input is 0 to VREF, not –VREF to VREF. This is because the signal cannot go below VSSA. Only half of the ADC range is usable because the positive input signal cannot swing below VSS, which effectively only generates an 11-bit result. The single-ended mode options of negative input include: VSSA, VREF, or an external input from any of the eight pins with SARMUX connectivity. See the device datasheet for the pin details. This mode is configured by the global configuration register SAR_CTRL. When Vminus is connected to these SARMUX pins, the single-ended mode is equivalent to differential mode. However, when the odd pin of each differential pair is connected to the common alternate ground, these conversions are 11-bit, because measured signal value (SARMUX.vplus) cannot go below ground. 19.3.1.3 Result data format is configurable from two aspects: ■ Signed/unsigned ■ Left/right alignment When the result is considered signed, the most significant bit of the conversion is used for sign extension to 16 bits with MSB. For an unsigned conversion, the result is zero extended to 16-bits. It can be configured by SAR_SAMPLE_CTRL [3:2] for differential and single-ended conversion, respectively. To get a single-ended conversion with 12 bits, it is necessary to connect VREF to the negative input of the SAR ADC; then, the input range can be from 0 to 2 × VREF. Note that temperature sensor can only be used in singleended mode; it will override the SAR_CTRL [11:9] to 0. The differential conversion is not available for temperature sensors; the result is undefined. 19.3.1.2 Result Data Format The sample value can either be right-aligned or left-aligned within the 16 bits of the result register. By default, data is right-aligned in data[11:0], with sign extension to 16 bits, if required. A lower resolution combined with left-alignment will cause lower significant bits to be made zero. Input Range All inputs should be in the range of VSSA to VDDA. Input voltage range is also limited by VREF. If voltage on negative Combined with signed and unsigned, and left and right alignment for 12-, 10-, and 8-bit conversion, the result data format can be shown as follows. Table 19-1. Result Data Format Alignment Right Right Left Signed/ Unsigned Unsigned Signed – Resolution Result Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12 – – – – 11 10 9 8 7 6 5 4 3 2 1 0 10 – – – – – – 9 8 7 6 5 4 3 2 1 0 8 – – – – – – – – 7 6 5 4 3 2 1 0 12 11 11 11 11 11 10 9 8 7 6 5 4 3 2 1 0 10 9 9 9 9 9 9 9 8 7 6 5 4 3 2 1 0 8 7 7 7 7 7 7 7 7 7 6 5 4 3 2 1 0 12 11 10 9 8 7 6 5 4 3 2 1 0 – – – – 10 9 8 7 6 5 4 3 2 1 0 – – – – – – 8 7 6 5 4 3 2 1 0 – – – – – – – – PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 203 SAR ADC 19.3.1.4 Negative Input Selection The negative input connection choice affects the voltage range, SNR, and effective resolution (Table 19-2). In single-ended mode, negative input of the SAR ADC can be connected to VSSA, VREF, or any of the eight pins with SARMUX connectivity. Table 19-2. Negative Input Selection Comparison Single-ended/ Differential Signed/Unsigned SARMUX Vminus N/Aa VSSA Single-ended Single-ended VREF Unsigned Single-ended VREF Signed Single-ended Unsigned Single-ended Vx Signed differential Vx Unsigned differential Vx Signed Vx SARMUX Vplus Range +VREF Result Register 0x7FF VSSA = 0 0x000 +2 × VREF 0xFFF VREF 0x800 VSSA = 0 0 +2 × VREF 0x7FF VREF 0x000 VSSA = 0 0x800 Vx + VREF 0xFFF Vx 0x800 Vx – VREF 0 Vx + VREF 0x7FF Vx 0x000 Vx – VREF 0x800 Vx + VREF 0xFFF Vx 0x800 Vx – VREF 0 Vx + VREF 0x7FF Vx 0x000 Vx – VREF 0x800 Maximum SNR Better Good Good Best Best Best Best a. For single-ended mode with Vminus connected to VSSA, conversions are effectively 11-bit because voltages cannot swing below VSSA on any PSoC 4 pin. Because of this, the global configuration bit SINGLE_ENDED_SIGNED (SAR_SAMPLE_CTRL[2]) will be ignored and the result is always (0x000-0x7FF). To get a single-ended conversion with 12-bits, it is necessary to connect VREF to the negative input of the SAR ADC; then, the input range can be from 0 to 2 × VREF. rate. Lower resolution results in higher conversion rate. Note that single-ended conversions with Vminus connected to the pins with SARMUX connectivity are electrically equivalent to differential mode. However, when the odd pin of each differential pair is connected to the common alternate ground, these conversions are 11-bit, because measured signal value (SARMUX.vplus) cannot go below ground. Acquisition time is the time taken by sample and hold (S/H) circuit inside SAR ADC to settle. After acquisition time, the input signal source is disconnected from the SARADC core, and the output of the S/H circuit will be used for conversion. Each channel can select one from four acquisition time options, from 4 to 1023 SAR clock cycles defined in global configuration registers SAR_SAMPLE_TIME01 and SAR_SAMPLE_TIME23. 19.3.1.5 Resolution 19.3.1.6 Acquisition Time PSoC 4 supports 12-bit resolution (default) and a selectable alternate resolution: either 8-bit or 10-bit for each channel. Resolution affects conversion time: Conversion time (sar_clk) = resolution (bit) + 2 Total acquisition and conversion time (sar_clk) = acquisition time + resolution (bit) + 2 For 12-bit conversion and acquisition time = 4, 18 sar_clk is required. For example, if sar_clk is 18 MHz, 18 sar_clk is required for conversion and you will get 1 Msps conversion 204 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.1.7 Figure 19-2. Acquisition Time Inside PSoC4 Signal Source RSRC RSW2 RSW1 + - SWACQ DC SAR Logic CSHOLD DAC The acquisition time should be sufficient to charge the internal hold capacitor of the ADC through the resistance of the routing path, as shown in Figure 19-2. The recommended value of acquisition time is: tACQ >= 9 × (RSRC + RSW2 + RSW1) × CSHOLD Where: CSHOLD ~= 10 pF RSW2 + RSW1 = ~ 500 to 1000 ohms, depending on the routing path (See Analog Routing on page 206 for details). RSRC = series resistance of the signal source SAR ADC Clock SAR ADC clock frequency must be between 1 MHz and 18 MHz for PSoC 4200 and 1 MHz to 14.5 MHz for PSoC 4100, which comes from the HFCLK via a clock divider. Note that a fractional divider is not supported for SAR ADC. To get a 1-Msps sample rate in PSoC 4200, an 18-MHz SAR ADC clock is required. To achieve this, the system clock (HFCLK) must be set to 36 MHz rather than 48 MHz. To get a 806-ksps sample rate for the PSoC 410041xxBL4100M device, IMO must be set to 29 MHz. A 12-bit ADC conversion with the minimum acquisition time of four clocks (at 18 MHz) requires 18 clocks in which to complete. A 10bit and 8-bit conversion requires 16 and 14 clocks respectively. Note that the minimum acquisition time of four clock cycles at 18 MHz is based on the minimum acquisition time supported by the SAR block (RSW1 and CSHOLD in Figure 19-2 on page 205), which is 194 ns. 19.3.1.8 SAR ADC Timing As Figure 19-3 shows, there is a sar_clk delay before raising start-of-conversion (SOC). A 12-bit resolution conversion needs 14 clocks (one bit needs one sar_clk, plus two excess sar_clk for G and F state). With acquisition time equal to four sar_clk cycles by default, 18 clock sar_clk cycles are required for total ADC acquisition and conversion. After sample (acquisition), it will output the next pulse (or dsi_sample_done), the SARMUX can route to other pin and signal, it will be done automatically with sequencer control (see SARSEQ on page 213 for details). Figure 19-3. SAR ADC Timing SARADC CLK DSI trigger SOC sample 18 sar_clk cycles State * SAMPLE G S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 F SAMPLE G S12 S11S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 F SAMPLE EOC Next Data_out Data PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Data 205 SAR ADC 19.3.2 SARMUX SARMUX is an analog dedicated programmable multiplexer. The main features of SARMUX are: ■ Switch on resistance: 600 (maximum) ■ Internal temperature sensor ■ Controlled by sequencer controller block (SARSEQ) or UDBs. ■ Charge pump inside: ■ ❐ Analog signals from pins (port 2) ❐ Temperature sensor output ❐ CTBm output via sarbus0/1 (not fast enough to sample at 1 Msps) ❐ AMUXBUS_A/B (not fast enough to sample at 1 Msps) 19.3.2.1 ❐ If VDDA < 4.0 V, charge pump should be turned on to reduce switch resistance ❐ If VDDA >= 4.0 V, charge pump is turned off and delivers VDDA as its output Analog Routing SARMUX has many switches that may be controlled by SARSEQ block (sequencer controller), or the DSI. Sequencer and DSI are the hardware control method, which can be masked by the hardware control bit in the register, SAR_MUX_SWITCH_HW_CTRL. Different control methods have different control capability on the switches. See Figure 19-4. Multiple inputs: CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-4. SARMUX Switches and Control Capability P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 Port3 vplus vminus source shield csh cmod CSIDAC1 iout - + - + CAPSENSE vminus sarbus0 sarbus1 vplus CSD0 CSIDAC0 iout OA1 OA0 TEMP0 10x ~ 1x ~ 1x Firmware Only 10x Switch Control Legend Firmware + DSI Firmware + DSI + SAR-Sequencer temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI SAR Comp out to DSI Sequencer control: The switches are controlled by the sequencer in SARSEQ block. After configuring each channel's analog routing, it enables multi-channel automatic scan in a round-robin fashion, without CPU intervention. Not every switch can be controlled by the sequencer; see Figure 19-4. The corresponding registers are: SAR_CHANx_CONFIG, SAR_MUX_SWITCH0, SAR_CTRL, and SAR_MUX_SWITCH_HW_CTRL. The detailed configuration is available in register mode; see Firmware Analog Routing on page 222. Firmware control: Programmable registers directly define the VPLUS/VMINUS connection. It can control every switch in SARMUX; see Figure 19-4. For example, in firmware control, it is possible to do a differential measurement between any two pins or signals, not just two adjacent pins (as in sequencer control). However, it needs CPU intervention for multi-channel acquisition. The corresponding registers are: SAR_MUX_SWITCH0, SAR_MUX_SWITCH_HW_CTRL. and SAR_CTRL. The detailed configuration is available in register mode; see Firmware Analog Routing on page 222. DSI control: Switches are controlled by DSI signals from the UDB, which can act as a secondary sequencer with a customized logic design. DSI can control most switches. Thus, it can do a differential measurement between any two pins and signals and firmware control. The detailed configuration is available in DSI mode; see SARMUX Analog Routing on page 218. 206 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.2.2 Analog Interconnection PSoC 4 analog interconnection is very flexible. SAR ADC can be connected to multiple inputs via SARMUX, including both external pins and internal signals. For example, it can connect to a neighboring block such as CTBm. It can also connect to other pins except port 2 through AMUXBUS_A/B, at the expense of scanning performance (more parasitic coupling, longer RC time to settle). Several cases are discussed here to provide a better understanding of analog interconnection. Input from External Pins Figure 19-5 shows how two GPIOs that support SARMUX are connected to SAR ADC as a differential pair (Vpuls/Vminus) via switches. These two switches can be controlled by sequencer, firmware, or DSI. The pins are arranged in adjacent pairs; for example, in SARMUX port P2[0] and P2[1], P2[2] and P2[3], and so on. If you need to use pins that are not paired as a differential pair, such as P2[1] and P2[2], the sequencer does not work; use firmware or DSI. CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-5. Input from External Pins P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus Legend Switch Closed CSD0 vminus Analog route used Analog route not used vplus Switch Sequenced/Controlled from FW/UDB Switch Open or don’t care sarbus0 sarbus1 source shield csh cmod CSIDAC1 iout - + - CAP SENSE CSIDAC0 + iout OA1 OA0 10x ~ 1x 1x ~ 10x TEMP0 temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI SAR Comp out to DSI PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 207 SAR ADC Input from Analog Bus (AMUXBUS_A/B) Figure 19-6 shows how two pins that do not support SARMUX connectivity are connected to ADC as a differential pair. Additional switches must connect these to two pins: AMUXBUS_A and AMUX-BUS_B, and then connect AMUXBUS_A and AMUXBUS_B to ADC. The additional switches reduce the scanning performance (more parasitic coupling, longer RC time to settle) – it is not fast enough to sample at 1 Msps. This is not recommended for external signals; the dedicated SARMUX port should be used, if possible. CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-6. Input from Analog Bus P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus Legend Switch Closed CSD0 vminus Analog route used Analog route not used sarbus0 sarbus1 vplus Switch Sequenced/Controlled from FW/UDB Switch Open or don’t care source shield csh cmod CSIDAC1 iout - + - + CAP SENSE CSIDAC0 iout OA1 OA0 10x ~ 1x ~ 1x 10x TEMP0 temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI 208 SAR Comp out to DSI PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC Input from CTBm Output via sarbus SAR ADC can be connected to CTBm output via sarbus 0/1. Figure 19-7 shows how to connect an opamp (configured as a follower) output to a single-ended SAR ADC. Negative terminal is connected to VREF. Figure 19-8 shows how to connect two opamp outputs to SAR ADC as a differential pair. It must connect opamp output to sarbus 0/1, then connect SAR ADC input to sarbus 0/1. Because there are also additional switches, it is not fast enough to sample at 1 Msps. However, the on-chip opamps add value for many applications. CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-7. Input from CTBm Output via sarbus P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus Legend Switch Closed CSD0 vminus Analog route used Analog route not used vplus Switch Sequenced/Controlled from FW/UDB Switch Open or don’t care sarbus0 sarbus1 source shield csh cmod CSIDAC1 iout - + - CAP SENSE CSIDAC0 + iout OA1 OA0 10x ~ 1x ~ 1x 10x TEMP0 temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI SAR Comp out to DSI PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 209 SAR ADC CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-8. Inputs from CTBm Output via sarbus0 and sarbus1 P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus Legend Switch Closed CSD0 vminus Analog route used Analog route not used sarbus0 sarbus1 vplus Switch Sequenced/Controlled from FW/UDB Switch Open or don’t care source shield csh cmod CSIDAC1 iout - + - CAP SENSE CSIDAC0 + iout OA1 OA0 10x ~ 1x 1x ~ 10x TEMP0 temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI 210 SAR Comp out to DSI PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC Input from Temperature Sensor One on-chip temperature sensor is available for temperature sensing and temperature-based calibration. Note for temperature sensor, differential conversions are not available (conversion result is undefined), thus always use it in singled-ended mode. Reference is from internal 1.024 V. As Figure 19-9 shows, temperature sensor can be routed to positive input of SAR ADC via switch, which can be controlled by sequencer, firmware, or DSI. Setting the MUX_FW_TEMP_VPLUS bit (SAR_MUX_SWITCH0[17]) can enable the temperature sensor and connect its output to VPLUS of SAR ADC; clearing this bit will disable temperature sensor by cutting its bias current. CTBm SARMUX Port1 Port2 P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5] P2[4] P2[3] P2[2] P2[1] P2[0] Figure 19-9. Inputs from Temperature Sensor P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] Port0 AMUXBUS_A AMUXBUS_B LPCOMP0 P4[3] P4[2] P4[1] P4[0] Port4 LPCOMP1 vplus vminus P3[7] P3[6] P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Port3 vplus vminus Legend Switch Closed CSD0 Switch Sequenced/Controlled from FW/UDB vminus Analog route used Analog route not used source shield csh vplus Switch Open or don’t care sarbus0 sarbus1 cmod CSIDAC1 iout - + - CAP SENSE CSIDAC0 + iout OA1 OA0 10x ~ 1x ~ 1x 10x TEMP0 temp Vssa_kelvin SARADC0 vplus vminus ext_vref Comp out to DSI 19.3.3 SAR Comp out to DSI SARREF The main features of SARREF are: ■ Reference options: VDDA, VDDA/2, 1.024-V bandgap (±1 percent), external reference ■ Reference buffer + bypass cap to enhance internal reference drive capability Figure 19-10. SARREF Block Diagram VDD VDD/2 Bandgap Internal 1.024V Vref SARREFMUX Vref_ext / bypass cap Reference buffer Vref for SAR ADC core SARREF PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 211 SAR ADC 19.3.3.1 Reference Options The reference voltage selection for the SAR ADC consists of a reference mux and switches inside the SARREF. The selection allows connecting VDDA, VDDA/2, and 1.024-V internal reference from a bandgap or an external VREF connected to an Ext Vref/SAR bypass pin (see the device datasheet for details). The control for the reference mux in SARREF is in the global configuration register SAR_CTRL [6:4]. 19.3.3.2 Bypass Capacitors The internal references, 1.024 V from bandgap or VDDA/2 are buffered with the reference buffer. This reference may be routed to the Ext Vref/SAR bypass pin where an external capacitor can be used to filter internal noise that may exist on the reference signal. The SAR ADC sample rate is limited to 100 ksps (at 12-bit) without an external reference bypass capacitor. For example, without a bypass capacitor and with 1.024-V internal VREF, the maximum SAR ADC clock frequency is 1.6 MHz. When using an external reference, it is recommended that an external capacitor is used. Bypass capacitors can be enabled by setting SAR_CTRL [7]. Table 19-3 lists different reference modes and its maximum frequency/sample rate for 12-bit continuous mode operation. Table 19-3. Reference Modes Reference SAR_CTRL [6:4] Bypass Cap SAR_CTRL[7] Buffer Max Frequency Max Sample Rate (12-bit) 1.024 V internal VREF without bypass cap 4 0 Yes 1.6 MHz 100 ksps 1.024 V internal VREF with bypass cap 4 1 Yes 18 MHz 1 Msps No 18 MHz 1 Msps Reference Mode External VREF (low-impedance path) 5 X VDDA/2 without bypass cap 6 0 Yes 1.6 MHz 100 ksps VDDA/2 with bypass cap 6 1 Yes 18 MHz 1 Msps VDDA 7 X No 9 MHz 500 ksps 1.024-V internal VREF startup time varies with the different bypass capacitor size, Table 19-4 lists two common values for the bypass capacitor and its startup time specification. If reference selection is changed between scans or when scanning after Sleep/Deep-Sleep, make sure the 1.024-V internal VREF is settled when SAR ADC starts sampling. The worst case settling time (when VREF is completely discharged) is the same as the startup time. Table 19-4. Bypass Capacitor Values Internal VREF Startup Time Startup time for reference with external capacitor (1 uF) Startup time for reference with external capacitor (100 nF) 19.3.3.3 Maximum Specification 2 ms 200 µs Input Range versus Reference All inputs should be between VSSA and VDDA. The ADCs input range is limited by VREF selection. If negative input is Vn and the ADC reference is VREF, the range on the positive input is Vn ± VREF. This criteria applies for both single-ended and differential modes as long as both negative and positive inputs stay within VSSA to VDDA. 212 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.4 SARSEQ ❐ SARSEQ is a dedicated sequencer controller that automatically sequences the input mux from one channel to the next while placing the result in an array of registers, one per channel. ■ Control SARMUX analog routing automatically without CPU intervention ■ ■ Control SAR ADC core (such as resolution, acquisition time, and reference) ■ Receive data from SAR ADC and pre-process (average, range detect) ■ Results are double-buffered so the CPU can safely read the results of the last scan while the next scan is in progress. The features of SARSEQ are: ■ Eight channels can be individually enabled as an automatic scan without CPU intervention ■ A ninth channel (injection channel) for infrequent signal to insert in an automatic scan ■ ■ ■ ■ Result averaging Scan triggering ❐ One shot, periodic, or continuous mode ❐ Triggered by any digital signal or input from GPIO pin ❐ Triggered by internal UDB of fixed-function block ❐ Software triggered Hardware averaging support ❐ First order accumulate ❐ From 2 to 256 samples averaging (powers of 2) ❐ Results in 16-bit representation Double buffering of output data ❐ Left or right adjusted results ❐ Results in working register and result register Interrupt generation ❐ Finished scan conversion ❐ Channel saturation detect in all control modes ❐ Over range (configurable) detect for every channel Each channel has the following features: ❐ Scan results overflow ❐ Input from external pin or internal signal (AMUXBUS/ CTBm/temperature sensor) ❐ Collision detect ❐ Up to four programmable acquisition time ❐ ❐ Default 12-bit resolution, selectable alternate resolution: either 8-bit or 10-bit Can be interleaved between two scan sequences (tailgating) ❐ ❐ Single-ended or differential mode Selectable sample time, resolution, single ended, or differential, averaging ■ Configurable injection channel Figure 19-11. SARSEQ Block Diagram SARSEQ AHB BUS interface Result Registers CHAN_RESULT0 ? ? ? Configuration Registers CHAN_RESULT7 STATUS VPLUS Accumulate/Average /Align/Sign extended sarbus 0/1 INTR_MASK INTR saturate_intr sar_dsi_data[] Reference Voltage Pin Saturation Detect DSI output to UDB SARREF DSI input from UDB Temperature Sensor RANGE_THRES PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D sar_interrupt SARADC VMINUS RANGE_COND < = > range_intr eos/collision/overflow_intr AMUXBUS_A/_B SARMUX Sequencer logic & state machine ? ? ? Port with SARMUX connectivity INJ_CHAN_RESULT 213 SAR ADC 19.3.4.1 Averaging The SARSEQ block has a 20-bit accumulator and shift register to implement averaging. Averaging is after signed extension. The global configuration SAR_SAMPLE_CTRL register specifies the details of averaging. In register control mode, channel configuration SAR_CHAN_CONFIG register has an enable bit (AVG_EN) to enable averaging. In DSI control mode, average is enabled by dsi_cfg_average signal. In global configuration, AVG_CNT (SAR_SMAPLE_CTRL [6:4]) specifies the number of samples (N) according to this formula: N=2^(AVG_CNT+1) N range = [2..256] For example, if AVG_CNT (SAR_SMAPLE_CTRL [6:4]) = 3, then N = 16. results of a complete scan while the next scan is in progress. The SAR ADC results are written to a set of working registers until the scan is complete, at which time the data is copied to a second set of registers where the data can be read by the user's application. This allows sufficient time for the firmware to read the previous scan before the present scan is completed. All input channels are double buffered with 16 registers, except the injection channel. The injection channel is not required to be doubled buffered because it is not normally part of a normal channel scan. 19.3.4.4 Injection Channel The conversions for the injection channel can be configured in the same way as the regular channels by setting SAR_INJ_CHAN_CONFIG register, it supports: ■ Pin or signal selection AVG_SHIFT bit (SAR_SAMPLE_CTRL[7]) is used to shift the result to get averaged; it should be set if averaging is enabled. ■ Single-ended or differential selection ■ Choice of resolution between 12-bit or the globally specified SUB_RESOLUTION If a channel is configured for averaging, the SARSEQ will take N consecutive samples of the specified channel in every scan. Because the conversion result is 12-bit and the maximum value of N is 256 (left shift 8 bits), the 20-bit accumulator will never overflow. ■ Sample time select from one of the four globally specified sample times ■ Averaging select If AVG_SHIFT in SAR_SAMPLE_CTRL register is set, SAR sequencer performs sign extension and then accumulation. The accumulated result is shifted right AVG_CNT + 1 bits to get averaged. If it is not, the result is forced to shift right to ensure it fits in 16 bits. Right shift is done by maximum (0, AVG_CNT-3) – if the number of samples is more than 16 (AVG_CNT >3), then the accumulation result is shifted right AVG_CNT-3bits; it AVG_CNT<3, the result is not shifted. Note in this case, the average result is bigger than expected; it is recommended to set AVG_SHIFT. This mode always uses the selected resolution of ADC (12, 10, or 8 bits). 19.3.4.2 Range Detection The SARSEQ supports range detection to allow automatic detection of result values compared to two programmable thresholds without CPU involvement. Range detection is defined by the SAR_RANGE_THRES register. The RANGE_LOW field (SAR_RANGE_THRES [15:0]) value defines the lower threshold and RANGE_HIGH field (SAR_RANGE_THRES [31:16]) defines the upper threshold of the range. The SAR_RANGE_COND bits define the condition that triggers a channel maskable range detect interrupt (RANGE_INTR). The following conditions can be selected: 0: result < RANGE_LOW (below range) 1: RANGE_LOW result < RANGE_HIGH (inside range) 2: RANGE_HIGH result (above range) 3: result <RANGE_LOW || RANGE_HIGH <= result (outside range) See Range Detection Interrupts on page 215 for details. 19.3.4.3 It supports the same interrupts as the regular channel except the overflow interrupt. ■ Maskable end-of-conversion interrupt INJ_EOC_INTR ■ Maskable range detect interrupt INJ_RANGE_INTR ■ Maskable saturation detect interrupt INJ_SATURATE_INTR ■ Maskable collision interrupt INJ_COLLISION_INTR SAR_INTR, SAR_INTR_MASK, SAR_INTR_MASKED, and SAR_INTR_SET are the corresponding registers. These features are described in detail in Global SARSEQ Configuration on page 219, Channel Configurations on page 220, and Interrupt on page 215. Tailgating The injection channel conversion can be triggered by setting the start or enable bit INJ_START_EN (SAR_INJ_CHAN_CONFIG [31]). You should select tailgating by setting INJ_TAILGATING=1 (SAR_INJ_CHAN_CONFIG [30]). The injection channel will be scanned at the end of the ongoing scan of regular channels without any collision. However, if there is no ongoing scan or the SAR ADC is idle, INJ_START_EN will enable the injection channel to be scanned at the end of the next scan of regular channels. After completing the conversion for the injection channel, the end-of conversion interrupt (INJ_EOC_INTR) is set and the INJ_START_EN bit is cleared. The conversion data of the injection is put in the SAR_INJ_RESULT register. Similar to the SAR_CHAN_RESULT, the registers contain mirror bits for "valid" (=INJ_EOC_INTR), range detect, saturation detect interrupt, and a mirror bit of the collision interrupt (INJ_COLLISSION_INTR). Double Buffer Double buffering is used so that firmware can read the 214 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.5 Interrupt Each of the interrupts described in this section has an interrupt mask in the SAR_INTR_MASK register. By making the interrupt mask low, the corresponding interrupt source is ignored. The SAR interrupt is generated if the interrupt mask bit is high and the corresponding interrupt source is pending. When servicing an interrupt, the interrupt service routine (ISR) clears the interrupt source by writing a ‘1’ to the interrupt bit after reading the data. The SAR_INTR_MASKED register is the logical AND between the interrupts sources and the interrupt mask. This provides a convenient way for the firmware to determine the source of the interrupt. For verification and debug purposes, a set bit (such as EOS_SET in the SAR_INTR_SET register) is used to trigger each interrupt. This allows the firmware to generate an interrupt without the actual event occurring. 19.3.5.1 End-of-Scan Interrupt (EOS_INTR) After completing a scan, the end-of-scan interrupt (EOS_INTR) is raised. Firmware should clear this interrupt after picking up the data from the RESULT registers. Optionally, the EOS_INTR can also be sent out on the DSI bus by setting the EOS_DSI_OUT_EN bit in SAR_SAMPLE_CTRL [31]. The EOS_INTR signal is maintained on the DSI bus for two system clock cycles. These cycles coincide with the data_valid signal for the last channel of the scan (if selected). EOS_INTR can be masked by making the EOS_MASK bit 0 in the SAR_INTR_MASK register. EOS_MASKED bit of the SAR_INTR_MASKED register is the logic AND of the interrupt flags and the interrupt masks. Writing a ‘1’ to EOS_SET bit in SAR_INTR_SET register can set the EOS_INTR, which is intended for debug and verification. 19.3.5.2 Overflow Interrupt If a new scan completes and the hardware tries to set the EOS_INTR and EOS_INTR is still high (firmware does not clear it fast enough), then an overflow interrupt (OVERFLOW_INTR) is generated by the hardware. This usually means that the firmware is unable to read the previous results before the current scan completes. In this case, the old data is overwritten. OVERFLOW_INTR can be masked by making the OVERFLOW_MASK bit 0 in SAR_INTR_MASK register. OVERFLOW_MASKED bit of SAR_INTR_MASKED register is the logic AND of the interrupt flags and the interrupt masks, which is for firmware convenience. Writing a ‘1’ to the OVERFLOW_SET bit in SAR_INTR_SET register can set OVERFLOW_INTR, which is intended for debug and verification. 19.3.5.3 Collision Interrupt notify the firmware that the new sample is invalid. This is done through the collision interrupt, which is raised any time a new trigger, other than the continuous trigger, is received. There are two collision interrupts: for the DSI trigger (DSI_COLLISION_INTR), and for the injection channel (INJ_COLLISION_INTR). This allows the firmware to identify which trigger collided with an ongoing scan. When the DSI trigger is used in level mode, the DSI_COLLISION_INTR will never be set. The three collision interrupts can be masked by making the corresponding bit ‘0’ in the SAR_INTR_MASK register. The corresponding bit in the SAR_INTR_MASKED register is the logic AND of the interrupt flags and the interrupt masks. Writing a ‘1’ to the corresponding bit in SAR_INTR_SET register can set the collision interrupt, which is intended for debug and verification. 19.3.5.4 Injection End-of-Conversion Interrupt (INJ_EOC_INTR) After completing a conversion for the injection channel, the injection end-of-conversion interrupt is raised (INJ_EOC_INTR). The firmware clears this interrupt after picking up the data from the INJ_RESULT register. Note that if the injection channel is tailgating a scan, the EOS_INTR is raised in parallel to starting the injection channel conversion. The injection channel is not considered part of the scan. INJ_EOC_INTR can be masked by making the INJ_EOC_MASK bit ‘0’ in the SAR_INTR_MASK register. The INJ_EOC_MASKED bit of SAR_INTR_MASKED register is the logic AND of the interrupt flags and the interrupt masks. Writing a ‘1’ to the INJ_EOC_SET bit in SAR_INTR_SET register can set INJ_EOC_INTR, which is intended for debug and verification. 19.3.5.5 Range Detection Interrupts Range detection interrupt flag can be set after averaging, alignment, and sign extension (if applicable). This means it is not required to wait for the entire scan to complete to determine whether a channel conversion is over-range. The threshold values need to have the same data format as the result data. Range detection interrupt for a specified channel can be masked by setting the SAR_RANGE_INTR_MASK register specified bit to ‘0’. Register SAR_RANGE_INTR_MASKED reflects a bitwise AND between the interrupt request and mask registers. If the value is not zero, then the SAR interrupt signal to the NVIC is high. SAR_RANGE_INTR_SET can be used for debug/verification. Write a '1' to set the corresponding bit in the interrupt request register; when read, this register reflects the interrupt request register. There is a range detect interrupt for each channel (RANGE_INTR and INJ_RANGE_INTR). It is possible that a new trigger is generated while the SARSEQ is still busy with the scan started by the previous trigger. Therefore, the scan for the new trigger is delayed until after the ongoing scan is completed. It is important to PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 215 SAR ADC 19.3.5.6 Saturate Detection Interrupts The saturation detection is always applied to every conversion. This feature detects if a sample value is equal to the minimum or the maximum value for the specific resolution. If it is, a maskable interrupt flag is set for the corresponding channel. This allows the firmware to take action, such as discarding the result, when the SAR ADC saturates. The sample value is tested right after conversion, before averaging. This means that the interrupt is set while the averaged result in the data register is not equal to the minimum or maximum. When a 10-bit or 8-bit resolution is selected for the channel, saturate detection is done on 10-bit or 8-bit data. Saturation interrupt flag is set immediately to enable a fast response to saturation, before the full scan and averaging. Saturation detection interrupt for specified channel can be masked by setting the SAR_SATURATE_INTR_MASK register specified bit to ‘0’. SAR_SATURATE_INTR_MASKED register reflects a bit-wise AND between the interrupt request and mask registers. If the value is not zero, then the SAR interrupt signal to the NVIC is high. SAR_SARTURATE_INTR_SET can be used for debug/verification. Write a '1' to set the corresponding bit in the interrupt request register; when read, this register reflects the interrupt request register. 19.3.5.7 Interrupt Cause Overview INTR_CAUSE register contains an overview of all the pending SAR interrupts. It allows the ISR to determine the cause of the interrupt. The register consists of a mirror copy of SAR_INTR_MASKED. In addition, it has two bits that aggregate the range and saturate detection interrupts of all channels. It includes a logical OR of all the bits in RANGE_INTR_MASKED and SATURATE_INTR_MASKED registers (does not include INJ_RANGE_INTR and INJ_SATURATE_INTR). mode, after completing a scan the SARSEQ starts the next scan immediately; therefore, the SARSEQ is always BUSY. As a result, all other triggers are essentially ignored. The two triggers are mutually exclusive, although there is no hardware requirement. When a DSI trigger coincides with a continuous trigger, both triggers are effectively handled at the same time (a collision interrupt may be set for the DSI trigger). For continuous trigger, it takes only one SAR ADC clock cycle before the sequencer tells the SAR ADC to start sampling (provided the sequencer is idle). For the DSI trigger, it depends on the trigger configuration setting. 19.3.6.1 ■ Trigger The two possible ways to trigger a scan are: ■ ■ A periodic trigger comes in over the DSI connections (dsi_trigger). This trigger is connected to the output of a TCPWM; however, it can also be connected to any GPIO pin or a UDB. The UDB can implement a state machine looking for a certain sequence of events. A continuous trigger is activated by setting the CONTINUOUS bit in SAR_SAMPLE_CTRL register. In this DSI Synchronization The DSI interface of SARSEQ runs at the system clock frequency (clk_sys); see Clocking System chapter on page 61 for details. If the incoming DSI trigger signal is not synchronous to the AHB clock, the signal needs to be synchronized by double flopping it (default). However, if the DSI trigger signal is already synchronized with the AHB clock, then these two flops can be bypassed. The configuration bit, DSI_SYNC_TRIGGER in the SAR_SAMPLE_CTRL register, controls the double flop bypass. DSI_SYNC_TRIGGER affects the trigger width (TW) and trigger interval (TI) requirement of the DSI pulse trigger signal. ■ DSI Trigger Level The DSI trigger can either be a pulse or a level; this is indicated by the configuration bit, DSI_TRIGGER_LEVEL in the SAR_SAMPLE_CTRL register. If it is a level, then the SAR starts new scans for as long as the DSI trigger signal remains high. When the DSI trigger signal is a pulse input, a positive edge detected on the DSI trigger signal triggers a new scan. ■ 19.3.6 DSI Trigger Configuration Transmission Time After the 'dsi_trigger' is raised, it takes some transmission time before the SAR ADC is told to start sampling. With different DSI_SYNC_TRIGGER and DSI_TRIGGER_LEVEL configuration, the transmission time is different; Table 19-5 shows the maximum time. Two trigger pulse intervals should be longer than the transmission time, otherwise, the second trigger is ignored. When the SAR is disabled (ENABLED=0), the DSI trigger is ignored. Table 19-5. DSI Trigger Maximum Time Maximum DSI_TRIGGER Transmission Time Bypass Sync DSI_SYNC_TRIGGER=0 Enable Sync DSI_SYNC_TRIGGER=1 (by default) Pulse trigger: DSI_TRIGGER_LEVEL=0 (by default) 1 clk_sys+2 clk_sar 3 clk_sys+2 clk_sar Level Trigger: DSI_TRIGGER_LEVEL=1 2 clk_sar 2 clk_sys+2 clk_sar 216 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC Table 19-6. Trigger Signal Requirement Trigger Specification Requirement Trigger Width (TW) TW should be greater enough so that a trigger can be locked. If DSI_SYNC_TRIGGER=1, TW >= 2 clk_sys cycle. If DSI_SYNC_TRIGGER=0, TW >= 1 SAR clock cycle. Trigger interval (TI) Trigger interval of the DSI pulse trigger signal should be longer than the transmission time (as specified in Table 19-5); otherwise, the second trigger pulse will be ignored. 19.3.7 SAR ADC Status The current SAR status can be observed through the BUSY and CUR_CHAN fields in the SAR_STATUS register. The BUSY bit is high whenever the SAR is busy sampling or converting a channel; the CUR_CHAN [4:0] bits indicate the number of the current channel being sampled (channel 16 indicates the injection channel). SW_VREF_NEG bit indicates the current switch status, including DSI and register controls, of the switch in the SAR ADC that shorts NEG with VREF input. CHAN_WORK_VALID in the CHAN_WORK_VALID register will be set if the WORK data that was sampled during the last scan is valid. When CHAN_RESULT_VALID is set in the CHAN_RESULT_VALID register, indicating that the RESULT data is valid, then the corresponding CHAN_WORK_VALID bit is cleared. The CUR_AVG_ACCU and CUR_AVG_CNT fields in the SAR_AVG_STAT register indicate the current averaging accumulator contents and the current sample counter value for averaging (counts down). SAR_MUX_SWITCH_STATUS register gives the current switch status of MUX_SWITCH0 register. These status registers help to debug SAR behavior. 19.3.8 Low-Power Mode The current consumption of the SAR ADC can be divided into two parts: SAR ADC core and SARREF. There are several methods to reduce the power consumption of the SAR ADC core. The easiest way is to reduce the trigger frequency; that is, reduce the number of conversions per second. Another option is to use a lower resolution for channels that do not need high accuracy. This shortens the conversion by up to four out of 18 cycles (for 8-bit resolution and minimum sample time). In addition, the SAR ADC offers the ICONT_LV[1:0] configuration bits, which control overall power of the SAR ADC. Maximum clock rates for each power setting should be observed. Table 19-7. ICONT_LV for Low Power Consumption ICONT_LV[1:0] Relative Power of SAR ADC Core [%] Maximum Frequency [MHz] Minimum Sample Time [cycles] Maximum Sample Speed (at 12bit) [ksps] 0 100 18 4 1000 1 50 9 3 529 2 133 18 4 1000 3 25 4.5 2 281 In PSoC 4100/4200, the maximum frequency supported by the block without external bypass capacitor is 1.6 MHz. The VDDA range supported without external bypass capacitor is 2.7 V to 5.5 V. 19.3.9 System Operation After the SAR analog is enabled by setting the ENABLED bit (SAR_CTRL [31]), follow these steps to start ADC conversions with the SARSEQ: 1. Set SAR ADC control mode: 19.3.10 Register Mode or 19.3.11 DSI Mode 2. Set SARMUX analog routing (pin/signal selection) via sequencer/firmware/DSI 3. Set the global SARSEQ conversion configurations 4. Configure each channel source (such as pin address) 5. Enable the channels 6. Set the trigger type 7. Set interrupt masks 8. Start the trigger source PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 217 SAR ADC 9. Retrieve data after each end of conversion interrupt 10. Perform injection conversions if needed Register mode means using registers to control the SARMUX and SAR ADC conversion; DSI mode means using DSI from UDB to control. The major difference between these two control modes is shown in Table 19-8. DSI mode can be enabled by setting DSI_MODE bit (SAR_CTRL [29]). Table 19-8. Difference between Control Modes Control Mode Register DSI DSI_MODE 0 1 SARMUX control Sequencer control registers: SAR_CHANx_CONFIG, SAR_MUX_SWITCH0, SAR_MUX_HW_SWITCH_CTRL SAR_CTRL Firmware control registers: SAR_MUX_SWITCH0, SAR_MUX_HW_SWITCH_CTRL, SAR_CTRL DSI signal control signals: dsi_out, dsi_oe,dsi_swctrl, dsi_sw_negvref Firmware control registers: SAR_MUX_SWITCH0, SAR_MUX_HW_SWITCH_CTRL, SAR_CTRL Global configure registers: Global configuraSAR_CTRL, SAR_SAMPLE_CTRL, SAR_SAMPLE01, tion SAR_SAMPLE23, SAR_RANGE_THES, SAR_RANGE_COND Global configure registers: SAR_CTRL, SAR_SAMPLE_CTRL, SAR_SAMPLE01, SAR_SAMPLE23, SAR_RANGE_THES, SAR_RANGE_COND Channel configuration Channel configure registers: CHAN_CONFIG, CHAN_EN, INJ_CHAN_CONFIG By DSI signal: dsi_cfg_st_sel, dsi_cfg_average, dsi_cfg_resolution, dsi_cfg_differential (CHAN_CONFIG, CHAN_EN, INJ_CHAN_CONFIG are ignored) Trigger All Apply Firmware trigger (SAR_START_CTRL[0]) DSI trigger (dsi_trigger) Continuous trigger (SAR_SAMPLE_CTRL [0]) All Apply Firmware trigger (SAR_START_CTRL[0]) DSI trigger (dsi_trigger) Continuous trigger (SAR_SAMPLE_CTRL [0]) Interrupt All Apply All Apply (only EOS_INTR, RANGE_INTR, SATURATE_INTR output on DSI signal) DSI output Support Support Result data 8 channel result registers 1 injection channel result register Only channel0 result register is available Injection Support Not supported Average Support average on one PIN/signal Support average on different PIN/signal 19.3.10 Register Mode with corresponding SARMUX selection. The unused port/ pins are reserved for other products in the PSoC 4 series. Use registers to configure the SAR ADC; this is the most common usage. Detailed register bit definition is available in the PSoC 4100/4200 Family: PSoC 4 Registers TRM. Table 19-9. PORT_ADDR and PIN_ADDR PORT_ADDR PIN_ADDR SARMUX Analog Routing 0 0..7 8 dedicated pins of the SARMUX In register mode, there are two ways to control the SARMUX analog routing: sequencer and firmware. 1 X sarbus0a 1 X sarbus1a 7 0 Temperature sensor 7 2 AMUXBUS-A 7 3 AMUXBUS-B 19.3.10.1 Sequencer Control It is essential that the appropriate hardware control bits in MUX_SWITCH_HW_CTRL register and the firmware control bits in MUX_SWITCH0 register are both set to ‘1’. Ensure that SWITCH_DISABLE=0; setting SWITCH_DISABLE disables sequencer control. With sequencer control, the pin or internal signal a channel converts is specified by the combination of port and pin address. The PORT_ADDR bits are SAR_CHANx_CONFIG [6:4] and PIN_ADDR bits are SAR_CHANx_CONFIG [2:0]. Table 19-9 shows the PORT_ADDR and PIN_ADDR setup 218 Description a. sarbus0 and sarbus1 connect to the output of the CTBm block, which contains opamp0/1. See the Continuous Time Block mini (CTBm) chapter on page 251 for more information. When PORT_ADDR=1, sarbus0 connects to positive terminal of SAR ADC regardless of the value of PIN_ADDR; sarbus1 can only connect to the negative terminal of SAR ADC when differential mode is enabled and PORT_ADDR=1. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC For differential conversion, the negative terminal connection is dependent on the positive terminal connection, which is defined by PORT_ADDR and PIN_ADDR. By setting DIFFERENTIAL_EN, the channel will do a differential conversion on the even/odd pin pair specified by the pin address with PIN_ADDR [0] ignored. P2.0/P2.1, P2.2/P2.3, P2.4/P2.5, P2.6/P2.7 are valid differential pairs for sequencer control. More flexible analog can be implemented by firmware or DSI. For single-ended conversions, NEG_SEL (SAR_CTRL [11:9]) is intended to decide which signal is connected to negative input. In differential mode, these bits are ignored. Negative input choice affects the input voltage range and effective resolution. See Negative Input Selection on page 204 for details. The options include: VSSA, VREF, or an external input from any of the eight pins with SARMUX connectivity. To connect negative input to VREF, an additional bit, SAR_HW_CTRL_NEGVREF (SAR_CTRL[13]) must be set, because the MUX_SWITCH_HW_CTRL register does not have that hardware control bit. Firmware Control By default, the SARMUX operates in firmware control. VPLUS (positive) and VMINUS (negative) inputs of SAR ADC can be controlled separately by setting the appropriate bits in SAR_MUX_SWITCH0 [29:0]. Clear appropriate bits in the hardware switch control register (SAR_MUX_SWITCH_HW_CTR[n]=0). Otherwise, hardware control method (sequencer/DSI) will control the SARMUX analog routing. SAR_CTRL register bit SWITCH_DISABLE is used to disable SAR sequencer from enabling routing switches. Note that firmware control mode can always close switches independent of this bit value; however, it is recommended to set it to ‘1’. NEG_SEL (SAR_CTRL [11:9]) decides which signal is connected to the negative terminal (vminus) of SAR ADC in single-ended mode. In differential mode, these bits are ignored. In single-ended mode, when using sequencer control, you must set these bits. When using firmware control, NEG_SEL is ignored and SAR_MUX_SWITCH0 should be set to control the negative input. A special case is when SAR_MUX_SWITCH0 does not connect internal VREF to vminus; then, set NEG_SEL to ‘7’. Negative input choice affects the input voltage range, SNR, and effective resolution. See Negative Input Selection on page 204 for details. 19.3.10.2 Global SARSEQ Configuration A number of conversion options that apply to all channels are configured globally. In several cases, the channel configuration has bits to choose what parts of the global configuration to use. Global configuration is applied to both register control and DSI control mode. SAR_CTRL, SAR_SAMPLE_CTRL, SAR_SAMPLE01, SAR_SAMPLE23, SAR_RANGE_THES, and SAR_RANGE_COND are all global configuration registers. Typically, these configurations should not be modified while a scan is in progress. If configuration settings that are in use are changed, the results are undefined. Configuration settings that are not currently in use can be changed without affecting the ongoing scan. Table 19-10. Global Configuration Registers Configurations Control Registers Detailed Reference Reference selection SAR_CTRL[6:4] 19.3.3.1 Reference Options Signed/unsigned selection SAR_SAMPLE_CTRL [3:2] 19.3.1.3 Result Data Format Data left/right alignment SAR_SAMPLE_CTRL [1] 19.3.1.3 Result Data Format Negative input selection in single-ended mode SAR_CTRL[11:9] 19.3.1.4 Negative Input Selection Resolution SAR_SAMPLE_CTRL[0]a 19.3.1.5 Resolution Acquisition time SAR_SAMPLE_TIME01 [25:0] SAR_SAMPLE_TIME32 [25:0] 19.3.1.6 Acquisition Time Averaging count SAR_SAMPLE_CTRL[7:4] 19.3.4.1 Averaging Range detection SAR_RANGE_THRES [31:0] SAR_RANGE_COND [31:30] 19.3.4.2 Range Detection a. The alternate resolution should be enabled by the SAR_RESOLUTION bit in the SAR_CHAN_CONFIG register. If the alternate resolution is not enabled, the ADC operates at 12-bits of resolution, irrespective of the resolution set by the SAR_SAMPLE_CTRL register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 219 SAR ADC 19.3.10.3 Channel Configurations Channel configuration includes: ■ Differential or single-ended mode selection ■ Global configuration selection: sample time, resolution, averaging enable ■ DSI output enable As a general rule, the channel configurations should only be updated between scans (same as global configurations). However, if a channel is not enabled for the ongoing scan, then the configuration for that channel can be changed freely without affecting the ongoing scan. If this rule is violated, the results are undefined. The channels that enable themselves are the only exception to this rule; enabled channels can be changed during the on-going scan, and it will be effective in the next scan. Changing the enabled channels may change the sample rate. Table 19-11. Channel Configuration Registers Configurations Registers Detailed Reference Single-ended/differential SAR_CHANx_CONFIG [8] 19.3.1.1 Single-ended and Differential Mode Acquisition time selection SAR_CHANx_CONFIG [13:12] 19.3.1.6 Acquisition Time Resolution selection SAR_CHANx_CONFIG [9] 19.3.1.5 Resolution Average enable SAR_CHANx_CONFIG [10] 19.3.4.1 Averaging DSI output enable SAR_CHANx_CONFIG [30] 19.3.11.8 DSI Output Enable SUB_RESOLUTION (SAR_SAMPLE_CTRL[0]) can choose which alternate resolution will be used, either 8-bit or 10 bit. Resolution (SAR_CHANx_CONFIG [9]) can determine whether default resolution 12-bit or alternate resolution is used. When averaging is enabled, the SUB_RESOLUTION is ignored; the resolution will be fixed to the maximum 12-bit. Table 19-12. Resolution SUB_RESOLUTION SAR_SAMPLE_CTRL[0] Register Mode Resolution SAR_CHANx_CONFIG [9] OFF 0 1 8-bit OFF 1 1 10-bit OFF 0 0 12-bit OFF 1 0 12-bit ON X X 12-bit Average 220 Channel Resolution PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.10.4 Channel Enables A CHAN_EN register is available to individually enable each channel. All enabled channels are scanned when the next trigger happens. After a trigger, the channel enables can immediately be updated to prepare for the next scan. This does not affect the ongoing scan. Note that this is an exception to the rule; all other configurations (global or channel) should not be changed while a scan is in progress. 19.3.10.5 Interrupt Masks There are six interrupt sources; all have an interrupt mask: For firmware convenience, bit [31] in SAR_CHAN_WORK register is the mirror bit of the corresponding bit in SAR_CHAN_WORK_VALID register. Bit[29], bit [30],and bit[31] in SAR_CHAN_RESULT are the mirror bits of the corresponding bit in SAR_SATURATE_INTR, SAR_RANGE_INTR, and SAR_CHAN_RESULT_VALID registers. Note that the interrupt bits mirrored here are the raw (unmasked) interrupt bits. It helps firmware to check if the data is valid by just reading the data register. If DSI output is enabled, it allows the SARSEQ result data to be processed by the UDBs and the channel number allows the possibility of applying different processing to data of different channels. See 19.3.11.8 DSI Output Enable for detailed description. ■ End-of-scan interrupt ■ Overflow interrupt ■ Collision interrupt 19.3.10.8 ■ Injection end-of-conversion interrupt ■ Range detection interrupt ■ Saturate detection interrupt Injection channel can be triggered by setting the start bit INJ_START_EN (INJ_CHAN_CONFIG [31]). To prevent the collision of regular automatic scan, it is recommended to enable tailgating by setting INJ_CHAN_CONFIG [30]. When it is enabled, INJ_START_EN will enable the injection channel to be scanned at the end of next scan of regular channels. DSI trigger: dsi_trigger ■ Continuous trigger: SAR_SAMPLE_CTRL [16] See 19.3.6 Trigger for details. 19.3.10.7 Retrieve Data after Each Interrupt Make sure you read the data from the result register after each scan; otherwise, the data may change because of the next scan's configuration. The 16-bit data registers are used to implement double buffering for up to eight channels (injection channel do not have double buffer). Double buffering means that there is one working register and one result register for each channel. Data is written to the working register immediately after sampling this channel. It is then copied to the result register from the working register after all enabled channels in this scan have been sampled. The CHAN_WORK_VALID bit is set after the corresponding WORK data is valid, that is, it was already sampled during the current scan. Corresponding CHAN_RESULT_VALID is set after completed scan. When CHAN_RESULT_VALID is set, the corresponding CHAN_WORK_VALID bit is cleared. SARADC Sequencer Logic and State Machine sar_dsi_sample_done Firmware trigger: SAR_START_CTRL [0] ■ sar_dsi_eos_intr ■ Figure 19-12. DSI Control Mode Block Diagram sar_dsi_chan_id[] The three ways to start an A/D conversion are: In DSI control mode, all of SAR ADC configuration can be done by DSI signals from UDB except the global configuration, such as interrupt masks, range detect settings, and triggers. The major difference between DSI mode and register mode is that the DSI mode allows hardware to dynamically control the ADC configuration. Figure 19-12 is a subset of the SAR ADC block diagram (Figure 19-1), which specifies the DSI input and output signals. sar_dsi_data[] Trigger DSI Mode dsi_cfg ** 19.3.10.6 19.3.11 dsi_trigger, dsi_data_hilo_sel See 19.3.5 Interrupt for details. See 19.3.4.4 Injection Channel for details. Dsi_out[], dsi_oe[], dsi_swctrl[], dsi_sw_negvef, Each interrupt has an interrupt request register (INTR, SATURATE_INTR, RANGE_INTR), a software interrupt set register (INTR_SET, SATURATE_INTR_SET, RANGE_INTR_SET), an interrupt mask register (INTR_MASK, SATURATE_INTR_MASK, RANGE_INTR_MASK), and an interrupt re-quest masked result register (INTR_MASKED, SATURATE_INTR_MASKED, RANGE_INTR_MASKED). An interrupt cause register is also added to have an overview of all the currently pending SAR interrupts and allows the ISR to determine the interrupt cause by just reading this register. Injection Conversions UDB The DSI control mode is selected by setting the DSI_MODE bit in the SAR_CTRL register. In this mode, the SARSEQ ignores all channel configurations in CHAN_EN, CHAN_CONFIG, and INJ_CHAN_CONFIG. Instead, it uses the configuration coming in via the DSI signal. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 221 SAR ADC The following DSI signals are used. Table 19-13. DSI Signals Signal Width Description sar_dsi_sample_done 1 Pulse to indicate that SAR ADC sampling is done. Switches can be changed to the next signal that need to be converted (identical to SAR ADC next output) sar_dsi_chan_id_valid 1 Valid signal for channel ID sar_dsi_chan_id 4 Regular mode: Channel ID, ID of the channel that is currently being converted (early) DSI control mode: [0]=saturation detect interrupt [1]=range detect interrupt (valid together with data output) sar_dsi_data_valid 1 Valid signal for data value sar_dsi_data 12 Result of converting (and averaging, if available) for one channel; the internal averaging result is 16bit wide. If dsi_data_hilo_sel=0 then sar_dsi_data[11:0]= sar_data[11:0]. If dsi_data_hilo_sel=1 then sar_dsi_data[7:0]= sar_data[15:8] and sar_dsi_data[11:8]=<undefined>. sar_dsi_eos_intr 1 End-Of-Scan interrupt to indicate that SARSEQ just finished a scan of all enabled channels 8 dsi_out[0]=1, P2.0 connected to ADC dsi_out[1]=1, P2.1 connected to ADC … dsi_out[7]=1, P2.7 connected to ADC Note MUX_SWITCH0 configuration determines whether the pin is connected to vplus or vminus. dsi_oe 4 dsi_oe[0]=1, AMUXBUSA connected to ADC dsi_oe[1]=1, AMUXBUSB connected to ADC dsi_oe[2]=1, opamp0 output connected to ADC dsi_oe[3]=1, opamp1 output connected to ADC Note MUX_SWITCH0 configuration determines whether the signal is connected to vplus or vminus. dsi_swctrl[0] 1 SARMUX analog switch control, connect vssa_kelvin to vminus dsi_swctrl[1] 1 SARMUX analog switch control, connect temp_sens to vplus dsi_sw_negvref 1 SAR ADC internal switch control, connect VREF input to NEG input dsi_out dsi_cfg_st_sel 2 Configuration control for DSI control mode: select 1 of 4 global sample times dsi_cfg_average 1 Configuration control for DSI control mode: enable averaging dsi_cfg_resolution 1 Configuration control for DSI control mode: 0=12-bit resolution 1=use globally configured alternate resolution (8 or 10 bit) dsi_cfg_differential 1 Configuration control for DSI control mode: 0= single-ended, 1=differential dsi_trigger 1 Trigger to start SARSEQ scanning all enabled channels dsi_data_hilo_sel 1 Selects between high and low byte output for sar_dsi_data[7:0]. This signal is fully asynchronous (affects sar_dsi_data without any clock involved). 19.3.11.1 Firmware Analog Routing In DSI mode, analog routing can be implemented by DSI signals and firmware. Firmware control is always available regardless of the register configuration and it is the same as in register mode. See 19.3.2.1 Analog Routing for firmware control details. 19.3.11.2 DSI Analog Routing DSI signals from UDB block are used to control SARMUX switches. In DSI control mode, the SARSEQ does not output any switch enables from the sequencer. Figure 19-4 shows that DSI can control every switch, except the DFT (design 222 for test) switch. Thus, negative and positive input of SAR ADC can be connected to any switches in DSI mode. Besides the DSI signals, appropriate hardware and firmware control bits in registers should be set. These registers and signals include SAR_MUX_SWITCH0 [n] = 1 and SAR_MUX_SWITCH_HW_CTRL[n] = 1. When VREF is connected to the negative input, set SAR_CTRL [11:9] = 7 (firmware control field) and SAR_CTRL [13] = 1 (hardware control bit) except DSI signals. DSI signals have control over the negative terminal of SAR ADC through dsi_swctrl[0] and dsi_sw_neg vREF for singleended mode. If NEG_SEL (SAR_CTRL[11:9]) is set, only NEG_SEL=7 is useful; the other value is ignored. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC Table 19-14 shows the DSI signals. Table 19-14. DSI Analog Routing Signal Width Description 8 dsi_out[0]=1, P2.0 connected to ADC dsi_out[1]=1, P2.1 connected to ADC … dsi_out[7]=1, P2.7 connected to ADC Note Whether the pin is connected to vplus or vminus is determined by MUX_SWITCH0 configuration. dsi_oe 4 dsi_oe[0]=1, AMUXBUSA connected to ADC dsi_oe[1]=1, AMUXBUSB connected to ADC dsi_oe[2]=1, sarbus0 output connected to ADC dsi_oe[3]=1, sarbus1 output connected to ADC Note Whether the signal is connected to vplus or vminus is determined by MUX_SWITCH0 configuration. dsi_swctrl[0] 1 SARMUX analog switch control, connect VSSA to vminus dsi_swctrl[1] 1 SARMUX analog switch control, connect temperature sensor to vplus 1 SAR ADC internal switch control, connect VREF input to NEG input dsi_out dsi_sw_negvref 19.3.11.3 Global SARSEQ Configuration Global configuration applies to both register mode and DSI control mode. See 19.3.10.2 Global SARSEQ Configuration for details. 19.3.11.4 DSI Channel Configuration For DSI control mode, only channel 0 is available. The channel 0 configuration can be done with DSI signals, as shown in Table 19-15. CHAN_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored. The dsi_cfg_* signals can optionally be synchronized to the SAR clock domain (actually clk_hf) by setting DSI_SYNC_CONFIG. Bypassing synchronization may be required when running the SAR at a low frequency. Table 19-15. DSI Channel Configuration Signal Width Configuration Description dsi_cfg_st_sel 2 Acquisition time Configuration control for DSI control mode: select 1 of 4 global sample times dsi_cfg_average 1 Average enable Configuration control for DSI control mode: enable averaging dsi_cfg_resolution 1 Resolution Configuration control for DSI control mode: 0: 12-bit resolution 1: use globally configure resolution bit SUB_RESOLUTION (8 or 10 bit) dsi_cfg_differential 1 Differential/single-ended Configuration control for DSI control mode: 0: single-ended 1: differential 19.3.11.5 Interrupt For an introduction to the SAR ADC interrupt, see Interrupt Masks on page 221. All interrupt masks work normally in register control mode. Not all interrupts are sent on DSI; SATURATE_INTR, RANGE_INTR, and EOS_INTR are sent via the DSI signal. ■ Along with the data, SATURATE_INTR is output on dsi_chan_id[0]; SATURATE_INTR[0] is set in DSI control mode because only channel 0 is valid in DSI mode. ■ Along with the data, RANGE_INTR is output on dsi_chan_id[1]; RANGE _INTR[0] is set in DSI control mode because only channel 0 is valid in DSI mode. ■ Channel enables are ignored; this means only one conversion is done per trigger. An EOS_INTR is generated for each conversion. ■ EOS_INTR is always sent via the DSI sar_dsi_eos_intr (a copy of dsi_data_valid). PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D signal 223 SAR ADC Table 19-16 lists the interrupts that are sent via DSI signals. 19.3.11.8 Table 19-16. DSI Signal Interrupts If the DSI_OUT_EN bit (SAR_CHANx_CONFIG[31]) is set, the result data and channel number are also sent out on the DSI bus (sar_dsi_data, sar_dsi_chan_id), next to being stored in the regular result register. This allows for the SARSEQ result data to be processed by the UDBs and the channel number allows for the possibility to apply different processing to data of different channels. Signal Width sar_dsi_chan_id sar_dsi_eos_intr 19.3.11.6 4 1 Description Register mode: Channel ID (ID of the channel that is currently being converted) DSI control mode: [0]=saturation detect interrupt [1]=range detect interrupt (valid together with data output) End-of-scan interrupt to indicate that the SARSEQ has finished a scan of all enabled channels Trigger Typically, DSI control mode is used along with the DSI trigger. However, other trigger sources, such as firmware trigger and continuous trigger are also supported. The trigger configuration is the same as in the register control mode. See Trigger on page 216 for details. For DSI trigger, the configuration settings (dsi_cfg_*) and switch settings should be stable no later than the cycle in which the dsi_trigger is sent. They should remain stable until the positive edge of the sar_dsi_sample_done. 19.3.11.7 Retrieve Data DSI Output Enable The data sent out on the DSI bus is formatted in the same way it is stored in the result register. However, by default only the 12 LSBs are sent out; it is not recommended to use left alignment unless more than 12 bits are required. To get the upper eight LSBs, the dsi_data_hilo_sel input needs to be set to ‘1’. To get the full 16-bit data from result register, first set dsi_data_hilo_sel = 0 to get the lower 12-bit data and then set dsi_data_hilo_sel = 1 to get the upper 8-bit data. Additional data process is needed to deal with the data overlap. The channel number (sar_dsi_chan_id) will be sent out earlier, after the SAR ADC has completed sampling that channel. The channel number by itself can trigger the UDBs to drive some GPIO pins, which in turn can power up (or down) some off-chip device. This drives an analog input pin that will be scanned by one of the subsequent channels in the same scan (a long sample time is useful here). Note that the data is sent out one cycle after the conversion is completed. Channel numbers, data, and their respective valid signals are maintained for two system clock cycles on the DSI bus. The result data and channel number are sent out on sar_dsi_data. It is equivalent to dsi_out_en high in register control mode. See 19.3.11.8 DSI Output Enable for details. After each conversion, the data is also written to both CHAN_WORK0 and CHAN_RESULT0 registers. Table 19-17. DSI Output Signals Signal Width Description sar_dsi_sample_done 1 Pulse to indicate that SAR ADC sampling is done. Switches can be changed to the next signal that need to be converted (identical to SAR ADC next output) sar_dsi_chan_id_valid 1 Valid signal for channel ID sar_dsi_chan_id 4 Regular mode: Channel ID, ID of the channel that is currently being converted (early) DSI control mode: [0]=saturation detect interrupt [1]=range detect interrupt (valid together with data output) sar_dsi_data_valid 1 Valid signal for data value sar_dsi_data 12 Result of converting (and averaging if there is) for one channel. The internal averaging result is 16-bit wide. If dsi_data_hilo_sel=0 then sar_dsi_data[11:0]= sar_data[11:0] If dsi_data_hilo_sel=1 then sar_dsi_data[7:0]= sar_data[15:8] and sar_dsi_data[11:8]=<undefined> sar_dsi_eos_intr 1 End-Of-Scan interrupt to indicate that SARSEQ just finished a scan of all enabled channels dsi_data_hilo_sel 1 Selects between high and low byte output for sar_dsi_data[7:0]. This signal is fully asynchronous (affects sar_dsi_data without any clock involved) 19.3.12 Analog Routing Configuration Example Table 19-18 shows some examples of pin and signal selection for sequencer control, firmware control, and DSI control. 224 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC Table 19-18. Analog Routing Configuration Example P2.0 Sequencer Control DIFFERENTIAL_EN = 0 VPLUS SARADC VSSA VMINUS Firmware Control DSI Control (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) DIFFERENTIAL_EN = 0 DSI_MODE = 1 (CTRL[29]) PORT_ADDR = 0 (CHANx_CONFIG[6:4]) (CHANx_CONFIG[8]) dsi_cfg_differential = 0 SWITCH_DISABLE = 1 (CTRL[30]) dsi_out [0] =1 PIN_ADDR = 0 MUX_SWITCH0[0] = 1 dsi_swctrl[0]=1 (CHANx_CONFIG[2:0]) MUX_SWITCH0[16] = 1 MUX_SWITCH0[0] = 1 NEG_SEL = 0 (CTRL [11:9]) MUX_SWITCH_HW_CTRL[0] = 0 MUX_SWITCH_HW_CTRL[0] = 1 MUX_SWITCH0[0] = 1 MUX_SWITCH_HW_CTRL[16] = 0 MUX_SWITCH_HW_CTRL[16]=1 MUX_SWITCH0[16] = 1 MUX_SWITCH0 [16] = 1 MUX_SWITCH_HW_CTRL[0] = 1 P2.0 MUX_SWITCH_HW_CTRL[16]= 1 DIFFERENTIAL_EN = 0 VPLUS SARADC Vref VMINUS (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) DIFFERENTIAL_EN = 0 DSI_MODE = 1 (CTRL[29]) PORT_ADDR = 0 (CHANx_CONFIG[8]) dsi_cfg_differential = 0 (CHANx_CONFIG[6:4]) SWITCH_DISABLE = 1 (CTRL[30]) MUX_SWITCH0[0] = 1 PIN_ADDR = 0 MUX_SWITCH0[0] = 1 MUX_SWITCH_HW_CTRL[0] = 1 (CHANx_CONFIG[2:0]) MUX_SWITCH_HW_CTRL[0] =0 dsi_out [0] =1 NEG_SEL = 7 (CTRL [11:9]) NEG_SEL = 7 (CTRL [11:9]) dsi_sw_negvref =1 MUX_SWITCH0[0] = 1 HW_CTRL_NEGVREF =0 HW_CTRL_NEGVREF =1 MUX_SWITCH_HW_CTRL[0]=1 (CTRL[13]) (CTRL[13]) DIFFERENTIAL_EN = 1 DSI_MODE = 1 (CTRL[29]) (CHANx_CONFIG[8]) dsi_cfg_differential = 1 SWITCH_DISABLE = 1 dsi_out [0] =1 (CTRL[30]) dsi_out [1] =1 MUX_SWITCH0[0] = 1 MUX_SWITCH0[0] = 1 MUX_SWITCH0[9] = 1 MUX_SWITCH_HW_CTRL[0] = 1 MUX_SWITCH_HW_CTRL[0] = 0 MUX_SWITCH0 [9] = 1 MUX_SWITCH_HW_CTRL[1] = 0 MUX_SWITCH_HW_CTRL[1]=1 HW_CTRL_NEGVREF =1 P2.0 (CTRL[13]) DIFFERENTIAL_EN = 1 VPLUS SARADC P2.1 (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) VMINUS PORT_ADDR = 0 (CHANx_CONFIG[6:4]) PIN_ADDR = 0 or PIN_ADDR = 1 (CHANx_CONFIG[2:0]) MUX_SWITCH0[0] = 1 MUX_SWITCH0[9] = 1 MUX_SWITCH_HW_CTRL[0] = 1 MUX_SWITCH_HW_CTRL[1] = 1 DIFFERENTIAL_EN = 0 sarbus0 VPLUS SARADC VSSA VMINUS (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) PORT_ADDR = 1 (CHANx_CONFIG[6:4]) NEG_SEL = 0 (CTRL [11:9]) MUX_SWITCH0[22] = 1 MUX_SWITCH0[16] = 1 MUX_SWITCH_HW_CTRL[22] =1 DIFFERENTIAL_EN = 0 (CHANx_CONFIG[8]) SWITCH_DISABLE = 1 (CTRL[30]) MUX_SWITCH0[22] = 1 MUX_SWITCH0[16] = 1 MUX_SWITCH_HW_CTRL[22] = 0 MUX_SWITCH_HW_CTRL[16] = 0 MUX_SWITCH_HW_CTRL[16] =1 DSI_MODE = 1 (CTRL[29]) dsi_cfg_differential = 0 dsi_oe [2] =1 dsi_swctrl[0]=1 MUX_SWITCH0 [16] = 1 MUX_SWITCH0[22] = 1 MUX_SWITCH_HW_CTRL[16]=1 MUX_SWITCH_HW_CTRL[22] =1 Note Connecting sarbus1 to VPLUS is not supported for Port/Pin control PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 225 SAR ADC Table 19-18. Analog Routing Configuration Example<Italic> (continued) Sequencer Control DIFFERENTIAL_EN = 1 sarbus0 VPLUS SARADC sarbus1 VMINUS (CHANx_CONFIG[8]) DIFFERENTIAL_EN = 1 SWITCH_DISABLE = 0 (CTRL[30]) (CHANx_CONFIG[8]) PORT_ADDR = 1 SWITCH_DISABLE = 1 (CTRL[30]) (CHANx_CONFIG[6:4]) MUX_SWITCH0[22] = 1 MUX_SWITCH0[22] = 1 MUX_SWITCH0[25] = 1 MUX_SWITCH0[25] = 1 MUX_SWITCH_HW_CTRL[22] = 0 MUX_SWITCH_HW_CTRL[22]=1 MUX_SWITCH_HW_CTRL[23] = 0 MUX_SWITCH_HW_CTRL[23]=1 DIFFERENTIAL_EN = 0 AMUXBUSA VPLUS SARADC VSSA Firmware Control VMINUS DSI Control DSI_MODE = 1 (CTRL[29]) dsi_cfg_differential = 1 dsi_oe [2] = 1 dsi_oe [3] = 1 MUX_SWITCH0[22] = 1 MUX_SWITCH0[25] = 1 MUX_SWITCH_HW_CTRL[22]=1 MUX_SWITCH_HW_CTRL[23]=1 (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) PORT_ADDR = 7 (CHANx_CONFIG[6:4]) PIN_ADDR = 2 (CHANx_CONFIG[2:0]) NEG_SEL = 0 (CTRL [11:9]) MUX_SWITCH0[18] = 1 MUX_SWITCH0[16] = 1 DIFFERENTIAL_EN = 0 (CHANx_CONFIG[8]) SWITCH_DISABLE = 1 (CTRL[30]) MUX_SWITCH0[18] = 1 MUX_SWITCH0[16] = 1 MUX_SWITCH_HW_CTRL[18]= 0 MUX_SWITCH_HW_CTRL[16]= 0 DSI_MODE = 1 (CTRL[29]) dsi_cfg_differential = 0 dsi_oe [0] = 1 dsi_swctrl[0]=1 MUX_SWITCH0[18] = 1 MUX_SWITCH_HW_CTRL[18]= 1 MUX_SWITCH_HW_CTRL[16]=1 MUX_SWITCH0 [16] = 1 MUX_SWITCH_HW_CTRL[18]= 1 MUX_SWITCH_HW_CTRL[16]= 1 DIFFERENTIAL_EN = 1 AMUXBUSA VPLUS SARADC AMUXBUSB VMINUS (CHANx_CONFIG[8]) SWITCH_DISABLE = 0 (CTRL[30]) DIFFERENTIAL_EN = 1 PORT_ADDR = 7 (CHANx_CONFIG[8]) (CHANx_CONFIG[6:4]) SWITCH_DISABLE = 1 (CTRL[30]) PIN_ADDR = 2 MUX_SWITCH0[18] = 1 (CHANx_CONFIG[2:0]) MUX_SWITCH0[21] = 1 MUX_SWITCH0[18] = 1 MUX_SWITCH_HW_CTRL[18]= 0 MUX_SWITCH0[21] = 1 MUX_SWITCH_HW_CTRL[19]= 0 MUX_SWITCH_HW_CTRL[18]= 1 DSI_MODE = 1 (CTRL[29]) dsi_cfg_differential = 1 dsi_oe [0] = 1 dsi_oe [1] = 1 MUX_SWITCH0[18] = 1 MUX_SWITCH0[21] = 1 MUX_SWITCH_HW_CTRL[18]= 1 MUX_SWITCH_HW_CTRL[19]= 1 MUX_SWITCH_HW_CTRL[19]= 1 AMUXBUSB VPLUS DIFFERENTIAL_EN = 1 SARADC AMUXBUSA (CHANx_CONFIG[8]) VMINUS Not supported. SWITCH_DISABLE = 1 (CTRL[30]) The differential pair is fixed for Port/Pin control MUX_SWITCH0[19] = 1 MUX_SWITCH0[20] = 1 MUX_SWITCH_HW_CTRL[18] =0 MUX_SWITCH_HW_CTRL[19] = 0 226 DSI_MODE = 1 (CTRL[29]) dsi_cfg_differential = 1 dsi_oe [0] = 1 dsi_oe [1] = 1 MUX_SWITCH0[19] = 1 MUX_SWITCH0[20] = 1 MUX_SWITCH_HW_CTRL[18] =1 MUX_SWITCH_HW_CTRL[19] = 1 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D SAR ADC 19.3.13 Temperature Sensor Configuration One on-chip temperature sensor is available for temperature sensing and temperature-based calibration. Differential conversions are not available for temperature sensors (conversion result is undefined). Therefore, always use it in single-ended mode. The reference is from internal 1.024 V. A pin or signal can be routed to the SAR ADC in three ways. Table 19-19 lists the methods to route temperature sensors to SAR ADC. Setting the MUX_FW_TEMP_VPLUS bit (SAR_MUX_SWITCH0[17]) can enable the temperature sensor and connect its output to VPLUS of SAR ADC; clearing this bit disables temperature sensor by cutting its bias current. Table 19-19. Route Temperature to SAR ADC Control Methods Sequencer Setup DIFFERENTIAL_EN = 0 (SAR_CHANx_CONFIG[8]) VREF_SEL = 0 (SAR_CTRL[6:4]) PORT_ADDR = 7 (SAR_CHANx_CONFIG[6:4]) PIN_ADDR = 0 (SAR_CHANx_CONFIG[2:0]) SWITCH_DISABLE = 0 (SAR_CTRL[30]) SAR_MUX_SWITCH0[16] = 1 SAR_MUX_SWITCH0[17] = 1 SAR_MUX_SWITCH_HW_CTRL[16]= 1 SAR_MUX_SWITCH_HW_CTRL[17]= 1 NEG_SEL = 0 (SAR_CTRL [11:9]) override to 0a Firmware DIFFERENTIAL_EN = 0 (SAR_CHANx_CONFIG[8]) VREF_SEL = 0 (SAR_CTRL[6:4]) SWITCH_DISABLE = 1 (SAR_CTRL[30]) SAR_MUX_SWITCH0[16] = 1 SAR_MUX_SWITCH0[17] = 1 SAR_MUX_SWITCH_HW_CTRL[16]= 0 SAR_MUX_SWITCH_HW_CTRL[17]= 0 NEG_SEL = 0 (SAR_CTRL [11:9]) override to 0a DSI SWITCH_DISABLE = 1 (SAR_CTRL[30]) VREF_SEL = 0 (SAR_CTRL[6:4]) Set DSI Signals: dsi_cfg_differential=1 dsi_swctrl[1]=1 dsi_swctrl[0]=1 SAR_MUX_SWITCH0[16] = 1 SAR_MUX_SWITCH0[17] = 1 SAR_MUX_SWITCH_HW_CTRL[16]= 1 SAR_MUX_SWITCH_HW_CTRL[17]= 1 NEG_SEL = 0 (SAR_CTRL [11:9]) override to 0a a. For temperature sensor, override NEL_SEG (SAR_CTRL [11:9]) to ‘0’. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 227 SAR ADC 19.4 Registers Name Offset Qty. Width Description SAR_CTRL 0x0000 1 32 Global configuration register Analog control register SAR_SAMPLE_CTRL 0x0004 1 32 Global configuration register Sample control register SAR_SAMPLE_TIME01 0x0010 1 32 Global configuration register Sample time specification ST0 and ST1 SAR_SAMPLE_TIME23 0x0014 1 32 Global configuration register Sample time specification ST2 and ST3 SAR_RANGE_THRES 0x0018 1 32 Global range detect threshold register SAR_RANGE_COND 0x001C 1 32 Global range detect mode register SAR_CHAN_EN 0x0020 1 32 Enable bits for the channels SAR_START_CTRL 0x0024 1 32 Start control register (firmware trigger) SAR_CHAN_CONFIG 0x0080 8 32 Channel configuration register SAR_CHAN_WORK 0x0100 8 32 Channel working data register SAR_CHAN_RESULT 0x0180 8 32 Channel result data register SAR_CHAN_WORK_VALID 0x0200 1 32 Channel working data register valid bits SAR_CHAN_RESULT_VALID 0x0204 1 32 Channel result data register valid bits SAR_STATUS 0x0208 1 32 Current status of internal SAR registers (for debug) SAR_AVG_STAT 0x020C 1 32 Current averaging status (for debug) SAR_INTR 0x0210 1 32 Interrupt request register SAR_INTR_SET 0x0214 1 32 Interrupt set request register SAR_INTR_MASK 0x0218 1 32 Interrupt mask register SAR_INTR_MASKED 0x021C 1 32 Interrupt masked request register: If the value is not zero, then the SAR interrupt signal to the NVIC is high. When read, this register reflects a bit-wise AND between the interrupt request and mask registers SAR_SATURATE_INTR 0x0220 1 32 Saturate interrupt request register SAR_SATURATE_INTR_SET 0x0224 1 32 Saturate interrupt set request register SAR_SATURATE_INTR_MASK 0x0228 1 32 Saturate interrupt mask register SAR_SATURATE_INTR_MASKED 0x022C 1 32 Saturate interrupt masked request register SAR_RANGE_INTR 0x0230 1 32 Range detect interrupt request register SAR_RANGE_INTR_SET 0x0234 1 32 Range detect interrupt set request register SAR_RANGE_INTR_MASK 0x0238 1 32 Range detect interrupt mask register SAR_RANGE_INTR_MASKED 0x023C 1 32 Range interrupt masked request register SASR_INTR_CAUSE 0x0240 1 32 Interrupt cause register SAR_INJ_CHAN_CONFIG 0x0280 1 32 Injection channel configuration register SAR_INJ_RESULT 0x0290 1 32 Injection channel result register SAR_MUX_SWITCH0 0x0300 1 32 SARMUX firmware switch controls SAR_MUX_SWITCH_CLEAR0 0x0304 1 32 SARMUX firmware switch control clear SAR_MUX_SWITCH_HW_CTRL 0x0340 1 32 SARMUX switch hardware control SAR_MUX_SWITCH_STATUS 0x0348 1 32 SARMUX switch status SAR_PUMP_CTRL 0x0380 1 32 Switch pump control 228 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 20. Low-Power Comparator PSoC® 4 devices have two low-power comparators. These comparators can perform fast analog signal comparison in all system power modes except the Stop mode. Refer to the Power Modes chapter on page 79 for details on various device power modes. The positive and negative inputs can be connected to dedicated GPIO pins or to AMUXBUS-A/AMUXBUS-B. The comparator output can be read by the CPU through a status register, used as an interrupt or wakeup source. 20.1 Features PSoC 4 comparators have the following features: ■ Configurable positive and negative inputs ■ Programmable power and speed ■ Ultra low-power mode support (<4 µA) ■ Optional 10-mV input hysteresis ■ Low-input offset voltage (<4 mV after trim) ■ Wakeup source in Deep-Sleep/Hibernate modes 20.2 Block Diagram Figure 20-1 shows the block diagram for the low-power comparator. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 229 Low-Power Comparator Figure 20-1. Low-Power Comparator Block Diagram AHB IF AHB MMIO Registers CLK_ahb Active Power Domain Comparator 0 intr_comp1 intr_comp2 Software‐set Interrupt 2 Software‐set Interrupt 1 I/0 pad P0.0 Intr_clr Falling, Rising, both Not part of Low power comparator It is in GPIO block Each GPIO connects to AMUXBUS_A/_B dsi_comp1_edge Edge Detector I/0 pad P0.1 comp_intr I/0 pad P0.2 Comparator 1 dsi_comp2_edge Edge Detector I/0 pad P0.3 20.3 AMUXBUS_B AMUXBUS_A Hibernate Power Domain How It Works connected to the comparator input through AMUXBUSA/AMUXBUS-B. The following sections describe the operation of the PSoC 4 low-power comparator, including input configuration, power and speed mode, output and interrupt configuration, hysteresis, wake up from low-power modes, comparator clock, and offset trim. 20.3.1 Input Configuration Inputs to the comparators can be as follows: From Figure 20-1, note that P0.0 and P0.1 connect to positive and negative inputs of Comparator 0; P0.2 and P0.3 connect to the inputs of Comparator 1. Also, note that the AMUXBUS nets do not have a direct connection to the comparator inputs. Therefore, the comparator connection is routed to the AMUXBUS nets through the corresponding input pin. These input pins will not be available for other purposes when using AMUXBUS for comparator connections. They should be left open in designs that use AMUXBUS for comparator input connection. Note that AMUXBUS connections are not available in Deep-Sleep and Hibernate modes. If Deep-Sleep or Hibernate operation is required, the low-power comparator must be connected to the dedicated pins. This restriction also includes routing of any internally-generated signal, which uses the AMUXBUS for the connection. See the I/O System chapter on page 53 for more details on connecting the GPIO to AMUXBUS A/B or setting up the GPIO for comparator input. ■ Both positive and negative inputs from dedicated input pins. ■ Both positive and negative inputs from any pin through AMUXBUS (not available in Deep-Sleep mode). ■ One input from an external pin and another input from an internally-generated signal. Both inputs can be connected to either positive or negative inputs of the comparator. The internally-generated signal is connected to the comparator input through the analog AMUXBUS. 20.3.2 Both positive and negative inputs from internallygenerated signals. The internally-generated signals are The output of Comparator0 and Comparator1 are available in the OUT1 bit [6] and OUT2 bit [14], respectively, in the ■ 230 Output and Interrupt Configuration PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Low-Power Comparator LPCOMP_CONFIG register (Table 20-1). The values available in the OUTx bits are the direct (unflopped) or instantaneous output from the comparators, which can be metastable. This means, accessing the comparator output may not be reliable. The output of each comparator is connected to a corresponding edge detector block. This block determines the edge that triggers the interrupt. The edge selection and interrupt enable is configured using the INTTYPE1 bits [5:4] and INTTYPE2 bits [13:12] in the LPCOMP_CONFIG register. Using the INTTYPEx bits, the interrupt type can be selected to disabled, rising edge, falling edge, or both edges, as described in Table 20-1. The comparator output is not available directly to the hardware or DSI routing. Only the edge detector block's output is available. The edge detector's output is an interrupt signal that is set on a rising/falling/either edge on the actual comparator's output. The signal (dsi_comp1_edge/ dsi_comp2_edge in Figure 20-1) should be cleared by the CPU by writing a ‘1’ to the LPCOMP_INTR bit[0] and bit[1] for COMP1 and COMP2 outputs, respectively. This action generates the intr_clr signal shown in Figure 20-1 for clearing the respective interrupts and edge detector output. The edge detector output can be connected to an interrupt for processing by the CPU or can be used routed to the UDBs for processing. During an edge event, the comparator will trigger an interrupt (intr_comp1/intr_comp2 signals in Figure 20-1). The interrupt request is registered in the COMP1 bit [0] and COMP2 bit [1] of the LPCOMP_INTR register for Comparator0 and Comparator1, respectively. Both Comparator0 and Comparator1 share a common interrupt (comp_intr signal in Figure 20-1), which is a logical OR of the two interrupts and mapped as the low-power comparator block's interrupt in the CPU NVIC. Refer to the Interrupts chapter on page 37 for details. If both the comparators are used in a design, the COMP1 and/or COMP2 bits of the LPCOMP_INTR register need to be read in the interrupt service routine to know which one triggered the interrupt. After the interrupt is processed, the interrupt should be cleared by writing a '1' to the COMP1 and COMP2 bits of the LPCOMP_INTR register in firmware. If the interrupt is not cleared, the next compare event will not trigger an interrupt and the CPU will not be able to process the event. In Active and Sleep modes, the dsi_comp1_edge/ dsi_comp2_edge outputs can be routed to UDB mapped interrupts for processing each comparator's trigger separately. However, the UDB/DSI routing is not available in Deep-Sleep and Hibernate modes. The LPCOMP interrupt (comp1_intr/comp2_intr) is synchronous with SYSCLK. The LPCOMP DSI output dsi_comp1_edge/dsi_comp2_edge is asynchronous. Clearing dsi_comp1_edge/dsi_comp2_edge and comp1_intr/comp2_intr are all synchronous. In Active and Sleep modes, dsi_comp1_edge/ dsi_comp2_edge can be routed to GPIO or other blocks through DSI routing in UDB with or without synchronization; there is an optional synchronizer on UDB DSI output. See the Universal Digital Blocks (UDB) chapter on page 131 for details on the DSI signal synchronization. In Deep-Sleep and Hibernate modes, this routing is unavailable because the UDBs are powered off. In addition, if the dsi_comp1_edge/dsi_comp2_edge is routed to the UDB for further processing, the timing depends on the user's algorithm and synchronizer choice. LPCOMP_INTR_SET register bits [1:0] can be used to assert an interrupt for software debugging. In Deep-Sleep and Hibernate mode, the wakeup interrupt controller (WIC) can be activated by a comparator edge event, which then wakes up the CPU. Thus, the LPCOMP has the capability to monitor a specified signal in low-power modes. Table 20-1. Output and Interrupt Configuration in LPCOMP_CONFIG Register Register[Bit_Pos] LPCOMP_CONFIG[6] LPCOMP_CONFIG[14] Bit_Name OUT1 OUT2 LPCOMP_CONFIG[5:4] INTTYPE1 Description Current/Instantaneous output value of Comparator0 Current/Instantaneous output value of Comparator1 Sets on which edge Comparator0 will trigger an IRQ 00: Disabled 01: Rising Edge 10: Falling Edge 11: Both rising and falling edges Sets on which edge Comparator1 will trigger an IRQ 00: Disabled LPCOMP_CONFIG[13:12] INTTYPE2 01: Rising Edge 10: Falling Edge LPCOMP_INTR[0] COMP1 LPCOMP_INTR[1] COMP2 LPCOMP_INTR_SET[0] LPCOMP_INTR_SET[1] COMP1 COMP2 11: Both rising and falling edges Comparator0 Interrupt: hardware sets this interrupt when Comparator0 triggers. Write a '1' to clear the interrupt Comparator2 Interrupt: hardware sets this interrupt when Comparator1 triggers. Write a '1' to clear the interrupt Write a '1' to trigger the software interrupt for Comparator0 Write a 1 to trigger the software interrupt for Comparator1 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 231 Low-Power Comparator 20.3.3 Power Mode and Speed Configuration The low-power comparators can operate in three power modes: ■ Fast ■ Slow ■ Ultra low-power The power or speed setting for Comparator0 is configured using MODE1 bits [1:0] in the LPCOMP_CONFIG register. The power or speed setting for Comparator1 is configured using MODE2 bits [9:8] in the same register. The power consumption and response time vary depending on the selected power mode; power consumption is highest in fast mode and lowest in ultra-low-power mode, response time is fastest in fast mode and slowest in ultra-low-power mode. Refer to the device datasheet for specifications for the response time and power consumption for various power settings. The comparators are enabled/disabled using ENABLE1 bit [7] and ENABLE2 bit [15] in the LPCOMP_CONFIG register, as described in Table 20-2. Note The output of the comparator may glitch when the power mode is changed while comparator is enabled. To avoid this, disable the comparator before changing the power mode. Table 20-2. Comparator Power Mode Selection Bits MODE1 and MODE2 Register[Bit_Pos] Bit_Name LPCOMP_CONFIG[1:0] MODE1 LPCOMP_CONFIG[9:8] MODE2 LPCOMP_CONFIG[7] ENABLE1 LPCOMP_CONFIG[15] ENABLE2 20.3.4 Description Compartor0 power mode selection 00: Slow operating mode (uses less power) 01: Fast operating mode (uses more power) 10: Ultra low-power operating mode (uses lowest possible power) Compartor1 power mode selection 00: Slow operating mode (uses less power) 01: Fast operating mode (uses more power) 10: Ultra low-power operating mode (uses lowest possible power) Comparator0 enable bit 0: Disables Comparator0 1: Enables Comparator0 Comparator1 enable bit 0: Disables Comparator1 1: Enables Comparator1 Hysteresis For applications that compare signals close to each other and slow changing signals, hysteresis helps to avoid oscillations at the comparator output when the signals are noisy. For such applications, a fixed 10-mV hysteresis may be enabled in the comparator block. The 10-mV hysteresis level is enabled/disabled by using the HYST1 bit [2] and HYST2 bit [10] in the LPCOMP_CONFIG register, as described in Table 20-3. Table 20-3. Hysteresis Control Bits HYST1 and HYST2 Register[Bit_Pos] LPCOMP_CONFIG[2] Bit_Name HYST1 Description Enable/Disable 10 mV hysteresis to Comparator0 - 0: Enable Hysteresis - 1: Disable Hysteresis Enable/Disable 10 mV hysteresis to Comparator1 LPCOMP_CONFIG[10] HYST2 - 0: Enable Hysteresis - 1: Disable Hysteresis 232 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Low-Power Comparator 20.3.5 Wakeup from Low-Power Modes The comparator is operational in the device’s low-power modes, including Sleep, Deep-Sleep, and Hibernate modes. The comparator output interrupt can wake the device from Sleep, Deep-Sleep, and Hibernate modes. No special setting is needed, other than enabling the comparators in the LPCOMP_CONFIG register. The features that are not available during the Deep-Sleep and Hibernate modes include: ■ Comparisons involving AMUXBUS connections ■ Routing comparator output through DSI In the Deep-Sleep or Hibernate power mode, a compare event on either Comparator0 or Comparator1 output will generate a wakeup interrupt. This behavior is unrelated to the settings of INTTYPE bit in the LPCOMP_CONFIG register. 20.3.6 Comparator Clock The comparator uses the system main clock SYSCLK as the clock for interrupt synchronization. 20.3.7 Offset Trim The comparator offset is trimmed at the factory to less than 4.0 mV. The trim is a two-step process, trimmed first at common mode voltage equal to 0.1 V, then at common mode voltage equal to VDD–0.1 V. Offset voltage is guaranteed to be less than 10.0 mV over the input voltage range of 0.1 V to VDD–0.1 V. For normal operation, further adjustment of trim values is not recommended. If a tighter trim is required at a specific input common mode voltage, a trim may be performed at the desired input common mode voltage. The comparator offset trim is performed using the LPCOMP_TRIM1/2/3/4 registers. LPCOMP_TRIM1 and LPCOMP_TRIM2 are used to trim comparator 0. LPCOMP_TRIM3 and LPCOMP_TRIM4 are used to trim comparator 1. The bit fields that change the trim values are TRIMA bits [4:0] in LPCOMP_TRIM1 and LPCOMP_TRIM3, and TRIMB bits [3:0] in LPCOMP_TRIM2 and LPCOMP_TRIM4. TRIMA bits are used to coarse tune the offset; TRIMB bits are used to fine tune. The use of TRIMB bits for offset correction is restricted to slow mode of comparator operation. Any standard comparator offset trim procedure can be used to perform the trimming. The following method can be used to improve the offset at a given reference/common mode voltage input. 1. Short the comparator inputs externally and connect the voltage reference, Vref, to the input. 2. Set up the comparator for comparison, turn off hysteresis, and check the output. 3. If the output is high, the offset is positive. Otherwise, the offset is negative. Follow these steps to tune the offset: a. Tune the TRIMA bits[4:0] until the output switches direction. TRIMA bits[3:0] control the amount of offset and TRIMA bit[4] controls the polarity of offset ('1' indicates positive offset and '0' indicates negative offset). b. When the tuning of TRIMA bits is complete, tune the TRIMB bits[3:0] until the output switches direction again. The TRIMB bit tuning is valid only for slow mode of comparator operation. TRIMB bit[3] controls the polarity of offset. Increasing TRIMB bits [2:0] reduces the offset. c. After completing step 3-b, the values available in the TRIMA and TRIMB bits will be the closest possible trim value for that particular Vref. 20.4 Register Summary Table 20-4. Low-Power Comparator Register Summary Register Function LPCOMP_ID Includes the information of LPCOMP controller ID and revision number LPCOMP_CONFIG LPCOMP configuration register LPCOMP_INTR LPCOMP interrupt register LPCOMP_INTR_SET LPCOMP interrupt set register LPCOMP_TRIM1 Trim fields for comparator 0 LPCOMP_TRIM2 Trim fields for comparator 0 LPCOMP_TRIM3 Trim fields for comparator 1 LPCOMP_TRIM4 Trim fields for comparator 1 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 233 Low-Power Comparator 234 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 21. Continuous Time Block mini (CTBm) The Continuous Time Block mini (CTBm) provides discrete operational amplifiers (opamps) inside the chip for use in continuous-time signal chains. Each CTBm block includes a switch matrix for input/output configuration, two identical opamps, which are also configurable as two comparators, a charge pump inside each opamp, and a digital interface for comparator output routing, switch controls, and interrupts. The PSoC 4100/4200 family has one CTBm block - two discrete opamps. 21.1 Features The opamps in the PSoC 4 CTBm block have the following features: ■ Discrete, high-performance, and highly configurable on-chip amplifiers ■ Programmable power, bandwidth, compensation, and output drive strength ■ 1-mA or 10-mA selectable output current drive capability ■ 6-MHz gain bandwidth for 20-pF load ■ Less than 1-mV offset with trim ■ Support for opamp follower mode ■ Comparator mode with optional 10-mV hysteresis ■ Buffer/pre-amplifier for SAR inputs ■ Rail-to-rail within 0.2 V of VSS or VDDA for 1-mA load ■ Rail-to-rail within 0.5 V of VSS or VDDA for 10-mA load ■ Slew rate 4 V/µs for 50-pF load 21.2 Block Diagram Figure 21-1 shows the block diagram for the CTBm block available in PSoC 4 devices. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 235 Continuous Time Block mini (CTBm) Figure 21-1. CTBm Block Diagram P1.2 CTBM_dsi_comp0 MUX 10X P1.0 Clk_comp P1.6 Interrupt Request Edge Detector AMUXBUSA Sync OPAMP 0 CTBM_comp0_out P1.1 1X SW1 sarbus0 P1.3 CTBM_dsi_comp1 MUX 10X P1.5 Clk_comp P1.7 Interrupt Request Edge Detector AMUXBUSB Sync OPAMP 1 CTBM_comp1_out P1.4 1X SW2 sarbus0 sarbus1 SW3 Switch: CTBm Regsiter control Swtich: CTBm Regsiter + SARADC register+ DSI control Note: 10X or 1X output driver cannot be on at the same time. 21.3 How It Works After enabling the opamps and charge pumps, follow these steps to set up the amplifier: As the block diagram shows, CTBm has two identical opamps and a switch routing matrix. Each opamp has one input and three output stages, all of which share a common input stage, as shown in Figure 21-1; only one of them can be selected at a time. The output stage can be operated as Class-A(1X), Class-AB(10X), or comparator. The other configurable features are power and speed, compensation, and switch routing control. To use the CTBm block, the first step is to set up external components (such as resistors), if required. Then, enable the block by setting the CTB_CTRL [31] bit. To have almost rail-to-rail input range and minimal distortion common mode input, there is one charge pump inside each opamp. The charge pump can be enabled by setting the CTBM_OA_RES0_CTRL [11] bit for opamp0 and CTBM_OA_RES1_CTRL [11] bit for opamp1. 236 1. Configure power mode 2. Configure output strength 3. Configure compensation 4. Configure input switch 5. Configure output switch, especially when opamp output needs to be connected to SAR ADC Follow these steps to set up a comparator: 1. Configure the power mode 2. Configure the input switch 3. Configure the comparator output circuitry, as required interrupt generation, DSI output, and so on 4. Configure hysteresis and enable the comparator PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Continuous Time Block mini (CTBm) 21.3.1 Power Mode Configuration The opamp can operate in three power modes – low, medium, and high. CTBm adjusts the power consumed by adjusting the reference currents coming into the opamp. Power modes are configured using the PWR_MODE bits [1:0] in CTBM_OA_RESx_CTRL. The slew rate and gain 21.3.2 bandwidth are maximum in high-power mode and minimum in low-power mode. Note that power mode configuration also affects the maximum output drive capability (IOUT) in 1X mode. See Table 21-1 for details. See the device datasheet for gain bandwidth, slew rate, and IOUT specifications in various power modes. Output Strength Configuration The output driver of each opamp can be configured to internal driver (Class A/1X driver) or external driver (Class AB/10X driver). 1X and 10X drivers are mutually exclusive – they cannot be active at the same time. 1X output driver is suited to drive smaller on-chip capacitive and resistive loads at higher speeds. The 10X output driver is useful for driving large off-chip capacitive and resistive loads. The 1X driver output is routed to sarbus 0/1 and 10X driver output is routed to an external pin. Each driver mode has a low, medium, or high power mode, as shown in Table 21-1. Table 21-1. Output Driver versus Power Mode Power Mode IOUT Drive Capability External Driver (10X) Internal Driver (1X) 00 (disable) Off Off CTBM_OA_RESx_CTRL[1:0] 01 (low) 10 (medium) 10 mA 10 mA 100 µA 400 µA 11 (high) 10 mA 1 mA The CTBM_OA_RESx_CTRL[2] bit is used to select between the 10X and 1X output capability (0: 1X, 1: 10X). If the output of the opamp is connected to the SAR ADC, it is recommended to choose the 1X output driver. If the output of the opamp is connected to an external pin, then, choose the 10X output driver. In special instances, to connect the output to an external pin with 1X output driver or an internal load (for example, SAR ADC) with 10X output driver, set CTBM_OAx_SW [21] to ‘1’. However, Cypress does not guarantee performance in this case. Table 21-2 summarizes the bits used to configure the opamp output drive strength and power modes. Table 21-2. Output Strength and Power Mode Configuration in CTBM Registers Register[Bit_Pos] Bit_Name Description CTB_CTRL[31] ENABLE CTBM power mode selection 0: CTBM is disabled 1: CTBM is enabled CTBM_OA_RES0_CTRL [11] OA0_PUMP_EN Opamp0 pump enable bit 0: Opamp0 pump is disabled 1: Opamp0 pump is enabled CTBM_OA_RES1_CTRL [11] OA1_PUMP_EN Opamp1 pump enable bit 0: Opamp1 pump is disabled 1: Opamp1 pump is enabled PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 237 Continuous Time Block mini (CTBm) Table 21-2. Output Strength and Power Mode Configuration in CTBM Registers Register[Bit_Pos] Bit_Name Description OA0_PWR_MODE Opamp0 power mode select bits 00: Opamp0 is OFF 01: Opamp0 is in low power mode 10: Opamp0 is in medium power mode 11: Opamp0 is in high power mode CTBM_OA_RES1_CTRL [1:0] OA1_PWR_MODE Opamp1 power mode select bits 00: Opamp1 is OFF 01: Opamp1 is in low power mode 10: Opamp1 is in medium power mode 11: Opamp1 is in high power mode CTBM_OA_RES0_CTRL [2] OA0_DRIVE_STR_SEL Opamp0 output drive strength select bits 0: Opamp0 output drive strength is 1X 1: Opamp0 output drive strength is 10X CTBM_OA_RES1_CTRL [2] OA1_DRIVE_STR_SEL Opamp1 output drive strength select bits 0: Opamp1 output drive strength is 1X 1: Opamp1 output drive strength is 10X CTBM_OA_RES0_CTRL [1:0] 21.3.3 Compensation Each opamp also has a programmable compensation capacitor block, which allows optimizing the stability of the opamp performance based on output load. The compensation of each opamp is controlled by the respective CTBM_OAx_COMP_TRIM register, as explained in Table 21-3. Note that all the GBW slew rate specifications in the device datasheet are applied for all compensation trims. Table 21-3. Opampx (Opamp0 or Opamp1) Compensation Bits in CTMB Register[Bit_Pos] Bit_Name Description Opampx compensation trim bits 00: No compensation CTBM_OAx_COMP_TRIM[1:0] OAx_COMP_TRIM 01: Minimum compensation, high speed, and low stability 10: Medium compensation, balanced speed, and stability 11: Maximum compensation, low speed, and high stability 21.3.4 Switch Control The CTBm has many switches to configure the opamp input and output. Most of them are controlled by configuring CTBm registers (CTBM_OA0_SW, CTBM_OA1_SW), except three switches, which are used to connect the output of opamps to SAR ADC through sarbus0 and sarbus1. They must be controlled by SAR ADC registers, CTBm registers, and DSI signals. Switches can be closed by setting the corresponding bit in register CTBM_OAx_SW; clearing them will cause the corresponding switches to open. Writing ‘1’ to CTBM_OAx_SW_CLEAR can clear the corresponding bit in CTBM_OAx_SW. See the PSoC 4100/4200 Family: PSoC 4 Registers TRM for details on the switches and the connections they enable. 21.3.4.1 Input Configuration Positive and negative input to the operational amplifier can be selected from several options through analog switches. These switches serve to connect the opamp inputs from the external pins or AMUX buses, or to form a local feedback loop (for buffer function). Each opamp has a switch connecting to one of the two AMUXBUS line: Opamp0 connects to AMUXBUS-A and Opamp1 connects to AMUXBUS-B. Note Only one switch should be closed for the positive and negative input paths; otherwise, different input source may short together. 238 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Continuous Time Block mini (CTBm) ■ Positive input: Both opamp0 and opamp1 have three positive input options through analog switches: two external pins and one AMUXBUS line. See Table 21-4 for details. Table 21-4. Positive Input Selection Positive Input Opamp0 Opamp1 ■ AMUXBUSA P1.0 Switch Control Bit CTBM_OA0_SW [0] CTBM_OA0_SW [2] Description 0: open 1: close switch 0: open 1: close switch P1.6 CTBM_OA0_SW [3] 0: open 1: close switch AMUXBUSB P1. 5 P1.7 CTBM_OA1_SW [0] CTBM_OA1_SW [1] CTBM_OA1_SW [4] 0: open 1: close switch 0: open 1: close switch 0: open 1: close switch Negative input: Both opamp0 and opamp1 have two negative input options through analog switches: one external pin or output feedback, which is controlled by the CTBM_OAx_SW register. Table 21-5 shows the control bits. Table 21-5. Negative Input Selection Opamp0 Opamp1 Negative Input P1.1 Opamp0 output feedback through 1X output driver P1.4 Opamp1 output feedback through 1X output driver Switch Control Bit CTBM_OA0_SW [8] CTBM_OA0_SW [14] CTBM_OA1_SW [8] CTBM_OA1_SW [14] PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Description 0: open 1: close switch 0: open 1: close switch 0: open 1: close switch 0: open 1: close switch 239 Continuous Time Block mini (CTBm) 21.3.4.2 Output Configuration Each opamp’s output is connected directly to a fixed pin; no additional setup is needed. Optionally, it can be connected to sarbus0 or sarbus1 through three switches (SW1/2/3). The opamp0 output can be connected to sarbus0 and opamp1 can be connected to sarbus0 or sarbus1. sarbus0 and sarbus1 are intended to connect opamp output to the SAR ADC input mux. The three output routing switches to sarbus are controlled by the CTBm register, SAR ADC register, and DSI signals together; the other switches can be controlled only by CTBm register. The following truth tables (Table 21-6, Table 21-7, and Table 21-8) show the control logic of the three switches. PORT_ADDR, PIN_ADDR, and DIFFERENTIAL_EN are from SAR_CHANx_CONFIG [6:4], SAR_CHANx_CONFIG [2:0], and SAR_CHANx_CONFIG [2:0], respectively. Either PORT_ADDR =0 or PIN_ADDR = 0 will set SW[n]=0. CTBM_SW_HW_CTRL bit [2] or [3] should be set when using the SAR register or a DSI signal to control switches. CTBM_OAx_SW[18]/[19] can mask the other control bits – if CTBM_OAx_SW[18]/[19] = 0, SW[n] = 0. Register CTBM__SW_STATUS [30:28] gives the current switch status of SW1/2/3. Table 21-6. Truth Table of SW1 Control Logic PORT_ADDR PIN_ADDR CTBM_SW_HW_CTRL[2] dsi_out[2] CTBM_OA0_SW[18] SW1 X X X 0 0 X 0 1 0 1 0 0 X 1 0 1 0 X X X 1 1 1 X X 0 X 1 1 1 2 X X 1 1 X Table 21-7. Truth Table of SW2 Control Logic DIFFERENTIAL_ PORT_ADDR EN PIN_ADDR CTBM_SW_HW_CTRL[3 ] dsi_out[3] CTBM_OA0_SW[18] SW2 X X X 0 0 X X X X 0 1 0 1 0 X 0 X 1 0 1 0 1 X X X 0 1 0 X X X 0 X 1 1 X X X X X 1 1 0 1 3 X X 1 1 CTBM_OA0_SW[18] SW3 Table 21-8. Truth Table of SW3 Control Logic DIFFERENTIAL_ EN PORT_ADDR PIN_ADDR CTBM_SW_HW_CTRL[3 ] dsi_out[3] X X X X X 0 0 X X 0 1 0 1 0 X 0 X 1 0 1 0 0 X X X 0 1 0 X X X 0 X 1 1 X X X X X 1 1 1 1 2 X X 1 1 240 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Continuous Time Block mini (CTBm) 21.3.4.3 Comparator Mode Each opamp can be configured as a comparator by setting the respective CTBM_OA_RESx_CTRL[4] bit. Note that enabling the comparator completely disables the compensation capacitors and shuts down the Class A (1X) and Class AB (10X) output drivers. The comparator has the following features: ■ Optional 10-mV input hysteresis ■ Configurable power/speed ■ Optional DSI output synchronization ■ Offset trimmed to less than 1 mV ■ Configurable edge detection (rising/falling/both/disable) 21.3.4.4 Comparator Configuration also have three power modes: low, medium, and high, controlled by setting CTBM_OA_RESx_CTRL [1:0]. Power modes differ in response time and power consumption; power consumption is maximum in fast mode and minimum in ultra-low-power mode. Exact specifications for power consumption and response time are provided in the datasheet. The comparator output is routed to the DSI with optional synchronization. The synchronization with comparator clock (system AHB clock) can be configured in CTBM_OA_RESx_CTRL[6]. The output state of comparator0 and comparator1 are stored in CTBM_COMP_STAT[0] and CTBM_COMP_STAT[16], respectively. Table 21-9 summarizes various bits used to configure the comparator mode in the CTBM block. The hysteresis of 10 mV ±5 percent can be enabled in one direction (low to high). Input hysteresis can be enabled by setting CTBM_OA_RESx_CTRL[5]. The two comparators Table 21-9. Comparator Mode and Configuration Register Settings Register[Bit_Pos] Bit_Name Description Opampx comparator enable bit CTBM_OA_RESyx_CTRL[4] OAx_COMP_EN 0: Comparator mode is disabled in opampx 1: Comparator mode is enabled in opampx Opampx Comparator hysteresis enable bit CTBM_OA_RESx_CTRL[5] OAx_HYST_EN 0: Hysteresis is disabled in opampx 1: Hysteresis is enabled in opampx CTBM_OA_RESx_CTRL[6] OAx_BYPASS_DSI_SYNC Opampx bypass comparator output synchronization for DSI (trigger) output 0: Synchronize (level or pulse) 1: Bypass Opampx comparator DSI (trigger) output synchronization level CTBM_OA_RESx_CTRL[7] OAx_ DSI_LEVEL 0: Pulse 1: Level PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 241 Continuous Time Block mini (CTBm) 21.3.4.5 Comparator Interrupt The comparator output is connected to an edge detector block, which is used to detect the edge (disable/rising/falling/ both) that generates interrupt. It can be configured by the CTBM_OA_RESx_CTRL[9:8] bits. Each comparator has a separate IRQ. CTBM_INTR [0] is for comparator0 IRQ, CTBM_INTR [1] is for comparator1 IRQ. Each interrupt has an interrupt mask bit in the CTBM_INTR_MASK register. By setting the interrupt mask low, the corresponding interrupt source is ignored. The CTBm comparator interrupt to the NVIC will be raised if logic AND of the interrupt flags in CTBM_INTR registers and the 21.4 corresponding interrupt masks in CTBM_INTR_MASK register is 1. Writing a ‘1’ to the CTBM_INTR bit [1:0] can clear corresponding interrupt. For firmware convenience, the intersection (logic AND) of the interrupt flags and the interrupt masks is also made available in the CTBM_INTR_MASKED register. For verification and debug purposes, a set bit is provided for each interrupt in CTBM_INTR_SET register. This allows the firmware to raise the interrupt without a real comparator switch event. Register Summary Table 21-10. Register Summary Name Description CTBM_CTRL Global CTBm block enable CTBM_OA_RES0_CTRL Opamp0 control register CTBM_OA_RES1_CTRL Opamp1 control register CTBM_COMP_STAT Comparator status CTBM_INTR Interrupt request register CTBM_INTR_SET Interrupt request set register CTBM_INTR_MASK Interrupt request mask CTBM_INTR_MASKED Interrupt request masked CTBM_OA0_SW Opamp0 switch control CTBM_OA0_SW_CLEAR Opamp0 switch control clear CTBM_OA1_SW Opamp1 switch control CTBM_OA1_SW_CLEAR Opamp1 switch control clear CTBM_SW_HW_CTRL CTBm hardware control enable CTBM_SW_STATUS CTBm bus switch control status CTBM_OA0_OFFSET_TRIM Opamp0 trim control CTBM_OA0_SLOPE_OFFSET_TRIM Opamp0 trim control CTBM_OA0_COMP_TRIM Opamp0 trim control CTBM_OA1_OFFSET_TRIM Opamp1 trim control CTBM_OA1_SLOPE_OFFSET_TRIM Opamp1 trim control CTBM_OA1_COMP_TRIM Opamp1 trim control 242 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 22. LCD Direct Drive The PSoC® 4 Liquid Crystal Display (LCD) drive system is a highly configurable peripheral that allows the PSoC device to directly drive STN and TN segment LCDs. 22.1 Features The PSoC 4 LCD segment drive block has the following features: ■ Supports up to 32 segments and four commons ■ Supports Type A (standard) and Type B (low-power) drive waveforms ■ Any GPIO can be configured as a common or segment ■ Supports five drive methods: ❐ Digital correlation ❐ PWM at 1/2 bias ❐ PWM at 1/3 bias ❐ PWM at 1/4 bias ❐ PWM at 1/5 bias ■ Ability to drive 3-V displays from 1.8 V VDD in Digital Correlation mode ■ Operates in active, sleep, and deep-sleep modes ■ Digital contrast control 22.2 LCD Segment Drive Overview A segmented LCD panel has the liquid crystal material between two sets of electrodes and various polarization and reflector layers. The two electrodes of an individual segment are called commons (COM) or backplanes and segment electrodes (SEG). From an electrical perspective, an LCD segment can be considered as a capacitive load; the COM/SEG electrodes can be considered as the rows and columns in a matrix of segments. The opacity of an LCD segment is controlled by varying the root-mean-square (RMS) voltage across the corresponding COM/SEG pair. The following terms/voltages are used in this chapter to describe LCD drive: ■ VRMSOFF: The voltage that the LCD driver can realize on segments that are intended to be off. ■ VRMSON: The voltage that the LCD driver can realize on segments that are intended to be on. ■ Discrimination Ratio (D): The ratio of VRMSON and VRMSOFF that the LCD driver can realize. This depends on the type of waveforms applied to the LCD panel. Higher discrimination ratio results in higher contrast. Liquid crystal material does not tolerate long term exposure to DC voltage. Therefore, any waveforms applied to the panel must produce a 0-V DC component on every segment (on or off). Typically, LCD drivers apply waveforms to the COM and SEG electrodes that are generated by switching between multiple voltages. The following terms are used to define these waveforms: ■ Duty: A driver is said to operate in 1/M duty when it drives 'M' number of COM electrodes. Each COM electrode is effectively driven 1/M of the time. ■ Bias: A driver is said to use 1/B bias when its waveforms use voltage steps of (1/B) × VDRV. VDRV is the highest drive voltage in the system (equals to VDD in PSoC 4). PSoC 4 supports 1/2, 1/3, 1/4, and 1/5 biases in PWM drive modes. ■ Frame: A frame is the length of time required to drive all the segments. During a frame, the driver cycles through the commons in sequence. All segments receive 0-V DC (but non-zero RMS voltage) when measured over the entire frame. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 243 LCD Direct Drive PSoC 4 supports two different types of drive waveforms in all drive modes. These are: ■ Type-A Waveform: In this type of waveform, the driver structures a frame into M sub-frames. 'M' is the number of COM electrodes. Each COM is addressed only once during a frame. For example, COM[i] is addressed in sub-frame i. ■ Type-B Waveform: The driver structures a frame into 2M sub-frames. The two sub-frames are inverses of each other. Each COM is addressed twice during a frame. For example, COM[i] is addressed in sub-frames i and M+i. Type-B waveforms are slightly more power efficient because it contains fewer transitions per frame. 22.2.1 Drive Modes PSoC 4 supports the following drive modes. ■ PWM drive at 1/2 bias ■ PWM drive at 1/3 bias ■ PWM drive at 1/4 bias with high-frequency clock input ■ PWM drive at 1/5 bias with high-frequency clock input ■ Digital correlation 22.2.1.1 PWM Drive In PWM drive mode, multi-voltage drive signals are generated using a PWM output signal together with the intrinsic resistance and capacitance of the LCD. Figure 22-1 illustrates this. Figure 22-1. PWM Drive (at 1/3 Bias) GPIO Output Impedance ITO Panel Resistance LCD Segment Capacitance PWM Generator COM VPWM VLCD PWM Generator SEG VPWM Vddd 0 VLCD t Vddd 2/3 Vddd 1/3 Vddd 0 t The output waveform of the drive electronics is a PWM waveform. With the Indium Tin Oxide (ITO) panel resistance and the segment capacitance to filter the PWM, the voltage across the LCD segment is an analog voltage, as shown in Figure 22-1. This figure illustrates the generation of a 1/3 bias waveform (four commons and voltage steps of VDD/3). The PWM is derived from either ILO (32 kHz, low-speed operation) or IMO (high-speed operation). The generated analog voltage typically runs at very low frequency (~ 50 Hz) for segment LCD driving. Figure 22-2 and Figure 22-3 illustrate the Type A and Type B waveforms for COM and SEG electrodes for 1/2 bias and 1/4 duty. Only COM0/COM1 and SEG0/SEG1 are drawn for demonstration purpose. Similarly, Figure 22-4 and Figure 22-5 illustrate the Type A and Type B waveforms for COM and SEG electrodes for 1/3 bias and 1/4 duty. 244 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D LCD Direct Drive Figure 22-2. PWM1/2 Type-A Waveform Example One ‘Frame’ of Type A Waveform (addresses all segments once) VDD COM0 1/2 VDD 0 VDD COM1 1/2 VDD 0 VDD SEG0 1/2 VDD 0 VDD SEG1 1/2 VDD 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.661 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.433 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.661 VDD 0 -VDD VDD COM1 -SEG1 Segment Off: VRMS = 0.433 VDD 0 -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.661/0.433 = 1.527 Segment is Off PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 245 LCD Direct Drive Figure 22-3. PWM1/2 Type-B Waveform Example One ‘Frame’ of Type B Waveform (addresses all segments twice) VDD COM0 1/2 VDD 0 VDD COM1 1/2 VDD 0 VDD SEG0 1/2 VDD 0 VDD SEG1 1/2 VDD 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.661 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.433 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.661 VDD 0 -VDD VDD COM1 -SEG1 Segment Off: VRMS = 0.433 VDD 0 -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.661/0.433 = 1.527 Segment is Off 246 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D LCD Direct Drive Figure 22-4. PWM1/3 Type-A Waveform Example One ‘Frame’ of Type A Waveform (addresses all segments once) VDD COM0 2/3 VDD 1/3 VDD 0 VDD COM1 2/3 VDD 1/3 VDD 0 VDD SEG0 2/3 VDD 1/3 VDD 0 VDD SEG1 2/3 VDD 1/3 VDD 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.577 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.333 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.577 VDD 0 -VDD VDD COM1 -SEG1 0 Segment Off: VRMS = 0.333 VDD -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.577/0.333 = 1.732 Segment is Off PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 247 LCD Direct Drive Figure 22-5. PWM1/3 Type-B Waveform Example One ‘Frame’ of Type B Waveform (addresses all segments twice) VDD COM0 2/3 VDD 1/3 VDD 0 VDD COM1 2/3 VDD 1/3 VDD 0 VDD SEG0 2/3 VDD 1/3 VDD 0 VDD SEG1 2/3 VDD 1/3 VDD 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.577 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.333 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.577 VDD 0 -VDD VDD COM1 -SEG1 Segment Off: VRMS = 0.333 VDD 0 -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.577/0.333 = 1.732 Segment is Off 248 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D LCD Direct Drive The effective RMS voltage for ON and OFF segments can be calculated easily using these equations: V RMS OFF = 2 V DRV 2-------------------------------------------------- B – 2 + 2 M – 1 -x ------------ B 2M V RMS ON = Equation 22-1 2 2B + 2 M – 1 V DRV --------------------------------------x -------------- B 2M Equation 22-2 Where B is the bias and M is the duty (number of COMs). For example, if the number of COMs is four, the resulting discrimination ratios (D) for 1/2 and 1/3 biases are 1.528 and 1.732, respectively. 1/3 bias offers better discrimination ratio in two and three COM drives also. Therefore, 1/3 bias offers better contrast than 1/2 bias and is recommended for most applications. 1/4 and 1/5 biases are available only in high-speed operation of the LCD. They offer better discrimination ratio especially when used with high COM designs. When the low-speed operation of LCD is used, the PWM signal is derived from the 32-kHz ILO. To drive a low-capacitance display with acceptable ripple and rise/fall times using a 32-kHz PWM, additional external series resistances of 100 k-1 M should be used. External resistors are not required for PWM frequencies greater than ~1 MHz. The ideal PWM frequency depends on the capacitance of the display and the internal ITO resistance of the ITO routing traces. The 1/2 bias mode has the advantage that PWM is only required on the COM signals; the SEG signals use only logic levels, as shown in Figure 22-2 and Figure 22-3. 22.2.1.2 Digital Correlation The digital correlation mode, instead of generating bias voltages between the rails, takes advantage of the characteristic of LCDs that the contrast of LCD segments is determined by the RMS voltage across the segments. In this approach, the correlation coefficient between any given pair of COM and SEG signals determines whether the corresponding LCD segment is on or off. Thus, by doubling the base drive frequency of the COM signals in their inactive sub-frame intervals, the phase relationship of the COM and SEG drive signals can be varied to turn segments on and off. This is different from varying the DC levels of the signals as in the PWM drive approach. Figure 22-8 and Figure 22-9 are example waveforms that illustrate the principles of operation. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 249 LCD Direct Drive Figure 22-6. Digital Correlation Type-A Waveform One ‘Frame’ of Type A Waveform (addresses all segments once) VDD COM0 0 VDD COM1 0 VDD SEG0 0 VDD SEG1 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.791 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.612 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.791 VDD 0 -VDD VDD COM1 -SEG1 Segment Off: VRMS = 0.612 VDD 0 -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.791/0.612 = 1.291 Segment is Off 250 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D LCD Direct Drive Figure 22-7. Digital Correlation Type-B Waveform One ‘Frame’ of Type B Waveform (addresses all segments twice) VDD COM0 0 VDD COM1 0 VDD SEG0 0 VDD SEG1 0 t0 t1 t2 t3 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments (VDC = 0) VDD COM0 -SEG0 Segment On: VRMS = 0.791 VDD 0 -VDD VDD COM0 -SEG1 0 Segment Off: VRMS = 0.612 VDD -VDD VDD COM1 -SEG0 Segment On: VRMS = 0.791 VDD 0 -VDD VDD COM1 -SEG1 Segment Off: VRMS = 0.612 VDD 0 -VDD t0 t1 t2 Segment is On t3 Discrimination ratio: D = 0.791/0.612 = 1.291 Segment is Off PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 251 LCD Direct Drive The RMS voltage applied to on and off segments can be calculated as follows: V RMS OFF = V M – 1 -------------------x V DD 2M 2 + M – 1 ----------------------------x V DD 2M RMS ON = Where B is the bias and M is the duty (number of COMs). This leads to a discrimination ratio (D) of 1.291 for four COMs. Digital correlation mode also has the ability to drive 3-V displays from 1.8 V VDD. 22.2.2 Recommended Usage of Drive Modes The PWM drive mode has higher discrimination ratios compared to the digital correlation mode, as explained in 22.2.1.1 PWM Drive and 22.2.1.2 Digital Correlation. Therefore, the contrast in digital correlation method is lower than PWM method but digital correlation has lower power consumption because its waveforms toggle at low frequencies. The digital correlation mode creates reduced, but acceptable contrast on TN displays, but no noticeable difference in contrast or viewing angle on higher contrast STN displays. Because each mode has strengths and weaknesses, recommended usage is as follows. Table 22-1. Recommended Usage of Drive Modes Display Type Deep-Sleep Mode Sleep/Active Mode Four COM TN Glass Digital correlation Four COM STN Glass Digital correlation Eight and Sixteen COM, STN 22.2.3 PWM 1/3 bias Not supported Notes Firmware must switch between LCD drive modes before going to deep sleep or waking up. No contrast advantage for PWM drive with STN glass. PWM 1/4 bias and Supported only in the high-speed LCD mode. The low-speed clock is not 1/5 bias fast enough to make the PWM work at high multiplex ratios. Digital Contrast Control In all drive modes, digital contrast control can be used to change the contrast level of the segments. This method reduces contrast by reducing the driving time of the segments. This is done by inserting a ‘Dead-Time’ interval after each frame. During dead time, all COM and SEG signals are driven to a logic 1 state. The dead time can be controlled in fine resolution. Figure 22-8 illustrates the dead-time contrast control method for 1/3 bias and 1/4 duty implementation. Figure 22-8. Dead-Time’ Contrast Control Two Frames of of Type A Waveform with Dead-time (Example for 1/4th Duty and 1/3rd bias) VDD COM0 2/3 VDD 1/3 VDD 0 VDD COM1 2/3 VDD 1/3 VDD 0 VDD SEG0 2/3 VDD 1/3 VDD 0 VDD SEG1 2/3 VDD 1/3 VDD 0 t0 t1 t2 t3 dt t0 t1 t2 t3 dt Dead-Time 252 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D LCD Direct Drive 22.3 Block Diagram Figure 22-9. Block Diagram of LCD Direct Drive System High Frequency Clock AHB High Speed (HS) LCD Master Generator HS COM Signals HS SEG Signals AHB interface Active Power Domain DeepSleep Power Domain COM Signals LCD com[0] HS Sub Frame Data LCD seg[0] SEG Signals Multiplexer Low Speed (LS) LCD Master Generator LCD com[1] Sub Frame Data LS COM Signals Low Frequency Clock (32Khz) HSIO Matrix LS SEG Signals LCD seg[1] HSIO Matrix LCD Pin Logic LS Sub Frame Data LCD Mode Select (HS/LS) Config&Control Registers Display Data [0] Display Display Data Data Registers LCD com[n] Display Data [1] LCD seg[n] HSIO Matrix Display Data [n] 22.3.1 How it Works The LCD controller block contains two generators; one with a high-speed clock source HFCLK and the other with a lowspeed clock source (32 kHz) derived from the ILO. These are called high-speed LCD master generator and low-speed LCD master generator, respectively. Both the generators support PWM and digital correlation drive modes. PWM drive mode with low-speed generator requires external resistors, as explained in PWM Drive on page 244. The multiplexer selects one of these two generator outputs to drive LCD, as configured by the firmware. The LCD pin logic block routes the COM and SEG outputs from the generators to the corresponding I/O matrices. Any GPIO can be used as either COM or SEG. This configurable pin assignment for COM or SEG is implemented in GPIO and I/O matrix; see High-Speed I/O Matrix on page 57. These two generators share the same configuration registers. These memory mapped I/O registers are connected to the system bus (AHB) using an AHB interface. The LCD controller works in three device power modes: active, sleep, and deep-sleep. High-speed operation is supported in active and sleep modes. Low-speed operation is supported in active, sleep, and deep-sleep modes. The LCD controller is unpowered in hibernate and stop modes. 22.3.2 High-Speed and Low-Speed Master Generators The high-speed and low-speed master generators are similar to each other. The only exception is that the high-speed version has larger frequency dividers to generate the frame and sub-frame periods. This is because the clock of the high-speed block (HFCLK) is derived from the IMO, which is typically at 30 to 100 times the frequency of the ILO (32 kHz) clock fed to the low-speed block. The high-speed generator is in the active power domain and the low-speed generator is in the deep-sleep power domain. A single set of configuration registers is provided to control both high-speed and lowspeed blocks. Each master generator has the following features and characteristics: ■ Register bit configuring the block for either Type A or Type B drive waveforms (LCD_MODE bit in LCD_CONTROL register). ■ Register bits to select the number of COMs (COM_NUM field in LCD_CONTROL register). The available values are 2, 3, and 4. ■ Operating mode configuration bits enabled to select one of the following: ❐ Digital correlation ❐ PWM 1/2 bias ❐ PWM 1/3 bias PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 253 LCD Direct Drive ❐ PWM 1/4 bias (not supported in low-speed generator) ❐ PWM 1/5 bias (not supported in low-speed generator) ❐ Off/disabled. Typically, one of the two generators will be configured to be Off OP_MODE and BIAS fields in LCD_CONTROL bits select the drive mode. ■ ■ A counter to generate the sub-frame timing. The SUBFR_DIV field in the LCD_DIVIDER register determines the duration of each sub-frame. If the divide value written into this counter is C, the sub-frame period is 4 × (C+1). The low-speed generator has an 8-bit counter. This generates a maximum half sub-frame period of 8 ms from the 32-kHz ILO clock. The high-speed generator has a 16-bit counter. A counter to generate the dead time period. These counters have the same number of bits as the sub-frame period counters and use the same clocks. DEAD_DIV field in the LCD_DIVIDER register controls the dead time period. 22.3.3 Multiplexer and LCD Pin Logic The multiplexer selects the output signals of either highspeed or low-speed master generator blocks and feeds it to the LCD pin logic. This selection is controlled by the configuration and control register. The LCD pin logic uses the subframe signal from the multiplexer to choose the display data. This pin logic will be replicated for each LCD pin. 22.3.4 Display Data Registers Each LCD segment pin is part of an LCD port with its own display data register, LCD_DATAnx. The device has eight such LCD ports. Note that these ports are not real pin ports but the ports/connections available in the LCD hardware for mapping the segments to commons. Each LCD segment configured is considered as a pin in these LCD ports. The LCD_DATAnx registers are 32-bit wide and store the ON/ OFF data for all SEG-COM combination enabled in the design. LCD_DATA0x holds SEG-COM data for COM0 to COM3. The bits [4i+3:4i] (where 'i' is the pin number) of each LCD_DATA0x register represent the ON/OFF data for Pin[i] in Port[x] and COM[3,2,1,0] combinations, as shown in Table 22-2. The LCD_DATAnx register should be programmed according to the display data of each frame. The display data registers are Memory Mapped I/O (MMIO) and accessed through the AHB slave interface. Table 22-2. SEG-COM Mapping in LCD_DATA0x Registers (each SEG is a pin of the LCD port) BITS[31:28] = PIN_7[3:0] PIN_7-COM3 PIN_7-COM2 PIN_7-COM1 BITS[27:24] = PIN_6[3:0] PIN_7-COM0 PIN_6-COM3 BITS[23:20] = PIN_5[3:0] PIN_5-COM3 PIN_5-COM2 PIN_5-COM1 PIN_3-COM2 PIN_3-COM1 PIN_5-COM0 PIN_4-COM3 PIN_4-COM2 22.4 PIN_1-COM2 PIN_1-COM1 PIN_6-COM0 PIN_4-COM1 PIN_4-COM0 BITS[11:8] = PIN_2[3:0] PIN_3-COM0 PIN_2-COM3 PIN_2-COM2 BITS[7:3] = PIN_1[3:0] PIN_1-COM3 PIN_6-COM1 BITS[19:16] = PIN_4[3:0] BITS[15:12] = PIN_3[3:0] PIN_3-COM3 PIN_6-COM2 PIN_2-COM1 PIN_2-COM0 BITS[3:0] = PIN_0[3:0] PIN_1-COM0 PIN_0-COM3 PIN_0-COM2 PIN_0-COM1 PIN_0-COM0 Register List Table 22-3. LCD Direct Drive Register List Register Name Description LCD_ID This register includes the information of LCD controller' ID and revision number LCD_DIVIDER This register controls the sub-frame and dead-time period LCD_CONTROL This register is used to configure high-speed and low-speed generators LCD_DATA0x LCD port pin data register for COM0 to COM3; x = port number, eight ports are available 254 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 23. CapSense PSoC® 4 uses a capacitive touch sensing method known as CapSense® Sigma Delta (CSD). The CapSense Sigma Delta touch sensing method provides the industry's best-in-class signal-to-noise ratio (SNR). CSD is a combination of hardware and firmware techniques. This chapter explains how the CSD hardware is implemented in PSoC 4. See the PSoC 4 CapSense Design Guide for more details on the basics of CSD operation, available CapSense design tools, the easy-to-use PSoC Creator™ component, performance tuning using the tuner GUI, and PCB layout design considerations. 23.1 Features PSoC 4 CapSense has the following features: ■ Robust sensing technology ■ CSD operation provides best-in-class SNR ■ High-performance sensing across a variety of overlay materials and thicknesses ■ SmartSense™ auto-tuning technology ■ Supports as many as 35 sensors ■ High-range proximity sensing ■ Water tolerant operation using shield signal, available on all GPIOs ■ Low power consumption ■ Two IDAC operation for improved scan speed and SNR ■ Any GPIO pin can be used for sensing or shielding ■ Pseudo random sequence (PRS) clock source for lower electromagnetic interference (EMI) ■ Dedicated charge tank capacitor for quick charge transfer on to shield lines ■ GPIO cell precharge support to quickly initialize external tank capacitors 23.2 Block Diagram Figure 23-1 shows the CSD system block diagram. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 255 CapSense Figure 23-1. CapSense Module Block Diagram GPIO Pin Sensor 1 Capacitance to current converter IS1 CS1 GPIO Pin Sensor 2 Capacitance to current converter IS2 Capacitance to current converter ISN Analog Multiplexer CS2 Current to digital raw count converter (sigma delta) Firmware processing touch status GPIO Pin Sensor N CSN 23.3 How It Works Figure 23-2. Raw Count Versus Time With CSD, each GPIO has a switched capacitance circuit that converts the sensor capacitance into an equivalent current. An analog multiplexer then selects one of the currents and feeds it into the current-to-digital converter. The currentto-digital converter is similar to a sigma delta ADC. The output count of the current-to-digital converter, known as raw count, is a digital value that is proportional to the sensor capacitance. Figure 23-2 shows a plot of raw count over time. When a finger touches the sensor, the sensor capacitance increases; the raw count increases proportionally. By comparing the change in raw count to a predetermined threshold, logic in firmware can decide whether the sensor is active (finger is present). 256 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D CapSense 23.4 CapSense CSD Sensing Figure 23-3 shows the block diagram of the PSoC 4 CapSense hardware. Figure 23-3. PSoC 4 CapSense CSD Sensing AMUXBUS A forms an analog multiplexer for the sensors current to digital converter IO cells configured as switched capacitance circuits for capacitance to current conversion GPIO pin sensor 1 7 bit IDAC GPIO cell CS1 GPIO pin sensor 2 8 bit IDAC GPIO cell CS2 IDAC control GPIO pin sensor N GPIO cell counter CSN VREF (1.2V) sense comparator raw counts sigma-delta converter CMOD pin Integrating capacitor for sigma-delta converter CMOD switching clock for GPIO switched capacitance circuits, frequency FSW 23.4.1 modulation clock frequency FMOD switching clock CapSense clock generator GPIO Cell Capacitance to Current Converter Figure 23-4. PSoC 4 GPIO Cell AMUXBUS AMUXBUS A B In the CapSense CSD system, the GPIO cells are configured as switched capacitance circuits, which convert the sensor capacitance to equivalent currents. Figure 23-4 shows a simplified diagram of the PSoC 4 GPIO cell structure. PSoC 4 has two analog multiplexer buses: AMUXBUS A is used for CSD sensing and AMUXBUS B is used for CSD shielding. The GPIO switched capacitance circuit has two possible configurations: source current to AMUXBUS A or sink current from AMUXBUS A. Figure 23-5 shows the switched capacitance configuration for sourcing current to AMUXBUS A. modulation clock (Both from system resources) VDDD SW2 SW3 GPIO Pin SW4 SW1 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 257 CapSense Figure 23-5. Sourcing Current to AMUXBUS A AMUXBUS A VDDD ISW ISW SW2 AMUXBUS A VDDD RS SW3 CS ISW Two non-overlapping, out of phase clocks of frequency FSW (see Figure 23-3) control the switches SW2 and SW3. The continuous switching of SW2 and SW3 forms an equivalent resistance RS, as Figure 23-5 shows. The value of the equivalent resistance RS is: 1 R S = -----------------C S F SW Equation 23-1 Where: CS = Sensor capacitance FSW = Frequency of the switching clock The sigma delta converter maintains the voltage of AMUXBUS A at a constant VREF (this process is explained in Sigma Delta Converter on page 259). Figure 23-6 shows the voltage waveform across the sensor capacitance. Figure 23-6. Voltage Across Sensor Capacitance V SW2 Closed SW3 Open VDDD SW2 Open SW3 Closed VREF (1.2 V) t 0 TSW = 1/FSW Equation 23-3 gives the value of average current supplied to AMUXBUS A. I S = C S F SW V DDD – V REF Equation 23-2 Figure 23-7 shows the switched capacitance configuration for sinking current from AMUXBUS A. Figure 23-8 shows the resulting voltage waveform across CS. 258 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D CapSense Figure 23-7. Sinking Current From AMUXBUS A ISW AMUXBUS A AMUXBUS A SW3 RS SW1 CS ISW ISW ers are used. The first clock divider generates modulation clock and the second one generates switching clock. Figure 23-8. Voltage Across Sensor Capacitance V VREF (1.2 V) SW1 Open SW3 Closed However, the final switching clock frequency depends on the CapSense clock generator. It has the following output options: SW1 Closed SW3 Open 0 Divide by 2. Divides the clocks by two. To select this option, clear the PRS_SELECT and BYPASS_SEL bits in the CSD_CONFIG register. ■ Pseudo random sequence (PRS): Reduces the EMI in the CapSense system by spreading the switching frequency over a broader range. To select this option, set the PRS_SELECT bit and clear the BYPASS_SEL bit in the CSD_CONFIG register. You can select between 8and 12- bit pseudo random sequence using the PRS_12_8 bit in the same register. Set this bit to select a 12- bit sequence; clear it for 8- bit PRS. t TSW = 1/FSW Equation 23-4 gives the value of average current taken from AMUXBUS A. I S = C S FSW V REF Equation 23-3 The sigma delta converter scans one sensor at a time. AMUXBUS A is used to select one of the GPIO cells and connects it to the input of the sigma delta converter, as Figure 23-3 shows. The AMUXBUS A and the GPIO cell switches (see SW3 in Figure 23-4) form this analog multiplexer. AMUXBUS A can connect to all PSoC 4 pins that support CSD. See the device datasheet to know the CSD capable pins. See the I/O System chapter on page 53 to know how to configure a GPIO cell for sensing, shielding, and connecting CMOD. 23.4.2 ■ If PRS is selected, the maximum switching frequency is F in F SW maximum = ------2 Where Fin is the frequency output of the switching divider. The minimum frequency is: F in F SW minimum = -------------------------------PRS length-1 The switching clock is required for the GPIO cell switched capacitance circuits. The sigma delta converter uses the modulation clock for timing. Any two programmable clock dividers from the system resources can be used to divide the HFCLCK and generate the required frequencies. See the Clocking System chapter on page 63 for details. Typically, two cascaded clock divid- Equation 23-5 Where PRS length is either 12 or 8 bits. The average switching frequency is: CapSense Clock Generator This block, together with the programmable clock dividers from the system resources, generates the switching clock FSW and the modulation clock FMOD, as Figure 23-3 shows. For details, see the Clocking System chapter on page 63. Equation 23-4 F in F SW average = ------4 Equation 23-6 The PRS_CLEAR bit in CSD_CONFIG can be used to clear the PRS; when set, this bit forces the pseudo-random generator to its initial state. 23.4.3 Sigma Delta Converter The sigma delta converter converts the input current to a corresponding digital count. It consists of a comparator, a voltage reference VREF, a counter, and two current sourcing/ sinking digital-to-analog converters (IDACs), as Figure 23-3 shows. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 259 CapSense The sigma delta modulator controls the current of the 8-bit IDAC in an on/off manner. This IDAC is known as the modulation IDAC. The 7-bit IDAC, known as the compensation IDAC, is either always on or always off. The sigma delta converter can operate in either single IDAC mode or dual IDAC mode. In the single IDAC mode, the compensation IDAC is always off. In the dual IDAC mode, the compensation IDAC is always on. The sigma delta converter also requires an external integrating capacitor CMOD, as Figure 23-1 shows. The recommended value of CMOD is 2.2 nF. PSoC 4 has a dedicated CMOD pin. See the pinout in the device datasheet for details. The sigma delta modulator maintains the voltage across CMOD at VREF. It works in one of the following modes: ■ IDAC sourcing mode: If the switched capacitor circuit sinks current from AMUXBUS A, the IDACs source current to AMUXBUS A to balance its voltage. ■ IDAC sinking mode: In this mode, the IDACs sink current from CMOD and the switched capacitor circuit sources current to CMOD. In both cases, the modulation IDAC current is switched on and off corresponding to the small voltage variations across CMOD to maintain the CMOD voltage at VREF. The sigma delta converter can operate from 8-bit to 16-bit resolutions. In the single IDAC mode, the raw count is proportional to the sensor capacitance. If 'N' is the resolution of the sigma delta converter and IMOD is the value of the modulation IDAC current, the approximate value of raw count in IDAC sourcing mode is given by Equation 16-7. N V REF F SW Rawcount = 2 ------------------------- C S I MOD Equation 23-7 Similarly, the approximate value of raw count in IDAC sinking mode is: N V DD – V REF F SW Rawcount = 2 ----------------------------------------------- C S I MOD Equation 23-8 In both cases, the raw count is proportional to sensor capacitance CS. This raw count can be processed by the firmware to detect touches. You can use both the IDACs in a dual IDAC mode to improve the CapSense performance. In this dual IDAC mode, the compensation IDAC is always on. If ICOMP is the compensation IDAC current, the equation for the raw count in IDAC sourcing mode is: N V DD – V REF F SW N I COMP Rawcount = 2 ----------------------------------------------- C S – 2 ---------------I MOD I MOD Equation 23-10 Note that raw count values are always positive. The hardware parameters such as ICOMP, IMOD, and FSW, should be tuned to optimum values for reliable touch detection. For a detailed discussion of the tuning process, see the PSoC 4 CapSense Design Guide. Registers CSD_CONFIG, CSD_COUNTER, and CSD_IDAC control the operation of the sigma delta converter. The important bits in the CSD_CONFIG register are: ■ ENABLE in CSD_CONFIG: Master enable of the CSD block. Must be set to '1' for any CSD operation. ■ POLARITY in CSD_CONFIG: Selects between IDAC sinking mode and IDAC sourcing mode. 0: IDAC sourcing mode, 1: IDAC sinking mode. ■ SENSE_COMP_BW in CSD_CONFIG: Selects the bandwidth of the sensing comparator. Setting this bit gives high bandwidth and clearing it gives low bandwidth. High bandwidth is recommended for CSD operation. ■ SENSE_COMP_EN in CSD_CONFIG: Turns on the sense comparator circuit. 0: Sense comparator is powered off. 1: Sense comparator is powered on. ■ SENSE_EN: Enables the sigma delta modulator output. Also turns on the IDACs. The IDACs must be configured properly for CSD operation. See the CSD_IDAC register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM for details. CSD_COUNTER register is used to initiate a sampling of the currently selected sensor and to read the result. The 16bit COUNTER field in this register increments whenever the comparator is sampled (at the modulation clock frequency) and the sample is 1. Firmware typically writes ‘0’ to this field whenever a new sense operation is initiated. The 16-bit PERIOD field in the CSD_COUNTER register is used to initiate the capacitance to digital conversion. Writing a nonzero value to this register initiates a sensing operation. The value written to this field by the firmware determines the period during which the COUNTER field samples the comparator output. The clocks, GPIOs, IDACs, and the sigma delta modulator must be properly configured before starting the CSD operation. The period field decrements after every modulation clock cycle. When it reaches 0, the COUNTER field stops incrementing. The value of this field at this time is the raw count corresponding to the value of sensor capacitance. N V REF F SW N I COMP Rawcount = 2 ------------------------- C S – 2 ---------------I MOD I MOD Equation 23-9 Raw count in IDAC sinking mode is given by equation 16-10. 260 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D CapSense 23.5 CapSense CSD Shielding PSoC 4 CapSense supports shield electrodes for waterproofing and proximity sensing. For waterproofing, the shield electrode is always kept at the same potential as the sensors. PSoC 4 CapSense has a shielding circuit that drives the shield electrode with a replica of the sensor switching signal (see GPIO Cell Capacitance to Current Converter on page 257) to nullify the potential difference between sensors and the shield electrode. See the PSoC 4 CapSense Design Guide to understand the basics of shielding. In the sensing circuit, the sigma delta converter keeps the AMUXBUS A at VREF (see Sigma Delta Converter on page 259). The GPIO cells generate the sensor waveforms by switching the sensor between AMUXBUS A and a supply rail (either VDD or ground, depending on the configuration). The shielding circuit works in a similar way; AMUXBUS B is always kept at VREF. The GPIO cell switches the shield between AMUXBUS B and a supply rail (either VDDD or ground, the same configuration as the sensor). This process generates a replica of the sensor switching waveform on the shield electrode. Depending on how AMUXBUS B is maintained at VREF, two different configurations are possible. ■ Shield driving using VREF buffer: In this configuration, a voltage buffer is used to drive AMUXBUS B to VREF, as Figure 23-9 shows. An external CSH_TANK capacitor is recommended to reduce switching transients. Setting the REBUF_OUTSEL bit in the CSD_CONFIG register connects the buffer output to AMUXBUS B. The REFBUF_DRV bit field in the same register can be used to set the drive strength of the buffer. Writing a '0' to this field disables the buffer; writing 1, 2, and 3 selects the low, mid, and high-current drive modes respectively. Figure 23-9. Shield Driving Using VREF Buffer Shield Tank Capacitor (optional) GPIO Pin VREF CSH_TANK (1.2V) GPIO Pin VREF Buffer GPIO Cell Shield electrode capacitance AMUXBUS B (Always kept at VREF) CSHIELD Shield Electrode ■ Shield driving using GPIO cell precharge: This configuration requires an external CSH_TANK capacitor, as Figure 23-10 shows. A special GPIO cell and a reference comparator is used to charge the CSH_TANK capacitor and hence the AMUXBUS B to VREF. The reference comparator always monitors the voltage on the CSH_TANK capacitor and controls the GPIO cell switch to keep the voltage at VREF. The reference comparator connects to the CSH_TANK capacitor using a dedicated sense line known as Channel 2 sensing line, as Figure 23-10 shows. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 261 CapSense Figure 23-10. Shield Driving Using GPIO Precharge VDD GPIO cell switch CSH_TANK Pin Reference Comparator Shield Tank Capacitor CSH_TANK Channel 2 sensing line GPIO Pin GPIO Cell VREF (1.2V) Shield electrode capacitance AMUXBUS B (Always kept at VREF) CSHIELD Shield Electrode This GPIO cell precharge capability is available only on a fixed CSH_TANK pin. See the device pinout in the device datasheet for details. COMP_MODE bit in the CSD_CONFIG register selects between the reference buffer precharge and GPIO precharge; 0: reference buffer precharge, 1: GPIO precharge. 23.5.1 CMOD Precharge Figure 23-11. GPIO Cell Precharge When the CapSense hardware is enabled for the first time, the voltage across CMOD starts at zero. Then the sigma delta converter slowly charges the CMOD to VREF. The charging current is supplied by the IDACs in the IDAC sourcing mode and by the sensor switched capacitance circuit in the IDAC sinking mode. However, this is a slow process because CMOD is a relatively large capacitor. Precharging of CMOD is the process of quickly initializing the voltage across CMOD to VREF. Precharging reduces the time required for the sigma delta converter to start its operation. There are two options for precharging CMOD. ■ ■ Precharge using VREF buffer: When the shield is enabled, the VREF buffer output is always connected to AMUXBUS B (Figure 23-9). To precharge using the VREF buffer, CMOD is initially connected to AMUXBUS B. After the precharging process, CMOD is connected to AMUXBUS A for normal sigma delta operation. When the shield is disabled, the VREF buffer output is always connected to AMUXBUS A for precharging and disconnected afterwards. Precharge using GPIO cell: In this configuration, a special GPIO cell and a reference comparator is used to charge the CMOD capacitor to VREF. This GPIO cell precharge capability is available only on a fixed CMOD pin. See the pinout in the device datasheet for details. The comparator used for this purpose is the same reference comparator used for CSH_TANK precharge. COMP_PIN bit in the CSD_CONFIG register is used to 262 select which capacitor is connected to the reference comparator. If this bit is 0, the sense line designated as "Channel 1" is used to connect CMOD to the reference comparator as Figure 23-11 shows; if this bit is 1, Channel 2 sense line is used to connect CSH_TANK to the reference comparator, as Figure 23-10 shows. Note that the GPIO cells must be configured properly for the GPIO cell precharge to work. VDD CMOD Pin CMOD GPIO cell switch Reference Comparator Channel 1 sensing line VREF (1.2V) AMUXBUS A (Always kept at VREF) Precharge using a GPIO cell is faster than using the VREF buffer. Therefore, GPIO precharge is the recommended precharge configuration. However, if you do not need a fast initialization of CapSense, use the VREF buffer precharge. The Channel 1 sense line can also be used to connect CMOD to the sensing comparator in the sigma delta modulator. Setting the SENSE_INSEL bit in the CSD_CONFIG register to '1' enables this option. Clearing this bit connects CMOD to the sensing comparator using AMUXBUS A. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D CapSense 23.6 General-Purpose Resources: IDACs If the CapSense block is not used for touch sensing, the two IDACs can be used as general-purpose analog blocks. The 8-bit IDAC can operate in either 0 to 306 µA (1.2 µA/bit) or 0 to 612 µA (2.4 µA/bit) ranges. The 7-bit IDAC supports 0 to 152.4 µA (1.2 µA/bit) and 0 to 304.8 µA (2.4 µA/bit) ranges. Both the 8-bit and 7-bit IDACs can connect to GPIOs using AMUXBUS A and AMUXBUS B. It is also possible to connect both IDACs to a single AMUXBUS. The IDACS can operate in three different modes: CSD-only mode, General-purpose (GP) mode, and CSD and GP mode. Table 23-1 describes how IDAC1 and IDAC2 are connected to AMUXBUS A and AMUXBUS B in each of these modes. Table 23-1. IDAC Modes Mode AMUXBUS A AMUXBUS B CSD only Both IDACs sink/source current at 1.2 V No IDACs connected General-purpose mode 8-bit IDAC sink/source current 7-bit IDAC sink/source current CSD and GP mode 8-bit IDAC sink/source current at 1.2 V 7-bit IDAC sink/source current See the CSD_IDAC register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM for details. The CSD_CONFIG register can be used to enable the IDACs and set the polarity, as mentioned in Sigma Delta Converter on page 259. See the I/O System chapter on page 53 for details on how to connect GPIOs to AMUXBUS A and B. 23.7 Register List Table 23-2. CapSense Register List Register Name Description CSD_CONFIG This register is used to configure and control the CSD block and its resources. CSD_IDAC This register is used to control the IDAC current settings. CSD_COUNTER This register is used to initiate a sampling of the selected capacitive sensor and read the result of conversion. CSD_STATUS This register allows the observation of key signals in the CSD block. CSD_INTR This is the CSD interrupt request register. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 263 CapSense 264 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 24. Temperature Sensor PSoC® 4 has an on-chip temperature sensor that is used to measure the internal die temperature. The sensor consists of a transistor connected in diode configuration. 24.1 Features The temperature sensor has the following features: ■ ± 5° Celsius accuracy over temperature range –40 °C to +85 °C ■ 0.5° Celsius/LSB resolution (without amplification) when using a 12-bit SAR ADC with a 1.024-V reference ■ 10 µs settling time 24.2 How it Works The temperature sensor consists of a single bipolar junction transistor (BJT) in the form of a diode. Its base-to-emitter voltage (VBE) has a strong dependence on temperature at a constant collector current and zero collector-base voltage. This property is used to calculate the die temperature by measuring the VBE of the transistor using SAR ADC, as shown in Figure 24-1. Figure 24-1. Temperature Sensing Mechanism Current from Precision Reference Block Ibias 2.5 uA SAR_MUX_FW_ TEMP_VPLUS vplus Temperature Sensor SAR ADC CPU vssa_kelvin SARMUX 12 bit vminus 1.024 V Vssa Vssa The analog output from the sensor (VBE) is measured using the SAR ADC. Die temperature in °C can be calculated from the ADC results as given in the following equation: 10 Temp = A SAR out + 2 xB + T adjust Equation 24-1 ■ Temp is the slope compensated temperature in °C represented as Q16.16 fixed point number format. ■ ‘A’ is the 16-bit multiplier constant. The value of A is determined using the PSoC 4 family characterization data of two point slope calculation. It is calculated as given in the following equation. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 265 Temperature Sensor 16 100 C – – 40 C A = signed int 2 -------------------------------------------------------- SAR 100C – SAR – 40C Equation 24-2 Where, SAR100C = ADC counts at 100°C SAR–40C = ADC counts at –40°C Constant 'A' is stored in a register SFLASH_SAR_TEMP_MULTIPLIER. ■ ‘B’ is the 16-bit offset value. The value of B is determined on a per die basis by taking care of all the process variations and the actual bias current (Ibias) present in the chip. It is calculated as given in the following equation. 6 A SAR 100C - B = unsigned int 2 x100 C – -------------------------------10 2 Equation 24-3 Where, SAR100C = ADC counts at 100°C Constant 'B' is stored in a register SFLASH_SAR_TEMP_OFFSET. ■ Tadjust is the slope correction factor in °C. The temperature sensor is corrected for dual slopes using the slope correction factor. It is evaluated based on the result obtained without slope correction, that is, evaluating Tinitial = (A×SARout+ 210×B). If it is greater than the center value (15°C), then Tadjust is given by the following equation. 0.5 C 16 T adjust = ----------------------------------- 100 C 2 – T initial 100 C – 15 C Equation 24-4 If less than center value, then Tadjust is given by the following equation. 0.5 C 16 T adjust = -------------------------------- 40 C 2 – T initial 40 C + 15 C Equation 24-5 Figure 24-2. Temperature Error Compensation Temperature Error Compensation curve 0.5°C Tadjust 0°C -0.5°C Sensor Error Curve Actual Temperature -40°C 15°C 100°C Note A and B are 16-bit constants stored in flash during factory calibration. Note that these constants are valid only when the SAR ADC is running at 12-bit resolution with a 1.024-V reference. 24.3 Temperature Sensor Configuration As shown in Figure 24-3, the temperature sensor output is routed to the positive input of SAR ADC via dedicated switches, which can be controlled by sequencer, firmware, or digital system interconnect (DSI).The control signal for the switch (SAR_MUX_FW_TEMP_VPLUS shown in Figure 24-1) enables the temperature sensor by passing bias current from precision reference block and connecting the sensor output to the positive input of SAR ADC. The SAR_MUX_FW_TEMP_VPLUS control bit is a part of the SAR_MUX_SWITCH0 register. The switch status can be read using the SAR_MUX_SWITCH_STATUS register. 266 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Temperature Sensor SARMUX Figure 24-3. Routing Temperature Sensor Output to SAR ADC PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 267 Temperature Sensor 24.4 Algorithm 1. Enable the SARMUX and SAR ADC. 2. Configure SAR ADC in single-ended mode with VNEG = VSS, VREF = 1.024 V, 12-bit resolution, and right-aligned result. 3. Enable the temperature sensor. 4. Get the digital output from the SAR ADC. 5. Fetch ‘A’ from SFLASH_SAR_TEMP_MULTIPLIER and ‘B’ from SFLASH_SAR_TEMP_OFFSET. 6. Calculate the die temperature using the linear equation (Equation 24-1). For example, let A = 0xBC4B and B = 0x65B4. Assume that the output of SAR ADC (VBE) is 0x595 at a given temperature. Firmware does the following calculations: a. Multiply A and VBE: 0xBC4B × 0x595 = (–17333)10 × (1429)10 = (–24768857)10 b. Multiply B and 1024: 0x65B4 × 0x400 = (26036)10 × (1024)10 = (26660864)10 c. Add the result of steps 1 and 2 to get Tinitial: (–24768857)10 + (26660864)10 = (1892007)10 = 0x1CDEA7 d. Calculate Tadjust using Tinitial value: Tinitial is the upper 16 bits multiplied by 216, that is, 0x1C00 = (1835008)10. It is greater than 15°C (0x1C - upper 16 bits). Use Equation 4 to calculate Tadjust. It comes to 0x6C6C = (27756)10 e. Add Tadjust to Tinitial: (1892007)10 + (27756)10 = (1919763)10 = 0x1D4B13 f. The integer part of temperature is the upper 16 bits = 0x001D = (29)10 g. The decimal part of temperature is the lower 16 bits = 0x4B13 = (0.19219)10 h. Combining the result of steps f and g, Temp = 29.19219 °C ~ 29.2°C 24.5 Registers Name SAR_MUX_SWITCH0 Description This register has the SAR_MUX_FW_TEMP_VPLUS field to connect the temperature sensor to the SAR MUX terminal. SAR_MUX_SWITCH_STATUS This register provides the status of the temperature sensor switch connection to SAR MUX. SFLASH_SAR_TEMP_MULTIPLIER Multiplier constant 'A' as defined in Equation 24-1. SFLASH_SAR_TEMP_OFFSET Constant 'B' as defined in Equation 24-1. 268 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Section G: Program and Debug This section encompasses the following chapters: ■ Program and Debug Interface chapter on page 271 ■ Nonvolatile Memory Programming chapter on page 279 Top Level Architecture Program and Debug Block Diagram System Bus PROGRAM AND DEBUG Program Debug and Trace PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 269 270 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 25. Program and Debug Interface The PSoC® 4 Program and Debug interface provides a communication gateway for an external device to perform programming or debugging. The external device can be a Cypress-supplied programmer and debugger, or a third-party device that supports PSoC 4 programming and debugging. The serial wire debug (SWD) interface is used as the communication protocol between the external device and PSoC 4. 25.1 Features ■ Programming and debugging through the SWD interface ■ Four hardware breakpoints and two hardware watchpoints while debugging ■ Read and write access to all memory and registers in the system while debugging, including the Cortex-M0 register bank when the core is running or halted 25.2 Functional Description Figure 25-1 shows the block diagram of the program and debug interface in PSoC 4. The Cortex-M0 debug and access port (DAP) acts as the program and debug interface. The external programmer or debugger, also known as the "host", communicates with the DAP of the PSoC 4 "target" using the two pins of the SWD interface - the bidirectional data pin (SWDIO) and the host-driven clock pin (SWDCK). The SWD physical port pins (SWDIO and SWDCK) communicate with the DAP through the high-speed I/O matrix (HSIOM). See the I/O System chapter on page 53 for details on HSIOM. Figure 25-1. PSoC 4 Program and Debug Interface PSoC 4 ARM Cortex-M0 subsystem Host Device SWDIO Cortex-M0 DAP HSIOM SWDCK SWD Debug Port (DP) Cortex-M0 CPU AP Access AHB Access Port (AP) DAP AHB AHB FLASH SPC Interface AHB SROM SRAM Peripheral Modules The DAP communicates with the Cortex-M0 CPU using the ARM-specified advanced high-performance bus (AHB) interface. AHB is the systems interconnect protocol used inside PSoC 4, which facilitates memory and peripheral register access by the AHB master. PSoC 4 has two AHB masters – ARM CM0 CPU core and DAP. The external device can effectively take control of the entire device through the DAP to perform programming and debugging operations. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 271 Program and Debug Interface 25.3 Serial Wire Debug (SWD) Interface PSoC 4’s Cortex-M0 supports programming and debugging through the SWD interface. The SWD protocol is a packet-based serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK). The host programmer always drives the clock line, whereas either the host or the target drives the data line. A complete data transfer (one SWD packet) requires 46 clocks and consists of three phases: ■ Host Packet Request Phase – The host issues a request to the PSoC 4 target. ■ Target Acknowledge Response Phase – The PSoC 4 target sends an acknowledgement to the host. ■ Data Transfer Phase – The host or target writes data to the bus, depending on the direction of the transfer. When control of the SWDIO line passes from the host to the target, or vice versa, there is a turnaround period (Trn) where neither device drives the line and it floats in a high-impedance (Hi-Z) state. This period is either one-half or one and a half clock cycles, depending on the transition. Figure 25-2 shows the timing diagrams of read and write SWD packets. Figure 25-2. PSoC 4 SWD Write and Read Packet Timing Diagrams Host Packet Request Phase Target ACK Phase ... Parity ACK[0:2] wdata[1] 0 wdata[0] 0 1 Trn (Hi-Z) Trn (Hi-Z) Park (1) Stop (0) A[2:3] Parity ... RnW (0) SWDIO APnDP ... Start (1) SWDCK wdata[31] SWD Write Packet Host Data Transfer Phase Host Packet Request Phase a. The start bit initiates a transfer; it is always logic 1. b. The “AP not DP” (APnDP) bit determines whether the transfer is an AP access – 1b1 or a DP access – 1b0. c. The “Read not Write” bit (RnW) controls which direction the data transfer is in. 1b1 represents a ‘read from’ the target, or 1b0 for a ‘write to’ the target. d. The Address bits (A[3:2]) are register select bits for AP or DP, depending on the APnDP bit value. See Table 25-3 and Table 25-4 for definitions. Note Address bits are transmitted with the LSB first. e. The parity bit contains the parity of APnDP, RnW, and ADDR bits. It is an even parity bit; this means, when XORed with the other bits, the result will be 0. Trn (Hi-Z) Target ACK and Data Transfer Phases The sequence to transmit SWD read and write packets are as follows: 1. Host Packet Request Phase: SWDIO driven by the host ... Parity ACK[0:2] 0 rdata[1] 0 1 rdata[0] Trn (Hi-Z) Park (1) Stop (0) A[2:3] Parity ... RnW (1) SWDIO APnDP ... Start (1) SWDCK rdata[31] SWD Read Packet The programming operation should be aborted and retried again by following a device reset. f. The stop bit is always logic 0. g. The park bit is always logic 1. 2. Target Acknowledge Response Phase: SWDIO driven by the target a. The ACK[2:0] bits represent the target to host response, indicating failure or success, among other results. See Table 25-1 for definitions. Note ACK bits are transmitted with the LSB first. 3. Data Transfer Phase: SWDIO driven by either target or host depending on direction a. The data for read or write is written to the bus, LSB first. b. The data parity bit indicates the parity of the data read or written. It is an even parity; this means when XORed with the data bits, the result will be 0. If the parity bit is not correct, the header is ignored by PSoC 4; there is no ACK response (ACK = 3b111). 272 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Program and Debug Interface If the parity bit indicates a data error, corrective action should be taken. For a read packet, if the host detects a parity error, it must abort the programming operation and restart. For a write packet, if the target detects a parity error, it generates a FAULT ACK response in the next packet. According to the SWD protocol, the host can generate any number of SWDCK clock cycles between two packets with SWDIO low. It is recommended to generate three or more dummy clock cycles between two SWD packets if the clock is not free-running or to make the clock free-running in IDLE mode. The SWD interface can be reset by clocking the SWDCK line for 50 or more cycles with SWDIO high. To return to the idle state, clock the SWDIO low once. 25.3.1 SWD Timing Details The SWDIO line is written to and read at different times depending on the direction of communication. The host drives the SWDIO line during the Host Packet Request Phase and, if the host is writing data to the target, during the Data Transfer phase as well. When the host is driving the SWDIO line, each new bit is written by the host on falling SWDCK edges, and read by the target on rising SWDCK edges. The target drives the SWDIO line during the Target Acknowledge Response Phase and, if the target is reading out data, during the Data Transfer Phase as well. When the target is driving the SWDIO line, each new bit is written by the target on rising SWDCK edges, and read by the host on falling SWDCK edges. 25.3.2 The acknowledge (ACK) bit-field is used to communicate the status of the previous transfer. OK ACK means that previous packet was successful. A WAIT response requires a data phase. For a FAULT status, the programming operation should be aborted immediately. Table 25-2 shows the ACK bit-field decoding details. Table 25-2. SWD Transfer ACK Response Decoding Response 3b001 WAIT 3b010 FAULT 3b100 NO ACK 3b111 Details on WAIT and FAULT response behaviors are as follows: ■ For a WAIT response, if the transaction is a read, the host should ignore the data read in the data phase. The target does not drive the line and the host must not check the parity bit as well. ■ For a WAIT response, if the transaction is a write, the data phase is ignored by the PSoC 4. But, the host must still send the data to be written to complete the packet. The parity bit corresponding to the data should also be sent by the host. ■ For a WAIT response, it means that the PSoC 4 is processing the previous transaction. The host can try for a maximum of four continuous WAIT responses to see if an OK response is received. If it fails, then the programming operation should be aborted and retried again. ■ For a FAULT response, the programming operation should be aborted and retried again by doing a device reset. Table 25-1. SWDIO Bit Write and Read Timing Host Packet Request Host Data Transfer Target Ack Response Target Data Transfer SWDIO Edge Falling Host Write Rising Target Read 25.3.3 Host Read ACK[2:0] OK Table 25-1 and Figure 25-2 illustrate the timing of SWDIO bit writes and reads. SWD Packet Phase ACK Details Target Write Turnaround (Trn) Period Details There is a turnaround period between the packet request and the ACK phases, as well as between the ACK and the data phases for host write transfers, as shown in Figure 25-2. According to the SWD protocol, the Trn period is used by both the host and target to change the drive modes on their respective SWDIO lines. During the first Trn period after the packet request, the target starts driving the ACK data on the SWDIO line on the rising edge of SWDCK. This ensures that the host can read the ACK data on the next falling edge. Thus, the first Trn period lasts only onehalf cycle. The second Trn period of the SWD packet is one and a half cycles. Neither the host nor PSoC 4 should drive the SWDIO line during the Trn period. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 273 Program and Debug Interface 25.4 Cortex-M0 Debug and Access Port (DAP) The Cortex-M0 program and debug interface includes a Debug Port (DP) and an Access Port (AP), which combine to form the DAP. The debug port implements the state machine for the SWD interface protocol that enables communication with the host device. It also includes registers for the configuration of access port, DAP identification code, and so on. The access port contains registers that enable the external device to access the Cortex-M0 DAP-AHB interface. Typically, the DP registers are used for a one time configuration or for error detection purposes, and the AP registers are used to perform the programming and debugging operations. Complete architecture details of the DAP is available in the ARM® Debug Interface v5 Architecture Specification. 25.4.1 Debug Port (DP) Registers Table 25-3 shows the Cortex-M0 DP registers used for programming and debugging, along with the corresponding SWD address bit selections. The APnDP bit is always zero for DP register accesses. Two address bits (A[3:2]) are used for selecting among the different DP registers. Note that for the same address bits, different DP registers can be accessed depending on whether it is a read or a write operation. See the ARM® Debug Interface v5 Architecture Specification for details on all of the DP registers. Table 25-3. Main Debug Port (DP) Registers APnDP Address A[3:2] RnW ABORT 0 (DP) 2b00 0 (W) AP Abort Register This register is used to force a DAP abort and to clear the error and sticky flag conditions. IDCODE 0 (DP) 2b00 1 (R) Identification Code Register This register holds the SWD ID of the Cortex-M0 CPU, which is 0x0BB11477. CTRL/STAT 0 (DP) 2b01 X (R/W) Control and Status Register This register allows control of the DP and contains status information about the DP. SELECT 0 (DP) 2b10 0 (W) AP Select Register This register is used to select the current AP. In PSoC 4, there is only one AP, which interfaces with the DAP AHB. RDBUFF 0 (DP) 2b11 1 (R) Read Buffer Register This register holds the result of the last AP read operation. Register 25.4.2 Full Name Register Functionality Access Port (AP) Registers Table 25-4 lists the main Cortex-M0 AP registers that are used for programming and debugging, along with the corresponding SWD address bit selections. The APnDP bit is always one for AP register accesses. Two address bits (A[3:2]) are used for selecting the different AP registers. Table 25-4. Main Access Port (AP) Registers APnDP Address A[3:2] CSW 1 (AP) 2b00 Control and Status X (R/W) Word Register (CSW) TAR 1 (AP) 2b01 X (R/W) Transfer Address Register DRW 1 (AP) 2b11 X (R/W) Data Read and Write This register holds the 32-bit data read from or to be written to Register the address specified in the TAR register Register 274 RnW Full Name Register Functionality This register configures and controls accesses through the memory access port to a connected memory system (which is the PSoC 4 Memory map) This register is used to specify the 32-bit memory address to be read from or written to PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Program and Debug Interface 25.5 Programming the PSoC 4 Device if (time_elapsed >= 1.5 ms) return FAIL; //check for acquire time out PSoC 4 is programmed using the following sequence. Refer to the PSoC 4 Device Programming Specifications for complete details on the programming algorithm, timing specifications, and hardware configuration required for programming. 1. Acquire the SWD port in PSoC 4. 2. Enter the programming mode. 3. Execute the device programming routines such as Silicon ID Check, Flash Programming, Flash Verification, and Checksum Verification. 25.5.1 25.5.1.1 SWD Port Acquisition Primary and Secondary SWD Pin Pairs The first step in device programming is to acquire the SWD port in PSoC 4. Refer to the device datasheet for information on SWD pins. If two SWD pin pairs are available in the device, the SWD_CONFIG register in the supervisory flash region is used to select between one of the two SWD pin pairs that can be used for programming and debugging. Note that only one of the SWD pin pairs can be used during any programming or debugging session. The default selection for devices coming from the factory is the primary SWD pin pair. To select the secondary SWD pin pair, it is necessary to program the device using the primary pair with the hex file that enables the secondary pin pair configuration. Afterwards, the secondary SWD pin pair may be used. 25.5.1.2 SWD Port Acquire Sequence The first step in device programming is for the host to acquire the target's SWD port. The host first performs a device reset by asserting the external reset (XRES) pin. After removing the XRES signal, the host must send an SWD connect sequence for the device within the acquire window to connect to the SWD interface in the DAP. The pseudo code for the sequence is given here. if (ID != CM0_ID) return FAIL; //confirm SWD ID of Cortex-M0 CPU. (0x0BB11477) In this pseudo code, SWD_LineReset() is the standard ARM command to reset the debug access port. It consists of more than 49 SWDCK clock cycles with SWDIO high. The transaction must be completed by sending at least one SWDCK clock cycle with SWDIO asserted LOW. This sequence synchronizes the programmer and the chip. Read_DAP() refers to the read of the IDCODE register in the debug port. The sequence of line reset and IDCODE read should be repeated until an OK ACK is received for the IDCODE read or a timeout (1.5 ms) occurs. The SWD port is said to be in the acquired state if an OK ACK is received within the time window and the IDCODE read matches with that of the Cortex-M0 DAP. 25.5.2 SWD Programming Mode Entry After the SWD port is acquired, the host must enter the device programming mode within a specific time window. This is done by setting the TEST_MODE bit (bit 31) in the test mode control register (MODE register). The debug port should also be configured before entering the device programming mode. Timing specifications and pseudo code for entering the programming mode are detailed in the PSoC 4 Device Programming Specifications document. 25.5.3 SWD Programming Routines Executions When the device is in programming mode, the external programmer can start sending the SWD packet sequence for performing programming operations such as flash erase, flash program, checksum verification, and so on. The programming routines are explained in the Nonvolatile Memory Programming chapter on page 279. The exact sequence of calling the programming routines is given in the PSoC 4 Device Programming Specifications document. Code 1. SWD Port Acquire Pseudo Code ToggleXRES(); // Toggle XRES pin to reset device //Execute ARM’s acquire SWD-port do connection sequence to { SWD_LineReset(); //perform a line reset (50+ SWDCK clocks with SWDIO high) ack = Read_DAP ( IDCODE, out ID); //Read the IDCODE DP register }while ((ack != OK) && time_elapsed < 1.5 ms); // retry connection until OK ACK or timeout PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 275 Program and Debug Interface 25.6 PSoC 4 SWD Debug Interface Cortex-M0 DAP debugging features are classified into two types: invasive debugging and noninvasive debugging. Invasive debugging includes program halting and stepping, breakpoints, and data watchpoints. Noninvasive debugging includes instruction address profiling and device memory access, which includes the flash memory, SRAM, and other peripheral registers. ■ The breakpoint control register (CM0_BP_CTRL) is used to enable the BPU and store the number of hardware breakpoints supported by the debug system (four for CM0 DAP in PSoC 4). ■ Each hardware breakpoint has a Breakpoint Compare Register (CM0_BP_COMPx). It contains the enable bit for the breakpoint, the compare address value, and the match condition that will trigger a breakpoint debug event. The typical use case is that when an instruction fetch address matches the compare address of a breakpoint, a breakpoint event is generated and the processor is halted. The DAP has three major debug subsystems: ■ Debug Control and Configuration registers ■ Breakpoint Unit (BPU) – provides breakpoint support ■ Debug Watchpoint (DWT) – provides watchpoint support. Trace is not supported in Cortex-M0 Debug. See the ARMv6-M Architecture Reference Manual for complete details on the debug architecture. 25.6.1 Debug Control and Configuration Registers The debug control and configuration registers are used to execute firmware debugging. The registers and their key functions are as follows. See the ARMv6-M Architecture Reference Manual for complete bit level definitions of these registers. ■ Debug Halting Control and Status Register (CM0_DHCSR) – This register contains the control bits to enable debug, halt the CPU, and perform a singlestep operation. It also includes status bits for the debug state of the processor. ■ Debug Fault Status Register (CM0_DFSR) – This register describes the reason a debug event has occurred. This includes debug events, which are caused by a CPU halt, breakpoint event, or watchpoint event. ■ Debug Core Register Selector Register (CM0_DCRSR) – This register is used to select the general-purpose register in the Cortex-M0 CPU to which a read or write operation must be performed by the external debugger. ■ Debug Core Register Data Register (CM0_DCRDR) – This register is used to store the data to write to or read from the register selected in the CM0_DCRSR register. ■ Debug Exception and Monitor Control Register (CM0_DEMCR) – This register contains the enable bits for global debug watchpoint (DWT) block enable, reset vector catch, and hard fault exception catch. 25.6.2 Breakpoint Unit (BPU) The BPU provides breakpoint functionality on instruction fetches. The Cortex-M0 DAP in PSoC 4 supports up to four hardware breakpoints. Along with the hardware breakpoints, any number of software breakpoints can be created by using the BKPT instruction in the Cortex-M0. The BPU has two types of registers. 276 25.6.3 Data Watchpoint (DWT) The DWT provides watchpoint support on a data address access or a program counter (PC) instruction address. Trace is not supported by the Cortex-M0 in PSoC 4. The DWT supports two watchpoints. It also provides external program counter sampling using a PC sample register, which can be used for noninvasive coarse profiling of the program counter. The most important registers in the DWT are as follows. ■ The watchpoint compare (CM0_DWT_COMPx) registers store the compare values that are used by the watchpoint comparator for the generation of watchpoint events. Each watchpoint has an associated DWT_COMPx register. ■ The watchpoint mask (CM0_DWT_MASKx) registers store the ignore masks applied to the address range matching in the associated watchpoints. ■ The watchpoint function (CM0_DWT_FUNCTIONx) registers store the conditions that trigger the watchpoint events. They may be program counter watchpoint event or data address read/write access watchpoint events. A status bit is also set when the associated watchpoint event has occurred. ■ The watchpoint comparator PC sample register (CM0_DWT_PCSR) stores the current value of the program counter. This register is used for coarse, non-invasive profiling of the program counter register. 25.6.4 Debugging the PSoC 4 Device The host debugs the target PSoC 4 device by accessing the debug control and configuration registers, registers in the BPU, and registers in the DWT. All registers are accessed through the SWD interface; the SWD debug port (SW-DP) in the Cortex-M0 DAP converts the SWD packets to appropriate register access through the DAP-AHB interface. The first step in debugging the target PSoC 4 device is to acquire the SWD port. The acquire sequence consists of an SWD line reset sequence and read of the DAP SWDID through the SWD interface. The SWD port is acquired when the correct CM0 DAP SWDID is read from the target device. For the debug transactions to occur on the SWD interface, the corresponding pins should not be used for any other purpose. See the I/O System chapter on page 53 to understand PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Program and Debug Interface how to configure the SWD port pins, allowing them to be used only for SWD interface or for other functions such as LCD and GPIO. If debugging is required, the SWD port pins should not be used for other purposes. If only programming support is needed, the SWD pins can be used for other purposes. When the SWD port is acquired, the external debugger sets the C_DEBUGEN bit in the DHCSR register to enable debugging. Then, the different debugging operations such as stepping, halting, breakpoint configuration, and watchpoint configuration are carried out by writing to the appropriate registers in the debug system. 25.7 Debugging the target device is also affected by the overall device protection setting, which is explained in the Device Security chapter on page 93. Only the OPEN protected mode supports device debugging. Also, the external debugger loses connection to the target device when the device enters either Hibernate or Stop modes. The connection must be re-established after the device enters the Active mode again. The external debugger and the target device connection is not lost for a device transition from Active mode to either Sleep or Deep-Sleep modes. When the device enters the Active mode from either Deep-Sleep or Sleep modes, the debugger can resume its actions without initiating a connect sequence again. Registers Table 25-5. List of Registers Register Name Description CM0_DHCSR Debug Halting Control and Status Register CM0_DFSR Debug Fault Status Register CM0_DCRSR Debug Core Register Selector Register CM0_DCRDR Debug Core Register Data Register CM0_DEMCR Debug Exception and Monitor Control Register CM0_BP_CTRL Breakpoint control register CM0_BP_COMPx Breakpoint Compare Register CM0_DWT_COMPx Watchpoint Compare Register CM0_DWT_MASKx Watchpoint Mask Register CM0_DWT_FUNCTIONx Watchpoint Function Register CM0_DWT_PCSR Watchpoint Comparator PC Sample Register PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 277 Program and Debug Interface 278 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 26. Nonvolatile Memory Programming Nonvolatile memory programming refers to the programming of flash memory in the PSoC® 4Analog Coprocessor device. This chapter explains the different functions that are part of device programming, such as erase, write, program, and checksum calculation. Cypress-supplied programmers and other third-party programmers can use these functions to program the PSoC 4 device with the data in an application hex file. They can also be used to perform bootload operations where the CPU will update a portion of the flash memory. 26.1 Features ■ Supports programming through the debug and access port (DAP) and Cortex-M0 CPU ■ Supports both blocking and non-blocking flash program and erase operations from the Cortex-M0 CPU 26.2 Functional Description Flash programming operations are implemented as system calls. System calls are executed out of SROM in the privileged mode of operation. The user has no access to read or modify the SROM code. The DAP or the CM0 CPU requests the system call by writing the function opcode and parameters to the System Performance Controller Interface (SPCIF) input registers, and then requesting the SROM to execute the function. Based on the function opcode, the System Performance Controller (SPC) executes the corresponding system call from SROM and updates the SPCIF status register. The DAP or the CPU should read this status register for the pass/fail result of the function execution. As part of function execution, the code in SROM interacts with the SPCIF to do the actual flash programming operations. PSoC 4 flash is programmed using a Program Erase Program (PEP) sequence. The flash cells are all programmed to a known state, erased, and then the selected bits are programmed. This increases the life of the flash by balancing the stored charge. When writing to flash the data is first copied to a page latch buffer. The flash write functions are then used to transfer this data to flash. External programmers program the flash memory in PSoC 4 using the SWD protocol by sending the commands to the Debug and Access Port (DAP). The programming sequence for the PSoC 4 device with an external programmer is given in the PSoC 4 Device Programming Specifications. Flash memory can also be programmed by the CM0 CPU by accessing the relevant registers through the AHB interface. This type of programming is typically used to update a portion of the flash memory as part of a bootload operation, or other application requirements, such as updating a lookup table stored in the flash memory. All write operations to flash memory, whether from the DAP or from the CPU, are done through the SPCIF. Note It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or unexpected changes may be made to portions of the flash. Reset sources (see the Reset System chapter on page 89) include XRES pin, software reset, and watchdog; make sure that these are not inadvertently activated. In addition, the low-voltage detect circuits should be configured to generate an interrupt instead of a reset. Note PSoC 4 implements a User Supervisory Flash (SFlash), which can be used to store application-specific information. These rows are not part of the hex file; their programming is optional. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 279 Nonvolatile Memory Programming 26.3 System Call Implementation A system call consists of the following items: ■ Opcode: A unique 8-bit opcode ■ Parameters: Two 8-bit parameters are mandatory for all system calls. These parameters are referred to as key1 and key2, and are defined as follows: key1 = 0xB6 key2 = 0xD3 + Opcode The two keys are passed to ensure that the user system call is not initiated by mistake. If the key1 and key2 parameters are not correct, the SROM does not execute the function, and returns an error code. Apart from these two parameters, additional parameters may be required depending on the specific function being called. ■ Return Values: Some system calls also return a value on completion of their execution, such as the silicon ID or a checksum. ■ Completion Status: Each system call returns a 32-bit status that the CPU or DAP can read to verify success or determine the reason for failure. 26.4 Blocking and Non-Blocking System Calls System call functions can be categorized as blocking or non-blocking based on the nature of their execution. Blocking system calls are those where the CPU cannot execute any other task in parallel other than the execution of the system call. When a blocking system call is called from a process, the CPU jumps to the code corresponding in SROM. When the execution is complete, the original thread execution resumes. Non-blocking system calls allow the CPU to execute some other code in parallel and communicate the completion of interim system call tasks to the CPU through an interrupt. Non-blocking system calls are only used when the CPU initiates the system call. The DAP will only use system calls during the programming mode and the CPU is halted during this process. The three non-blocking system calls are Non-Blocking Write Row, Non-Blocking Program Row, and Resume Non-Blocking, respectively. All other system calls are blocking. Because the CPU cannot execute code from flash while doing an erase or program operation on the flash, the nonblocking system calls can only be called from a code executing out of SRAM. If the non-blocking functions are called from flash memory, the result is undefined and may return a bus error and trigger a hard fault when the flash fetch operation is being done. The System Performance Controller (SPC) is the block that generates the properly sequenced high-voltage pulses required for erase and program operations of the flash memory. When a non-blocking function is called from SRAM, the SPC timer triggers its interrupt when each of the sub-operations in a write or program operation is complete. Call the 280 Resume Non-Blocking function from the SPC interrupt service routine (ISR) to ensure that the subsequent steps in the system call are completed. Because the CPU can execute code only from the SRAM when a non-blocking write or program operation is being done, the SPC ISR should also be located in the SRAM. The SPC interrupt is triggered once in the case of a non-blocking program function or thrice in a non-blocking write operation. The Resume Non-Blocking function call done in the SPC ISR is called once in a nonblocking program operation and thrice in a non-blocking write operation. The pseudo code for using a non-blocking write system call and executing user code out of SRAM is given later in this chapter. 26.4.1 Performing a System Call The steps to initiate a system call are as follows: 1. Set up the function parameters: The two possible methods for preparing the function parameters (key1, key2, additional parameters) are: a. Write the function parameters to the CPUSS_SYSARG register: This method is used for functions that retrieve their parameters from the CPUSS_SYSARG register. The 32-bit CPUSS_SYSARG register must be written with the parameters in the sequence specified in the respective system call table. b. Write the function parameters to SRAM: This method is used for functions that retrieve their parameters from SRAM. The parameters should first be written in the specified sequence to consecutive SRAM locations. Then, the starting address of the SRAM, which is the address of the first parameter, should be written to the CPUSS_SYSARG register. This starting address should always be a word-aligned (32-bit) address. The system call uses this address to fetch the parameters. 2. Specify the system call using its opcode and initiating the system call: The 8-bit opcode should be written to the SYSCALL_COMMAND bits ([15:0]) in the CPUSS_SYSREQ register. The opcode is placed in the lower eight bits [7:0] and 0x00 be written to the upper eight bits [15:8]. To initiate the system call, set the SYSCALL_REQ bit (31) in the CPUSS_SYSREG register. Setting this bit triggers a non-maskable interrupt that jumps the CPU to the SROM code referenced by the opcode parameter. 3. Wait for the system call to finish executing: When the system call begins execution, it sets the PRIVILEGED bit in the CPUSS_SYSREQ register. This bit can be set only by the system call, not by the CPU or DAP. The DAP should poll the PRIVILEGED and SYSCALL_REQ bits in the CPUSS_SYSREG register continuously to check whether the system call is completed. Both these bits are cleared on completion of the system call. The maximum execution time is one second. If these two bits are not cleared after one second, the operation should be considered a failure and aborted without executing the following steps. Note that unlike the DAP, the CPU application code cannot poll these bits during system call PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming execution. This is because the CPU executes code out of the SROM during the system call. The application code can check only the final function pass/fail status after the execution returns from SROM. 4. Check the completion status: After the PRIVILEGED and SYSCALL_REQ bits are cleared to indicate completion of the system call, the CPUSS_SYSARG register should be read to check for the status of the system call. If the 32-bit value read from the CPUSS_SYSARG register is 0xAXXXXXXX (where ‘X’ denotes don’t care hex values), the system call was successfully executed. For a failed system call, the status code is 0xF00000YY where YY indicates the reason for failure. See Table 26-1 for the complete list of status codes and their description. 5. Retrieve the return values: For system calls that return values such as silicon ID and checksum, the CPU or DAP should read the CPUSS_SYSREG and CPUSS_SYSARG registers to fetch the values returned. 26.5 System Calls Table 26-1 lists all the system calls supported in PSoC 4 along with the function description and availability in device protection modes. See the Device Security chapter on page 93 for more information on the device protection settings. Note that some system calls cannot be called by the CPU as given in the table. Detailed information on each of the system calls follows the table. Table 26-1. List of System Calls System Call DAP Access Description Open Protected Kill CPU Access Silicon ID Returns the device Silicon ID, Family ID, and Revision ID ✔ ✔ – ✔ Load Flash Bytes Loads data to the page latch buffer to be programmed later into the flash row, in 1 byte granularity, for a row size of 128 bytes ✔ – – ✔ Write Row Erases and then programs a row of flash with data in the page latch buffer ✔ – – ✔ Program Row Programs a row of flash with data in the page latch buffer ✔ – – ✔ Erase All Erases all user code in the flash array; the flash row-level protection data in the supervisory flash area ✔ – – Checksum Calculates the checksum over the entire flash memory (user and supervisory area) or checksums a single row of flash ✔ ✔ – Write Protection This programs both flash row-level protection settings and chip-level protection settings into the supervisory flash (row 0) ✔ ✔ – – – – ✔ Erases and then programs a row of flash with data in the page latch bufNon-Blocking Write Row fer. During program/erase pulses, the user may execute code from SRAM. This function is meant only for CPU access ✔ Non-Blocking Program Row Programs a row of flash with data in the page latch buffer. During program/erase pulses, the user may execute code from SRAM. This function is meant only for CPU access – – – ✔ Resume Non-Blocking Resumes a non-blocking write row or non-blocking program row. This function is meant only for CPU access – – – ✔ 26.5.1 Silicon ID This function returns a 12-bit family ID, 16-bit silicon ID, and an 8-bit revision ID, and the current device protection mode. These values are returned to the CPUSS_SYSARG and CPUSS_SYSREQ registers. Parameters are passed through the CPUSS_SYSARG and CPUSS_SYSREQ registers. Parameters Address Value to be Written Description CPUSS_SYSARG Register Bits [7:0] 0xB6 Key1 Bits [15:8] 0xD3 Key2 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 281 Nonvolatile Memory Programming Address Bits [31:16] Value to be Written Description 0x0000 Not used Bits [15:0] 0x0000 Silicon ID opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [7:0] Silicon ID Lo Bits [15:8] Silicon ID Hi Bits [19:16] Minor Revision Id Bits [23:20] Major Revision Id See the PSoC 4 Device Programming Specifications for these values Bits [27:24] 0xXX Not used (don’t care) Bits [31:28] 0xA Success status code See the device datasheet for Silicon ID values for different part numbers CPUSS_SYSREQ register Family ID is 0x093 for PSoC 4200 and PSoC 4100 Bits [11:0] Family ID Bits [15:12] Chip Protection See the Device Security chapter on page 93 Bits [31:16] 0xXXXX Not used 26.5.2 Load Flash Bytes This function loads the page latch buffer with data to be programmed into a row of flash. The load size can range from 1-byte to the maximum number of bytes in a flash rowwhich is 128 bytes. Data is loaded into the page latch buffer starting at the location specified by the “Byte Addr” input parameter. Data loaded into the page latch buffer remains until a program operation is performed, which clears the page latch contents. The parameters for this function, including the data to be loaded into the page latch, are written to the SRAM; the starting address of the SRAM data is written to the CPUSS_SYSARG register. Note that the starting parameter address should be a word-aligned address. Parameters Address Value to be Written Description SRAM Address - 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Bits [15:8] 0xD7 Key1 Key2 Start address of page latch buffer to write data Bits [23:16] Byte Addr 0x00 – Byte 0 of latch buffer 0x7F – Byte 127 of latch buffer 0x00 – Flash Macro 0 Bits [31:24] Flash Macro Select 0x01 – Flash Macro 1 (Refer to the Cortex-M0 CPU chapter on page 31 for the number of flash macros in the device) SRAM Address- 32’hYY + 0x04 Number of bytes to be written to the page latch buffer. Bits [7:0] 282 Load Size 0x00 – 1 byte 0x7F – 128 bytes PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming Address Value to be Written Description Bits [15:8] 0xXX Don’t care parameter Bits [23:16] 0xXX Don’t care parameter Bits [31:24] 0xXX Don’t care parameter SRAM Address- From (32’hYY + 0x08) to (32’hYY + 0x08 + Load Size) Byte 0 Data Byte [0] First data byte to be loaded . . . . . . Byte (Load size –1) Data Byte [Load size –1] Last data byte to be loaded 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0004 Load Flash Bytes opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit CPUSS_SYSARG register Bits [31:0] CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.3 Write Row This function erases and then programs the addressed row of flash with the data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The parameters for this function are stored in SRAM. The start address of the stored parameters is written to the CPUSS_SYSARG register. This function clears the page latch buffer contents after the row is programmed. Usage Requirements: Call the Load Flash Bytes function before calling this function. This function can do a write operation only if the corresponding flash row is not write protected. Note that this system call disables the 36-MHz IMO output before performing the flash write operation. The 36-MHz IMO output can be used to source the analog switch pump or the CTBm pump. If the 36-MHz IMO output is used, it must be manually re-enabled after the system call completes. Specifically, the CLK_IMO_CONFIG EN_CLK36 and FLASHPUMP_SEL must be reset. Refer to the CLK_IMO_CONFIG register in the PSoC 4100/4200 Family: PSoC 4 Registers TRM for more information. Parameters Address Value to be Written Description SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xD8 Key2 Bits [31:16] Row ID Row number to write 0x0000 – Row 0 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0005 Write Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit CPUSS_SYSARG register Bits [31:0] CPUSS_SYSREQ register PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 283 Nonvolatile Memory Programming Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.4 Program Row This function programs the addressed row of the flash, with data in the page latch buffer. If all data in the page latch buffer is 0, then the program is skipped. The row must be in an erased state before calling this function. This clears the page latch buffer contents after the row is programmed. Usage Requirements: Call the Load Flash Bytes function before calling this function. The row must be in an erased state before calling this function. This function can do a program operation only if the corresponding flash row is not write-protected. Parameters Address Value to be Written Description SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xD9 Key2 Bits [31:16] Row ID Row number to program 0x0000 – Row 0 CPUSS_SYSARG register 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0006 Program Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Bits [31:0] CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.5 Erase All This function erases all the user code in the flash main arrays and the row-level protection data in supervisory flash row 0 of each flash macro. Usage Requirements: This API can be called only from the DAP in the programming mode and only if the chip protection mode is OPEN. If the chip protection mode is PROTECTED, then the Write Protection API must be used by the DAP to change the protection settings to OPEN. Changing the protection setting from PROTECTED to OPEN automatically does an erase all operation. Parameters Address Value to be Written Description SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDD Key2 Bits [31:16] 0xXXXX Don’t care 284 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming Address Value to be Written Description CPUSS_SYSARG register 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x000A Erase All opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Bits [31:0] CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.6 Checksum This function reads either the whole flash memory or a row of flash and returns the 24-bit sum of each byte read in that flash region. When performing a checksum on the whole flash, the user code and supervisory flash regions are included. When performing a checksum only on one row of flash, the flash row number is passed as a parameter. Bytes 2 and 3 of the parameters select whether the checksum is performed on the whole flash memory or a row of user code flash. Parameters Address Value to be Written Description CPUSS_SYSARG register Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDE Key2 Selects the flash row number on which the checksum operation is done Bits [31:16] Row number – 16 bit flash row number Row ID or 0x8000 – Checksum is performed on entire flash memory CPUSS_SYSREQ register Bits [15:0] 0x000B Checksum opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Bits [27:24] 0xX Not used (don’t care) Bits [23:0] Checksum 24-bit checksum value of the selected flash region 26.5.7 Success status code Write Protection This function programs both the flash row-level protection settings and the device protection settings in the supervisory flash row. The flash row-level protection settings are programmed separately for each flash macro in the device. Each row has a single protection bit. The total number of protection bytes is the number of flash rows divided by eight. The chip-level protection settings (1-byte) are stored in flash macro zero in the last byte location in row zero of the supervisory flash. The size of the supervisory flash row is the same as the user code flash row size. Usage Requirements: The Load Flash Bytes function is used to load the flash protection bytes of a flash macro into the page PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 285 Nonvolatile Memory Programming latch buffer corresponding to the macro. The starting address parameter for the load function should be zero. The flash macro number should be one that needs to be programmed; the number of bytes to load is the number of flash protection bytes in that macro. Then, the Write Protection function is called, which programs the flash protection bytes from the page latch to be the corresponding flash macro’s supervisory row. In flash macro zero, which also stores the device protection settings, the device level protection setting is passed as a parameter in the CPUSS_SYSARG register. Parameters Address Value to be Written Description CPUSS_SYSARG register Bits [7:0] 0xB6 Key1 Bits [15:8] 0xE0 Key2 Parameter applicable only for Flash Macro 0 Bits [23:16] Device Protection Byte 0x01 – OPEN mode 0x02 – PROTECTED mode 0x04 – KILL mode Bits [31:24] Flash Macro Select 0x00 – Flash Macro 0 0x01 – Flash Macro 1 CPUSS_SYSREQ register Bits [15:0] 0x000D Write Protection opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:24] 0xX Not used (don’t care) Bits [23:0] 0x000000 26.5.8 Non-Blocking Write Row This function is used when a flash row needs to be written by the CM0 CPU in a non-blocking manner, so that the CPU can execute code from SRAM while the write operation is being done. The explanation of non-blocking system calls is explained in Blocking and Non-Blocking System Calls on page 280. The non-blocking write row system call has three phases: Pre-program, Erase, Program. Pre-program is the step in which all of the bits in the flash row are written a ‘1’ in preparation for an erase operation. The erase operation clears all of the bits in the row, and the program operation writes the new data to the row. While each phase is being executed, the CPU can execute code from SRAM. When the non-blocking write row system call is initiated, the user cannot call any system call function other than the Resume Non-Blocking function, which is required for completion of the non-blocking write operation. After the completion of each phase, the SPC triggers its interrupt. In this interrupt, call the Resume Non-Blocking system call. Note The device firmware must not attempt to put the device to sleep during a non-blocking write row. This will reset the page latch buffer and the flash will be written with all zeroes. Usage Requirements: Call the Load Flash Bytes function before calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking write row function can be called only from the SRAM. This is because the CM0 CPU cannot execute code from flash while doing the flash erase program operations. If this function is called from the flash memory, the result is undefined, and may return a bus error and trigger a hard fault when the flash fetch operation is being done. 286 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming Parameters Address Value to be Written Description SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDA Key2 Bits [31:16] Row ID Row number to write 0x0000 – Row 0 CPUSS_SYSARG register 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0007 Non-Blocking Write Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Bits [31:0] CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.9 Non-Blocking Program Row This function is used when a flash row needs to be programmed by the CM0 CPU in a non-blocking manner, so that the CPU can execute code from the SRAM when the program operation is being done. The explanation of non-blocking system calls is explained in Blocking and Non-Blocking System Calls on page 280. While the program operation is being done, the CPU can execute code from the SRAM. When the non-blocking program row system call is called, the user cannot call any other system call function other than the Resume Non-Blocking function, which is required for the completion of the non-blocking write operation. Unlike the Non-Blocking Write Row system call, the Program system call only has a single phase. Therefore, the Resume Non-Blocking function only needs to be called once from the SPC interrupt when using the Non-Blocking Program Row system call. Usage Requirements: Call the Load Flash Bytes function before calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking program row function can be called only from SRAM. This is because the CM0 CPU cannot execute code from flash while doing flash program operations. If this function is called from flash memory, the result is undefined, and may return a bus error and trigger a hard fault when the flash fetch operation is being done. Parameters Address Value to be Written Description SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDB Key2 Bits [31:16] Row ID Row number to write 0x0000 – Row 0 CPUSS_SYSARG register 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0008 Non-Blocking Program Row opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit Bits [31:0] CPUSS_SYSREQ register PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 287 Nonvolatile Memory Programming Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.5.10 Resume Non-Blocking This function completes the additional phases of erase and program that were started using the non-blocking write row and non-blocking program row system calls. This function must be called thrice following a call to Non-Blocking Write Row or once following a call to Non-Blocking Program Row from the SPC ISR. No other system calls can execute until all phases of the program or erase operation are complete. More details on the procedure of using the non-blocking functions are explained in Blocking and Non-Blocking System Calls on page 280. Parameters Address Value to be Written Description SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address) Bits [7:0] 0xB6 Key1 Bits [15:8] 0xDC Key2 Bits [31:16] 0xXXXX Don’t care. Not used by SROM 32’hYY 32-bit word-aligned address of the SRAM that stores the first function parameter (key1) Bits [15:0] 0x0009 Resume Non-Blocking opcode Bits [31:16] 0x8000 Set SYSCALL_REQ bit CPUSS_SYSARG register Bits [31:0] CPUSS_SYSREQ register Return Address Return Value Description CPUSS_SYSARG register Bits [31:28] 0xA Success status code Bits [27:0] 0xXXXXXXX Not used (don’t care) 26.6 System Call Status At the end of every system call, a status code is written over the arguments in the CPUSS_SYSARG register. A success status is 0xAXXXXXXX, where X indicates don’t care values or return data in the case of the system calls that return a value. A failure status is indicated by 0xF00000XX, where XX is the failure code. 288 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming Table 26-2. System Call Status Codes Status Code (32-bit value in CPUSS_SYSARG register) AXXXXXXXh Description Success – The “X” denotes a don’t care value, which has a value of ‘0’ returned by the SROM, unless the API returns parameters directly to the CPUSS_SYSARG register. F0000001h Invalid Chip Protection Mode – This API is not available during the current chip protection mode. F0000003h Invalid Page Latch Address – The address within the page latch buffer is either out of bounds or the size provided is too large for the page address. F0000004h Invalid Address – The row ID or byte address provided is outside of the available memory. F0000005h Row Protected – The row ID provided is a protected row. F0000007h Resume Completed – All non-blocking APIs have completed. The resume API cannot be called until the next non-blocking API. F0000008h Pending Resume – A non-blocking API was initiated and must be completed by calling the resume API, before any other APIs may be called. F0000009h System Call Still In Progress – A resume or non-blocking is still in progress. The SPC ISR must fire before attempting the next resume. F000000Ah Checksum Zero Failed – The calculated checksum was not zero. F000000Bh Invalid Opcode – The opcode is not a valid API opcode. F000000Ch Key Opcode Mismatch – The opcode provided does not match key1 and key2. F000000Eh Invalid Start Address – The start address is greater than the end address provided. 26.7 Non-Blocking System Call Pseudo Code This section contains pseudo code to demonstrate how to set up a non-blocking system call and execute code out of SRAM during the flash programming operations. #define #define #define #define #define REG(addr) CM0_ISER_REG CPUSS_CONFIG_REG CPUSS_SYSREQ_REG CPUSS_SYSARG_REG #define ROW_SIZE_128 #define ROW_SIZE (*((volatile uint32 *) (addr))) REG( 0xE000E100 ) REG( 0x40100000 ) REG( 0x40100004 ) REG( 0x40100008 ) (128) (ROW_SIZE_128) /*Variable to keep track of how many times SPC ISR is triggered */ __ram int iStatusInt = 0x00; __flash int main(void) { DoUserStuff(); /*CM0 interrupt enable bit for spc interrupt enable */ CM0_ISER_REG |= 0x00000040; /*Set CPUSS_CONFIG.VECS_IN_RAM because SPC ISR should be in SRAM */ CPUSS_CONFIG_REG |= 0x00000001; /*Call non-blocking write row API */ NonBlockingWriteRow(); PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 289 Nonvolatile Memory Programming /*End Program */ while(1); } __sram void SpcIntHandler(void) { /* Write key1, key2 parameters to SRAM */ REG( 0x20000000 ) = 0x0000DCB6; /*Write the address of key1 to the CPUSS_SYSARG reg */ CPUSS_SYSARG_REG = 0x20000000; /*Write the API opcode = 0x09 to the CPUSS_SYSREQ.COMMAND * register and assert the sysreq bit */ CPUSS_SYSREQ_REG = 0x80000009; /* Number of times the ISR has triggered */ iStatusInt ++; } __sram void NonBlockingWriteRow(void) { int iter; /*Load the Flash page latch with data to write*/ * Write key1, key2, byte address, and macro sel parameters to SRAM */ REG( 0x20000000 ) = 0x0000D7B6; //Write load size param (128bytes) to SRAM REG( 0x20000004 ) = 0x0000007F; for(i = 0; i < ROW_SIZE/4; i += 1) { REG( 0x20000008 + i*4 ) = 0xDADADADA; } /*Write the address of the key1 param to CPUSS_SYSARG reg*/ CPUSS_SYSARG_REG = 0x20000000; /*Write the API opcode = 0x04 to CPUSS_SYSREQ.COMMAND * register and assert the sysreq bit */ CPUSS_SYSREQ_REG = 0x80000004; /*Perform Non-Blocking Write Row on Row 200 as an example. * Write key1, key2, row id to SRAM row id = 0xC8 -> which is row 200 */ REG( 0x20000000 ) = 0x00C8DAB6; /*Write the address of the key1 param to CPUSS_SYSARG reg */ CPUSS_SYSARG_REG = 0x20000000; /*Write the API opcode = 0x07 to CPUSS_SYSREQ.COMMAND * register and assert the sysreq bit */ CPUSS_SYSREQ_REG = 0x80000007; /*Execute user code until iStatusInt equals 3 to signify 290 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Nonvolatile Memory Programming * 3 SPC interrupts have happened. This should be 1 in case * of non-blocking program System Call */ while( iStatusInt != 0x03 ) { DoOtherUserStuff(); } /* Get the success or failure status of System Call*/ syscall_status = CPUSS_SYSARG_REG; } In the code, the CM0 exception table is configured to be in SRAM by writing 0x01 to the CPUSS_CONFIG register. The SRAM exception table should have the vector address of the SPC interrupt as the address of the SpcIntHandler() function, which is also defined to be in SRAM. See the Interrupts chapter on page 37 for details on configuring the CM0 exception table to be in SRAM. The pseudo code for a non-blocking program system call is also similar, except that the function opcode and parameters will differ and the iStatusInt variable should be polled for 1 instead of 3. This is because the SPC ISR will be triggered only once for a non-blocking program system call. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 291 Nonvolatile Memory Programming 292 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. A accumulator In a CPU, a register in which intermediate results are stored. Without an accumulator, it is necessary to write the result of each calculation (addition, subtraction, shift, and so on.) to main memory and read them back. Access to main memory is slower than access to the accumulator, which usually has direct paths to and from the arithmetic and logic unit (ALU). active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. active low 1. A logic signal having its asserted state as the logic 0 state. 2. A logic signal having its logic 1 state as the lower voltage of the two states: inverted logic. address The label or number identifying the memory location (RAM, ROM, or register) where a unit of information is stored. algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation. ambient temperature The temperature of the air in a designated area, particularly the area surrounding the PSoC device. analog See analog signals. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog output An output that is capable of driving any voltage between the supply rails, instead of just a logic 1 or logic 0. analog signals A signal represented in a continuous form with respect to continuous times, as contrasted with a digital signal represented in a discrete (discontinuous) form in a sequence of time. analog-to-digital (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 293 Glossary AND See Boolean Algebra. API (Application Programming Interface) A series of software routines that comprise an interface between a computer application and lower-level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. array An array, also known as a vector or list, is one of the simplest data structures in computer programming. Arrays hold a fixed number of equally-sized data elements, generally of the same data type. Individual elements are accessed by index using a consecutive range of integers, as opposed to an associative array. Most high-level programming languages have arrays as a builtin data type. Some arrays are multi-dimensional, meaning they are indexed by a fixed number of integers; for example, by a group of two integers. One- and two-dimensional arrays are the most common. Also, an array can be a group of capacitors or resistors connected in some common form. assembly A symbolic representation of the machine language of a specific processor. Assembly language is converted to machine code by an assembler. Usually, each line of assembly code produces one machine instruction, though the use of macros is common. Assembly languages are considered low-level languages; where as C is considered a high-level language. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. attenuation The decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector, but not including the reduction due to geometric spreading. Attenuation is usually expressed in dB. B bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. bias current 294 The constant low-level DC current that is used to produce a stable operation in amplifiers. This current can sometimes be changed to alter the bandwidth of an amplifier. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary binary The name for the base 2 numbering system. The most common numbering system is the base 10 numbering system. The base of a numbering system indicates the number of values that may exist for a particular positioning within a number for that system. For example, in base 2, binary, each position may have one of two values (0 or 1). In the base 10, decimal, numbering system, each position may have one of ten values (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). bit A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8 bits is called a byte. Because the PSoC's M8CP is an 8-bit microcontroller, the PSoC devices's native data chunk size is a byte. bit rate (BR) The number of bits occurring per unit of time in a bit stream, usually expressed in bits per second (bps). block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. Boolean Algebra In mathematics and computer science, Boolean algebras or Boolean lattices, are algebraic structures which "capture the essence" of the logical operations AND, OR and NOT as well as the set theoretic operations union, intersection, and complement. Boolean algebra also defines a set of theorems that describe how Boolean equations can be manipulated. For example, these theorems are used to simplify Boolean equations, which will reduce the number of logic elements needed to implement the equation. The operators of Boolean algebra may be represented in various ways. Often they are simply written as AND, OR, and NOT. In describing circuits, NAND (NOT AND), NOR (NOT OR), XNOR (exclusive NOT OR), and XOR (exclusive OR) may also be used. Mathematicians often use + (for example, A+B) for OR and for AND (for example, A*B) (in some ways those operations are analogous to addition and multiplication in other algebraic structures) and represent NOT by a line drawn above the expression being negated (for example, ~A, A_, !A). break-before-make The elements involved go through a disconnected state entering (‘break”) before the new connected state (“make”). broadcast net A signal that is routed throughout the microcontroller and is accessible by many blocks or systems. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. byte A digital storage unit consisting of 8 bits. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 295 Glossary C C A high-level programming language. capacitance A measure of the ability of two adjacent conductors, separated by an insulator, to hold a charge when a voltage differential is applied between them. Capacitance is measured in units of Farads. capture To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file. chaining Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another. checksum The checksum of a set of data is generated by adding the value of each data word to a sum. The actual checksum can simply be the result sum or a value that must be added to the sum to generate a pre-determined value. clear To force a bit/register to a value of logic ‘0’. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. clock generator A circuit that is used to generate a clock signal. CMOS The logic gates constructed using MOS transistors connected in a complementary manner. CMOS is an acronym for complementary metal-oxide semiconductor. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high-level language, such as C, into machine language. configuration In a computer system, an arrangement of functional units according to their nature, number, and chief characteristics. Configuration pertains to hardware, software, firmware, and documentation. The configuration will affect system performance. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crowbar A type of over-voltage protection that rapidly places a low-resistance shunt (typically an SCR) from the signal to one of the power supply rails, when the output voltage exceeds a predetermined value. CPUSS CPU subsystem crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. 296 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary cyclic redundancy check (CRC) A calculation used to detect errors in data communications, typically performed using a linear feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. D data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. data stream A sequence of digitally encoded signals used to represent information in transmission. data transmission Sending data from one place to another by means of signals over a channel. debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. decimal A base-10 numbering system, which uses the symbols 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 (called digits) together with the decimal point and the sign symbols + (plus) and - (minus) to represent numbers. default value Pertaining to the pre-defined initial, original, or specific setting, condition, value, or action a system will assume, use, or take in the absence of instructions from the user. device The device referred to in this manual is the PSoC device, unless otherwise specified. die An non-packaged integrated circuit (IC), normally cut from a wafer. digital A signal or function, the amplitude of which is characterized by one of two discrete values: ‘0’ or ‘1’. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital logic A methodology for dealing with expressions containing two-state variables that describe the behavior of a circuit or system. digital-to-analog (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC) converter performs the reverse operation. direct access The capability to obtain data from a storage device, or to enter data into a storage device, in a sequence independent of their relative positions by means of addresses that indicate the physical location of the data. duty cycle The relationship of a clock period high time to its low time, expressed as a percent. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 297 Glossary E External Reset (XRES_N) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. F falling edge A transition from a logic 1 to a logic 0. Also known as a negative edge. feedback The return of a portion of the output, or processed portion of the output, of a (usually active) device to the input. filter A device or process by which certain frequency components of a signal are attenuated. firmware The software that is embedded in a hardware device and executed by the CPU. The software may be executed by the end user, but it may not be modified. flag Any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission). Flash An electrically programmable and erasable, volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Nonvolatile means that the data is retained when power is off. Flash bank A group of flash ROM blocks where flash block numbers always begin with ‘0’ in an individual flash bank. A flash bank also has its own block level protection information. Flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected. A flash block holds 64 bytes. flip-flop A device having two stable states and two input terminals (or types of input signals) each of which corresponds with one of the two states. The circuit remains in either state until it is made to change to the other state by application of the corresponding signal. frequency The number of cycles or events per unit of time, for a periodic function. G gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. gate 1. A device having one output channel and one or more input channels, such that the output channel state is completely determined by the input channel states, except during switching transients. 2. One of many types of combinational logic elements having at least two inputs (for example, AND, OR, NAND, and NOR (also see Boolean Algebra)). 298 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary ground 1. The electrical neutral line having the same potential as the surrounding earth. 2. The negative side of DC power supply. 3. The reference point for an electrical system. 4. The conducting paths between an electric circuit or equipment and the earth, or some conducting body serving in place of the earth. H hardware A comprehensive term for all of the physical parts of a computer or embedded system, as distinguished from the data it contains or operates on, and the software that provides instructions for the hardware to accomplish tasks. hardware reset A reset that is caused by a circuit, such as a POR, watchdog reset, or external reset. A hardware reset restores the state of the device as it was when it was first powered up. Therefore, all registers are set to the POR value as indicated in register tables throughout this document. hexadecimal A base 16 numeral system (often abbreviated and called hex), usually written using the symbols 0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits. Compare the binary, hex, and decimal representations: bin = hex = dec 0000b = 0x0 = 0 0001b = 0x1 = 1 0010b = 0x2 = 2 ... 1001b = 0x9 = 9 1010b = 0xA = 10 1011b = 0xB = 11 ... 1111b = 0xF = 15 So the decimal numeral 79 whose binary representation is 0100 1111b can be written as 4Fh in hexadecimal (0x4F). high time The amount of time the signal has a value of ‘1’ in one period, for a periodic digital signal. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 299 Glossary I I2C A two-wire serial computer bus by Phillips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bidirectional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 Kbps in standard mode and 400 Kbps in fast mode. idle state A condition that exists whenever user messages are not being transmitted, but the service is immediately available for use. impedance 1. The resistance to the flow of current caused by resistive, capacitive, or inductive devices in a circuit. 2. The total passive opposition offered to the flow of electric current. Note the impedance is determined by the particular combination of resistance, inductive reactance, and capacitive reactance in a given circuit. input A point that accepts data, in a device, process, or channel. input/output (I/O) A device that introduces data into or extracts data from a system. instruction An expression that specifies one operation and identifies its operands, if any, in a programming language such as C or assembly. instruction mnemonics A set of acronyms that represent the opcodes for each of the assembly-language instructions, for example, ADD, SUBB, MOV. integrated circuit (IC) A device in which components such as resistors, capacitors, diodes, and transistors are formed on the surface of a single piece of semiconductor. interface The means by which two systems or devices are connected and interact with each other. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the M8CP receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. J jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. 300 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary L latency The time or delay that it takes for a signal to pass through a given circuit or network. least significant bit (LSb) The binary digit, or bit, in a binary number that represents the least significant value (typically the right-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in LSb. least significant byte (LSB) The byte in a multi-byte word that represents the least significant values (typically the right-hand byte). The byte versus bit distinction is made by using an upper case “B” for byte in LSB. Linear Feedback Shift Register (LFSR) A shift register whose data input is generated as an XOR of two or more elements in the register chain. load The electrical demand of a process expressed as power (watts), current (amps), or resistance (ohms). logic function A mathematical function that performs a digital operation on digital data and returns a digital value. lookup table (LUT) A logic block that implements several logic functions. The logic function is selected by means of select lines and is applied to the inputs of the block. For example: A 2 input LUT with 4 select lines can be used to perform any one of 16 logic functions on the two inputs resulting in a single logic output. The LUT is a combinational device; therefore, the input/output relationship is continuous, that is, not sampled. low time The amount of time the signal has a value of ‘0’ in one period, for a periodic digital signal. low-voltage detect (LVD) A circuit that senses VDDD and provides an interrupt to the system when VDDD falls below a selected threshold. M M8CP An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside a PSoC device by interfacing to the flash, SRAM, and register space. macro A programming language macro is an abstraction, whereby a certain textual pattern is replaced according to a defined set of rules. The interpreter or compiler automatically replaces the macro instance with the macro contents when an instance of the macro is encountered. Therefore, if a macro is used five times and the macro definition required 10 bytes of code space, 50 bytes of code space will be needed in total. mask 1. To obscure, hide, or otherwise prevent information from being derived from a signal. It is usually the result of interaction with another signal, such as noise, static, jamming, or other forms of interference. 2. A pattern of bits that can be used to retain or suppress segments of another pattern of bits, in computing and data processing systems. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 301 Glossary master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. microcontroller An integrated circuit device that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of devices, thus achieving maximal possible miniaturization. This in turn, will reduce the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mnemonic A tool intended to assist the memory. Mnemonics rely on not only repetition to remember facts, but also on creating associations between easy-to-remember constructs and lists of data. A two to four character string representing a microprocessor instruction. mode A distinct method of operation for software or hardware. For example, the Digital PSoC block may be in either counter mode or timer mode. modulation A range of techniques for encoding information on a carrier signal, typically a sine-wave signal. A device that performs modulation is known as a modulator. Modulator A device that imposes a signal on a carrier. MOS An acronym for metal-oxide semiconductor. most significant bit (MSb) The binary digit, or bit, in a binary number that represents the most significant value (typically the left-hand bit). The bit versus byte distinction is made by using a lower case “b” for bit in MSb. most significant byte (MSB) The byte in a multi-byte word that represents the most significant values (typically the left-hand byte). The byte versus bit distinction is made by using an upper case “B” for byte in MSB. multiplexer (mux) 1. A logic function that uses a binary value, or address, to select between a number of inputs and conveys the data from the selected input to the output. 2. A technique which allows different input (or output) signals to use the same lines at different times, controlled by an external signal. Multiplexing is used to save on wiring and I/O ports. N NAND See Boolean Algebra. negative edge A transition from a logic 1 to a logic 0. Also known as a falling edge. net The routing between devices. nibble A group of four bits, which is one-half of a byte. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. 302 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary NOR See Boolean Algebra. NOT See Boolean Algebra. O OR See Boolean Algebra. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. output The electrical signal or signals which are produced by an analog or digital block. P parallel The means of communication in which digital data is sent multiple bits at a time, with each simultaneous bit being sent over a separate line. parameter Characteristics for a given block that have either been characterized or may be defined by the designer. parameter block A location in memory where parameters for the SSC instruction are placed prior to execution. parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). path 1. The logical sequence of instructions executed by a computer. 2. The flow of an electrical signal through a circuit. pending interrupts An interrupt that is triggered but not serviced, either because the processor is busy servicing another interrupt or global interrupts are disabled. phase The relationship between two signals, usually the same frequency, that determines the delay between them. This delay between signals is either measured by time or angle (degrees). pin A terminal on a hardware component. Also called lead. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts will involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. positive edge A transition from a logic 0 to a logic 1. Also known as a rising edge. posted interrupts An interrupt that is detected by the hardware but may or may not be enabled by its mask bit. Posted interrupts that are not masked become pending interrupts. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 303 Glossary Power On Reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. program counter The instruction pointer (also called the program counter) is a register in a computer processor that indicates where in memory the CPU is executing instructions. Depending on the details of the particular machine, it holds either the address of the instruction being executed, or the address of the next instruction to be executed. protocol A set of rules. Particularly the rules that govern networked communications. PSoC® Cypress’s Programmable System-on-Chip (PSoC®) devices. PSoC blocks See analog blocks and digital blocks. PSoC Creator™ The software for Cypress’s next generation Programmable System-on-Chip technology. pulse A rapid change in some characteristic of a signal (for example, phase or frequency), from a baseline value to a higher or lower value, followed by a rapid return to the baseline value. pulse width modulator (PWM) An output in the form of duty cycle which varies as a function of the applied measure. R RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a know state. See hardware reset and software reset. resistance The resistance to the flow of electric current measured in ohms for a conductor. revision ID A unique identifier of the PSoC device. ripple divider An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2n - 1. rising edge See positive edge. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. routine A block of code, called by another block of code, that may have some general or frequent use. routing Physically connecting objects in a design according to design rules set in the reference library. 304 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary runt pulses In digital circuits, narrow pulses that, due to non-zero rise and fall times of the signal, do not reach a valid high or low level. For example, a runt pulse may occur when switching between asynchronous clocks or as the result of a race condition in which a signal takes two separate paths through a circuit. These race conditions may have different delays and are then recombined to form a glitch or when the output of a flip-flop becomes metastable. S sampling The process of converting an analog signal into a series of digital values or reversed. schematic A diagram, drawing, or sketch that details the elements of a system, such as the elements of an electrical circuit or the elements of a logic diagram for a computer. seed value An initial value loaded into a linear feedback shift register or random number generator. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. set To force a bit/register to a value of logic 1. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift The movement of each bit in a word one position to either the left or right. For example, if the hex value 0x24 is shifted one place to the left, it becomes 0x48. If the hex value 0x24 is shifted one place to the right, it becomes 0x12. shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. sign bit The most significant binary digit, or bit, of a signed binary number. If set to a logic 1, this bit represents a negative quantity. signal A detectable transmitted energy that can be used to carry information. As applied to electronics, any transmitted electrical impulse. silicon ID A unique identifier of the PSoC silicon. skew The difference in arrival time of bits transmitted at the same time, in parallel transmission. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. software A set of computer programs, procedures, and associated documentation about the operation of a data processing system (for example, compilers, library routines, manuals, and circuit diagrams). Software is often written first as source code, and then converted to a binary format that is specific to the device on which the code will be executed. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 305 Glossary software reset A partial reset executed by software to bring part of the system back to a known state. A software reset will restore the M8CP to a know state but not PSoC blocks, systems, peripherals, or registers. For a software reset, the CPU registers (CPU_A, CPU_F, CPU_PC, CPU_SP, and CPU_X) are set to 0x00. Therefore, code execution will begin at flash address 0x0000. SRAM An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, when a value is loaded into an SRAM cell, it will remain unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code, operating from flash. stack A stack is a data structure that works on the principle of Last In First Out (LIFO). This means that the last item put on the stack is the first item that can be taken off. stack pointer A stack may be represented in a computer’s inside blocks of memory cells, with the bottom at a fixed location and a variable stack pointer to the current top cell. state machine The actual implementation (in hardware or software) of a function that can be considered to consist of a set of states through which it sequences. sticky A bit in a register that maintains its value past the time of the event that caused its transition, has passed. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. switching The controlling or routing of signals in circuits to execute logical or arithmetic operations, or to transmit data between specific points in a network. switch phasing The clock that controls a given switch, PHI1 or PHI2, in respect to the switch capacitor (SC) blocks. The PSoC SC blocks have two groups of switches. One group of these switches is normally closed during PHI1 and open during PHI2. The other group is open during PHI1 and closed during PHI2. These switches can be controlled in the normal operation, or in reverse mode if the PHI1 and PHI2 clocks are reversed. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. T tap The connection between two blocks of a device created by connecting several blocks/components in a series, such as a shift register or resistive voltage divider. terminal count The state at which a counter is counted down to zero. 306 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Glossary threshold The minimum value of a signal that can be detected by the system or sensor under consideration. Thumb-2 The Thumb-2 instruction set is a highly efficient and powerful instruction set that delivers significant benefits in terms of ease of use, code size, and performance. The Thumb-2 instruction set is a superset of the previous 16-bit Thumb instruction set, with additional 16-bit instructions alongside 32-bit instructions. transistors The transistor is a solid-state semiconductor device used for amplification and switching, and has three terminals: a small current or voltage applied to one terminal controls the current through the other two. It is the key component in all modern electronics. In digital circuits, transistors are used as very fast electrical switches, and arrangements of transistors can function as logic gates, RAM-type memory, and other devices. In analog circuits, transistors are essentially used as amplifiers. tristate A function whose output can adopt three states: 0, 1, and Z (high impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. U UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user The person using the PSoC device and reading this manual. user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. V VDDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 or 3.3 volts. volatile Not guaranteed to stay the same value or level when not in scope. VSS A name for a power net meaning "voltage source." The most negative power supply signal. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 307 Glossary W watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU will reset after a specified period of time. waveform The representation of a signal as a plot of amplitude versus time. X XOR 308 See Boolean Algebra. PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D Index A active mode PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 block diagram program and debug interface . . . . . . . . . . . . . . . . 271 watchdog timer circuit . . . . . . . . . . . . . . . . . . . . . . 85 brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 C 66 63 31 34 33 development kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 document glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 E F features H hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Hibernate wakeup reset . . . . . . . . . . . . . . . . . . . . . . . . .90 high impedance analog drive mode . . . . . . . . . . . . . . . .56 high impedance digital drive mode . . . . . . . . . . . . . . . . .56 how it works watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 66 D exception HardFault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PendSV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SVCall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 GPIO pins in creation of buttons and sliders . . . . . . . . .60 B clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock sources distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clocking system introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cortex-M0 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 40 40 40 39 40 40 90 I I/O drive mode high impedance analog . . . . . . . . . . . . . . . . . . . . . .56 high impedance digital . . . . . . . . . . . . . . . . . . . . . . .56 open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 resistive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 strong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 I/O system analog I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 CapSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 LCD drive capabilities . . . . . . . . . . . . . . . . . . . . . . .60 open drain modes . . . . . . . . . . . . . . . . . . . . . . . . . .56 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .61 resistive modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 slew rate control . . . . . . . . . . . . . . . . . . . . . . . . . . .56 strong drive mode . . . . . . . . . . . . . . . . . . . . . . . . . .56 identifying reset sources . . . . . . . . . . . . . . . . . . . . . . . . .90 internal low speed oscillator . . . . . . . . . . . . . . . . . . . . . .65 internal main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .64 internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 introduction clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 successive approximation register analog to digital convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D 309 L W LCD drive I/O system capabilities . . . . . . . . . . . . . . . . . . . . . . 60 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . watchdog timer disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . how it works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . O oscillators internal PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 overview, document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 89 87 87 85 86 88 87 P power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 program and debug PSoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 protection fault reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PSoC active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 program and debug . . . . . . . . . . . . . . . . . . . . . . . . . 21 R register summary I/O system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 registers Cortex-M0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 regulator internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reset identifying sources . . . . . . . . . . . . . . . . . . . . . . . . . 90 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 reset sources description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 S SAR ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 slew rate control in I/O system . . . . . . . . . . . . . . . . . . . . 56 software initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . 90 stop wakeup reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SWD interface program and debug interface . . . . . . . . . . . . . . . . 272 system call overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 U upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 310 PSoC 4100/4200 Family PSoC 4 Architecture TRM, Document No. 001-85634 Rev. *D