Datasheet

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The technical content of this TAOS datasheet is still valid.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
r
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102 × 1 Sensor Element Organization
300 Dots-per-Inch Pixel Pitch
High Sensitivity
On-Chip 8-Bit Analog-to-Digital Conversion
Three-Zone Programmable Offset (Dark Level) and Gain
High Speed Serial Interface
1 MHz Pixel Rate
Single 3-V to 5.5-V Supply
Replacement for TSL3301
RoHS Compliant
CL PACKAGE
(TOP VIEW)
SCLK 1
8 NC
VDD 2
7 GND
SDIN 3
6 GND
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D
D
D
D
D
D
D
D
D
D
TAOS141 − JULY 2011
SDOUT 4
5 NC
NC − No internal connection
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Package Drawing is Not to Scale
Description
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The TSL3301CL is a high-sensitivity 300-dpi, linear optical sensor array with integrated 8-bit analog-to-digital
converters. The array consists of 102 pixels: 100 inner pixels and 2 end pixels. The inner pixels measure 85 μm
(H) by 77 μm (W) on 85-μm centers and the end pixels are 132 μm (H) by 49 μm (W). Associated with each pixel
is a charge integrator/amplifier and sample-hold circuit. All pixels have concurrent integration periods and
sampling times. The array is split into three 34-pixel zones, with each zone having programmable gain and offset
levels. Data communication is accomplished through a three-wire serial interface.
Intended for use in high performance, cost-sensitive scanner applications, the TSL3301CL is based on a linear
sensor array die that has expanded capability, including multi-die addressing and cascade options. Please
contact TAOS for additional information on die and multi-die package availability.
Functional Block Diagram
PIXEL ARRAY WITH INTEGRATORS AND S−H
(51-bit shift register)
PIXCLK
SI
HOLD
ZERO
LEFT ODD
8
SCLK
DIGITAL I/O
AND
CONTROL
3
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SDIN
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5
SDOUT
LEFT EVEN
RIGHT ODD
RIGHT EVEN
IREF
DB<7:0>
ADDR<4:0>
READ
WRITE
OUTPUT CHARGE-TOVOLTAGE CONVERTER
WITH PROGRAMMABLE
GAINS AND OFFSETS
VREF
IREF
SECTOR
ch
BIAS
BLOCK
VREF
RESET/SAMPLE
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START
DUAL 8−BIT
SA ADC
IREF
ADCLK
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Copyright E 2011, TAOS Inc.
r
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972)
r 673-0759
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1
TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
6, 7
Ground
SCLK
1
I
System clock input for serial I/O and all internal logic.
SDIN
3
I
Serial data input. Data is clocked in on the rising edge of SCLK.
SDOUT
4
O
Serial data output. Data is clocked out on the falling edge of SCLK.
VDD
2
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Positive supply voltage.
Detailed Description
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The TSL3301CL is a 102 × 1 linear optical array with onboard A/D conversion. It communicates over a serial
digital interface and operates over a 3 V to 5.5 V range. The array is divided into three 34-pixel zones (left, center,
and right), with each zone having programmable gain and offset (dark signal) correction.
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The sensor consists of 102 photodiodes, also called pixels, arranged in a linear array. Light energy impinging
on a pixel generates a photocurrent, which is then integrated by the active integration circuitry associated with
that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through
an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity
(Ee) on that pixel and to the integration time (tint). At maximum programmed gain, one LSB corresponds to
approximately 300 electrons.
Integration, sampling, output, and reset of the integrators are performed by the control logic in response to
commands input via the SDIN pin. Data is read out on the SDOUT pin. A normal sequence of operation consists
of a pixel reset (RESET), start of integration (STARTInt), integration period, sampling of integrators
(SAMPLEInt), and pixel output (READPixel). Reset sets all the integrators to zero. Start of integration releases
the integrators from the reset state and defines the beginning of the integration period. Sampling the integrators
ends the integration period and stores the charge accumulated in each pixel in a sample and hold circuit.
Reading the pixels causes the sampled value of each pixel to be converted to 8-bit digital format and output on
the SDOUT pin. All 102 pixels are output sequentially unless interrupted by an abort (ABORTPixel) command
or reset by a RESET command.
Gain adjustment is controlled by three 5-bit DACs, one for each of the the three zones. Table 1 lists the gain
settings and the corresponding pixel values. Offset is affected by the gain setting and may have to be adjusted
after gain changes are made.
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Offset correction is controlled by three 8-bit sign-magnitude† DACs and is performed in the analog domain prior
to the digital conversion. There is a separate offset DAC for each of the three zones. Codes 0h − 7Fh correspond
to positive offset values and codes 80h – FFh correspond to negative offset values.
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The offset correction is proportional to the gain setting. At minimal gain, one LSB of the offset DAC corresponds
to approximately 1/3 LSB of the device output, and at maximum gain, to about 1 LSB of the device output.
Sign-magnitude is a binary representation in which the most significant bit (MSB) is used to represent the sign of the number, with the
remaining bits representing the magnitude. An MSB of 1 indicates a negative number.
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Note that the gain and offset registers are in indeterminate states after power up and must be set by the controller
as required.
Copyright E 2011, TAOS Inc.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Table 1. Gain Settings and Results
1
1.02
2
1.05
3
4
GAIN CODE
RELATIVE GAIN
% INCREASE
16
1.52
3.23
2.17
17
1.57
3.33
2.22
18
1.62
3.45
1.07
2.27
19
1.68
3.57
1.09
2.33
20
1.74
3.70
5
1.12
2.38
21
1.81
6
1.15
2.44
22
1.88
7
1.18
2.50
23
1.96
8
1.21
2.56
24
2.05
9
1.24
2.63
25
2.14
10
1.27
2.70
26
2.24
11
1.31
2.78
27
2.35
12
1.34
2.86
28
2.48
1.38
2.94
29
2.61
5.56
1.43
3.03
30
2.77
5.88
1.47
3.13
31
2.94
6.25
13
14
15
Serial Interface
% INCREASE
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1
3.85
4.00
4.17
4.35
4.55
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RELATIVE GAIN
0
4.76
5.00
5.26
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GAIN CODE
The serial interface follows a USART format, with start bit, 8 data bits, and one or more stop bits. Data is clocked
in synchronously on the rising edge of SCLK and clocked out on the falling edge of SCLK. Stop bits are not
required on the input. When clocking data out continuously (i.e., reading out pixels) there will be one stop bit
between data words.
The receive and transmit state machines are independent, which means commands can be issued while
reading data. This feature allows starting new integration cycles while reading data. Note that this allows
undefined conditions so care must be taken not to issue commands that will cause outputs (such as register
read) while reading out data. For instance, issuing a register read command while reading out image data will
result in garbage out. Likewise, it is possible to change offset and gain registers during a readout, which can
give unpredictable results.
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It is not necessary to have a continuously active clock, but a minimum of 5 clocks after the stop bit is required
after any command has been issued to ensure that the corresponding internal logic actions have been
completed. When reading register contents, there will be a 4-clock delay from the completion of the REGRead
command before the register contents are output (see Figure 5). When reading out pixel values, there will be
a 44-clock delay from completion of the READPixel command until the first pixel data is output. When starting
integration (STARTInt), it is necessary to have 22 clocks to complete the pixel reset cycle (see Imaging below).
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Register Address Map
The TSL3301CL contains seven registers as defined in Table 2. Data in these registers may be written to or read
from using the REGWrite and REGRead commands. Three registers control the gain of the analog-to-digital
converters (ADC). Three other registers allow the offset of the system to be adjusted. Together the gain and
offset registers are used to maximize the achievable dynamic range.
REGISTER DESCRIPTION
REGISTER WIDTH
0x00
Left (pixels 0−33) offset
8
0x01
Left (pixels 0−33) gain
5
0x02
Center (pixels 34−67) offset
8
0x03
Center (pixels 34−67) gain
5
0x04
Right (pixels 68−101) offset
8
0x05
Right (pixels 68−101) gain
5
0x1F
Mode
8
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ADDRESS
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Table 2. Register Address Map
The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed
offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset
correction.) These registers allow the user to maximize the dynamic range achievable in the given system.
The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip
arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device.
Users should always write 0s into the production test and multichip control bits.
0x1F
7
6
5
4
3
2
1
0
P2
0
0
SLP
P1
P0
C1
C0
SLP = Sleep Mode:
1 places device into sleep mode
MODE
C1, C0 are Reserved (should be written 0)
P2 to P0 are factory test bits (should be written 0)
0 places device in normal operating mode
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Figure 1. Mode Register Bit Assignments
Copyright E 2011, TAOS Inc.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Command Description
The TSL3301CL is a slave device that reacts strictly to commands received from the digital controller. These
commands cause the device to perform functions such as reset, integrate, sample, etc. Table 3 summarizes
the command types and formats and Table 4 lists the command set for the TSL3301CL. Each command is
described in more detail below.
FORMAT
Action command
< Command byte >
Register write
< Command byte > < Data byte >
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COMMAND TYPE
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Table 3. Command Type and Format Summary
Table 4. TSL3301CL Command Set
HEX CODE
SDIN held low for 30
clocks
IRESET
RESET
STARTInt
SAMPLEInt
READPixel
ABORTPixel
READHold
READHoldNStart
REGWrite
Interface Reset
0x1B
Reset Integration and read blocks
0x08
Start pixel integration
0x10
Stop light integration and sample results
0x02
Dump serial the contents of each sampled integrator
0x19
Abort any READPixel operation in progress
0x12
Combination of SAMPLEInt and READPixel commands
0x16
Combination of SAMPLEInt, READPixel and STARTInt commands
0x40 + address
Write a gain, offset, or mode register
0x60 + address
Read a gain, offset, or mode register
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REGRead
DESCRIPTION
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COMMAND
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
PROGRAMMING INFORMATION
A minimum of 5 clock cycles after the stop bit is required after any command to ensure that the internal logic
actions have been completed.
Reset Commands
Reset commands are used to put the TSL3301CL into a known state.
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IRESET — Interface Initialization
Encoding: Break Character (10 or more consecutive start bits, or zeros)
The commands vary in length from one to three bytes. IRESET initializes the internal state machine that keeps
track of which command bytes have been received. This command should be first and given only once after
power-up to synchronize the TSL3301CL internal command interpreter.
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An alternative is to issue three successive RESET commands.
RESET — Main Reset
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Encoding: 0x1b: <0001_1011>
RESET resets most of the internal control logic of the TSL3301CL and any READPixel command currently in
progress is aborted. RESET puts the pixel integrators into the auto-zero/reset state. Any values that were being
held in the array’s sample/hold circuits are lost.
NOTE:
The value on the SDOUT pin is not guaranteed from the time power is applied until 30 clocks after
the first RESET command is issued.
Pixel Action Commands
Pixel action commands allow the user to control pixel integration and reading of pixel data.
STARTInt — Start Integration
Encoding: 0x08: <0000_1000>
STARTInt causes each pixel to leave the reset state and to start integrating light. The actual execution
of STARTInt is delayed 22 clock cycles until the pixel reset cycle has been completed. (See imaging below.)
SAMPLEInt — Stop Integration
Encoding: 0x10: <0001_0000>
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SAMPLEInt causes each pixel to store its integrator’s contents into a sample and hold circuit. Also, the Integrator
is returned to the reset state.
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READPixel — Read Pixel Data
Encoding: 0x02: <0000_0010>
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READPixel causes the sampled value of each pixel to be converted to an 8-bit digital value that is clocked out
on the SDOUT pin. The LSB is the first data bit, which is preceded by a START bit (logic 0) and followed by a
STOP bit (logic 1). Each pixel in the device is presented on SDOUT starting from pixel 00 and completes with
pixel 101. There is a 44-clock cycle delay from the completion of the READPixel command until the first pixel
data is output.
Gain and offset registers are used to adjust the ADC converter to maximize dynamic range and should be
programmed prior to invoking the READPixel command.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
ABORTPixel — Abort Pixel Data Read
Encoding: 0x19: <0001_1001>
ABORTPixel is an optional command that stops a READPixel command during its execution. It also causes pixel
integration to terminate and the device to enter the auto-zero/reset state. Any values that were being held in
the array’s sample/hold circuits are lost.
READHold — Sample and Read Combination
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Encoding: 0x12: <0001_0010>
READHold is a macro command that combines both the SAMPLEInt and READPixel commands into a single
command.
READHoldNStart Combination
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Encoding: 0x16: <0001_0110>
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READHold is a macro command that combines the SAMPLEInt, READPixel, and StartInt commands into a
single command. 22 clock cycles are necessary to complete the pixel reset cycle.
Register Commands
The register commands provide the user the capability of setting gain and offset corrections for each of the three
zones of pixels. a4−a0 refer to the register address as given in Table 2.
REGWrite — Write a Gain/Offset/Mode Register
Encoding (2 bytes): 0x40 <data>: <010a4_a3a2a1a0> <d7d6d5d4_d3d2d1d0>
REGWrite writes a value into either a gain, offset, or mode register. The 5-bit address of the register is encoded
into the lower 5 bits of the command byte (the first byte). A second byte, which contains the data to be written,
follows the command byte.
REGRead — Read a Gain/Offset/Mode Register
Encoding: 0x60: <011a4_a3a2a1a0>
REGRead reads the value previously stored in a gain, offset, or mode register. The 5-bit address of the register
is encoded into the lower 5 bits of the command byte. Following receipt of the REGRead command, the device
places the contents of the selected register onto the SDOUT pin, LSB first.
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There is a 4-clock cycle delay from the completion of the REGRead command until the register contents are
output.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
OPERATION
Initialization Sequence
After powering on the device, a minimum of 10 clocks with SDIN held high must be received by the TSL3301CL
to clear the receiver logic so that a start bit will be detected correctly. The control logic may then be cleared by
either issuing an IRESET command (break character) or 3 RESET (0x1b) commands. An additional 30 clocks
must be received by the device to assure the state of SDOUT.
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Sleep Mode
The device can be put into a power down or sleep mode by writing a 0x10 to the mode register. This turns off
all the analog circuitry on the chip. Normal operation is restored by writing a 0x00 to the mode register. The
analog circuitry will require a minimum of 1 millisecond to recover from the sleep mode.†
For minimum sleep mode current consumption, voltage levels on logic inputs must be at either VDD or ground.
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†
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Note that putting the device in the sleep mode does not affect the logic states of the machine. If, for example,
a READPixel command is issued, the device will respond but the resulting data will be meaningless. Also note
that 0x00 and 0x10 are the only two legitimate user programmable values for the single-chip version of the
TSL3301CL. Other values may put the device into a non-operational mode.
Imaging
After powering up the device and completing the initialization sequence, it is necessary to allow a minimum of
1 millisecond for the internal analog circuitry to settle. This delay is also required when coming out of the sleep
mode.
Issuing a STARInt (0x08) command will release the pixel integrators from the reset state. After an appropriate
delay to integrate the image, the pixel data may be sampled by issuing a SAMPLEInt (0x10) command and then
read out by issuing a READPixel (0x02) command.
A STARTInt command can be issued anytime after the SAMPLEInt command is issued to start another cycle.
Thus, it is possible to be reading out one sample while integrating the next. However, the sampled data from
the previous SAMPLEInt must be completely read out before the next SAMPLEInt command is issued.
The compound commands READHold (0x12) and READHoldNStart ((0x16) are shortcut commands to simplify
the imaging sequence.
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It is important to note that a pixel reset sequence is initiated with the receipt of a STARTInt or READHoldNStart
command. The next integration sequence cannot start until the pixel reset sequence has been completed, which
requires 22 clocks AFTER the receipt of one of these commands. These clocks can also be used to clock
commands or data into or out of the device.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)†
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Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Digital output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD +0.3 V
Digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 to +10 mA
Digital input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25_C to 85_C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
†
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Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Not recommended for solder reflow.
Supply voltage, VDD
MIN
NOM
3
5
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Recommended Operating Conditions
MAX
UNIT
5.5
V
VDD
V
Low-level input voltage at SCLK, SDIN, VIL
0.8
V
Power supply ripple, 100 kHz sawtooth waveform
60
mVp-p
Input clock (SCLK) rise time, 10% to 90%
30
ns
High-level input voltage at SCLK, SDIN, VIH
2
Operating junction temperature, TJ
0
Maximum clock frequency, fSCLK
70
°C
10
MHz
Electrical Characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5 V
VOH
High level output voltage,
High-level
voltage SDOUT
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VDD = 3
3.3
3V
Low level output voltage,
Low-level
voltage SDOUT
IDD
Supply current
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VOL
IO = 50 μA
MIN
TYP
4.5
4.95
IO = 4 mA
4.6
IO = 50 μA
2.9
IO = 4 mA
MAX
UNIT
V
2.7
IO = 50 μA
0.01
IO = 4 mA
0.4
A/D active
11
17
6
11
A/D inactive
Sleep mode
0.1
V
mA
10
μΑ
0.8
V
Low-level input voltage (SCLK, SDIN)
VIH
High-level input voltage (SCLK, SDIN)
IIH
High-level input current (SCLK, SDIN)
VI = VDD
±10
μΑ
Low-level input current (SCLK, SDIN)
VI = 0
±10
μΑ
2
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
Light-to-Digital Transfer Characteristics at VDD = 5 V, TJ = 25°C, λp = 660 nm, tint = 250 μs (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
A-to-D converter resolution
Gain register = 00000b
3.6
Gain register = 11111b
1.24
For converter only, does not include
photodiode characteristics
Gain register = 00000b
Average dark-level
dark level offset
Gain register = 11111b
0
Gain register = 00000b
Ee = 11.3 μW/cm2
Dark level noise
10
200
LSB
240
LSB
±8
±10
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Integral nonlinearity
LSB
200
Ee = 11.3 μW/cm2, See Notes 2 and 3
%
±128
Gain register = 00000b
0.5
Gain register = 11111b
1.5
Dark-level change with temperature
Differential nonlinearity
30
14
160
Gain register = 11111b
Ee = 3.77 μW/cm2
Pixel-response non-uniformity (PRNU)
ppm/°C
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Average white level output
7
5
Gain register = 11111b, see Note 1
Offset register =
00000000b
nJ/cm 2
20
Gain register = 00000b, see Note 1
Dark signal nonuniformity (DSNU)
Bits
±150
Offset register = 00000000b
UNIT
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Full-scale reference temperature sensitivity
Programmable offset step size
MAX
8
Full scale reference
Full-scale
Programmable offset steps
TYP
0°C < TJ < 70°C
LSB
2
LSB
±0.5
LSB
±1
LSB
Gain register = 00000b
0.5
Gain register = 11111b
1.5
LSB
NOTES: 1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not
illuminated.
2. PRNU does not include DSNU.
3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly
illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN
NOM
MAX
UNIT
Maximum clock frequency
10
MHz
tw(CLKH)
Clock high pulse duration
30
ns
tw(CLKL)
Clock low pulse duration
30
ns
tsu
Input setup time
20
ns
th
Input hold time
20
ns
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fmax
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
TEST CONDITIONS
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PARAMETER
MIN
TYP
MAX
UNIT
tr
Rise time, output
tf
Fall time, output
td
Delay from clock edge to data-out stable
20
ns
Ci
Input pin capacitance
10
pF
Copyright E 2011, TAOS Inc.
CL = 20 pF
ns
10
ns
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
TYPICAL CHARACTERISTICS
VIH
tw(CLKH)
SCLK
tw(CLKL)
VIL
th
tsu
VIH
al
id
SDIN
VIL
lv
Figure 2. TSL3301CL Input Timing Requirements
VIH
am
lc s
on A
te G
nt
st
il
SCLK
VIL
td
VOH
SDOUT
VOL
Figure 3. TSL3301CL Output Switching Characteristics
SCLK
Start
B0
B2
B1
B3
B4
B5
B6
B7
Stop
Serial Input Data Format
ni
ca
SDIN
ch
SCLK
Te
SDOUT
The LUMENOLOGY r Company
Start
B0
B1
B2
B3
B4
B6
B5
B7
Stop
Serial Output Data Format
Figure 4. TSL3301CL Serial I/O
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
TYPICAL CHARACTERISTICS
SCLK
B7
SDIN
2
3
4
al
id
1
Stop
SDOUT
Start
lv
END of REGRead Command
B0
am
lc s
on A
te G
nt
st
il
Beginning of Output Response
Figure 5. TSL3301CL REGRead Output Response Timing
PHOTODIODE SPECTRAL RESPONSIVITY
1.2
Normalized to
660 nm
TA = 25°C
0.8
0.6
0.4
ca
Relative Responsivity
1.0
ch
ni
0.2
0
300
500
700
900
λ − Wavelength − nm
1100
Te
Figure 6. TSL3301CL Photodiode Spectral Response
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
APPLICATION INFORMATION
Normal Sequence
A typical programming sequence for the TSL3301CL device appears below:
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Send(IRESET);
Send(RESET);
Calibration Cycle
*
*
while(1) {
for(i=0;i<=2;i++) {/* for each pixel page */
Write page gain register
Write page offset register
Read page gain register and verify (optional)
Read page offset register and verify (optional)
}
}
Send(STARTInt);
DelayIntegrationTime(); /* wait for appropriate time interval to elapse */
Send(SAMPLEInt);
Send(READPixel);
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
APPLICATION INFORMATION: HARDWARE
PCB Pad Layout
Suggested PCB pad layout guidelines for the CL package are shown in Figure 7.
1.3
al
id
Pin 1
lv
1.4
am
lc s
on A
te G
nt
st
il
2.5
0.8
0.8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Te
ch
ni
ca
Figure 7. Suggested CL Package PCB Layout
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
PACKAGE INFORMATION
TOP VIEW
al
id
0.085
(Note B)
3.0 0.2
Pin 1
lv
8.573 (Note B)
Photodiode Array
(Not to Scale)
SIDE VIEW
am
lc s
on A
te G
nt
st
il
9.4 0.2
END VIEW
0.22
BOTTOM
VIEW
CL of Solder Contact
CL of Pixel 7 (Note C)
1.2 0.2
Photodiode Array
(Not to Scale)
0.011 Nominal
Pin 1
0.95
0.8
0.95
0.37 Nominal
0.6
CL of Package
ca
1.8
CL of Photodiode Array Area (Note C)
2.5
1.0
Pb
ni
0.6
7.5 0.08
Te
ch
NOTES: A. All linear dimensions are in millimeters. Dimension tolerance is ± 0.05 mm unless otherwise noted.
B. Nominal photodiode array dimension. The array is made up of 100 inner pixels and 2 end pixels with pixel #1 closer to
Pin 1. The inner pixel is 77 μm wide by 85 μm high, spaced on 85μm centers. The end pixel is 49μm wide by 132 μm high.
C. The die is centered within the package within a tolerance of ± 0.05 mm.
D. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.56.
E. Contact finish is soft gold plated.
F. This package contains no lead (Pb).
G. This drawing is subject to change without notice.
The LUMENOLOGY r Company
Figure 8. Package CL Configuration
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
CARRIER TAPE AND REEL INFORMATION
TOP VIEW
2.00
4.00
8.00
1.50
+ 0.10
− 0.00
1.75
al
id
B
16.00
+ 0.30
− 0.10
1.50
+ 0.25
− 0.00
8 Max
7 Max
9.85
1.53
Bo
Ko
ch
ni
ca
Ao
B
DETAIL B
0.30
0.02
3.45
A
am
lc s
on A
te G
nt
st
il
DETAIL A
A
lv
7.50
All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted.
The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481−B 2001.
Each reel is 178 millimeters in diameter and contains 1000 parts.
TAOS packaging tape and reel conform to the requirements of EIA Standard 481−B.
In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
This drawing is subject to change without notice.
Te
NOTES: A.
B.
C.
D.
E.
F.
G.
Figure 9. Package CL Carrier Tape
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
SOLDERING INFORMATION
The CL package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.
Table 5. Solder Reflow Profile
PARAMETER
REFERENCE
DEVICE
Average temperature gradient in preheating
tsoak
2 to 3 minutes
Time above 217°C (T1)
t1
Max 60 sec
Time above 230°C (T2)
t2
Max 50 sec
Time above Tpeak −10°C (T3)
t3
Max 10 sec
Tpeak
260°C
am
lc s
on A
te G
nt
st
il
Peak temperature in reflow
lv
Soak time
2.5°C/sec
Temperature gradient in cooling
Max −5°C/sec
Not to scale — for reference only
T3
T2
t3
t2
tsoak
t1
Figure 10. Solder Reflow Profile Graph
Te
ch
Time (sec)
ni
Temperature (C)
T1
ca
Tpeak
al
id
The solder reflow profile describes the expected maximum heat exposure of components during the solder
reflow process of product on a PCB. Temperature is measured on top of component. The components should
be limited to a maximum of three passes through this solder reflow profile.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
STORAGE INFORMATION
Moisture Sensitivity
al
id
Optical characteristics of the device can be adversely affected during the soldering process by the release and
vaporization of moisture that has been previously absorbed into the package. To ensure the package contains
the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping.
Devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them
from ambient moisture during shipping, handling, and storage before use.
The CL package has been assigned a moisture sensitivity level of MSL 5a and the devices should be stored
under the following conditions:
5°C to 50°C
60% maximum
6 months from the date code on the aluminized envelope — if unopened
24 hours or fewer
lv
Temperature Range
Relative Humidity
Total Time
Opened Time
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
Rebaking will be required if the devices have been stored unopened for more than 6 months or if the aluminized
envelope has been open for more than 24 hours. If rebaking is required, it should be done at 60°C for 24 hours.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS141 − JULY 2011
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
LEAD-FREE (Pb-FREE) and GREEN STATEMENT
al
id
Pb-Free (RoHS) TAOS’ terms Lead-Free or Pb-Free mean semiconductor products that are compatible with the current
RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous
materials. Where designed to be soldered at high temperatures, TAOS Pb-Free products are suitable for use in specified
lead-free processes.
Green (RoHS & no Sb/Br) TAOS defines Green to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and
Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
am
lc s
on A
te G
nt
st
il
lv
Important Information and Disclaimer The information provided in this statement represents TAOS’ knowledge and
belief as of the date that it is provided. TAOS bases its knowledge and belief on information provided by third parties,
and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate
information from third parties. TAOS has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and
chemicals. TAOS and TAOS suppliers consider certain information to be proprietary, and thus CAS numbers and other
limited information may not be available for release.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
ca
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
Te
ch
ni
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced
Optoelectronic Solutions Incorporated.
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TSL3301CL
102 × 1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
TAOS141 − JULY 2011
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