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TSB572
Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier
Datasheet - production data
Applications
Active filtering
Audio systems
Automotive
Power supplies
Industrial
Low/High side current sensing
MiniSO8
Description
The TSB572 dual operational amplifier offers
extended voltage operating range from 4 V to
36 V and rail-to-rail input/output.
The TSB572 offers a very good speed/power
consumption ratio with 2.5 MHz gain bandwidth
product while consuming only 380 µA typically at
36 V supply voltage.
DFN8 3x3
Stability and robustness of the TSB572 make it
an ideal solution for a wide voltage range of
applications.
Features
Low-power consumption: 380 µA typ
Wide supply voltage: 4 V - 36 V
Rail-to-rail input and output
Gain bandwidth product: 2.5 MHz
Low input bias current: 30 nA max
No phase reversal
High tolerance to ESD: 4 kV HBM
Extended temperature range:
-40 °C to 125 °C
Automotive grade
Small SMD packages
40 V BiCMOS technology
Enhanced stability vs. capacitive load
December 2015
DocID028308 Rev 2
This is information on a product in full production.
1/27
www.st.com
Contents
TSB572
Contents
1
Package pin connections................................................................ 3
2
Absolute maximum ratings and operating conditions ................. 4
3
4
Electrical characteristics ................................................................ 5
Application information ................................................................ 17
5
6
7
2/27
4.1
Operating voltages .......................................................................... 17
4.2
Input pin voltage ranges .................................................................. 17
4.3
Rail-to-rail input ............................................................................... 17
4.4
Input offset voltage drift over temperature ....................................... 18
4.5
Long term input offset voltage drift .................................................. 18
4.6
Capacitive load................................................................................ 20
4.7
PCB layout recommendations ......................................................... 21
4.8
Optimized application recommendation .......................................... 21
Package information ..................................................................... 22
5.1
MiniSO8 package information ......................................................... 23
5.2
DFN8 3x3 package information ....................................................... 24
Ordering information..................................................................... 25
Revision history ............................................................................ 26
DocID028308 Rev 2
TSB572
1
Package pin connections
Package pin connections
Figure 1: Pin connections for each package (top view)
1.
Exposed pad can be left floating or connected to ground
DocID028308 Rev 2
3/27
Absolute maximum ratings and operating
conditions
2
TSB572
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings
Symbol
VCC
Vid
Vin
Iin
Tstg
Parameter
Supply voltage
Input voltage
Input current
(4)
(2)
±1
(VCC )
V
+
- 0.2 to (VCC ) + 0.2
10
Storage temperature
Maximum junction temperature
Rthja
Thermal resistance junction to
(5)(6)
ambient
Human body model (HBM)
Machine model (MM)
mA
-65 to 150
Tj
ESD
Unit
40
Differential input voltage
(3)
Value
(1)
150
MiniSO8
190
DFN8 3x3
40
°C/W
(7)
(8)
CDM: charged device model
°C
(9)
Latch-up immunity
4
kV
100
V
1.5
kV
200
mA
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
All voltage values, except the differential voltage are with respect to network ground terminal.
Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
VCC-Vin must not exceed 6 V, Vin must not exceed 6 V.
Input current must be limited by a resistor in-series with the inputs.
Rth are typical values.
Short-circuits can cause excessive heating and destructive dissipation.
According to JEDEC standard JESD22-A114F.
According to JEDEC standard JESD22-A115A.
According to ANSI/ESD STM5.3.1.
Table 2: Operating conditions
Symbol
VCC
4/27
Parameter
Value
Supply voltage
Unit
4 to 36
Vicm
Common mode input voltage range
Toper
Operating free-air temperature range
DocID028308 Rev 2
(VCC )
+
- 0.1 to (VCC ) + 0.1
-40 to 125
V
°C
TSB572
Electrical characteristics
3
Electrical characteristics
Table 3: Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL
connected to Vcc/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
ΔVio/ΔT
Iio
Input offset voltage
Input offset voltage drift
Input offset current
-40 °C < T < 125 °C
-1.5
1.5
-2.1
2.1
-40 °C < T < 125 °C
1.5
6
2
15
-40 °C < T < 125 °C
35
8
30
mV
μV/°C
nA
Iib
Input bias current
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
Common mode rejection ratio
20 log (ΔVicm/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage
(drop voltage from (VCC+))
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current (per channel)
-40 °C < T < 125 °C
70
Vicm = (VCC-) to (VCC+) - 1.5 V,
Vout = VCC/2
90
-40 °C < T < 125 °C
80
Vicm = (VCC-) to (VCC+), Vout = VCC/2
75
-40 °C < T < 125 °C
70
RL= 10 kΩ, Vout = 0.5 to 3.5 V
90
-40 °C < T < 125 °C
85
RL = 10 kΩ
114
97
dB
100
19
-40 °C < T < 125 °C
60
80
RL = 10 kΩ
12
-40 °C < T < 125 °C
50
mV
70
Vout = VCC
20
-40 °C < T < 125 °C
5
Vout = 0 V
10
-40 °C < T < 125 °C
5
No load, Vout = VCC/2
38
mA
32
340
-40 °C < T < 125 °C
430
μA
500
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.5
-40 °C < T < 125 °C
1.2
2.2
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
45
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
5
dB
E
DocID028308 Rev 2
5/27
Electrical characteristics
Symbol
Parameter
Negative slew rate
SR
Positive slew rate
en
THD+N
6/27
TSB572
Equivalent input noise voltage
Total harmonic distortion +
noise
Conditions
Min.
Typ.
Vin = 3.5 to 0.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.50
0.78
-40 °C < T < 125 °C
0.37
Vin = 0.5 to 3.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.50
-40 °C < T < 125 °C
0.37
Max.
Unit
V/μs
0.89
f = 1 kHz
20
nV/√Hz
f = 0.1 Hz to 10 Hz
0.7
μVpp
0.001
%
f = 1 kHz, Vin = 3.8 Vpp, RL = 10 kΩ,
CL = 100 pF
DocID028308 Rev 2
TSB572
Electrical characteristics
Table 4: Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL
connected to Vcc/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
ΔVio/ΔT
Iio
Input offset voltage
Input offset voltage drift
Input offset current
-40 °C < T < 125 °C
-1.5
1.5
-2.1
2.1
-40 °C < T < 125 °C
1.5
6
2
15
-40 °C < T < 125 °C
35
8
30
mV
μV/°C
nA
Iib
Input bias current
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
SVR
Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Supply voltage rejection ratio
20 log (ΔVCC/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage
(drop voltage from VCC+)
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current (per channel)
-40 °C < T < 125 °C
70
Vicm = (VCC-) to (VCC+) - 1.5 V,
Vout = VCC/2
100
-40 °C < T < 125 °C
90
Vicm = (VCC-) to (VCC+), Vout = VCC/2
85
-40 °C < T < 125 °C
80
VCC = 4 to 12 V
90
-40 °C < T < 125 °C
80
RL= 10 kΩ, Vout = 0.5 to 11.5 V
95
-40 °C < T < 125 °C
90
RL = 10 kΩ
123
106
dB
99
106
38
-40 °C < T < 125 °C
100
150
RL = 10 kΩ
16
-40 °C < T < 125 °C
70
mV
90
Vout = VCC
20
-40 °C < T < 125 °C
8
Vout = 0 V
15
-40 °C < T < 125 °C
7
No load, Vout = VCC/2
42
mA
35
360
-40 °C < T < 125 °C
450
530
μA
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.6
-40 °C < T < 125 °C
1.3
2.4
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
50
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
6
dB
E
DocID028308 Rev 2
7/27
Electrical characteristics
Symbol
Parameter
Negative slew rate
SR
Positive slew rate
en
THD+N
8/27
TSB572
Conditions
Min.
Typ.
Vin = 10.5 to 1.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.53
0.82
-40 °C < T < 125 °C
0.40
Vin = 1.5 to 10.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.55
-40 °C < T < 125 °C
0.40
Max.
Unit
V/μs
0.92
Equivalent input noise
voltage
f = 1 kHz
20
nV/√Hz
f = 0.1 Hz to 10 Hz
0.7
μVpp
Total harmonic distortion +
noise
f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ,
CL = 100 pF
0.0005
%
DocID028308 Rev 2
TSB572
Electrical characteristics
Table 5: Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL
connected to Vcc/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
ΔVio/ΔT
ΔVio
Iio
Input offset voltage
-40 °C < T < 125 °C
-1.5
1.5
-2.1
2.1
Input offset voltage drift
-40 °C < T < 125 °C
1.5
Long-term input offset
(1)
voltage drift
T = 25 °C
1.5
Input offset current
2
-40 °C < T < 125 °C
6
μV/°C
µV/√month
15
35
8
mV
30
nA
Iib
Input bias current
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
SVR
Supply voltage rejection
ratio 20 log (ΔVCC/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage
(drop voltage from VCC+)
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current
(per channel)
-40 °C < T < 125 °C
70
Vicm = (VCC-) to (VCC+) - 1.5 V,
Vout = VCC/2
105
-40 °C < T < 125 °C
95
Vicm = (VCC-) to (VCC+),
Vout = VCC/2
95
-40 °C < T < 125 °C
90
VCC = 4 to 36 V
90
-40 °C < T < 125 °C
85
RL= 10 kΩ, Vout = 0.5 to 35.5 V
95
-40 °C < T < 125 °C
90
RL = 10 kΩ
129
115
dB
104
114
78
-40 °C < T < 125 °C
150
200
RL = 10 kΩ
30
-40 °C < T < 125 °C
90
mV
120
Vout = VCC
25
-40 °C < T < 125 °C
10
Vout = 0 V
20
-40 °C < T < 125 °C
10
No load, Vout = VCC/2
65
mA
50
380
-40 °C < T < 125 °C
470
550
μA
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.7
-40 °C < T < 125 °C
1.4
2.5
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
50
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
8
dB
E
DocID028308 Rev 2
9/27
Electrical characteristics
Symbol
Parameter
Negative slew rate
SR
Positive slew rate
en
THD+N
TSB572
Conditions
Min.
Typ.
Vin = 22.5 to 13.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.57
0.88
-40 °C < T < 125 °C
0.44
Vin = 13.5 to 22.5 V, Av = 1, 10 % to
90 %, RL = 10 kΩ, CL = 100 pF
0.60
-40 °C < T < 125 °C
0.44
Max.
Unit
V/μs
1.00
Equivalent input noise
voltage
f = 1 kHz
20
nV/√Hz
f = 0.1 Hz to 10 Hz
0.7
μVpp
Total harmonic distortion +
noise
f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ,
CL = 100 pF
0.001
%
Notes:
(1)
Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using Arrhenius law and assuming
an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.5).
10/27
DocID028308 Rev 2
TSB572
Electrical characteristics
Figure 2: Supply current vs. supply voltage
Figure 3: Input offset voltage distribution at VCC = 4 V
Figure 4: Input offset voltage distribution at VCC = 12 V
Figure 5: Input offset voltage distribution at VCC = 36 V
Figure 6: Input offset voltage vs. temperature
at VCC = 36 V
Figure 7: Input offset voltage temperature variation
distribution at VCC = 36 V
DocID028308 Rev 2
11/27
Electrical characteristics
TSB572
Figure 8: Input offset voltage vs. supply voltage
Figure 9: Input offset voltage vs. common-mode voltage
at VCC = 4 V
Figure 10: Input offset voltage vs. common-mode
voltage at VCC = 36 V
Figure 11: Input bias current vs. temperature
at VICM = VCC/2
Figure 12: Input bias current vs. common-mode voltage
at VCC = 36 V
Figure 13: Output current vs. output voltage
at VCC = 4 V
12/27
DocID028308 Rev 2
TSB572
Electrical characteristics
Figure 14: Output current vs. output voltage
at VCC = 36 V
Figure 15: Output voltage (Voh) vs. supply voltage
Figure 16: Output voltage (Vol) vs. supply voltage
Figure 17: Negative slew rate at VCC = 36 V
Figure 18: Positive slew rate at VCC = 36 V
Figure 19: Slew rate vs. supply voltage
DocID028308 Rev 2
13/27
Electrical characteristics
14/27
TSB572
Figure 20: Bode diagram at VCC = 4 V
Figure 21: Bode diagram at VCC = 36 V
Figure 22: Phase margin vs. output current
at VCC = 4 V
Figure 23: Phase margin vs. output current
at VCC = 36 V
Figure 24: Phase margin vs. capacitive load
Figure 25: Overshoot vs. capacitive load at VCC = 36 V
DocID028308 Rev 2
TSB572
Electrical characteristics
Figure 27: Output desaturation vs. time
Figure 28: Amplifier behavior close to the rails
at VCC = 36 V
Figure 29: Noise vs. frequency at VCC = 36 V
Equivalent Input Noise Voltage (nV/√Hz)
Figure 26: Small step response vs. time at VCC = 4 V
100
80
@Vcc=36V
@Vcc=12V
@Vcc=4V
Vicm=Vcc/2
T=25°C
60
40
20
0
10
Figure 30: Noise vs. time at VCC = 36 V
DocID028308 Rev 2
100
1000
Frequency (Hz)
10000
Figure 31: THD+N vs. frequency
15/27
Electrical characteristics
TSB572
Figure 32: THD+N vs. output voltage
Figure 33: PSRR vs. frequency at VCC = 36 V
Figure 34: Channel separation vs. frequency at VCC= 36 V
16/27
DocID028308 Rev 2
TSB572
Application information
4
Application information
4.1
Operating voltages
The TSB572 can operate from 4 V to 36 V. The parameters are fully specified for 4 V, 12 V,
and 36 V power supplies. However, the parameters are stable in the full VCC range.
Additionally, the main specifications are guaranteed in extended temperature ranges from
-40 to 125 °C.
4.2
Input pin voltage ranges
The TSB572 has internal ESD diode protection on the inputs. These diodes are connected
between the inputs and each supply rail to protect the input transistors from electrical
discharge.
If the input pin voltage exceeds the power supply by 0.2 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over
current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as shown in Figure 35: "Input current limitation".
Figure 35: Input current limitation
16 V
R
Vin
4.3
-
+
+
-
Vout
Rail-to-rail input
The TSB572 has rail-to-rail inputs. The input common mode range is extended from
(VCC-) - 0.1 V to (VCC+) + 0.1 V at T = 25 °C.
DocID028308 Rev 2
17/27
Application information
4.4
TSB572
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
V T – Vio 25 °C
= max io
∆T
T – 25 °C
where T = -40 °C and 125 °C.
The TSB572 datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
4.5
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
AFV = e
β . V S – VU
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3.
Equation 3
AFT = e
Ea
1
1
------ .
–
k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
18/27
DocID028308 Rev 2
TSB572
Application information
-5
-1
k is the Boltzmann constant (8.6173 x 10 eV.K )
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
AF = AFT × AFV
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = AF × 1000 h × 12 months / 24 h × 365.25 days
To evaluate the op amp reliability, a follower stress condition is used where V CC is defined
as a function of the maximum operating voltage and the absolute maximum rating
(as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
VCC = maxVop with Vicm = VCC 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of
the calculated number of months (Equation 7).
Equation 7
∆Vio =
Vio dr ift
month s
Where Vio drift is the measured drift value in the specified test conditions after 1000 h
stress duration.
DocID028308 Rev 2
19/27
Application information
4.6
TSB572
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load
capacitance produces gain peaking in the frequency response, with overshoot and ringing
in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an
op amp might become unstable.
Generally, unity gain configuration is the worst situation for stability and the ability to drive
large capacitive loads.
Figure 36: "Stability criteria with a serial resistor at different supply voltages" shows the
serial resistor that must be added to the output, to make a system stable. Figure 37: "Test
configuration for Riso" shows the test configuration using an isolation resistor, Riso.
Figure 36: Stability criteria with a serial resistor at different supply voltages
Figure 37: Test configuration for Riso
V CC+
Riso
VIN
+
Cload
V CC-
20/27
DocID028308 Rev 2
VOUT
10 kΩ
TSB572
4.7
Application information
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. The best practice is to use short and wide
PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
4.8
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A
good decoupling will help to reduce electromagnetic interference impact.
DocID028308 Rev 2
21/27
Package information
5
TSB572
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
22/27
DocID028308 Rev 2
TSB572
5.1
Package information
MiniSO8 package information
Figure 38: MiniSO8 package outline
Table 6: MiniSO8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Inches
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
0.80
0.016
e
L
0.85
0.65
0.40
0.60
0.006
0.033
0.026
0.024
L1
0.95
0.037
L2
0.25
0.010
k
ccc
0°
0.037
8°
0.10
DocID028308 Rev 2
0°
0.031
8°
0.004
23/27
Package information
5.2
TSB572
DFN8 3x3 package information
Figure 39: DFN8 3x3 package outline and mechanical data
24/27
DocID028308 Rev 2
TSB572
6
Ordering information
Ordering information
Table 7: Order codes
Order code
Temperature range
TSB572IQ2T
TSB572IYQ2T
TSB572IYST
Packing
-40 °C to 125 °C
Tape and reel
MiniSO8
(1)
Marking
K31
DFN8 3x3
(1)
TSB572IST
Package
K32
K31
K32
Notes:
(1)
Automotive qualification according to AEC-Q100.
DocID028308 Rev 2
25/27
Revision history
7
TSB572
Revision history
Table 8: Document revision history
Date
Version
12-Oct-2015
1
Initial release
2
Section 2: "Absolute maximum ratings and operating conditions":
updated ESD, MM value.
Section 6: "Ordering information": removed footnote (1) from order
code TSB572IQ2T.
17-Dec-2015
26/27
Changes
DocID028308 Rev 2
TSB572
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