DEMO MANUAL DC1945A LTC2185 and LTC6409 16-Bit, 125Msps Dual ADC Combo Board Description Demonstration circuit 1945A supports the LTC®2185 125Msps dual ADC and a LTC6409 low noise amplifier. The assembly may be modified to evaluate other members of the pin-compatible 16-bit LTC2185 and 14-bit/12-bit LTC2145 dual ADC families. DC1945A supports the LTC2185, DDR LVDS output mode. The circuitry on the analog inputs is optimized for analog input frequencies from DC to 100MHz. The DC1945A can Performance Summary also be used as a direct receiver board by attaching the analog inputs to a demodulator like the LTC5585. Refer to the data sheet for proper input networks for different input frequencies. Design files for this circuit board are available at http://www.linear.com/demo L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Specifications are at TA = 25°C PARAMETER CONDITIONS MIN TYP Supply Voltage: ADC Depending on sampling rate and the A/D converter provided, this supply must provide up to 150mA 4.5 6 V Supply Voltage: Amplifier Depending on supply voltage used, this supply must provide up to 150mA 2.7 5.2 V Analog Input Range Depending on SENSE Pin Voltage 62 125 mV Logic Input Voltages Minimum Logic High Maximum Logic Low Logic Output Voltages (OVDD = 1.8V) Minimum High Level Output Voltage Maximum Low Level Output Voltage Sampling Frequency (Convert Clock Frequency) Depending on ADC, this can vary between 20Msps and 125Msps 1 125 Msps Convert Clock Level Single-Ended Encode Mode (ENC– Tied to GND) 0 3.6 V Convert Clock Level Differential Encode Mode (ENC– Not Tied to GND) V V 1.395 1.065 V V 3.6 16 Input Frequency Range DC SFDR See Applicable Data Sheet SNR See Applicable Data Sheet UNITS 1.3 0.6 0.2 Resolution MAX V Bits 100 MHz dc1945af 1 DEMO MANUAL DC1945A Quick Start Procedure DC1945A is easy to set up to evaluate the performance of the LTC2185 family of A/D converters. Refer to Figure 1 for proper measurement equipment setup and follow the procedure in the Setup section. SETUP If a DC890 QuikEval™ II Data Acquisition and Collection System was supplied with the DC1945A demonstration circuit, follow the DC890 Quick Start Guide to install the required software and for connecting the DC890 to the DC1945A and to a PC. 2.7V TO 5.2V 4.5V + + SINGLE-ENDED INPUT SIGNAL JUMPERS ARE SHOWN IN DEFAULT POSITIONS CHANNEL 1 MATCHED SOURCE IMPEDANCE CHANNEL 2 PARALLEL DATA OUTPUT TO DC890 MATCHED SOURCE IMPEDANCE dc1945 F01 SINGLE-ENDED ENCODE CLOCK Figure 1. DC1945A Setup dc1945af 2 DEMO MANUAL DC1945A Hardware Setup SMAs: J1 I IN–: Negative analog input for channel 1. Apply the analog signal of interest to this SMA. For a single-ended signal a matching impedance should be connected on the positive input of channel 1 (J2) for proper balance. Use this channel when using a single-ended input. J2 I IN+: Positive analog input for channel 1. Apply the analog signal of interest to this SMA. Terminate this channel to an impedance that matches I IN– when using a singleended input on J1. If J2 is being driven single-ended, a matching impedance should be connected on the negative input of channel 1 (J1) for proper balance. J5 Q IN–: Negative analog input for channel 2. Apply the analog signal of interest to this SMA. For a single-ended signal a matching impedance should be connected on the positive input of channel 2 (J6) for proper balance. Use this channel when using a single-ended input. J6 Q IN+: Positive analog input for channel 2. Apply the analog signal of interest to this SMA. Terminate this channel to an impedance that matches Q IN– when using a singleended input on J5. If J6 is being driven single-ended, a matching impedance should be connected on the negative input of channel 2 (J5) for proper balance. J3 ENC+: Positive encode clock input. As a default the demo board is populated to accept a single-ended clock input from a DC1075A demo board, or an equivalent CMOS signal. For other population options see the encode clock section of this manual. J4 ENC–: Negative encode clock input. As a default this input port is grounded to accommodate the single-ended clock drive. For other population options see the encode clock section of this manual. Turrets: V+: Positive input voltage for the ADC and digital buffers. This voltage feeds a regulator that supplies the proper voltages for the ADC and buffers. The voltage range for this turret is 4.5V up to 6V. AMP VCC: Voltage supply for the amplifiers. This voltage input is unregulated, and supplies the two amplifiers directly. The voltage range for this turret is 2.7V to 5.2V. The recommended voltage is 3.3V. EXT REF: Optional reference programming voltage. This pin is connected directly to the SENSE pin of the ADC. If no external voltage is supplied this pin will be pulled to VDD through a weak pull-up resistor. This will select the ±1V input range. Connect to GND to select the ±0.5V input range, an external reference between 0.625V and 1.3V will select an input range of ±0.8 • VSENSE. SHDN1: Shutdown pin for the U2. As a default this pin is tied to Amp VCC through 100kΩ. Connect this pin to GND to manually shutdown U2. SHDN2: Shutdown pin for the U3. As a default this pin is tied to Amp VCC through 100kΩ. Connect this pin to GND to manually shutdown U3. GND: Ground connection. This demo board only has a single ground plane. This turret should be tied to the GND terminal of the power supply being used. Jumpers: The DC1945A demonstration circuit board should have the following jumper settings as default positions (as per Figure 1) which configures the ADC in serial programming mode. In the default configuration JP3 to JP6 should be left in the default locations. This will pull those pins high through weak pull-up resistors so that the SPI commands can be sent from the PC. When JP2 is set to PAR, then jumpers JP3 to JP6 can be configured manually. JP1 PAR/SER: Selects parallel or serial programming mode. (Default: serial) JP2 Duty Cycle Stab: In parallel programming mode enables or disables duty cycle stabilizer. In serial programming mode, pull up to VDD. (Default: Enable or pull-up) JP3 SHDN: In parallel programming mode enables or disables LTC2185. In serial programming mode, pull-up to VDD. (Default: Enable or pull-up) JP4 NAP: In parallel programming mode enables or disables NAP mode. In serial programming mode, pull up to VDD. (Default: Enable or pull-up) JP5 LVDS/CMOS: In parallel programming mode selects between LVDS or CMOS output signaling. In serial programming mode, pull up to VDD. (Default: LVDS or pull-up) Note: CMOS mode not supported on the DC1945 demo board. dc1945af 3 DEMO MANUAL DC1945A Applying Power & Signals To The DC1945A Demonstration Circuit If a DC890 is used to acquire data from the DC1945A, the DC890 must FIRST be connected to a powered USB port or provided an external 6V to 9V. Make this connection BEFORE applying 4.5V to 6V across the pins marked V+ and GND, or 2.7V to 5.2V on the AMP_VCC pin on the DC1945A. DC1945A requires 4.5V on the ADC input for proper operation, regulators on the board produce the voltages required for the ADC. The voltage applied to the amplifier is not regulated. The DC1945A demonstration circuit requires up to 150mA on the ADC input depending on the sampling rate and the A/D converter supplied, and up to 150mA on the amplifier power input. The DC890 data collection board is powered by the USB cable and does not require an external power supply unless it must be connected to the PC through an unpowered hub—in which case, it must be supplied an external 6V to 9V on turrets G7(+) and G1(–) or the adjacent 2.1mm power jack. Analog Input Network The input network of the DC1945 can be modified to accommodate various applications. In the default setup both of the inputs are brought out to SMA connectors so the demo board can be driven with a differential source. To drive the demo board with a single-ended source simply drive J1 or J5 and terminate J2 or J6 with the matched source impedance of the signal source. As a default the DC1945 is populated with no filtering between the input SMAs and the ADC. This allows a custom filter to be designed and installed between the amplifier and ADC. There are also pads for a filter before the amplifier itself. The gain of the amplifier can also be changed by varying the feedforward and feedback resistors. For optimal distortion and noise performance, the filter network can be implemented for different analog input frequencies after the LTC6409. Be sure not to overdrive the ADC by setting the gain too high; refer to the LTC6409 data sheet for resistor value considerations. The DC1945 can also be used to sample I and Q channels of a signal, and through the PScope software these channels can be processed to get image rejection in one of the channels. This requires the I channel (J1 and J2) and the Q channel (J5 and J6) be driven with the same demodulated signal. In almost all cases, off-board filters will be required on both analog input and encode clock to produce maximum SNR. The off-board filters should be located close to the SMA inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion. dc1945af 4 DEMO MANUAL DC1945A Encode Clock Apply an encode clock to the SMA connector on the DC1945A demonstration circuit board marked J3. As a default, the DC1945A is populated to have a single-ended input. For the best noise performance, the ENCODE INPUT must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VPP or 13dBm. When using a sinusoidal signal generator, a squaring circuit can be used. Linear Technology also provides DC1075A, a demo board that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2185. Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1945A, a bandpass filter used for the clock should be used prior to the DC1075A. Data sheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, nonharmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used with TTE bandpass filters for both the clock input and the analog input. An internally generated conversion clock output is available on P1, which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8-150 type connector or collected by the DC890 QuikEval II data acquisition board using PScope™ software. The clock network on the DC1945 can support a variety of clock inputs. As a default it is populated to accept a singleended square wave clock from a DC1075 or appropriate signal generator. This will drive the ENC+ pin single-ended and the ENC– pin on the ADC is tied to GND. When using a single-ended sine wave generator to drive the encode input of the ADC, it is best to use a single-ended to differential translation circuit. To modify the DC1945 to accommodate this first move the 0Ω resistor populated in position R47 to position R50, and move R54 and R48 to the R4 and R5 locations. This will direct the signal through the transformer T3 which will do the single-ended to differential translation. When using a PECL or LVDS clock you can drive the DC1945 differentially through J3 and J4. From the default population, remove the 0Ω resistor in the C1 position and add the appropriate termination for your clock signal. R46, R55, R49, R51 and R52 are available to provide the proper termination for LVDS, PECL, or CML signaling. Blocking capacitors can be installed in the R78 and R79 positions if the common mode voltage of the clock is not compatible with the LTC2185. dc1945af 5 DEMO MANUAL DC1945A Software The DC890 is controlled by the PScope system software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a DC890 was provided, follow the DC890 Quick Start Guide and the instructions below. Manual Configuration Settings: To start the data collection software if PScope.exe is installed (by default) in \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu and browse to the PScope directory and select PScope. Channs: 2 If the DC1945A demonstration circuit is properly connected to the DC890, PScope should automatically detect the DC1945A, and configure itself accordingly. If necessary, the following procedure explains how to manually configure PScope. Under the Configure menu, go to ADC Configuration. Check the Config Manually box and use the following configuration options (see Figure 2). Bits: 16 Alignment: 16 FPGA Ld: DDR LVDS Bipolar: Unchecked Positive-Edge Clk: Unchecked Figure 2: ADC configuration If everything is hooked up properly, powered and a suitable encode clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC890B Quick Start Guide and in the online help available within the PScope program itself. SERIAL PROGRAMMING PScope has the ability to program the DC1945A board serially through the DC890. There are several options available in the LTC2185 family that are only available through serially programming. PScope allows all of these features to be tested. These options are available by first clicking on the Set Demo Bd Options icon on the PScope toolbar (Figure 3). Figure 3. PScope Toolbar Figure 2. ADC Configuration dc1945af 6 DEMO MANUAL DC1945A Software This will bring up the menu shown in Figure 4. This menu allows any of the options available for the LTC2185 family to be programmed serially. The LTC2185 family has the following options: Power Control: Selects between normal operation, nap and sleep modes n n n Normal (default): Entire ADC is powered and active Nap: ADC core powers down while references stay active Shutdown: The entire ADC is powered down Clock Inversion: Selects the polarity of the CLKOUT signal n Normal (default): Normal CLKOUT polarity n Inverted: CLKOUT polarity is inverted Clock Delay: Selects the phase delay of the CLKOUT signal n 0 Deg (default): No CLKOUT delay n 45 Deg: CLKOUT delayed by 45 degrees n 90 Deg: CLKOUT delayed by 90 degrees n 135 Deg: CLKOUT delayed by 135 degrees Figure 4. Demobd Configuration Options dc1945af 7 DEMO MANUAL DC1945A Software Clock Duty Cycle: Enable or disables duty cycle stabilizer Test Pattern: Selects digital output test patterns n Stabilizer off (default): Duty cycle stabilizer disabled n Off (default): ADC data presented at output n Stabilizer on: Duty cycle stabilizer enabled n All Out =1: All digital outputs are 1 n All Out = 0: All digital outputs are 0 Output Current: Selects the LVDS output drive current. n 1.75mA (default): LVDS output driver current n 2.1mA: LVDS output driver current n 2.5mA: LVDS output driver current n n n 3mA: LVDS output driver current n 3.5mA: LVDS output driver current n 4mA: LVDS output driver current n n 4.5mA: LVDS output driver current n Off (default): Disables internal termination n On: Enables internal termination Outputs: Enables Digital Outputs n Enabled (default): Enables digital outputs n Disabled: Disables digital outputs Output Mode: Selects digital output mode n n n Full Rate: Full rate CMOS output mode. This mode is not supported by the DC1945A. Double LVDS (default): Double data rate LVDS output mode Alternating: Digital outputs alternate between all 1’s and all 0’s on alternating samples Alternate Bit: Alternate bit polarity (ABP) mode Internal Termination: Enables LVDS internal termination. n Checkerboard: OF and D13-D0 alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternating samples Off (default): Disables alternate bit polarity On: Enables alternate bit polarity. Before enabling ABP, be sure the part is in offset binary mode Randomizer: Enables data output randomizer n Off (default): Disables data output randomizer n On: Enables data output randomizer Two’s complement: Enables two’s complement mode n Off (default): Selects offset binary mode n On: Selects two’s complement mode Once the desired settings are selected, hit OK and PScope will automatically update the register of the device on the DC1945A demo board. Double CMOS: Double data rate CMOS output mode. This mode is not supported by the DC1945A. dc1945af 8 DEMO MANUAL DC1945A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components 1 1 CN1 CAPACITOR ARRAY, 4 ELEMENT, 2.2µF, 4V, 20%, X7S AVX, W2L14Z225MAT1A 2 7 C1, R47, R48, R53, R54, R78, R79 RES., CHIP, 0Ω, 1/16W, 0402 YAGEO, RC0402JR-070RL 3 5 C2, C3, C13, C59, C61 CAP., X7R, 0.01µF, 16V, 10%, 0402 AVX, 0402YC103KAQ2A, 2rls 4 19 C4, C15, C16, C20, C21, C25, C42-C44, CAP., OPT, 0402 C47-C52, C57, C58, C60, C62 OPTION 5 2 C5, C53 CAP., X7R, 0.01µF, 50V, 10%, 0402 TDK, C1005X7R1H103K 6 15 C6, C7, C26, C27-C32, C34-C36, C56, C65, C66 CAP., X7R, 0.1µF, 50V, 10%, 0603 TDK, C1608X7R1H104K 7 4 C8, C9, C10, C11 CAP., COG, 0.5pF, 50V, ±0.1pF, 0201 TDK, C0603C0G1H0R5B 8 1 C12 CAP., X5R, 4.7µF, 16V, 10%, 1210 MURATA, GRM32RR61C475KC01L 9 4 C14, C22, C72, C73 CAP., X7R, 1µF, 16V, 10%, 0603 NIC, NMC0603X7R105K16TRPF 10 2 C17, C23 CAP., X5R, 2.2µF, 6.3V, 20%, 0402 AVX, 04026D225MAT2A 11 5 C18, C19, C37, C39, C41 CAP., X5R, 0.1µF, 10V, 10%, 0402 TDK, C1005X5R1A104K 12 1 C24 CAP., X5R, 4.7µF, 6.3V, 20%, 0603 TDK, C1608X5R0J475MT 13 0 C33, C70, C71 CAP., OPT, 0603 OPTION 14 4 C45, C46, C63, C64 CAP., X7R, 0.1µF, 50V, 10%, 0402 TDK, C1005X7R1H104K 15 2 C54, C55 (BAL TO 1466B) CAP., X5R, 10µF, 16V, 10%, 0805 AVX, 0805YD106KAT2A 16 3 C67, C68, C69 CAP., NPO, 22pF, 16V, 5%, 0402 AVX, 0402YA220JAT2A 17 3 E1, E7, E8 TEST POINT, TURRET, 0.061" MILL-MAX, 2308-2-00-80-00-00-07-0 18 8 E2, E3, E4, E5, E6 TESTPOINT, TURRET, 0.094" MILL-MAX, 2501-2-00-80-00-00-07-0 19 5 JP1, JP2, JP3, JP4, JP5 HEADER, 3 PIN, 0.079 SAMTEC, TMM-103-02-L-S 20 6 J1, J2, J3, J4, J5, J6 CON., SMA, 50Ω, EDGE-LAUNCH EMERSON, 142-0701-851 21 0 L1, L5, L10, L13, L21 INDUCTOR, OPTION, 0603 OPTION 22 3 L2, L3, L4 FERRITE BEAD, 33Ω at 100MHz, 1206 MURATA, BLM31PG330SN1L 23 8 L6, L7, L8, L9, L16, L19, L20, L22 RES., CHIP, 0Ω, 1/10W, 0603 VISHAY, CRCW06030000Z0EA 24 4 L11, L12, L17, L18 RES., CHIP, 49.9Ω, 1/10W, 1%, 0603 NIC, NRC06F49R9TRF 25 4 L14, L15, L23, L24, RES., CHIP, 100Ω, 1/10W, 1%, 0603 NIC, NRC06F1000TRF 26 4 MH1, MH2, MH3, MH4 STANDOFF, SNAP-ON KEYSTONE, 8831 27 1 RN2 4 RES. ARRAY, 33Ω, 5%, 1/16W VISHAY, CRA04S08333R0JTD 28 10 R1, R2, R38, R41, R42, R44, R65, R66, R73, R85 RES., CHIP, 49.9Ω, 1/16W, 1%, 0402 VISHAY, CRCW040249R9FKED 29 0 R3, R4, R5, R9, R10, R13, R15, R27, R28, R31, R37, R40, R43, R49-R52, R57, R60, R63, R74, R82, R84, R86, R87, R88 RES., CHIP, OPT, 0402 OPTION 30 1 R6 RES., CHIP, 10k, 1/16W, 5%, 0402 NIC, NRC04J103TRF 31 1 R7 RES., CHIP, 180k, 1/16W, 1%, 0402 VISHAY, CRCW0402180KFKED 32 1 R8 RES., CHIP, 330k, 1/16W, 1%, 0402 YAGEO, RC0402FR-07330KL 33 2 R11, R12 RES., CHIP, 3k, 1/16W, 1%, 0402 VISHAY, CRCW04023K00FKED 34 6 R14, R33, R34, R35, R80, R81 RES., CHIP, 1k, 1/16W, 5%, 0402 VISHAY, CRCW04021K00JNED 35 3 R16, R46, R55 RES., CHIP, 100Ω, 1/16W, 1%, 0402 VISHAY, CRCW0402100RFKED dc1945af 9 DEMO MANUAL DC1945A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 36 17 R17-R23, R30, R61, R62, R64, R68, R69, R72, R75-R77 RES., CHIP, 100Ω, 1/20W, 5%, 0201 VISHAY, CRCW0201100RJNED 37 3 R24, R32, R36 (BAL TO 1968A) RES., CHIP, 100k, 1/16W, 1%, 0402 YAGEO, RC0402FR-07100KL 38 3 R25, R26, R29 (BAL TO 1466B) RES., CHIP, 4.99k, 1/10W, 1%, 0603 NIC, NRC06F4991TRF 39 4 R39, R45, R70, R71 RES., CHIP, 402Ω, 1/16W, 1%, 0402 VISHAY, CRCW0402402RFKED 40 4 R56, R59, R83, R89 RES., CHIP, 27.4Ω, 1/16W, 1%, 0402 VISHAY, CRCW040227R4FKED 41 2 R58, R67 RES., CHIP, 51.1Ω, 1/16W, 1%, 0402 VISHAY, CRCW040251R1FKED 42 1 T3 TRANSFORMER, RF~SMT~1:1 BALUN MACOM, MABA-007159-000000 43 1 U1 I.C., 16-BIT ADC, QFN LINEAR TECHNOLOGY, LTC2185IUP#PBF 44 2 U2, U3 I.C., HIGH SPEED DIFF. AMP./DRIVER, QFN LINEAR TECHNOLOGY, LTC6409IUDB#PBF 45 2 U4, U6 I.C., LOW DROPOUT REGULATOR, 3×3mm, DFN LINEAR TECHNOLOGY, LT3080EDD-1#PBF 46 1 U5 I.C., REMOTE 8-BIT I/O EXPANDER, SSOP-20 NXP, PCF8574TS/3,118 47 1 U7 I.C., LVDS REPEATER, US8 FAIRCHILD, FIN1101K8X 48 2 U8, U10 I.C., LVDS 8 PORT REPEATER, TSSOP FAIRCHILD, FIN1108MTDX 49 1 U9 (BAL TO 1876A, 1074A & 1685A) I.C., EEPROM, 2kB, 400kHz, 8TSSOP MICROCHIP, 24LC025-I/ST XJP1, XJP2, XJP3, XJP4, XJP5 50 5 SHUNT, 2mm SAMTEC, 2SN-BK-G 51 1 FAB, PRINTED CIRCUIT BOARD DEMO CIRCUIT 1945A (REV 1) 52 1 STENCIL SET (TOP & BOTTOM) STENCIL DC1945A dc1945af 10 A B C D E2 E1 J4 J3 1 1 C1 OPT 0402 C60 OPT C17 2.2uF 0 OHMS 0.01uF T3 5 4 1. ALL CAPACITORS AND RESISTORS ARE 0402. 5 3 2 1 6 3 MABA-007159-000000 4 5 7 2 VDD 8 R46 100 1% 0 OHMS 2 R5 OPT R48 0603 R54 0 OHMS R4 OPT R2 49.9 C3 1% 0.01uF L5 R1 49.9 1% OPT 1 CN1 2.2uF X4 1 (0 OHMS RESISTOR INSTALLED FOR C1) R53 C59 C2 0.01uF 0 OHMS R50 OPT R47 C41 0.1uF C39 0.1uF NOTES: UNLESSOTHERWISE SPECIFIED, ENC- ENC+ VCM2 AIN2+ AIN2- PAR/!SER VCM1 AIN1- AIN1+ GND EXT REF R78 C6 0.1uF 0603 4 C61 0.01uF 0 OHMS 0 OHMS R55 100 1% R52 OPT R79 R51 OPT R49 OPT C13 0.01uF C7 0.1uF 0603 VDD VDD VCM1 GND AIN1+ AIN1GND REFH REFL REFH REFL PAR/SER AIN2+ AIN2GND VCM2 VDD R16 100 SHT 2 SD0 R14 1K R17 100 0201 R18 100 0201 R19 100 0201 U1 LTC2185IUP R77 100 0201 R76 100 0201 R75 100 0201 R72 100 0201 R69 100 0201 PAD D1_4_5+ D1_4_5D1_2_3+ D1_2_3D1_0_1+ D1_0_1OVDD OGND CLKOUT+ CLKOUTD2_14_15+ D2_14_15D2_12_13+ D2_12_13D2_10_11+ D2_10_11- R20 100 0201 R30 100 0201 3 65 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 3 R21 100 0201 R68 100 0201 R64 100 0201 OVDD R22 100 0201 R62 100 0201 R23 100 0201 OUT-ENABLE1 1 2 3 4 24 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 3 22 27 46 13 +3.3V VBB IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4IN5IN5+ IN6+ IN6IN7IN7+ IN8+ IN8- EN12 EN34 EN56 EN78 EN RIN+ VCC DOUT+ DOUT- U7 +3.3V VBB IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4IN5IN5+ IN6+ IN6IN7IN7+ IN8+ IN8- EN12 EN34 EN56 EN78 EN OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUR4+ OUT4OUT5OUT5+ OUT6+ OUT6OUT7OUT7+ OUT8+ OUT8- 8 7 6 5 0603 C56 0.1uF FIN1101K8X RINGND EN GND 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 +3.3V OUT1OUT1+ OUT2+ OUT2OUT3OUT3+ OUR4+ OUT4OUT5OUT5+ OUT6+ OUT6OUT7OUT7+ OUT8+ OUT8- 2 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. CUSTOMER NOTICE 24 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 3 22 27 46 13 U8 FIN1108 OUT-ENABLE1 R61 100 0201 OUT-ENABLE1 U10 FIN1108 Figure 5. LTC2185 and LTC6409 Combo Board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD C23 2.2uF VDD ENC+ ENCCS SCK SDI CS SCK SDI SHT 2 4 SD0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDO SENSE VREF SDO OF2_1+ OF2_1D1_14_15+ D1_14_15D1_12_13+ D1_12_13D1_10_11+ D1_10_11D1_8_9+ D1_8_9D1_6_7+ D1_6_7VDD ENC+ ENCCS SCK SDI D2_0_1D2_0_1+ S2_2_3S2_0_3+ D2_4_5D2_4_5+ D2_6_7D2_6_7+ D2_8_9D2_8_9+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 12 25 26 47 48 VC1 VC2 VC3 VC4 VC5 VE1 VE2 VE3 VE4 VE5 1 2 23 36 37 5 ENG. C. MAYOTT PCB DES. M.HAWKINS APPROVALS CONTRACT NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 4 3 2 1 C27 DATE: WP SDA SCL R24 100K SCL SDA +3.3V VCC_IN SDA VSS SCL DATE SHT 2 SDA SHT 2 SCL 4/24/2012 4/24/2012 IC NO. 1 DEMO CIRCUIT 1945A LTC2185IUP, LTC6409IUDB SHEET 1 OF 2 2 REV LTC2185 AND LTC6409 COMBO BOARD 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only SDA R26 4.99K 1% 0603 SCL VCC_IN VSS OUT-ENABLE1 4.99K 1% 0603 R29 R25 4.99K 1% 0603 TECHNOLOGY 5 6 7 8 0.1uF 0603 VCC 24LC025-I /ST VSS A2 A1 A0 U9 TITLE: SCHEMATIC SIZE 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 EDGE-CON-100 C.MAYOTT P1 APPROVED PRODUCTION 2 1 DESCRIPTION REVISION HISTORY REV FAST DAACS BOARD ID CIRCUITRY - ECO A B C D DEMO MANUAL DC1945A Schematic Diagram dc1945af 11 A B C D Q IN + Q IN - I IN + I IN- 1 1 1 1 E8 E7 R13 OPT 0402 C16 OPT 0402 C20 OPT 0402 R10 OPT 0402 R31 OPT 0402 C47 OPT 0402 C48 OPT 0402 R28 OPT 0402 5 2.7V-5.2V AMP VCC SHDN 2 J6 J5 SHDN 1 J2 J1 E6 L15 100 0603 L24 100 0603 L23 100 C50 OPT 0402 2 C43 OPT 0402 2 2 C49 OPT 0402 2 C42 OPT 0402 C12 4.7uF 1210 AMPQVCC R32 100K 0603 AMPQVCC 1 1 R36 100K 0603 AMPQVCC 1 1 L14 100 0603 0603 L17 0603 L12 1 49.9 2 L1 OPT 0603 49.9 2 49.9 2 L10 OPT 0603 49.9 2 R15 OPT 0402 R66 R3 OPT 0402 R44 AMPQVCC R27 OPT 0402 R65 R67 R9 OPT 0402 R42 R58 AMPQVCC C4 OPT 0402 VCM2 AMPQVCC C15 OPT 0402 C51 OPT 0402 VCM1 AMPQVCC C52 OPT 0402 4 49.9 C5 0.01uF 51.1 49.9 49.9 C53 0.01uF 51.1 49.9 3 6 5 2 3 6 5 2 SHDN -IN Vocm +IN SHDN -IN Vocm +IN 4 R39 C9 - + 0.1uF C46 402 0.5pF 0201 7 1 49.9 R41 0603 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. 0402 R43 OPT 0603 L19 0 OHMS 1 2 C21 OPT 0402 R59 27.4 2 C44 OPT 0402 0402 2 ENG. C. MAYOTT PCB DES.M.HAWKINS APPROVALS DATE: SIZE AIN2- AIN2+ AIN1- AIN1+ 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only 1 1/09/2012 IC NO. 1 DEMO CIRCUIT 1945A LTC2185IUP, LTC6409IUDB SHEET 2 OF 3 2 REV LTC2185 AND LTC6409 COMBO BOARD TECHNOLOGY R63 OPT 0402 R37 OPT 0402 R87 OPT 0402 R86 OPT 0402 TITLE: SCHEMATIC R60 OPT 0603 L16 0 OHMS 1 2 0603 L22 0 OHMS 1 2 CONTRACT NO. C25 OPT 0402 L20 0 OHMS 1 2 0402 R57 OPT R40 OPT 0402 0402 0603 2 C62 OPT 0402 0 OHMS 0603 0 OHMS R88 OPT R56 27.4 R89 27.4 L8 1 L7 1 0402 R82 OPT 0402 2 C57 OPT 0402 R83 27.4 2 R74 OPT 0603 2 C58 OPT 0402 0 OHMS 0603 0 OHMS 49.9 L9 1 L6 1 R38 49.9 R73 49.9 R85 0402 R84 OPT CUSTOMER NOTICE LTC6409IUDB U3 +OUT -OUT 0.1uF C45 0.5pF 0201 AMPQVCC C8 402 402 R70 R45 0.5pF 0201 7 1 LTC6409IUDB U2 +OUT -OUT 0.1uF C63 C10 - + 0.1uF C64 0.5pF 0201 402 AMPQVCC C11 R71 3 Figure 6. LTC2185 and LTC6409 Combo Board NOTES: UNLESSOTHERWISE SPECIFIED, 1. ALL CAPACITORS AND RESISTORS ARE 0402. 0603 L18 L21 OPT 0603 1 1 L13 OPT 0603 1 L11 1 2 1 2 1 2 4 V+ V10 1 2 9 V+ 4 V+ V10 V8 V- PAD 11 V- PAD 9 V+ V8 12 11 5 A B C D DEMO MANUAL DC1945A Schematic Diagram dc1945af Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D GND GND E5 E4 E3 V+ 4.5V - 6V PAR/!SER CS SDI SD0 SCK SCL SDA C24 4.7uF 0603 JP2 3 2 1 R34 1K C22 1.0uF 0603 C14 1.0uF 0603 VIN 5 8 7 5 8 7 VCTRL VIN VIN U6 VCTRL VIN VIN U4 DUTY CYCLE STAB. DIS EN R33 1K 5 3 2 1 VDD SHDN 9 1 2 3 9 1 2 3 1% R8 330K PAD VOUT VOUT VOUT LT3080EDD 180K 1% R7 PAD VOUT VOUT VOUT LT3080EDD DIS EN JP3 1. ALL CAPACITORS AND RESISTORS ARE 0402. NOTES: UNLESSOTHERWISE SPECIFIED, SHT 2 3 PAR PAR/SER 2 1 SER JP1 VDD C73 1.0uF 0603 3 2 1 R12 3K 1% 1 1 1 MH3 1 MH4 4 C26 0.1uF 0603 0.1uF 0603 C31 C33 OPT 0603 1 2 3 4 0.1uF 0603 C32 C70 OPT 0603 8 7 6 5 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 ENG. C. MAYOTT PCB DES.M.HAWKINS APPROVALS 0.1uF 0603 C30 10 11 12 14 16 17 19 20 18 13 CONTRACT NO. 0.1uF 0603 C19 0.1uF 0402 P0 P1 P2 P3 P4 P5 P6 P7 NC NC 0.1uF 0603 C35 DATE: SIZE 0.1uF 0603 C66 C69 22 pF SCK SDI SD0 CS R6 10K 0.1uF 0603 C65 +3.3V 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 Fax: (408)434-0507 LTC Confidential-For Customer Use Only 1 IC NO. 1/09/2012 1 DEMO CIRCUIT 1945A LTC2185IUP, LTC6409IUDB SHEET 3 OF 3 3 REV LTC2185 AND LTC6409 COMBO BOARD TECHNOLOGY 0.1uF 0603 C36 C68 22 pF TITLE: SCHEMATIC 0.1uF 0603 C34 C71 OPT 0603 C67 22 pF RN2 ARRAY, 33 OHMS, 4 RES, SMT CUSTOMER NOTICE C29 0.1uF 0603 C18 0.1uF 0402 A0 A1 A2 SCL SDA NC NC INT C28 +3.3V VDD 6 7 9 2 4 3 8 1 U5 PCF8574-SSOP20 +3.3V 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. C37 0.1uF 3 Figure 7. LTC2185 and LTC6409 Combo Board 1206 +3.3V R81 1K OVDD LVDS/CMOS 3 2 1 VDD L4 FERRITE BEAD, 33 OHMS 1206 R11 3K 1% REPRESENTS STAND OFFS MH2 MH1 CMOS LVDS JP5 L2 VDD FERRITE BEAD, 33 OHMS 1206 R80 1K L3 FERRITE BEAD, 33 OHMS NAP C72 1.0uF 0603 DIS EN JP4 VDD USED TO MANUFACTURE PCB C55 10uF 0805 C54 10uF 0805 R35 1K 4 5 VDD GND 15 VDD SET 4 SET 4 5 A B C D DEMO MANUAL DC1945A Schematic Diagram dc1945af 13 DEMO MANUAL DC1945A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright © 2004, Linear Technology Corporation dc1945af 14 Linear Technology Corporation LT 0513 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2013