Copyright © 2002-2011 Macraigor Systems LLC, all rights reserved. Common OCD pinouts NOTE: Macraigor Systems accepts NO responsibility for the accuracy of the following information. We strongly recommend that you use the OCD header specified by the semiconductor manufacturer. Please refer to the manufacturer’s proper data book or reference design for information. The pinouts given below may show a subset of the signals specified by the manufacturer. General Notes: • • • • • • Unless otherwise indicated, all headers are male dual-row Berg style connectors on 0.1 centers. We do not specify the use of pull ups or pull downs on any signals although they may be needed. Check with the chip manufacturer. TVcc pins should be the I/O ring voltage and that signal is used to determine the electrical characteristics of the other signals. If you must current limit this line, allow the probe at least 1 mA. Unless otherwise indicated, RESET\ is an open collector signal from the probe to the target. It should directly drive the target processor and not drive power on reset circuits or the like. Some target boards may use a non-standard connector or a connector that we identify for a different target. Place the header as close to the processor as possible, use short traces of approximately equal length on all clock and data signals. Pin Specifications: Pins are identified by number and type. • • • • • • o i p oc = = = = output from target processor to OCD interface input to target processor from OCD interface power pin open collector driven from OCD interface, either floating or actively held low nc = not connected, ie: not driven nor read by OCD interface k = key, pin is typically missing from the target board Copyright © 2002-2011 Macraigor Systems LLC, all rights reserved. “COP” pinout Motorola PowerPC 6xx, 7xx, 8xxx IBM 4xx LSI SerialICE 2 TDO TDI HALTED TCK TMS SRESET HRESET CKSTP_OUT o i o i i i oc o 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 i i p nc nc p nc p QACK TRST\ TVcc GND GND “BDM” – Background Debug Mode There are actually several BDM pinouts. Motorola MPC8xx, MPC5xx NOTE: It is vital that pins 1 and 6 properly reflect the status of the target processor immediately following RESET. Some processors have configurable pins (MPC8xx, etc.) that are specified by a reset configuration word at the time of reset. These pins must be set properly and must ALWAYS reflect the status of the processor correctly. Check the ‘hardware reset configuration word’ in the Motorola User’s manual. FRZ or VFLS0 GND GND RESET\ TVcc o p p oc p 1 3 5 7 9 2 4 6 8 10 o i o i o SRESET DSCK FRZ or VFLS1 DSDI DSDO Motorola CPU32 (this version is obsolete and not recommended) GND GND RESET\ TVcc p p oc p 1 3 5 7 2 4 6 8 i o i o DSCK FRZ DSDI DSDO Copyright © 2002-2011 Macraigor Systems LLC, all rights reserved. Motorola CPU16, CPU32 Note: Most probes are powered via TVcc, hence don’t current limit. DS GND GND RESET\ TVcc o p p oc p 1 3 5 7 9 2 4 6 8 10 o i o i o BERR DSCK FRZ DSDI DSDO 2 4 6 8 10 12 14 p p p nc i p i GND GND GND “OnCE” – On Chip Emulation Motorola DSP, M•CORE, Tensilica, AMD AM32 TDI TDO TCK RESET\ TVcc i o i nc oc p nc 1 3 5 7 9 11 13 TMS GND TRST\ (note: RESET\ not supported for the AM32) ARM There are two standard ARM pinouts, and older 14 pin specification and a newer 20 pin specification. TVcc TRST\ TDI TMS TCK TDO TVcc p i i i i o p 1 3 5 7 9 11 13 2 4 6 8 10 12 14 p p p p p oc p GND GND GND GND GND RESET\ GND 2 4 6 8 10 12 14 16 18 20 p p p p p p p p p nc GND GND GND GND GND GND GND GND GND OR TVcc TRST\ TDI TMS TCK TDO RESET/ p i i i i nc o oc nc nc 1 3 5 7 9 11 13 15 17 19 Copyright © 2002-2011 Macraigor Systems LLC, all rights reserved. MIPS – EJTAG 2.5 There are many MIPS OCD headers in use. This is the one specified by MTI for EJTAG 2.5 TRST\ TDI TDO TMS TCK RESET\ DINT i i o i i oc i 1 3 5 7 9 11 13 2 4 6 8 10 12 14 p p p p p k p GND GND GND GND GND key TVcc TRST\ TDI TDO TMS TCK TVcc RESET\ i i o i i p oc nc nc nc 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 p p p p nc nc nc nc nc nc GND GND GND GND i i nc i i o o i TCK TMS Toshiba’s variant: AMD – Athlon These are the pins that Macraigor uses on the Athlon header. TVcc GND DBREQ RESET\ p nc nc nc nc p i oc 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 TDI TRST\ TDO DBRDY PLL_TEST