Datasheet

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Datasheet
A S1119
144-LED Cross-Plexing Driver with 320mA Charge-Pump
1 General Description
2 Key Features
The AS1119 is a compact LED driver for 144 (90) single LEDs. The
devices can be programmed via an I²C compatible interface.
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1MHz I²C-Compatible Interface
Open and Shorted LED Error Detection
The AS1119 offers two blocks driving each 72 LEDs (3 blocks each
30LEDs) with 1/9 (1/6) cycle rate. The required lines to drive all 144
(90 )LEDs are reduced to 18 by using the cross-plexing feature optimizing space on the PCB. Every block driving 72(30) LEDs can be
analog dimmed from 1 to 30mA in 256 steps (8 bit).
144 LEDs in Dot Matrix
Low-Power Shutdown Current
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Individual 8-bit LED PWM Control
Additionally each of the 144 (90) LEDs can be dimmed individually
with 8-bit allowing 256 steps of linear dimming. To reduce CPU
usage up to 6 frames can be stored with individual time delays
between frames to play small animations automatically.
8-bit Analog Brightness Control
(1:1), 2:3, 1:2 320mA Charge Pump
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6 Frames Memory for Animations
The AS1119 operates from 2.7V to 5.5V and includes a 320mA
charge-pump to drive also white LEDs. The charge-pump operates
in 2:3 and 1:2 mode.
System-clk synchronisation for multiple devices
Supply Voltage Range: 2.7V to 5.5V
The AS1119 features very low shutdown and operational current.
Minimum PCB space required
The device is available in a ultrasmall 36-pin WL-CSP.
36-pin WL-CSP package
3 Applications
The AS1119 is ideal for dot matrix displays in mobile phones, personal electronic and toys.
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Figure 1. AS1119 - Typical Application Diagram
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VDD
4.7µF
2.7V to 5.5V
9
9
9
VCP
4.7µF
9
VCP
VDD
2.2µF
2.2µF 4.7µF
1µF
AS1119
1µF
1µF
AS1119
1µF
SDA
µP
SCL
RSTN
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Revision 1.04
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AS1119
Datasheet - P i n o u t
4 Pinout
Pin Assignments
Table 1. Pin Descriptions
CS2
CS1
CS0
VDD1
A1
A2
A3
A4
A5
A6
C1-
CS5
CS4
CS3
GND1
SYNC_IN/
SYNC_OUT
B1
B2
B3
B4
B5
B6
C1+
CS8
CS7
CS6
AD0
SDA
C1
C2
C3
C4
C5
C6
C2+
CS11
CS10
CS9
AD1
SCL
D1
D2
D3
D4
D5
D6
VDD3
CS14
CS13
CS12
VDD2
IRQ
E1
E2
E3
E4
E5
E6
VCP
CS17
CS16
CS15
GND2
RSTN
F1
F2
F3
F4
F5
F6
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GND3
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Pin Descriptions
C2-
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Figure 2. Pin Assignments (Top View)
Pin Name
VDD1, VDD2,
VDD3
Pin Number
VCP
C1-, C1+
C2-, C2+
GND1
GND2
GND3
SDA
SCL
AD0
AD1
F1
B1, C1
A1, D1
B5
F5
A2
C6
D6
C5
D5
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A6, E5, E1
Description
Positive Supply Voltage. Connect to a +2.7V to +5.5V supply. Bypass this pin with 10µF capacitance
to GND1, GND2, GND3.
Charge-Pump Output Voltage. Connect a 2.2µF capacitor to GND3.
Flying Cap 1. Connect a 1µF capacitor.
Flying Cap 2. Connect a 1µF capacitor.
Ground for VDD1. Used for CS0-CS8
Ground for VDD2. Used for CS9-CS17
Ground for VDD3. Used for Charge-Pump
Serial-Data I/O. Open drain digital I/O I²C data pin.
Serial-Clock Input.
I²C Address for bit 0. Put to GND or VDD to set I²C addresses.
I²C Address for bit 1. Put to GND or VDD to set I²C addresses.
Reset Input. Pull this pin to logic low to reset all control registers (set to default values) and to put the
device into power-down. For normal operation pull this pin to VDD.
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RSTN
SYNC_IN,
SYNC_OUT
IRQ
F6
B6
Synchronization Clock Input or Output
E6
Interrupt Request. Open drain digital Output.
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AS1119
Datasheet - P i n o u t
Table 1. Pin Descriptions
CS9 - CS17
Sinks and Sources for 72 LEDs each matrix.
Sinks and Sources for 30 LEDs each matrix.
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CS0 - CS5
CS6 - CS11
CS12 - CS17
Description
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CS0 - CS8
Pin Number
A5-A3, B4-B2,
C4-C2
D4-D2, E4-E2,
F4-F2
A5-A3, B4-B2
C4-C2, D4-D2
E4-E2, F4-F2
3 Matrixes 2 Matrixes
Pin Name
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AS1119
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 5 is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Max
Units
-0.3
7
V
-0.3
7 or
VDD + 0.3
V
Electrical Parameters
VDD to GND
All other pins to GND
Sink Current
500
mA
Segment Current
100
mA
100
mA
Input Current (latch-up immunity)
-100
Norm: JEDEC 78
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Electrostatic Discharge
Comments
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Min
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Parameter
Electrostatic Discharge HBM
1.5
kV
Norm: MIL 883 E method 3015
Temperature Ranges and Storage Conditions
Junction Temperature
Storage Temperature Range
-55
Package Body Temperature
Humidity non-condensing
5
ºC
+125
ºC
+260
ºC
85
%
1
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020“Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
Represents a max. floor life time of unlimited
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Moisture Sensitive Level
+125
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AS1119
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7V to 5.5V, TAMB = -40°C to +85°C, typ. values are at TAMB = +25ºC (unless otherwise specified).
Table 3. Electrical Characteristics
Conditions
TAMB
Operating Temperature Range
VDD
Operating Supply Voltage
IDDSD
Software Shutdown Supply Current
All digital inputs at VDD or GND, VDD =
5.5V, TAMB = +25ºC
7
IDDFSD
Full Shutdown Supply Current
Pin RSTN = 0V, TAMB = +25ºC
0.1
CP disabled @ VDD = 5.5V
1.4
With CP in 2:3 mode
@ VDD = 2.7V
3
Operating Supply Current
(all current sources turned off)
IDD
ISTART
Min
Max
Unit
-40
85
°C
2.7
5.5
V
With CP in 1:2 mode
@ VDD = 2.7V
1
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700
CP disabled
Digit Drive Sink Current
1,2
(Drive capability of all sources of one digit )
Segment Drive Source Current LED
Segment Drive Current Matching LED
3
Saturation Voltage
VDSSAT
RDSON(N)
Resistance for NMOS
fOSC
Oscillator Frequency
fREFRESH
Display Scan Rate
CP enabled
µA
mA
1.5
max. Peak Inrush Current
ISEG
ΔISEG
µA
4
max. DC Current
IDIGIT
Typ
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Parameter
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Symbol
A
mA
500
VDD < 3.3V
160
VDD ≥ 3.3V
320
28
VOUT = 1.8V to VDD-400mV
Current = 30mA, VDD = 5V
2 time 9x8 matrixes
30
32
mA
mA
2
%
100
mV
0.5
1
Ω
0.9
1
1.1
MHz
0.39
0.43
0.48
kHz
1. Not all sources are allowed to be fully on at the same time.
2. guaranteed by design
I max – I min
I SEG = --------------------------- × 100
I max + I min
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3.
Table 4. Logic Inputs/Outputs Characteristics
VIH
VIL
Conditions
Logic Input Current
VIN = 0V or VDD
Min
-1
Typ
Max
1
Unit
µA
0.6
V
1.6
Logic High Input Voltage
V
Logic Low Input Voltage
0.1
Hysteresis Voltage
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ΔVI
Parameter
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Symbol
IIH, IIL
V
VOL(SDA)
SDA Output Low Voltage
ISINK = 3mA
0.4
V
IRQ Output Low Voltage
ISINK = 3mA
0.4
V
Sync Clock Output Low Voltage
ISINK = 1mA
0.4
V
VOH(SYNC_O
Sync Clock Output High Voltage
ISOURCE = 1mA
VDD-0.4
V
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VOL(IRQ)
VOL(SYNC_O
UT)
UT)
VDD-0.4
Open Detection Level Threshold
Short Detection Level Threshold
Capacitive Load for Each Bus Line
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VDD0.1
0.9
V
1.2
SCL Frequency = 400kHz
400
SCL Frequency = 1000kHz
100
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AS1119
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 5. I²C Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1000
kHz
fSCL
SCL Frequency
100
tBUF
Bus Free Time Between STOP and START Conditions
Hold Time for Repeated
START Condition
SCL Low Period
1.3
µs
160
ns
50
tSETUPDATA
SCL High Period
Setup Time for Repeated
START Condition
Data Setup Time
tHOLDDATA
Data Hold Time
tRISE(SCL)
10
tFALL(SCL)
SCL Rise Time
SCL Rise Time after Repeated START Condition and After
an ACK Bit
SCL Fall Time
tRISE(SDA)
SDA Rise Time
tFALL(SDA)
SDA Fall Time
tRISE(SCL1)
50
100
Notes:
ns
ns
70
ns
40
ns
80
ns
40
ns
20
80
ns
20
80
ns
10
10
160
Pulse Width of Spike Suppressed
ns
ns
10
tSETUPSTOP STOP Condition Setup Time
tSPIKESUP
75
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tSETUPSTART
75
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tLOW
tHIGH
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tHOLDSTART
50
ns
ns
1. The Min / Max values of the Timing Characteristics are guaranteed by design.
2. All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC
(Statistical Quality Control) methods.
Figure 3. Timing Diagram
SDI
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tBUF
tHOLDSTART
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SCL
tSPIKESUP
tSETUPDATA
tF
tSETUPSTOP
tSETUPSTART
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tR
tLOW
tHOLDSTART
tHIGH
tHOLDDATA
Repeated
START
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STOP START
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AS1119
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
Figure 5. Segment Drive Current vs. Temperature
30
29.5
29
+25°C
28.5
-45°C
+85°C
28
2.7
2.9
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30.5
31
30.5
30
29.5
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Segment Drive Source Current (mA)
31
29
Vdd = 2.7V
Vdd = 3.0V
28.5
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Segment Drive Source Current (mA)
Figure 4. Segment Drive Current vs. Supply Voltage
3.1
3.3
3.5
3.7
Vdd = 3.3V
Vdd = 4.0V
28
-45
3.9
-25
Supply Voltage (V)
55
75
Figure 7. RONNMOS vs. Supply Voltage
0.9
30.5
0.8
Ron NMOS ( Ω )
30
29.5
29
0.7
0.6
0.5
0.4
0.3
Vdd = 2.7V
0.2
Vdd = 3.3V
28.5
Vdd = 4.0V
-45°C
+25°C
0.1
+85°C
Vdd = 5.5V
1.6
2
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Segment Drive Source Current (mA)
35
1
28
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2
2.7
3.1
Output Voltage (V)
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4.3
4.7
5.1
5.5
1.1
-45°C
+25°C
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250
3.9
Figure 9. Short Detection Level vs. Supply Voltage
Short Detection Level (V)
300
3.5
Supply Voltage (V)
Figure 8. Open Detection Level vs. Supply Voltage
Open Detection Level (mV)
15
Temperature (°C)
Figure 6. Segment Drive Current vs. Output Voltage
31
-5
+85°C
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200
150
100
50
1.05
1
0.95
0.9
0.85
0.8
-45°C
0.75
+25°C
+85°C
0
0.7
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
Supply Voltage (V)
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3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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AS1119
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 10. Efficiency vs. Supply Voltage
Figure 11. Logic Input Voltage Levels
2
100
60
50
40
30
20
PWM = 0x255
PWM = 0x128
10
1.5
1
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Efficiency (%)
70
0.5
Logic High
Logic Low
PWM = 0x64
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
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Supply Voltage (V)
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80
Logic Input Voltage Level (V)
90
1:1 Mode
1:1.5 Mode
1:2 Mode
Figure 12. Charge Pump Voltage vs. Supply Voltage
Charge Pump Voltage (V)
7
6
5
4
3
PWM = 0x255
2
PWM = 0x128
PWM = 0x64
1
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
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Supply Voltage (V)
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AS1119
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
Block Diagram
Figure 13. AS1119 - Block Diagram
(#6
,-
+,1
(
(+,01
#$
5
1+,-
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"
&'(
&')*$
%
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+,-
"
#,
%
.
/
+,
1
5,
7
,1,+
#
8
8
4
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AS1119
Datasheet - D e t a i l e d D e s c r i p t i o n
I²C Interface
The AS1119 supports the I²C serial bus and data transmission protocol in fast mode at 1MHz. The AS1119 operates as a slave on the I²C bus.
The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and
STOP conditions. Connections to the bus are made via the open-drain I/O pins SCL and SDA.
Figure 14. I²C Interface Initialisation
8
9
1
8
9
0
SDA
1
1
1
A1
0
A0 R/W
D15 D14 D13 D12 D11 D10
D9
D8
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A0 and A1 are defined by the pins AD0 and AD1. Pin AD0 and AD1 must not be left floating.
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1
SCL
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Figure 15. Bus Protocol
MSB
SDI
ACK from
Receiver
Slave Address
R/W
Direction Bit
ACK from
Receiver
1
SCL
2
6
7
8
9
ACK
START
1
2
3-8
8
9
ACK
Repeat if More Bytes Transferred
STOP or
Repeated
START
The bus protocol (as shown in Figure 15) is defined as:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH will be interpreted as control signals.
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The bus conditions are defined as:
- Bus Not Busy. Data and clock lines remain HIGH.
- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
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- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
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- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device.
The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.
Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.
- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge
bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
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AS1119
Datasheet - D e t a i l e d D e s c r i p t i o n
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line HIGH to enable the master to generate the STOP condition.
- Figure 15 on page 10 details how data transfer is accomplished on the I²C bus. Depending upon the state of the
R/W bit, two types of data transfer are possible:
- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by
a number of data bytes. The slave returns an acknowledge bit after the slave address and each received byte.
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- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave
then returns an acknowledge bit. Next, a number of data bytes are transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received
byte, a not-acknowledge is returned. The master device generates all of the serial clock pulses and the START
and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since a
repeated START condition is also the beginning of the next serial transfer, the bus will not be released.
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The AS1119 can operate in the following slave modes:
- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial
transfer. Address recognition is performed by hardware after reception of the slave address and direction bit.
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- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver
mode. However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted on SDA by the AS1119 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
I²C Device Address Byte
The address byte (see Figure 16) is the first byte received following the START condition from the master device.
Figure 16. I²C Device Address Byte
address:
MSB
6
5
4
3
2
1
LSB
0
1
1
1
0
AD1
AD0
R/W
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- The bit 1 and bit 2 of the address byte are the device select pins AD0 and AD1, which must be set to VDD or to
GND. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at
one time.
- The last bit of the address byte (R/W) define the operation to be performed. When set to a 1 a read operation is
selected; when set to a 0 a write operation is selected.
Following the START condition, the AS1119 monitors the I²C bus, checking the device type identifier being transmitted. Upon receiving the
address code, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
Command Byte
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The AS1119 operation, (see Table 15 on page 21) is determined by a command byte (see Table 17).
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Figure 17. Command Byte
MSB
6
5
4
3
2
1
LSB
A7
A6
A5
A4
A3
A2
A1
A0
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AS1119
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 18. Command and Single Data Byte received by AS1119
From Master to Slave
AS1119 Registers
From Slave to Master
S
0
Slave Address
A7
A6
R/W A
A5
A4
A3
A2
A1
A0
D7
D6
D5
A
Command Byte
D4
D3
D2
A
Acknowledge
from AS1119
0
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Acknowledge
from AS1119
0
D0
Data Byte
1 Byte
Acknowledge
from AS1119
D1
0
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Autoincrement
Memory Word
Address
Figure 19. Setting the Pointer to a Address Register to select a Data Register for a Read Operation
From Master to Slave
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AS1119 Registers
From Slave to Master
S
0
Slave Address
A7
A6
R/W A
Acknowledge
from AS1119
A5
A4
A3
A2
A1
A0
A
Command Byte
Acknowledge
from AS1119
0
P
0
Figure 20. Reading n Bytes from AS1119
Autoincrement
Memory Word
Address
From Master to Slave
From Slave to Master
Acknowledge
from AS1119
Acknowledge
from Master
0
Stop reading
Not Acknowledge
from Master
0
1
n Bytes
S
Slave Address
R/W A
D7
D6
D5
D4
D3
D2
D1
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1
A
First Data Byte
D7
D6
D5
D4
D3
D2
D1
/A
P
D0
Autoincrement
to next address
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AS1119 Registers
D0
Second Data Byte
Initial Power-Up
ch
On initial power-up, the AS1119 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. At
this time, all registers should be programmed for normal operation.
Te
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control Register (see page
16) and (see page 20) is set to the minimum values.
Shutdown Mode
The AS1119 device features two different shutdown modes. A software shutdown via shutdown register (see Shutdown Register (0x0A)
on page 26) and a hardware shutdown via the RSTN pin.
The software shutdown disables all LED’s and stops the internal operation of the logic. A shutdown mode via the RSTN pin additionally powers
down the power-on-reset (PO) of the device. In this shutdown mode the AS1119 consumes only 100nA (typ.).
www.austriamicrosystems.com/LED-Driver-ICs/AS1119
Revision 1.04
12 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
9 Register Description
Register Selection
Within this register the access to one of the RAM sections or to the Control register is selected. After one section is selected this section is valid
as long as an other section is selected.
Table 6. Register Selection Address Map
Address
Data
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
Data Frame 1
2
0
0
0
0
0
0
1
0
Data Frame 2
3
0
0
0
0
0
0
1
4
0
0
0
0
0
1
0
5
0
0
0
0
0
1
0
253
1
1
1
1
1
1
Control Register
1
1
0
Selection of
RAM section for frame
1
am
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on A
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nt
st
il
Data Frame 4
0
No operation
lv
NOP
Data Frame 5
Description
HEX A7 A6 A5 A4 A3 A2 A1 A0 HEX D7 D6 D5 D4 D3 D2 D1 D0
Data Frame 0
Data Frame 3
al
id
Register Section
6
0
0
0
0
0
1
1
0
11
0
0
0
0
1
0
1
1
Selection of
Control Register
Data Definition of the single frames
One frame consits of 2 blocks (à 8x9 LED-matrix) or 3 blocks (à 5x6 LED-matrix). This configuration is set in the AS1119 config register (see
Table 20 on page 24).
In the internal DPRAM of the device 6 frames can be stored. For each frame the following parameters have to be stored.
- LED is ON or OFF.
- LED is steady ON or blinking.
- The intensity of every single LED can be set via a 8 bits PWM.
Note: After power-up the data in the DPRAM is undefined (either ‘0’ or ‘1’).
2 Blocks with 8x9 LED Matrix
The AS1119 can be configured to control two seperated blocks of LEDs matrixes. This must be set via the bit D0 in the AS1119 config register
(see AS1119 Config Register (0x04) on page 24).
Te
ch
ni
ca
Figure 21. 8x9 LED Matrix with two blocks
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Revision 1.04
13 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
The adress structure (as shown in Table 7) within on frame is always the same independent which frame was selected via the register selection
(see Table 6 on page 13).
Table 7. Dataframe Adress Structure for 2 Matrixes
Adresses within frame (HEX code)
Matrix B
CS9
CS10
CS11
CS12
CS13
CS14
CS15
CS16
CS17
Matrix B
0x01
0x03
0x05
0x07
0x09
0x0B
0x0D
0x0F
0x11
Matrix A
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
Intensity
Matrix B
0x13
0x15
0x17
0x19
0x1B
0x1D
0x1F
0x21
0x22
Matrix A
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
Matrix A
0x24-0x2B
0x34-0x3B
0x44-0x4B
0x54-0x5B
0x64-0x6B
0x74-0x7B
0x84-0x8B
0x94-0x9B
0xA4-0xAB
Matrix B
0x2C-0x33
0x3C-0x43
0x4C-0x53
0x5C-0x63
0x6C-0x73
0x7C-0x83
0x8C-0x93
0x9C-0xA3
0xAC-0xB3
am
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Matrix A
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
Blink
al
id
On / Off
lv
Current Source
In Table 8 it’s described which databit represents which LED in the matrix. Per default all databits are ‘0’, meaning no LED is on. A ‘1’ puts the
LED on.
Table 8. LEDs ON/OFF Register Format for 2 Matrixes Setup
Adress
Data
Matrix
Current
Source
HEX
A
CS0
0x00
0
0
0
0
0
0
0
0
B
CS9
0x01
0
0
0
0
0
0
0
1
A
CS1
0x02
0
0
0
0
0
0
1
0
B
CS10
0x03
0
0
0
0
0
0
1
1
A
CS2
0x04
0
0
0
0
0
1
0
0
B
CS11
0x05
0
0
0
0
0
1
0
1
A
CS3
0x06
0
0
0
0
0
1
1
0
B
CS12
A
CS4
ca
A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
1
1
1
0x08
0
0
0
0
1
0
0
0
A
ni
0x07
CS5
0x0A
0
0
0
0
1
0
1
0
B
CS14
0x0B
0
0
0
0
1
0
1
1
A
CS6
0x0C
0
0
0
0
1
1
0
0
B
CS15
0x0D
0
0
0
0
1
1
0
1
A
CS7
0x0E
0
0
0
0
1
1
1
0
B
CS16
0x0F
0
0
0
0
1
1
1
1
CS13
0x09
0
0
0
0
1
0
0
1
Te
ch
B
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Revision 1.04
D7
D6
LED7 LED
6
LED LED
15
14
LED LED
23
22
LED LED
31
30
LED LED
39
38
LED LED
47
46
LED LED
55
54
LED LED
63
62
LED LED
71
70
LED LED
79
78
LED LED
87
86
LED LED
95
94
LED LED
103 102
LED LED
111 110
LED LED
119 118
LED LED
127 126
D5
LED
5
LED
13
LED
21
LED
29
LED
37
LED
45
LED
53
LED
61
LED
69
LED
77
LED
85
LED
93
LED
101
LED
109
LED
117
LED
125
D4
LED
4
LED
12
LED
20
LED
28
LED
36
LED
44
LED
52
LED
60
LED
68
LED
76
LED
84
LED
92
LED
100
LED
108
LED
116
LED
124
D3
LED
3
LED
11
LED
19
LED
27
LED
35
LED
43
LED
51
LED
59
LED
67
LED
75
LED
83
LED
91
LED
99
LED
107
LED
115
LED
123
D2
LED
2
LED
10
LED
18
LED
26
LED
34
LED
42
LED
50
LED
58
LED
66
LED
74
LED
82
LED
90
LED
98
LED
106
LED
114
LED
122
D1
LED
1
LED
9
LED
17
LED
25
LED
33
LED
41
LED
49
LED
57
LED
65
LED
73
LED
81
LED
89
LED
97
LED
105
LED
113
LED
121
D0
LED
0
LED
8
LED
16
LED
24
LED
32
LED
40
LED
48
LED
56
LED
64
LED
72
LED
80
LED
88
LED
96
LED
104
LED
112
LED
120
14 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 8. LEDs ON/OFF Register Format for 2 Matrixes Setup
Data
Current
Source
HEX
A
CS8
0x10
0
0
0
1
0
0
0
0
B
CS17
0x11
0
0
0
1
0
0
0
1
A7 A6 A5 A4 A3 A2 A1 A0
D7
LED
135
LED
143
D6
LED
134
LED
142
D5
LED
133
LED
141
D4
LED
132
LED
140
D3
LED
131
LED
139
D2
LED
130
LED
138
D1
LED
129
LED
137
D0
LED
128
LED
136
al
id
Adress
Matrix
In the blink register (see Table 9) every single LED can be set to blink. The blink period is set in the display option register (see Display
Option Register (0x03) on page 23).
Table 9. LEDs Blink Register Format for 2 Matrixes Setup
A
CS0
0x12
0
0
0
1
0
0
1
0
B
CS9
0x13
0
0
0
1
0
0
1
1
A
CS1
0x14
0
0
0
1
0
1
0
0
B
CS10
0x15
0
0
0
1
0
1
0
1
A
CS2
0x16
0
0
0
1
0
1
1
0
B
CS11
0x17
0
0
0
1
0
1
1
1
A
CS3
0x18
0
0
0
1
1
0
0
0
B
CS12
0x19
0
0
0
1
1
0
0
1
A
CS4
0x1A
0
0
0
1
1
0
1
0
B
CS13
0x1B
0
0
0
1
1
0
1
1
A
CS5
0x1C
0
0
0
1
1
1
0
0
B
CS14
0x1D
0
0
0
1
1
1
0
1
A
CS6
B
CS15
A
D7
LED
7
LED
15
LED
23
LED
31
LED
39
LED
47
LED
55
LED
63
LED
71
LED
79
LED
87
LED
95
LED
103
LED
111
LED
119
LED
127
LED
135
LED
143
D6
LED
6
LED
14
LED
22
LED
30
LED
38
LED
46
LED
54
LED
62
LED
70
LED
78
LED
86
LED
94
LED
102
LED
110
LED
118
LED
126
LED
134
LED
142
D5
LED
5
LED
13
LED
21
LED
29
LED
37
LED
45
LED
53
LED
61
LED
69
LED
77
LED
85
LED
93
LED
101
LED
109
LED
117
LED
125
LED
133
LED
141
D4
LED
4
LED
12
LED
20
LED
28
LED
36
LED
44
LED
52
LED
60
LED
68
LED
76
LED
84
LED
92
LED
100
LED
108
LED
116
LED
124
LED
132
LED
140
D3
LED
3
LED
11
LED
19
LED
27
LED
35
LED
43
LED
51
LED
59
LED
67
LED
75
LED
83
LED
91
LED
99
LED
107
LED
115
LED
123
LED
131
LED
139
D2
LED
2
LED
10
LED
18
LED
26
LED
34
LED
42
LED
50
LED
58
LED
66
LED
74
LED
82
LED
90
LED
98
LED
106
LED
114
LED
122
LED
130
LED
138
D1
LED
1
LED
9
LED
17
LED
25
LED
33
LED
41
LED
49
LED
57
LED
65
LED
73
LED
81
LED
89
LED
97
LED
105
LED
113
LED
121
LED
129
LED
137
am
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on A
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st
il
0x1E
0
0
0
1
1
1
1
0
0x1F
0
0
1
1
1
1
1
1
CS7
0x20
0
0
1
0
0
0
0
0
CS16
0x21
0
0
1
0
0
0
0
1
ch
B
A7 A6 A5 A4 A3 A2 A1 A0
CS8
0x22
0
0
1
0
0
0
1
0
B
CS17
0x23
0
0
1
0
0
0
1
1
Te
A
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Revision 1.04
D0
LED
0
LED
8
LED
16
LED
24
LED
32
LED
40
LED
48
LED
56
LED
64
LED
72
LED
80
LED
88
LED
96
LED
104
LED
112
LED
120
LED
128
LED
136
lv
HEX
ca
Data
Current
Source
ni
Adress
Matrix
15 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
In the intensity register (see Table 10) the brightness of every single LED can bes set via a 8bit PWM (255 steps).
Table 10. LEDs Intensity Register Format for 2 Matrixes Setup
Adress
B
CS9
A
CS1
B
CS10
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
1
255 steps for intensity each single LED
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
1
255 steps for intensity each single LED
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
1
al
id
CS0
HEX
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
Te
ch
ni
ca
A
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
LED16
LED17
LED18
LED19
LED20
LED21
LED22
LED23
LED24
LED25
LED26
LED27
LED28
LED29
LED30
LED31
Data
lv
Current
Source
am
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on A
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st
il
Matrix
www.austriamicrosystems.com/LED-Driver-ICs/AS1119
Revision 1.04
16 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 10. LEDs Intensity Register Format for 2 Matrixes Setup
Adress
CS2
B
CS11
CS8
B
CS17
LED128
LED129
LED130
LED131
LED132
LED133
LED134
LED135
LED136
LED137
LED138
LED139
LED140
LED141
LED142
LED143
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
255 steps for intensity each single LED
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
1
.......................................
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
255 steps for intensity each single LED
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
1
Te
ch
ni
ca
A
HEX
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
al
id
A
LED32
LED33
LED34
LED35
LED36
LED37
LED38
LED39
LED40
LED41
LED42
LED43
LED44
LED45
LED46
LED47
Data
lv
Current
Source
am
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on A
te G
nt
st
il
Matrix
www.austriamicrosystems.com/LED-Driver-ICs/AS1119
Revision 1.04
17 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
3 Blocks with 5x6 LED Matrix
The AS1119 can be configured to control three seperated blocks of LEDs matrixes. This must be set via the bit D0 in the AS1119 config register
(see AS1119 Config Register (0x04) on page 24).
Figure 22. 5x6 LED Matrix with 3 Matrixes
Matrix B
Matrix C
am
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on A
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st
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lv
al
id
Matrix A
Table 11. Dataframe Adress Structure for 3 Matrixes
Adresses (HEX code)
Current Source
On / Off
Matrix
A
CS0
CS1
CS2
CS3
CS4
CS5
B
CS6
CS7
CS8
CS9
CS10
CS11
Blink
Matrix
C
CS12
CS13
CS14
CS15
CS16
CS17
B
A
0x00
0x02
0x04
0x06
0x08
0x0A
Intensity
Matrix
C
0x01
0x03
0x05
0x07
0x09
0x0B
A
0x12
0x14
0x16
0x18
0x1A
0x1C
B
Matrix
C
0x13
0x15
0x17
0x19
0x1B
0x1D
A
B
C
0x24-0x2B
0x2C-0x33
0x34-0x3B
0x3C-0x43
0x44-0x4B
0x4C-0x53
0x54-0x5B
0x5C-0x63
0x64-0x6B
0x6C-0x73
0x74-0x7B
0x7C-0x83
In Table 12 it’s described which databit represents which LED in the matrix. Per default all databits are ‘0’, meaning no LED is on. A ‘1’ puts the
LED on.
ca
Note: LED A01 is the first LED of the Current Source 0 in the Matrix A. LED B01 is the first LED of the Current Source 6 in the Matrix B. and
so on.
Table 12. LEDs ON/OFF Register Format for 3 Matrixes Setup
Adress
A7 A6 A5 A4 A3 A2 A1 A0
ni
HEX
Data
D7
LED
7
0x00
0
0
0
0
0
0
0
0
ch
Current
Source
0x01
0
0
0
0
0
0
0
1
X
0x02
0
0
0
0
0
0
1
0
LED
23
0x03
0
0
0
0
0
0
1
1
X
0x04
0
0
0
0
0
1
0
0
LED
39
0x05
0
0
0
0
0
1
0
1
X
CS0, CS6,
CS12
Te
CS1, CS7,
CS13
CS2, CS8,
CS14
www.austriamicrosystems.com/LED-Driver-ICs/AS1119
D6
LED
6
LED
14
LED
22
LED
30
LED
38
LED
46
Revision 1.04
D5
LED
5
LED
13
LED
21
LED
29
LED
37
LED
45
D4
LED
4
LED
12
LED
20
LED
28
LED
36
LED
44
D3
LED
3
LED
11
LED
19
LED
27
LED
35
LED
43
D2
LED
2
LED
10
LED
18
LED
26
LED
34
LED
42
D1
LED
1
LED
9
LED
17
LED
25
LED
33
LED
41
D0
LED
0
LED
8
LED
16
LED
24
LED
32
LED
40
18 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 12. LEDs ON/OFF Register Format for 3 Matrixes Setup
HEX
Data
A7 A6 A5 A4 A3 A2 A1 A0
D7
LED
55
0x06
0
0
0
0
0
1
1
0
0x07
0
0
0
0
0
1
1
1
X
CS4,
CS10,
CS16
0x08
0
0
0
0
1
0
0
0
LED
71
0x09
0
0
0
0
1
0
0
1
X
CS5,
CS11,
CS17
0x0A
0
0
0
0
1
0
1
0
LED
87
0x0B
0
0
0
0
1
0
1
1
X
CS3, CS9,
CS15
D6
LED
54
LED
62
LED
70
LED
78
LED
86
LED
94
D5 D4 D3
LED LED5 LED
53
2
51
LED LED LED
61
60
59
LED LED6 LED
69
8
67
LED LED LED
77
76
75
LED LED8 LED
85
4
83
LED LED LED
93
92
91
D2
LED
50
LED
58
LED
66
LED
74
LED
82
LED
90
D1
LED
49
LED
57
LED
65
LED
73
LED
81
LED
89
D0
LED
48
LED
56
LED
64
LED
72
LED
80
LED
88
al
id
Adress
lv
Current
Source
am
lc s
on A
te G
nt
st
il
In the blink register (see Table 13) every single LED can be set to blink. The blink period is set in the display option register (see Display
Option Register (0x03) on page 23).
Table 13. LEDs Blink Register Format for 3 Matrixes Setup
Adress
HEX
0
0x12
0
0x14
0
0x15
0
0x16
0
0x17
0
0x18
0
0x19
0
CS4,
CS10,
CS16
0x1A
0
0x1B
0
CS5,
CS11,
CS17
0x1C
0
CS1, CS7,
CS13
CS2, CS8,
CS14
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
1
0
LED
23
0
0
0
0
0
1
1
X
0
0
0
0
1
0
0
LED
39
0
0
0
0
1
0
1
X
0
0
0
0
1
1
0
LED
55
0
0
0
0
1
1
1
X
0
0
0
1
0
0
0
LED
71
0
0
0
1
0
0
1
X
0
0
0
1
0
1
0
LED
87
0
0
1
0
1
1
X
ch
CS3, CS9,
CS15
0
D7
LED
7
ni
0x12
CS0, CS6,
CS12
0
0
D6
LED
6
LED
14
LED
22
LED
30
LED
38
LED
46
LED
54
LED
62
LED
70
LED
78
LED
86
LED
94
D5 D4 D3
LED LED LED
5
4
3
LED LED LED
13
12
11
LED LED LED
21
20
19
LED LED LED
29
28
27
LED LED LED
37
36
35
LED LED LED
45
44
43
LED LED5 LED
53
2
51
LED LED LED
61
60
59
LED LED6 LED
69
8
67
LED LED LED
77
76
75
LED LED8 LED
85
4
83
LED LED LED
93
92
91
D2
LED
2
LED
10
LED
18
LED
26
LED
34
LED
42
LED
50
LED
58
LED
66
LED
74
LED
82
LED
90
D1
LED
1
LED
9
LED
17
LED
25
LED
33
LED
41
LED
49
LED
57
LED
65
LED
73
LED
81
LED
89
D0
LED
0
LED
8
LED
16
LED
24
LED
32
LED
40
LED
48
LED
56
LED
64
LED
72
LED
80
LED
88
Te
0x1D
Data
A7 A6 A5 A4 A3 A2 A1 A0
ca
Current
Source
www.austriamicrosystems.com/LED-Driver-ICs/AS1119
Revision 1.04
19 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
In the intensity register (see Table 14) the brightness of every single LED can be set via a 8bit PWM (255 steps).
Table 14. LEDs Intensity Register Format for 3 Matrixes Setup
Address
CS6
C
CS12
A
CS1
B
CS7
C
CS13
A
CS2
ch
CS8
Te
B
C
al
id
B
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
255 steps for intensity each single LED
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
1
0
1
0
255 steps for intensity each single LED
0
0
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
255 steps for intensity each single LED
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
0
1
0
...............................
am
lc s
on A
te G
nt
st
il
CS0
HEX
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
ni
A
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED16
LED17
LED18
LED19
LED20
LED21
LED22
LED23
LED24
LED25
LED26
LED27
LED28
LED29
LED30
LED32
LED33
LED34
LED35
LED36
LED37
LED38
LED39
LED40
LED41
LED42
LED43
LED44
LED45
LED46
Data
lv
Current
Source
ca
Matrix
CS14
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Revision 1.04
20 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 14. LEDs Intensity Register Format for 3 Matrixes Setup
Address
CS5
B
CS11
C
CS17
HEX
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
255 steps for intensity each single LED
1
0
1
0
1
0
1
1
1
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
0
al
id
A
LED80
LED81
LED82
LED83
LED84
LED85
LED86
LED87
LED88
LED89
LED90
LED91
LED92
LED93
LED94
Data
lv
Current
Source
am
lc s
on A
te G
nt
st
il
Matrix
Control-Registers
The AS1119 devices contain 13 control-registers which are listed in Table 15. All registers are selected using a 8-bit address word, and communication is done via the serial interface. Select the Control Register via the Register Selection (see Table 6 on page 13).
Table 15. Control Register Address Map
Register Name
HEX
Frame Address
Frame Play
Frame Time
Display Option
Register Data
A7
A6
A5
A4
A3
A2
A1
A0
D7:D0
0x00
0
0
0
0
0
0
0
0
(see Table 16 on page 22)
0x01
0
0
0
0
0
0
0
1
(see Table 17 on page 22)
0x02
0
0
0
0
0
0
1
0
(see Table 18 on page 23)
0x03
0
0
0
0
0
0
1
1
(see Table 19 on page 23)
0x04
0
0
0
0
0
1
0
0
(see Table 20 on page 24)
Current Source Matrix A
0x05
0
0
0
0
0
1
0
1
Current Source Matrix B
0x06
0
0
0
0
0
1
1
0
Current Source Matrix C
0x07
0
0
0
0
0
1
1
1
ni
ca
AS1119 Config
Register Address
(see Table 21 on page 25)
Chare Pump Config
0x08
0
0
0
0
1
0
0
0
(see Table 22 on page 25)
Open/Short Test
0x09
0
0
0
0
1
0
0
1
(see Table 23 on page 26)
0x0A
0
0
0
0
1
0
1
0
(see Table 24 on page 26)
0x0B
0
0
0
0
1
0
1
1
(see Table 25 on page 26)
Open/Short Status
0x0C
0
0
0
0
1
1
0
0
(see Table 26 on page 27)
AS1119 Status
0x0D
0
0
0
0
1
1
0
1
(see Table 27 on page 27)
Te
ch
Shutdown
I²C Interface Monitoring
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Revision 1.04
21 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Frame Address Register (0x00)
In this register it must be set if a picture or a movie is to display on the LED matrix. Also the start address of the the movie or the picture which
should be displayed must be set within this register. The default setting of this register is 0x00.
Table 16. Frame Address Register Format
0x00 Frame Address Register
7
Play Movie
6
Display Picture
5:3
Start Address for movie
Default
Access
0
R/W
0: no movie
1: play movie
0
R/W
0: no picture
1: display picture
R/W
000: Frame 0
001: Frame 1
010: Frame 2
011: Frame 3
100: Frame 4
101: Frame 5
2:0
am
lc s
on A
te G
nt
st
il
000
Bit Description
al
id
Bit Name
lv
Bit
Address of Picture
000
R/W
000: Frame 0
001: Frame 1
010: Frame 2
011: Frame 3
100: Frame 4
101: Frame 5
Note: If bit 6 and 7 are set to ‘1’ the AS1119 will play the movie first and than the picture will be displayed.
Frame Play Register (0x01)
Within this register two movie play obtions can be set. Per default this register is set to 0x00.
- The number of frames which are displayed in one movie.
- The number of loops to play in a movie.
Table 17. Frame Play Register Format
0x01 Frame Play Register
Bit
Bit Name
-
5:3
Number of loops played in
one movie
Access
00
n/a
ch
ni
ca
7:6
Default
Number of frames to
played in a movie
R/W
000
R/W
Te
2:0
000
Bit Description
000: no loop
001: 1 loop
010: 2 loops
011: 3 loops
100: 4 loops
101: 5 loops
110: 6 loops
111: play endless
000: 1 frame
001: 2 frames
010: 3 frames
011: 4 frames
100: 5 frames
101: 6 frames
Note: To stopp a movie in play endless mode, bits D5:D3 have to be set to a value between 000 to 110.
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Revision 1.04
22 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Frame Time Register (0x02)
Every single frame in a movie is displayed for a certain time before the next frame is displayed. This time can be set within this register with 4
bits. The stated values in Table 18 are typical values. Per default this register is set to 0x00.
Table 18. Frame Time Register Format
0x02 Frame Time Register
Access
7:4
-
00
n/a
3:0
Delay between frame
change in a movie
000
R/W
Bit Description
0000:play frame only one time
0001: 32.5ms
0010: 65ms
0011: 97.5ms
0100: 130ms
0101: 162.5ms
0110: 195ms
0111: 227.5ms
1000: 260ms
1001: 292.5ms
1010: 325ms
1011:357.5ms
1100: 390ms
1101: 422.5ms
1110: 455ms
1111: 487.5ms
al
id
Default
lv
Bit Name
am
lc s
on A
te G
nt
st
il
Bit
Display Option Register (0x03)
With the scan-limit it can be controlled how many digits are displayed in each matrix. When all 18 digits in the 2 matrix configuration are displayed, the display scan rate is 430Hz (typ.). If the number of digits to display is reduced, the update frequency is increased. Per default this register is set to 0x07.
Table 19. Display Option Register Format
0x03 Display Option Register
Bit Name
7
-
6
intensity setting
5
start with blink
4
blink period
Default
Access
0
n/a
0
R/W
0: use intensity setting of frame 0 for all other frames
1: set the intensity of each frame independently
0
R/W
0: start blinking with LED on
1: start blinking with LED off
0
R/W
0: 1.5s
1: 3s
Bit Description
Te
ch
ni
ca
Bit
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Revision 1.04
23 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Table 19. Display Option Register Format
0x03 Display Option Register
Default
Access
3:0
number of displayed
current sources in one
frame
(scan-limit)
0111
R/W
Bit Description
2 Matrix setting
Matrix A
0000: CS0
0001: CS0 to CS1
0010: CS0 to CS2
0011: CS0 to CS3
0100: CS0 to CS4
0101: CS0 to CS5
0110: CS0 to CS6
0111: CS0 to CS7
1000: CS0 to CS8
Matrix B
0000: CS0
0001: CS0 to CS1
0010: CS0 to CS2
0011: CS0 to CS3
0100: CS0 to CS4
0101: CS0 to CS5
0110: CS0 to CS6
0111: CS0 to CS7
1000: CS0 to CS8
al
id
Bit Name
lv
Bit
3 Matrixes setting
Matrix B
Matrix C
am
lc s
on A
te G
nt
st
il
Matrix A
0000: CS0
0001: CS0 to CS1
0010: CS0 to CS2
0011: CS0 to CS3
0100: CS0 to CS4
0101: CS0 to CS5
0000: CS6
0001: CS6 to CS7
0010: CS6 to CS8
0011: CS6 to CS9
0100: CS6 to CS10
0101: CS6 to CS11
0000: CS12
0001: CS12 to CS13
0010: CS12 to CS14
0011: CS12 to CS15
0100: CS12 to CS16
0101: CS12 to CS17
AS1119 Config Register (0x04)
In this register the configuration of the charge pumps is set to 2 or 3 blocks. The direction of the SYNC_IN/SYNC_OUT pin (input or output) is
also set. Per default this register is set to 0x00.
Table 20. AS1119 Config Register Format
0x04 AS1119 Config Register
Bit Name
7:3
-
2:1
Sync
0
Matrix Configuration
Default
Access
00000
n/a
00
R/W
ca
Bit
R/W
00: internal oscillator is system-clk. No synchronisation on pin B6. Tie pin to
high or low.
01: internal oscillator is system-clk. System-clk is available on pin B6 for
synchronization. (output)
10: internal oscillator is disabled. Pin B6 is used as clk input for system-clk.
11: do not use
0: 3 matrixes (à 5x6 LED-Matrix)
1: 2 matrixes (à 8x9 LED-Matrix)
Te
ch
ni
0
Bit Description
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Revision 1.04
24 - 30
AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Current Source Block A, B, C Registers (0x05, 0x06, 0x07)
Within this registers the current for every single LED in one block can be set from 0mA to 31mA in 255 steps (8 bits). Per default this register is
set to 0x00.
Table 21. Current Sourcer Register Format
Current Source Registers
Bit Name
Default
Access
Bit Description
0000000
R/W
00000000: 0mA
..........
11111111: 31mA
R/W
00000000: 0mA
..........
11111111: 31mA
al
id
Bit
Address 0x05
7:0
Analog Current
Matrix A
7:0
Analog Current
Matrix B
0000000
7:0
am
lc s
on A
te G
nt
st
il
Address 0x07
lv
Address 0x06
Analog Current
Matrix C
0000000
R/W
00000000: 0mA
..........
11111111: 31mA
Charge Pump Config Register (0x08)
In this register the characteristics of the Charge Pump can be set. By the use of the charge pump (bit 0) the supply voltage for the LEDs can be
boosted to 1.5- or 2-times of the device supply (VDD), if required. Additionally bit1 offers the option to check periodically if the LED supply can be
reduced again during operation. This period is defined by bit 4:2.
Alternatively, the LED supply can be (re)set to VDD by disabling the charge pump for a short time. In this case the period can be defined by user
(application). Per default this register is set to 0x1E.
Table 22. AS1119 Config Register Format
0x08 Charge Pump Config Register
Bit Name
-
4:2
Timeframe for reduce
supply test
1
Reduce supply option
Default
Access
000
n/a
111
R/W
000: 0.3s
001: 0.5s
010: 0.8s
011: 1.0s
100: 1.3s
101: 1.6s
110: 1.8s
111: 2.1s
R/W
0: reduce supply option off
1: reduce supply option on
Charge Pump
0
R/W
0: Charge Pump disable
1: Charge Pump enable
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Bit Description
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Bit
7:5
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AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Open/Short Test Register (0x09)
The AS1119 can detect open and shorted LEDs. To start this test the according bits have to be set. The result of the open/short test is written in
the Open/Short staturs register (see Table 26). The default setting of this register is 0x00.
Table 23. Open/Short Test Register Format
Bit Name
Default
Access
Bit Description
7:2
-
000000
n/a
1
Full Matrix
0
R/W
0: all LED’s are available in the matrixes
1: not all LED’s are available in the matrixes
0
Error detection
0
R/W
0: start test
1: no test
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0x09 Open/Short Test Register
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The Open/Short test is only checking LEDs which are defined as ON in the Data Frame Registers Table 8 on page 14 or Table 12 on
page 18. With the bit1 (Full Matrix) all LEDs of the matrixes will be defined as ON and will be tested intependently from the content of the Data
Frame Register. The function of bit1 is only available during the open/short test and not during normal operation.
Shutdown Register (0x0A)
The default setting of this register is 0x00. To get the AS1119 operational the bit D0 has to be set to ‘1’.
Table 24. Shutdown Register Format
0x0A Shutdown Register
Bit
Bit Name
7:1
-
0
shutdown
Default
Access
0000000
n/a
0
R/W
Bit Description
0: shutdown
1: normal operation
I²C Interface Monitoring Register (0x0B)
This register is used to monitor the activity on the I²C bus. If a deadlock situation occurs (e.g. the bus SDA pin is pulled to low and no communication is possible) the chip will reset the I²C interface and the master is able to start the communication again.
The time window for the reset of the interface of the AS1119 can bes set via 7 bits from 256µs to 33ms. The default setting of this register is
0xFF.
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Table 25. I²C Interface Monitoring Register Format
0x0B I²C Interface Monitoring Register
Bit Name
7:2
Time out window
Access
1111111
I²C Monitor
R/W
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1
Bit Description
0 to 127 => 1 to 128x256µs
0000000: 256µs
........
1111111: 32.7ms
0: I²C monitoring off
1: I²C monitoring on
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Bit
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AS1119
Datasheet - R e g i s t e r D e s c r i p t i o n
Open/Short Status Register (0x0C)
This is a read only register. Within this register the result of the open/short test can be read out. It’s also stated if the test is completed or still running. The default setting of this register is 0x00.
Table 26. Open/Short Status Register Format
0x0C Open/Short Status Register
Access
Bit Description
7
-
0
n/a
6
status
0
R
0: no test
1: test ongoing
5
short test result
Matrix C
0
R
0: no error detected
1: short in Matrix C
4
short test result
Matrix B
0
R
0: no error detected
1: short in Matrix B
3
short test result
Matrix A
0
R
0: no error detected
1: short in Matrix A
2
open test result
Matrix C
0
R
0: no error detected
1: open in Matrix C
1
open test result
Matrix B
0
R
0: no error detected
1: open in Matrix B
0
open test result
Matrix A
0
R
0: no error detected
1: open in Matrix A
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Bit
AS1119 Status Register (0x0D)
This is a read only register. From this register the actual status of the AS1119 can be read out. The default setting of this register is 0x00. After an
read command the bits 5:4 are set to ‘0’ again automatically.
Table 27. AS1119 Status Register Register Format
0x0D AS1119 Status Register
Bit Name
7
-
6
Movie status
5:4
Interrupt
Access
0
n/a
ni
00
actual displayed frame
000
Bit Description
R
0: no movie is playing
1: one movie is playing
R
00: no Interrupt triggered
01: POR triggered an interrupt
1
10: I²C monitor triggered an interrupt
11: both (I²C and POR) triggered an interrupt
R
000: frame 0
001: frame 1
010: frame 2
011: frame 3
100: frame 4
101: frame 5
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3:0
Default
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Bit
1. The power-on reset is part of the start sequence, hence after start-up this bit is also set.
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AS1119
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
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Figure 23. 36-pin WL-CSP Marking
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Table 28. Packaging Code YYWWIZZ
last two digits of the current year
I
ZZ
plant identifier
free choice / traceability code
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Figure 24. 36-pin WL-CSP
WW
manufacturing week
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AS1119
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 29.
Table 29. Ordering Information
Marking
AS1119-BWLT
AS1119
Desciption
144-LED Cross-Plexing Driver with
320mA Charge-Pump
Delivery Form
Package
Tape and Reel
36-pin WL-CSP
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
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Technical Support is found at http://www.austriamicrosystems.com/Technical-Support
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Ordering Code
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For further information and requests, please contact us mailto:[email protected]
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS1119
Datasheet
Copyrights
Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
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specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
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austriamicrosystems AG rendering of technical or other services.
Headquarters
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Contact Information
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austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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