CYRS1542AV18 CYRS1544AV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology Radiation Performance Radiation Data ■ JTAG 1149.1 compatible test access port ■ DLL for accurate data placement ■ Total Dose =300 Krad Configurations ■ Soft error rate (both Heavy Ion and proton) Heavy ions 1 × 10-10 upsets/bit-day with an external SECDED EDAC Controller CYRS1542AV18 – 4 M × 18 Neutrons = 2.0 × 1014 N/cm2 Functional Description ■ 109 rad(Si)/sec ■ Dose rate = 2.0 × ■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec ■ Latch up immunity = 120 MeV.cm2/mg (125 °C) Prototyping Options ■ Non qualified CYPT1542AV18 and CTPT1544AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array (CCGA) package Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250-MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz) ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 2.0 cycle read latency when delay lock loop (DLL) is enabled ■ Available in × 18 and × 36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD ■ Available in 165-ball CCGA (21 × 25 × 2.83 mm) ■ HSTL inputs and variable drive HSTL output buffers Cypress Semiconductor Corporation Document Number: 001-60006 Rev. *M • CYRS1544AV18 – 2 M × 36 The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques. The QDR II+ architecture consists of two separate ports to access the memory: the read port and the write port. The read port has dedicated data output bus to support read operations and the write port has dedicated data input bus to support write operations. QDR II+ architecture completely eliminates the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read are latched on the rising edges of the input (K) clock whereas addresses for write are latched on the falling edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of each another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words for CYRS1542AV18, or two 36-bit words for CYRS1544AV18 that burst sequentially into or out of the device. Since data can be transferred on every rising edge of both input clocks (K and K#), memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks as well. Reads and writes are conducted with on-chip synchronous self-timed circuitry. For a complete list of related resources, click here. Selection Guide Description 250 MHz Unit Maximum operating frequency Maximum operating current (concurrent R/W) 198 Champion Court • 250 MHz × 18 1700 mA × 36 1700 San Jose, CA 95134-1709 • 408-943-2600 Revised January 9, 2015 CYRS1542AV18 CYRS1544AV18 Logic Block Diagram – CYRS1542AV18 K CLK Gen. DOFF 21 Address Register Read Add. Decode K Write Reg 2M x 18 Array Address Register Write Reg 2M x 18 Array A(20:0) 21 18 Write Add. Decode D[17:0] A(20:0) RPS Control Logic Read Data Reg. CQ 36 VREF WPS 18 Control Logic 18 BWS[1:0] Reg. Reg. 18 Reg. 18 CQ 18 Q[17:0] QVLD Logic Block Diagram – CYRS1544AV18 K CLK Gen. DOFF 20 Address Register Read Add. Decode K Write Reg 1M x 36 Array Address Register Write Reg 1M x 36 Array A(19:0) 20 36 Write Add. Decode D[35:0] A(19:0) RPS Control Logic Read Data Reg. CQ 72 VREF WPS 36 Control Logic BWS[3:0] 36 Reg. Reg. 36 Reg. 36 CQ 36 Q[35:0] QVLD Document Number: 001-60006 Rev. *M Page 2 of 34 CYRS1542AV18 CYRS1544AV18 Contents Manufacturing Flow .......................................................... 4 Radiation Hardened Design ........................................ 4 Neutron Soft Error Immunity ........................................... 4 Pin Configuration ............................................................. 5 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 8 Read Operations ......................................................... 8 Write Operations ......................................................... 8 Byte Write Operations ................................................. 8 Concurrent Transactions ............................................. 8 Depth Expansion ......................................................... 8 Programmable Impedance .......................................... 8 Echo Clocks ................................................................ 9 Valid Data Indicator (QVLD) ........................................ 9 DLL .............................................................................. 9 Qualification and Screening ........................................ 9 Application Example ...................................................... 10 Truth Table ...................................................................... 11 Write Cycle Descriptions ............................................... 11 Write Cycle Descriptions ............................................... 12 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port ....................................................... 13 Performing a TAP Reset ........................................... 13 TAP Registers ........................................................... 13 TAP Instruction Set ................................................... 13 TAP Controller State Diagram ....................................... 15 TAP Controller Block Diagram ...................................... 16 TAP Electrical Characteristics ...................................... 16 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 18 Identification Register Definitions ................................ 19 Document Number: 001-60006 Rev. *M Scan Register Sizes ....................................................... 19 Instruction Codes ........................................................... 19 Boundary Scan Order .................................................... 20 Power Up Sequence in QDR II+ SRAM ......................... 21 Power Up Sequence ................................................. 21 DLL Constraints ......................................................... 21 Maximum Ratings ........................................................... 22 Operating Range ............................................................. 22 Electrical Characteristics ............................................... 22 DC Electrical Characteristics ..................................... 22 AC Electrical Characteristics ..................................... 23 Radiation Performance .................................................. 23 Capacitance .................................................................... 23 Thermal Resistance ........................................................ 23 AC Test Loads and Waveforms ..................................... 24 Switching Characteristics .............................................. 25 Switching Waveforms .................................................... 26 Ordering Information ...................................................... 27 Ordering Code Definitions ......................................... 27 Package Diagram ............................................................ 28 Acronyms ........................................................................ 29 Document Conventions ................................................. 29 Units of Measure ....................................................... 29 Glossary .......................................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC® Solutions ...................................................... 34 Cypress Developer Community ................................. 34 Technical Support ..................................................... 34 Page 3 of 34 CYRS1542AV18 CYRS1544AV18 Manufacturing Flow Step Screen Method Requirement 1 Wafer lot acceptance test TM 5007 2 Internal visual 2010, Condition A 3 Serialization 4 Temperature cycling 1010, Condition C, 50 cycles minimum 100% 5 Constant acceleration 2001, YI orientation only 100% 7 Particle impact noise detection (PIND) 2020 Condition A 8 Radiographic (X-ray) 2012, one view (Y-1 orientation) only 9 Pre burn in electrical parameters In accordance with applicable Cypress specification 100% 10 Dynamic burn in 1015, Condition D 100% 6 – 100% 100% Condition TBD (package in design) 100% 240 hours at 125 °C or 120 hours at 150 °C minimum 11 Interim (post dynamic burn in) electricals In accordance with applicable Cypress device specifications 100% 12 Static burn in 1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C minimum 100% 13 Interim (post static burn in) electricals In accordance with applicable Cypress device specifications 100% 14 Percent defective allowable (PDA) calculation 5% overall, 3% functional parameters at 25 °C All lots 15 Final electrical test 100% In accordance with applicable Cypress device specifications a. Static tests (1) 25 °C 5005, Table I, Subgroup 1 (2) –55 °C and +125 °C 5005, Table I, Subgroup 2, 3 b. Functional tests (1) 25 C 5005, Table I, Subgroup 7 (2) –55 °C and +125 C 5005, Table I, Subgroup 8a, 8b c. Switching test at 25 °C 5005, Table I, Subgroup 9 Seal (fine and gross leak test) 1014 17 External visual 2009 18 Wafer lot specific life test (Group C) Mil-PRF 38535, Appendix B, section B.4.2.c 16 Radiation Hardened Design The single event latch up (SEL) immunity is improved by a radiation hardened design technique developed by Cypress called RadStop. This design mitigation technique allows the SEL performance to achieve radiation hard performance levels. 100% 100% All wafer lots Neutron Soft Error Immunity Parameter Description LSBU Logical single-bit upsets Logical multi-bit upsets Single event latch up LMBU SEL Test Conditions 25 °C Typ Max* Unit 320 368 FIT/ Mb 25 °C 0 0.01 FIT/ Mb 125 °C 0 0.1 FIT/ Dev * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to application note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates” Document Number: 001-60006 Rev. *M Page 4 of 34 CYRS1542AV18 CYRS1544AV18 Pin Configuration Pin configurations for CYRS1542AV18 and CYRS1544AV18.[1] Figure 1. 165-ball CCGA pinout CYRS1542AV18 (4 M × 18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/144M A WPS BWS1 K NC/288M RPS A A CQ B NC Q9 D9 A NC K BWS0 A NC NC Q8 C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A QVLD A A NC D0 Q0 R TDO TCK A A A NC A A A TMS TDI CYRS1544AV18 (2 M × 36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/288M A WPS BWS2 K BWS1 RPS A NC/144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A A VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS A A A VSS Q10 D9 D1 P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 R TDO TCK A A A NC A A A TMS TDI Note 1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-60006 Rev. *M Page 5 of 34 CYRS1542AV18 CYRS1544AV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData input signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CYRS1542AV18 D[17:0] CYRS1544AV18 D[35:0] WPS InputWrite port select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. BWS0, BWS1, BWS2, BWS3 InputByte write select (BWS) 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CYRS1542AV18 BWS0 controls D[8:0] and BWS1 controls D[17:9]. CYRS1544AV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the BWS are sampled on the same edge as the data. Deselecting a BWS ignores the corresponding byte of data and it is not written into the device. A[x:0] InputAddress inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4 M × 18 (2 arrays each of 2 M × 18) for CYRS1542AV18, and 2 M × 36 (2 arrays each of 1 M × 36) for CYRS1544AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CYRS1542AV18, and 20 address inputs for CYRS1544AV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputData output signals. These pins drive out the requested data during a read operation. Valid data is Synchronous driven out on the rising edge of the K and K clock. When the read port is deselected, Q[x:0] are automatically tristated. CYRS1542AV18 Q[17:0] CYRS1544AV18 Q[35:0] RPS InputRead port select Active LOW. Sampled on the rising edge of positive input clock (K). When active, Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers. QVLD Valid Output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. Indicator K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock K. The timing for the echo clocks is shown in Switching Characteristics on page 25. CQ Echo Clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock K. The timing for the echo clocks is shown in the Switching Characteristics on page 25. ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL turn off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the operation with the DLL turned off differs from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 k or less pull up resistor. The device behaves in QDR I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR I timing. TDO Output Test data out (TDO) Pin for JTAG. Document Number: 001-60006 Rev. *M Page 6 of 34 CYRS1542AV18 CYRS1544AV18 Pin Definitions (continued) Pin Name I/O Pin Description TCK Input Test clock (TCK) Pin for JTAG. TDI Input Test data in (TDI) Pin for JTAG. TMS Input Test mode select (TMS) Pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/144M Input Not connected to the die. Can be tied to any voltage level. NC/288M Input Not connected to the die. Can be tied to any voltage level. VREF VDD VSS VDDQ InputReference Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Document Number: 001-60006 Rev. *M Page 7 of 34 CYRS1542AV18 CYRS1544AV18 Functional Overview Write Operations The CYRS1542AV18, and CYRS1544AV18 are synchronous pipelined burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR II+ completely eliminates the need to turnaround the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 18-bit data transfers in the case of CYRS1542AV18, and two 36-bit data transfers in the case of CYRS1544AV18 in one clock cycle. This device operates with a read latency of two cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then the device behaves in QDR I mode with a read latency of one clock cycle. DOFF is not a recommended mode of operation. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (K and K). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CYRS1542AV18 is described below. The descriptions also apply to CYRS1544AV18. same basic Read Operations The CYRS1542AV18 is organized internally as two arrays of 2 M × 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. The address presented to the address inputs is stored in the read address register. Following the next two K clock rising edges, the corresponding lower order 18-bit word of data is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is drive onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (K or K). When the read port is deselected, the CYRS1542AV18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive input clock (K). Document Number: 001-60006 Rev. *M Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched in and the information presented to D[17:0] is stored into the higher 18-bit write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port ignores all inputs after the pending write operations are complete. Byte Write Operations Byte write operations are supported by the CYRS1542AV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate BWS input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. Concurrent Transactions The read and write ports on the CYRS1542AV18 operate independently of one another. As each port latches the address inputs on different clock edges, you can read or write to any location, regardless of the transaction on the other port. You can start reads and writes in the same clock cycle. If the ports access the same location at the same time, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Depth Expansion The CYRS1542AV18 has a port select input for each port. This allows for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting one port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5 × the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Page 8 of 34 CYRS1542AV18 CYRS1544AV18 Echo Clocks Qualification and Screening Echo clocks are provided on the QDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDRII+. CQ is referenced with respect to K and CQb is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 25. The 90-nm RadStop technology was qualified by Cypress after meeting the criteria of the General Manufacturing Standards. The test flow includes screening units with the defined flow (Class Q, Class V) and the appropriate periodic or lot conformance testing (Groups B, C, D, and E). Both the 90-nm process and the SRAM products are subject to period or lot-based technology conformance inspection (TCI) and quality conformance inspection (QCI) tests, respectively. Cypress offers both prototyping models and flight units of these product configurations. Valid Data Indicator (QVLD) QVLD is provided on the QDR II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. Table 1. Qualification Tests Group A General electrical tests Group B Mechanical - Dimensions, bond strength, solvents, die shear, solderability, lead Integrity, seal, and acceleration Group C Life tests - 1000 hours at 125 C or equivalent Group D Package related mechanical tests - shock, vibration, accel, salt, seal, lead finish adhesion, lid torque, thermal shock, and moisture resistance Group E Radiation tests DLL These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL is locked after 10240 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time). For information refer to the application note AN5062, DLL Considerations in QDRII/DDRII. Document Number: 001-60006 Rev. *M Page 9 of 34 CYRS1542AV18 CYRS1544AV18 Application Example Figure 2 shows two QDR II+ used in an application. Figure 2. Application Example ZQ ZQ SRAM#1 D[x:0] A RPS WPS CQ/CQ Q[x:0] BWS K K SRAM#2 RQ D[x:0] A RPS WPS CQ/CQ Q[x:0] BWS K K RQ DATA IN[2x:0] DATA OUT [2x:0] ADDRESS RPS WPS BWS CLKIN1/CLKIN1 CLKIN2/CLKIN2 SOURCE K SOURCE K FPGA / ASIC Document Number: 001-60006 Rev. *M Page 10 of 34 CYRS1542AV18 CYRS1544AV18 Truth Table CYRS1542AV18 and CYRS1544AV18 [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write cycle: Load address on the rising edge of K; input write data on K and K rising edges. L–H X L D(A) at K(t) D(A + 1) at K(t) Read cycle:(2.0 cycle Latency) Load address on the rising edge of K; wait two cycles; read data on K and K rising edges. L–H L X Q(A) at K(t + 2) Q(A + 1) at K(t + 2) NOP: No operation L–H H H D=X Q = High Z D=X Q = High Z Stopped X X Previous state Previous state Standby: Clock stopped Write Cycle Descriptions CYRS1542AV18 [2, 8] BWS0 BWS1 K K L L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – Comments During the data portion of a write sequence Both bytes (D[17:0]) are written into the device. L–H During the data portion of a write sequence: Both bytes (D[17:0]) are written into the device. – During the data portion of a write sequence Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence Only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence Only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Notes 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tristate condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges. 7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2 and BWS2 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-60006 Rev. *M Page 11 of 34 CYRS1542AV18 CYRS1544AV18 Write Cycle Descriptions CYRS1544AV18 [9, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Notes 9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge. 10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2 and BWS2 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved Document Number: 001-60006 Rev. *M Page 12 of 34 CYRS1542AV18 CYRS1544AV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8 V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. Test Access Port Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 19). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high Z state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-60006 Rev. *M Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 16. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 20 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 19. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 19. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. Page 13 of 34 CYRS1542AV18 CYRS1544AV18 IDCODE BYPASS The IDCODE instruction loads a vendor specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a high Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. You must be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the K and K captured in the boundary scan register. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a high Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test Logic Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. Document Number: 001-60006 Rev. *M Page 14 of 34 CYRS1542AV18 CYRS1544AV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 0 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 0 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-60006 Rev. *M Page 15 of 34 CYRS1542AV18 CYRS1544AV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range Parameter [12, 13, 14] Description Test Conditions Min Max Unit VOH1 Output high voltage IOH =2.0 mA 1.4 – V VOH2 Output high voltage IOH =100 A 1.6 – V VOL1 Output low voltage IOL = 2.0 mA – 0.4 V VOL2 Output low voltage IOL = 100 A – 0.2 V VIH Input high voltage VIL Input low voltage IX Input and output load current 0.65 × VDD VDD + 0.3 GND VI VDD V –0.3 0.35 × VDD V –5 5 A Notes 12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in Electrical Characteristics on page 22. 13. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 14. All Voltage referenced to ground. Document Number: 001-60006 Rev. *M Page 16 of 34 CYRS1542AV18 CYRS1544AV18 TAP AC Switching Characteristics Over the Operating Range Parameter [15, 16] Description Min Max Unit 50 – ns TCK clock frequency – 20 MHz TCK clock HIGH 20 – ns TCK clock LOW 20 – ns tTCYC TCK clock cycle time tTF tTH tTL Setup Times tTMSS TMS setup to TCK clock rise 5 – ns tTDIS TDI setup to TCK clock rise 5 – ns tCS Capture setup to TCK rise 5 – ns Hold Times tTMSH TMS hold after TCK clock rise 5 – ns tTDIH TDI hold after clock rise 5 – ns tCH Capture hold after clock rise 5 – ns Output Times tTDOV TCK clock LOW to TDO valid – 10 ns tTDOX TCK clock LOW to TDO invalid 0 – ns Notes 15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-60006 Rev. *M Page 17 of 34 CYRS1542AV18 CYRS1544AV18 TAP Timing and Test Conditions Figure 3 shows the TAP timing and test conditions. [17] Figure 3. TAP Timing and Test Conditions 0.9 V ALL INPUT PULSES 1.8 V 0.9 V 50 TDO 0V Z0 = 50 (a) CL = 20 pF tTH GND tTL Test Clock TCK tTMSH tTMSS tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Note 17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document Number: 001-60006 Rev. *M Page 18 of 34 CYRS1542AV18 CYRS1544AV18 Identification Register Definitions Value Instruction Field CYRS1542AV18 CYRS1544AV18 000 000 Cypress device ID (28:12) 11010010100010100 11010010100100100 Cypress JEDEC ID (11:1) 00000110100 00000110100 1 1 Revision number (31:29) ID register presence (0) Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a high Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-60006 Rev. *M Page 19 of 34 CYRS1542AV18 CYRS1544AV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number: 001-60006 Rev. *M Page 20 of 34 CYRS1542AV18 CYRS1544AV18 Power Up Sequence in QDR II+ SRAM QDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 10240 cycles to lock the DLL. DLL Constraints ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 10240 cycles stable clock to relock to the desired clock frequency. ~ ~ Figure 4. Power Up Waveforms K ~ ~ K Unstable Clock > 10240 Stable Clock Start Normal Operation Clock Start (Clock Starts after VDD/VDDQ is Stable) VDD/VDDQ DOFF Document Number: 001-60006 Rev. *M VDD/VDDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to VDDQ) Page 21 of 34 CYRS1542AV18 CYRS1544AV18 DC input voltage [18] ........................... –0.5 V to VDD + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Case temperature under power ............... –55 °C to +125 °C Junction temperature under power ........... –55 °C to +150°C Current into outputs (LOW) ........................................ 20 mA Static discharge voltage (MIL-STD-883, TM. 3015) ...................................... > 2001 V Latch up current ..................................................... > 200 mA Operating Range Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD DC applied to outputs in high Z ........ –0.5 V to VDDQ + 0.5 V Range Military Case Temperature (Tc) VDD[19] VDDQ[19] –55 °C to +125 °C 1.8 ± 0.1 V 1.4 V to VDD Electrical Characteristics Over the Operating Range DC Electrical Characteristics Over the Operating Range Parameter [20] Description Test Conditions Min Typ Max Unit VDD Power supply voltage 1.7 1.8 1.9 V VDDQ I/O supply voltage 1.4 1.5 VDD V VOH Output high voltage Note 21 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOL Output low voltage Note 22 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V VOH(LOW) Output high voltage IOH =0.1 mA, nominal impedance VDDQ – 0.2 – VDDQ V VOL(LOW) Output low voltage IOL = 0.1 mA, nominal impedance VSS – 0.2 V VIH Input high voltage VREF + 0.1 – VDDQ + 0.3 V VIL Input low voltage –0.3 – VREF – 0.1 V IX Input leakage current GND VI VDDQ 20 – 20 A IOZ Output leakage current GND VI VDDQ, output disabled 20 – 20 A Typical value = 0.75 V 0.68 0.75 0.95 V mA VREF IDD [24] ISB1 Input reference voltage VDD operating supply Automatic power down current [23] VDD = Max, IOUT = 0 mA, TJ=125 °C, f = fMAX = 1/tCYC 250 MHz (× 18) – – 1700 (× 36) – – 1700 Max VDD, Both ports deselected, VIN VIH or VIN VIL, f = fMAX = 1/tCYC, TJ = 125 °C, Inputs static 250 MHz (× 18) – – 660 (× 36) – – 660 mA Notes 18. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 19. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 20. All Voltage referenced to ground. 21. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 . 22. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 . 23. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller. 24. The operation current is calculated with concurrent read and write cycles. Document Number: 001-60006 Rev. *M Page 22 of 34 CYRS1542AV18 CYRS1544AV18 AC Electrical Characteristics Over the Operating Range Parameter [25, 26] Description Test Conditions Min Typ Max Unit VIH Input high voltage VREF + 0.2 – – V VIL Input low voltage – – VREF – 0.2 V Radiation Performance Parameter Test Conditions Total dose TA = 25 °C, VDD = VDDQ = 1.8 V Soft error rate TA = 25 °C to 125 °C, VDD = VDDQ = 1.8 V with EDAC Transient dose rate upset Pulse width (FWHM) = 50 ns, X-Ray, TC = 25 °C, VDD = VDDQ = 1.8 V Neutron fluence 1 MeV equivalent energy, Unbiased TA = 25 C Latch up immunity TA = 125 °C, VDD = VDDQ = 1.9 V Limits Unit 300 Krad Rads(Si) Co60 1.0 × 10^-10 Upsets/bit-day 2.0 × 109 Rads(Si)/s 2e14 N/cm2 110 MeVcm2/mg Capacitance Parameter [27] Description Test Conditions Max Unit 10 pF CIN Input capacitance CCLK Clock input capacitance 10 pF CO Output capacitance 10 pF TA = 25 °C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V Thermal Resistance Parameter [27] JC Description Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165-ball CCGA Unit Package 8.9 °C/W Notes 25. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2). 26. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 27. Tested initially and after any design or process change that may affect these parameters. Document Number: 001-60006 Rev. *M Page 23 of 34 CYRS1542AV18 CYRS1544AV18 AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms VREF = 0.75 V VREF 0.75 V VREF OUTPUT DEVICE UNDER TEST Z0 = 50 RL = 50 VREF = 0.75 V ZQ R = 50 ALL INPUT PULSES 1.25 V 0.75 V OUTPUT DEVICE UNDER TEST ZQ RQ = 250 (a) 0.75 V INCLUDING JIG AND SCOPE 5 pF [28] 0.25 V SLEW RATE= 2 V/ns RQ = 250 (b) Note 28. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5. Document Number: 001-60006 Rev. *M Page 24 of 34 CYRS1542AV18 CYRS1544AV18 Switching Characteristics Over the Operating Range Parameters [29, 30] 250 MHz Description Cypress Consortium Parameter Parameter Min VDD(typical) to the first access [31] tPOWER Max Unit 1 – ms 4.0 8.4 ns Input clock (K/K) HIGH 1.6 – ns Input clock (K/K) LOW 1.6 – ns K clock rise to K clock rise (rising edge to rising edge) 1.8 – ns tCYC tKHKH K clock cycle time tKH tKHKL tKL tKLKH tKHKH tKHKH Setup Times tSA tAVKH Address setup to K clock rise 0.5 – ns tSC tIVKH Control setup to K clock rise (RPS, WPS) 0.5 – ns tSCDDR tIVKH DDR control setup to clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.5 – ns tSD tDVKH D[X:0] setup to clock (K/K) rise 0.5 – ns tHA tKHAX Address hold after K clock rise 0.5 – ns tHC tKHIX Control hold after K clock rise (RPS, WPS) 0.5 – ns tHCDDR tKHIX DDR control hold after clock (K/K) rise (BWS0, BWS1, BWS2, BWS3) 0.5 – ns tHD tKHDX D[X:0] hold after clock (K/K) rise 0.5 – ns Hold Times Output Times tCO tCHQV tDOH tCHQX Data output hold after output K/K clock rise (Active to active) tCCQO tCHCQV K/K clock rise to echo clock valid tCQOH tCHCQX tCQD tCQHQV tCQDOH tCQHQX K/K clock rise to data valid – 0.85 ns –0.85 – ns – 0.85 ns Echo clock hold after C/C clock rise Echo clock high to data valid –0.5 – ns – 0.50 ns Echo clock high to data invalid –0.30 – ns [32] 1.55 – ns 1.55 – ns tCQH tCQHCQL Output clock (CQ/CQ) HIGH tCQHCQH tCQHCQH CQ clock rise to CQ clock rise (rising edge to rising edge) [32] tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) tCLZ tCHQX1 Clock (K/K) rise to low Z [33, 34] [35] [33, 34] – 0.45 ns –0.45 – ns –0.5 0.5 ns tCQHQVLD Echo Clock High to QVLD Valid tKC Var tKC Var Clock phase jitter – 0.20 ns tKC lock tKC lock DLL lock time (K) 10240 – Cycles tKC Reset tKC Reset K static to DLL reset 30 – ns tQVLD DLL Timing Notes 29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 24. 30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 31. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially before initiating a read or write operation. 32. These parameters are extrapolated from the input timing parameters (tKHKH – 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production. 33. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 24. Transition is measured 100 mV from steady state voltage. 34. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 35. tQVLD Spec is applicable for both rising and falling edges of QVLD signal. Document Number: 001-60006 Rev. *M Page 25 of 34 CYRS1542AV18 CYRS1544AV18 Switching Waveforms Figure 6. Read/Write/Deselect Sequence [36, 37, 38] READ 1 WRITE 2 READ 3 READ 5 WRITE 4 NOP 7 WRITE 6 WRITE 8 NOP 9 10 11 12 K tKH tKHKH tCYC tKL K RPS tSC tHC WPS A D A0 D10 A1 A2 tSA tHA tSA tHA D11 D30 A3 A4 A5 D31 D50 D51 A6 D60 D61 tSD tHD tSD tHD tQVLD QVLD tQVLD Q tCQD tCO tCLZ Q00 tCHZ tDOH Q01 Q20 (Read Latency = 2.0 Cycles) Q21 Q40 Q41 tCQDOH tCCQO CQ tCQH tCQHCQH tCQOH tCCQO CQ tCQOH DON’T CARE UNDEFINED Notes 36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 37. Outputs are disabled (high Z) one clock cycle after a NOP. 38. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to Figure 6. Document Number: 001-60006 Rev. *M Page 26 of 34 CYRS1542AV18 CYRS1544AV18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for (× 18 option), contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (MHz) Ordering Code Package Diagram Description Package Type Operating Range 250 CYRS1542AV18-250GCMB 72M QDR II+, × 18, Burst of 2 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 CYRS1544AV18-250GCMB 72M QDR II+, × 36, Burst of 2 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 CYPT1542AV18-250GCMB 72M QDR II+, × 18, Burst of 2, Prototype 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 CYPT1544AV18-250GCMB 72M QDR II+, × 36, Burst of 2, Prototype 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 5962F1120101QXA 72M QDR II+, × 18, Burst of 2, DLAM Part 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 5962F1120101VXA 72M QDR II+, × 18, Burst of 2, DLAM Part 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 5962F1120201QXA 72M QDR II+, × 36, Burst of 2, DLAM Part 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military 250 5962F1120201VXA 72M QDR II+, × 36, Burst of 2, DLAM Part 001-58969 165-ball CCGA (21 × 25 × 2.83 mm) Military Ordering Code Definitions CY XX 154X A V18 - 250 GC M B Burn-in Thermal Rating: M = Military Package Type: GC = 165-ball CCGA Speed Grade: 250 MHz Core Voltage: 1.8 V Die Revision Part Number Identifier: Density, Organization, Burst 154X = 1542 or 1544 Marketing Code: XX = RS or PT RS = RadStop, PT = Prototype Company ID: CY = Cypress Document Number: 001-60006 Rev. *M Page 27 of 34 CYRS1542AV18 CYRS1544AV18 Package Diagram Figure 7. 165-ball Ceramic Column Grid Array (CCGA) (21 × 25 mm) Package Outline, 001-58969 001-58969 *D Document Number: 001-60006 Rev. *M Page 28 of 34 CYRS1542AV18 CYRS1544AV18 Acronyms Acronym BWS CCGA DED DLL DDR DSCC EDAC HSTL I/O JTAG LSB LSBU LMBU MSB PDA PIND PDA QDR RPS SEC SEL SRAM TAP TCK TDI TDO TMS WPS Document Conventions Description byte write select ceramic column grid array double error detection delay lock loop double data rate defense supply center columbus error detection and correction high speed transceiver logic input/output Joint Test Action Group least significant bit logical single-bit upsets logical multi-bit upsets most significant bit percent defect allowable particle impact noise detection percent defective allowable quad data rate read port select single error correction single event latch up static random access memory test access port test clock test data in test data out test mode select write port select Document Number: 001-60006 Rev. *M Units of Measure Symbol Unit of Measure °C degree Celsius Krad kiloradian MHz megahertz µA microampere µF microfarad µs microsecond mA milliampere mm millimeter ms millisecond mV N/cm millivolt 2 Neutron particles fluence per cm2 area ns nanosecond nm nanometer ohm % percent pF picofarad ps picosecond Rads(Si) unit of absorbed radiation energy from ionizing radiation per kg of material. (1 rad(Si)) = 10 mGy = 10 – 2 J/kg V volt W watt Page 29 of 34 CYRS1542AV18 CYRS1544AV18 Glossary Total Dose Permanent device damage due to ions over device life Heavy Ion Instantaneous device latch up due to single ion LET Linear energy transfer (measured in MeVcm2) Krad Unit of measurement to determine device life in radiation environments. Neutron Permanent device damage due to energetic neutrons or protons Prompt Dose Data loss of permanent device damage due to X-rays and gamma rays < 20 ns 165-ball Ceramic Column Grid Array Hermetic ceramic 165-column package. Columns attached by Six Sigma RadStop Technology Cypress's patented Rad Hard design methodology DLAM Defense Logistics Agency Land and Maritime LSBU Logical Single Bit Upset. Single bits in a single correction word are in error. LMBU Logical Multi Bit Upset. Multiple bits in a single correction word are in error Group A General electrical testing Group B Mechanical - Dimensions, bond strength, solvents, die shear, solderability, lead integrity, seal, acceleration Group C Life test - 1000 hours at 125 °C Group D Package related mechanical tests - shock, vibration, Accel, salt, seal, lead finish adhesion, lid torque, thermal shock, moisture resistance Group E Radiation testing Document Number: 001-60006 Rev. *M Page 30 of 34 CYRS1542AV18 CYRS1544AV18 Document History Page Document Title: CYRS1542AV18/CYRS1544AV18, 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology Document Number: 001-60006 Rev. ECN No. Submission Date Orig. of Change ** 2940931 05/31/2010 HRP New data sheet. *A 3016545 08/26/2010 HRP Changed part numbers from CYRS1512AV18/CYRS1514AV18 to reflect change to QDR II+ die. Updated Switching Characteristics (Updated minimum and maximum values for Setup Time, Hold Time parameters, and updated minimum and maximum values for tCO parameter under Output Time parameter). Updated Ordering Information (Added 200-MHz part numbers (CYRS1542AV18-250GCMB, CYRS1544AV18-250GCMB for Burst 2 mode). Updated Package Diagram. Added Units of Measure. *B 3281455 06/13/2011 HRP Changed status from Advanced to Final. Updated Configurations (corrected typo). Updated Selection Guide. Updated DC Electrical Characteristics (maximum current limit values for the parameters IDD and ISB1 based on device characterization). Updated Radiation Performance (Limits of Radiation Data based on RHA qualification. Updated Thermal Resistance. Updated Switching Characteristics (Minimum and Maximum timing values for the parameters tco, tDOH, tCCQO, tCQOH based on device characterization). Updated Ordering Information (Removed × 18 option from ordering table). Updated Package Diagram. Changed DLL lockup cycles from 2048 to 10240 throughout document. Updated in new template. *C 3471321 12/21/2011 HRP Updated Identification Register Definitions (Replaced the value of Cypress device ID (28:12) from 11010011010010100 to 11010010100010100 for CYRS1542AV18 and replaced the value of Cypress device ID (28:12) from 11010011010100100 to 11010010100100100 for CYRS1544AV18). *D 3524961 02/14/2012 HRP Updated Prototyping Options under Radiation Performance. (Added two devices). Updated Application Example. Updated Truth Table. Updated Maximum Ratings. Updated Radiation Performance. Updated Capacitance. Updated Thermal Resistance. Updated Switching Characteristics. Updated Ordering Information (Removed 200 MHz speed part CYRS1544AV18-200GCMB). *E 3537277 02/29/2012 HRP Updated Radiation Data under Radiation Performance. Updated Ordering Information (Removed the part number CYRS1544AV18-250GCMB and added the part numbers CYRS1543AV18-250GCMB, CYRS1545AV18-250GCMB, CYPT1543AV18-250GCMB, CYPT1545AV18-250GCMB, 5962F1120201VXA and 5962F1120202VXA). Description of Change *F 3580538 04/12/2012 HRP Updated Ordering Information (Updated part numbers). *G 3617759 05/15/2012 HRP Updated Radiation Performance (Updated Prototyping Options). Updated Ordering Information (Added part 5962F1120101VXA). Updated Glossary. Document Number: 001-60006 Rev. *M Page 31 of 34 CYRS1542AV18 CYRS1544AV18 Document History Page (continued) Document Title: CYRS1542AV18/CYRS1544AV18, 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology Document Number: 001-60006 Rev. ECN No. Submission Date Orig. of Change *H 3640834 06/08/2012 HRP Updated Radiation Performance (Updated Prototyping Options). Renamed the section Class V Flow as Manufacturing Flow. Updated Glossary. *I 3857750 01/04/2013 HRP Updated Ordering Information (Updated part numbers). *J 3900846 02/11/2013 HRP Updated Neutron Soft Error Immunity (Changed value of Test Conditions of SEL parameter from 85 °C to 125 °C). Description of Change Updated Pin Definitions (Changed Pin Name from A to A[x:0]). Updated Functional Overview (Updated Qualification and Screening (Replaced Class V with Class Q)). *K 3934155 03/15/2013 MISA Updated Selection Guide: Changed Maximum operating current (concurrent R/W) corresponding to “× 18” for 250 MHz frequency from 1650 mA to 1700 mA. Changed Maximum operating current (concurrent R/W) corresponding to “× 36” for 250 MHz frequency from 1650 mA to 1700 mA. Updated Electrical Characteristics: Updated DC Electrical Characteristics: Changed maximum value of IDD parameter corresponding 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of IDD parameter corresponding 250 MHz frequency from 1650 mA to 1700 mA. Changed maximum value of ISB1 parameter corresponding 250 MHz frequency from 600 mA to 660 mA. Changed maximum value of ISB1 parameter corresponding 250 MHz frequency from 550 mA to 660 mA. Removed 200 MHz frequency related information. to “× 18” for to “× 36” for to “× 18” for to “× 36” for Updated Switching Characteristics: Changed maximum value of tCO and tCHQV parameters from 0.7 ns to 0.85 ns. Changed minimum value of tDOH and tCHQX parameters from –0.7 ns to –0.85 ns. Changed maximum value of tCCQO and tCHCQV parameters from 0.7 ns to 0.85 ns. Changed minimum value of tCQOH and tCHCQX parameters from –0.7 ns to –0.85 ns. Removed 200 MHz frequency related information. Updated Package Diagram: spec 001-58969 – Changed revision from *C to *D. *L 4286754 02/21/2014 MISA Updated Functional Overview: Updated Qualification and Screening: Replaced “Class Q” with “Class Q, Class V”. Updated Ordering Information (Updated part numbers). Updated to new template. Document Number: 001-60006 Rev. *M Page 32 of 34 CYRS1542AV18 CYRS1544AV18 Document History Page (continued) Document Title: CYRS1542AV18/CYRS1544AV18, 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology Document Number: 001-60006 Rev. ECN No. Submission Date Orig. of Change *M 4618500 01/09/2015 PRIT Document Number: 001-60006 Rev. *M Description of Change Updated Radiation Performance: Updated Radiation Data: Updated 2nd bulleted point. Updated Prototyping Options: Updated 1st bulleted point. Updated Functional Description: Updated description. Added “For a complete list of related resources, click here.” at the end. Updated Pin Definitions: Updated description of CQ and CQ pins. Updated Functional Overview: Updated description. Updated Read Operations: Updated description. Updated Write Operations: Updated description. Updated Application Example: Updated Figure 2. Page 33 of 34 CYRS1542AV18 CYRS1544AV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-60006 Rev. *M Revised January 9, 2015 Page 34 of 34 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.