PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) 2.10 Features • Selectable resolutions, 8 to 20 bits (device dependent) • Eleven input ranges for each resolution • Sample rate 10 sps to 384 ksps • Operational modes: • • Single sample • Multi-sample • Continuous mode • Multi-sample (Turbo) High input impedance input buffer • Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass • Multiple internal or external reference options • Automatic power configuration • Up to four run-time ADC configurations General Description The Delta Sigma Analog to Digital Converter (ADC_DelSig) provides a low power, low noise front end for precision measurement applications. The ADC_DelSig is usable in a wide range of applications depending on resolution, sample rate and operating mode. It is capable 16-bit audio, high speed low resolution for communications processing, and high precision 20-bit low speed conversions for sensors such as strain gauges, thermocouples and other high precision sensors. When processing audio information, the ADC_DelSig is used in a continuous operation mode. When used for scanning multiple sensors, the ADC_DelSig is used in one of the multi-sample modes. When used for single point high resolution measurements, the ADC_DelSig is used in single sample mode. Delta sigma converters use oversampling to spread the quantization noise across a wider frequency spectrum. This noise is shaped to move most of it outside the input signal's bandwidth. An internal low pass filter is used to filter out the noise outside the desired input signal bandwidth. This makes delta sigma converters good for both high speed medium resolution (8 to 16 bits) and low speed high resolution (16 to 20 bits) applications. The sample rate can be adjusted between 10 and 375000 samples per second, depending on mode and Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-65192 Rev. ** Revised December 13, 2010 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet resolution. Choices of conversion modes simplify interfacing to single streaming signals such as audio, or multiplexing between multiple signal sources. The ADC_DelSig is composed of three blocks: input amplifier, third order Delta-Sigma modulator, and a decimator. The input amplifier provides a high impedance input and a userselectable input gain. The decimator block contains a 4 stage CIC decimation filter and a postprocessing unit. The CIC filter operates on the data sample directly from the modulator. The post-processing unit optionally performs gain, offset, and simple filter functions on the output of the CIC decimator filter. Figure 1: ADC_DelSig Block Diagram Delta Sigma Modulator + Input Decimator Result Input Buffer DAC Input/Output Connections Inputs and output connections to the ADC_DelSig component are displayed as pins on the component symbol in the schematic view. An asterisk (*) in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O. nVref – Input * The nVref is an optional pin. It is shown if you have selected the Enable_Vref_Vssa check box. This will allow you to connect the ADC's reference Vssa to the analog global (AGL[6]). If the Enable_Vref_Vssa check box is not selected, this pin will not be shown on the symbol. Refer to Enable_Vref_Vssa parameter description for more information. +Input – Analog Positive analog signal input to the ADC_DelSig. The positive input signal is always present in both the single ended and differential input modes. The ADC converter output returns a value that represents the difference in voltage between positive input and the negative input signal. Page 2 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) –Input – Analog * Negative analog signal input to the ADC_DelSig. The negative input pin is only displayed on the component when the ADC Input Mode is set to Differential. When ADC Input Mode is set to Single, the negative input will be connected to either Vssa or Vref depending on the input range selected. soc – Input * Start of Conversion (soc) starts hardware triggered ADC conversions when a rising edge is detected. A rising edge on this pin, has the same effect as calling the ADC_StartConversion() function. This input is shown when the user selects the "External soc" parameter. If "External soc" is not selected, the I/O pin on the component will be hidden. In Single Sample mode, a single conversion is executed, then the ADC halts. In Continuous and other modes, ADC conversions continue until either the ADC_StopConvert() or ADC_Stop() functions are executed. aclk – Input * External clock source. This pin is present if the Clock Source parameter is set to "External." If the Clock Source parameter is set to "Internal," the clock is configured automatically within the component and the aclk pin is not shown. The aclk input is a clock that is generated outside the component. This clock signal may be derived internal to the chip or from a source external to the PSoC. This clock should be set to the value displayed in the Clock Frequency parameter to achieve the selected sample rate. The duty cycle should be 50 percent. This clock determines the conversion rate as a function of conversion method and resolution. eoc – Output A rising edge on the End of Conversion (eoc) signals that a conversion is complete. The pin goes high for one ADC clock period. The eoc is typically connected to an interrupt or DMA request. The DMA request is typically used to transfer the conversion output to system RAM, DFB, or other component. Document Number: 001-65192 Rev. ** Page 3 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Component Parameters The Delta Sigma ADC is a highly configurable analog to digital converter. Drag an ADC_DelSig component onto your design and double-click it to open the Configure dialog. Sampling Conversion Mode The ADC_DelSig operates in one of four modes: Mode 0 - Single Sample Page 4 of 38 Description The ADC produces one sample per startup conversion. The interrupt should be enabled for ADC conversion with Single Sample conversion mode when the resolution is above 16 bits. To do so, enable the Global Interrupt (by calling CYGlobalIntEnable) in the application (main.c). Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Mode Delta Sigma Analog to Digital Converter (ADC_DelSig) Description 1 - Multi-Sample Multi-sample mode captures single samples back to back, resetting itself and the modulator between each sample automatically. This mode is useful when the input is switched between multiple signals. The filters are flushed between each sample so previous samples do not affect the current conversion. Note Care should be taken when switching signals between ADC conversions. Either switch the input quickly between conversions with hardware control or Stop the ADC conversion (ADC_StopConvert()) while switching the input then restart the ADC conversion (ADC_StartConvert()) after the new signal has been connected to the ADC. Failure to do this may result in contamination between signals in the ADC results. 2 - Continuous Continuous sample mode operates as a normal Delta-Sigma converter. Use this mode when measuring a single input signal. There is a latency of three conversion times before the first conversion result is available. This is the time required to prime the internal filter. After the first result, a conversion will be available at the selected sample rate. This mode should not be used when multiple signals are multiplexed and measured with a single ADC. 3 - Multi-Sample (Turbo) The Multi-Sample (Turbo) mode operates identically to the Multi-Sample mode for resolution of 8 to 16 bits. For resolutions of 17 to 20 bits, the performance of this mode is about 4 times faster than the Multi-Sample mode. Note Care should be taken when switching signals between ADC conversions. Either switch the input quickly between conversions with hardware control or stop the ADC conversion (ADC_StopConvert()) while switching the input. Then restart the ADC conversion (ADC_StartConvert()) after the new signal has been connected to the ADC. Failure to do this may result in contamination between signals in the ADC results. All four ADC modes fully flush the decimator when the ADC initially starts conversions. This insures that the first reading from the ADC will be valid as long as the input voltage is stable prior to starting conversions with either the ADC_StartConvert() API or when triggered by the "SOC" input. Although all modes reset the decimator when starting the ADC, only the Continuous mode does not reset the decimator between readings. Because of this, the first reading in "Continuous" mode will take four times longer than the subsequent readings. When using an analog mux to scan between multiple inputs, care must be taken to ensure that the ADC is not running while the input switches are changing. To switch input between samples when using modes other than "Continuous", use the "Analog Hardware Mux". When changing the Conversion Mode parameter, the clock frequency will change to maintain the selected sample rate. If the ADC clock frequency exceeds the minimum or maximum an error condition will be displayed. # Configs You may define up to four different configurations using the # Configs parameter. For example, the system may require switching between continuous mode 16 bit, 48 ksps for audio, single sample mode 20 bit 60 sps for low level analog sensors, and multi-sample mode for 12 bit general purpose multi-channel data logging. All configurations must use the same Input Mode, all single-ended or all differential. By default, the ADC will be set to the first configuration (Config1) unless the ADC_SelectConfiguration() function sets the configuration to a different value. When selecting Document Number: 001-65192 Rev. ** Page 5 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet between two and four configurations, additional tabs will appear in the Configure dialog. These multiple configurations allow you to change modes during run time. Each configuration is contained in its own tab. There are some considerations when using multiple ADC configurations: • All configurations must use the same Input Mode, all single-ended or all differential. • The Common tab contains the Hardware SOC, Clock Source, Low Power C-Pump, ADC Mode, and Enable_Vref_Vssa parameters, which are common to all modes. These parameters are described under Common Settings. • The Ref Mode parameter will also have some restrictions. If the options on Config 1 set an external reference or bypass mode, the other configurations may select the same mode or use the internal reference. • Each configuration will have a separate Interrupt Service Routine function. When the ADC_SelectConfiguration() function is called, the interrupt vector will be changed to the corresponding interrupt vector routine. When a clock external to the ADC (either external to the chip or supplied from user selected internal clock) is utilized, the required clock rate is displayed in this field. It is your responsibility to provide the appropriate clock for each configuration. Resolution The resolution of the ADC_DelSig is entered as an integer value, limited to 8 to 20 bits. Higher resolution results in lower sample rate. Default resolution is 16 bits. When changing the Resolution parameter, the clock frequency will change to maintain the selected sample rate. If the ADC clock frequency exceeds the minimum or maximum an error condition will be displayed. Delta-Sigma ADCs have inherent instability resulting in non-linearity at the positive and negative limits of the operating range. To correct for this phenomenon, the input has been attenuated by 10% at the front end of the modulator. The post processor then compensates for this attenuation with a gain of about 1.11. The end result expands the input range by 10%. For example if the input range ±1.024 V is selected, the actual range of the ADC is approximately ±1.126 V. The usable input range remains ±1.024 V, but the ADC will not saturate until the input exceeds ±1.126 V. The digital output from the ADC will also over range by 10%. If the ADC is configured for 10-bit operation, normally a 10-bit differential ADC's output will range from –512 to 511, for an input of -1.024 to +1.022 respectively. Because of this additional 10% of range, the digital output will not saturate until about ± 563 counts, instead of -512 to 511. This is not normally a concern unless a resolution of 8 or 16 bits is selected. When the resolution is set to either 8 or 16 bits, care must be taken to ensure that the numerical value does not wrap around from its most positive or negative value to a negative or positive value respectively. To ensure this does not occur, it is good practice to use the API function that returns a word larger than the set resolution. For example, if the resolution is set to 16 bits and there is a possibility that the most positive value may be larger than 32767 or less than -32768, the Page 6 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) ADC_GetResult32() function should be used instead of ADC_GetResult16(). The proper 16 bit value will be returned without over-ranging. When the resolution is set to 8 bits and the ADC output values may be less than –128 or greater than 127, the ADC_GetResult16() function should be used. The proper 8 bit value will be returned without over-ranging. Figure 2: Sample Rate Limits for ADC_DelSig 1000000 100000 10000 1000 Continuous Multi-Sample 100 Multi-SampleTurbo 10 1 6 8 10 12 14 16 18 20 22 Resolution, bits Conversion Rate ADC conversion rate is entered as an integer decimal value in samples per second (SPS). The maximum sample rate is a function of resolution, sample mode and maximum operating clock frequency; the higher the resolution, the lower the sample rate. The minimum clock for all resolutions is 128 kHz. The maximum clock for resolutions between 8 and 15 bits is 6.144 MHz. The maximum clock for resolutions between 16 and 20 bits is 3.027 MHz. See Figure 2 for valid conversion rates for each resolution and conversion mode combination; the same information is presented in tabular form in the following table. The following data applies to ADC range = ±1.024 V with Buffer Gain = 1.0. Table 1: Sample Rate Limits for ADC_DelSig (Buffer Gain = 1) Single-Sample Multi-Sample Continuous Multi-Sample Turbo Resolution Min Max Min Max Min Max Min Max 8 1911 91701 1911 91701 8000 384000 1829 87771 9 1543 74042 1543 74042 6400 307200 1489 71441 10 1348 64673 1348 64673 5566 267130 1307 62693 Document Number: 001-65192 Rev. ** Page 7 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) Single-Sample PSoC® Creator™ Component Data Sheet Multi-Sample Continuous Multi-Sample Turbo Resolution Min Max Min Max Min Max Min Max 11 1154 55351 1154 55351 4741 227555 1123 53894 12 978 46900 978 46900 4000 192000 956 45850 13 806 38641 806 38641 3283 157538 791 37925 14 685 32855 685 32855 2783 133565 674 32337 15 585 28054 585 28054 2371 113777 577 27675 16 495 11861 495 11861 2000 48000 489 11725 17 124 2965 124 2965 500 12000 282 6766 18 31 741 31 741 125 3000 105 2513 19 4 93 4 93 16 375 15 357 20 2 46 2 46 8 187 8 183 The ADC buffer has a finite gain bandwidth which affects settling time. Increasing the buffer gain reduces the available maximum sample rate. The maximum sample rate is the sample rate in Table 1 divided by the buffer gain. Other ranges and buffer gains will affect the maximum sample rate. When changing the Conversion Rate parameter, the clock frequency will change to maintain the selected sample rate. If the ADC clock frequency exceeds the minimum or maximum, an error indication displays next to the parameter. See Invalid Settings. Range [ __ SPS ] This field is a non-editable (always grayed out) area used to display the minimum and maximum available conversion rate for the current settings. Clock Frequency This text box is a non-editable (always grayed out) area used to display the required clock rate for the selected operating conditions: conversion mode, resolution, conversion rate, input range and buffer gain. It is updated when any of these conditions are changed. The clock frequency is displayed with a resolution of 1 Hz. If the required clock frequency for the selected operating conditions is outside of the minimum and maximum limits, an error indication displays next to the parameter. See Invalid Settings. The clock frequency is calculated based on the Resolution, Conversion Mode, and Conversion Rate. The rate will be displayed in the Design-Wide Resources Clock Editor, which will always show the clock frequency for Config 1. The ADC API will set the current clock frequency based Page 8 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) on the configuration selected during run time when the Clock Source parameter is set to "Internal." When a clock external to the ADC (either external to the chip or supplied from user selected internal clock) is utilized, the required clock rate is displayed in this field. It is your responsibility to provide the appropriate clock for each configuration. Invalid Settings The parameters Conversion Mode, Resolution, and Conversion Rate all affect the ADC clock frequency. Changing any of these parameters may cause the ADC clock frequency to exceed the maximum or minimum rate. The maximum ADC frequency is a function of Resolution, Buffer Gain and Input Range. If an invalid setting for these parameters occurs, a red circle with an exclamation point will appear, as follows: If you hover the cursor over one of the error symbols, it will display an error message. Change the parameters as needed to comply with the ADC specifications. Input Options Input Mode The ADC is inherently differential; however, you may use this parameter to simplify single-ended use. This parameter configures the ADC for a Differential or Single Ended input. The default selection is Differential. In this mode, both negative and positive inputs are shown on the symbol. When Single Ended mode is selected, the negative input to the ADC is connected to Vssa. Differential Single Ended The Input Mode can only be set in Config 1. If more than one configuration is used, all configurations must use the same Input Mode set in Config 1. If both Single Ended and Differential modes are required, the Differential mode must be selected and you can use an analog mux to connect Vssa to the negative input of the ADC to use as a single-ended ADC.. This parameter controls the options available in the Input Range parameter. Document Number: 001-65192 Rev. ** Page 9 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Input Range This parameter configures the ADC for a given input range. This configures the input to the ADC and is independent of the Input Buffer Gain setting. The analog signals connected to the IC must be between Vssa and Vdda no matter what input range settings are used. The absolute maximum of the ADC Input Range will always be dictated by the absolute maximum and minimum of the Buffer Mode. The options available for this parameter vary depending on the Input Mode selection; the following tables describe the options. The following options are available when Input Mode is set to Differential: For systems where both single ended and differential signals are scanned, connect the negative input to Vssa when scanning a single ended input. Depending on the application, you can select either Rail to Rail, Level Shift, or Bypass using the Buffer Mode parameter. See Buffer Mode parameter description for more details. An external reference may be used to provide a different operating range. The usable input range can be calculated with the equation. Table 2 Differential Input Range Options Input Range Internal Ref (External Ref) Description ±1.024 V (–Input ± Vref) When using the internal reference (1.024 V), the input range will be –Input ± 1.024 V. If the negative input is connected to 2.048 V the usable input range is 2.048 ±- 1.024 V or 1.024 to 3.072 V. ±2.048 V (–Input ± 2*Vref) When using the internal reference (1.024 V), the input range will be –Input +/- 2.048 V. If the negative input is connected to 2.028 volts the usable input range is 2.048 +/- 2.048 V or 0.0 to 4.096 V. ±6.144 V (–Input ± 6*Vref) When using the internal reference (1.024 V), the input range will be –Input ± 6.144 V., but not exceeding maximum electrical input range. This mode can be used to measure the supply voltages when connecting the negative input to Vssa. If you intend to measure the supply you must bypass the buffer.. ±0.512 V (-Input ± Vref/2) When using the internal reference (1.024 V), the input range will be –Input ± 0.512 V. If –Input is connected to 1.0 V the usable input range is 1.0 ± 0.512 V or 0.488 to 1.512 V. ±0.256 V (-Input ± Vref/4) When using the internal reference (1.024 V), the input range will be –Input ± 0.256 V. If –Input is connected to 1.0 V the usable input range is 1.0 ± 0.256 V or 0.744 to 1.256 V. ±0.128 V (-Input ± Vref/8) When using the internal reference (1.024 V), the input range will be –Input ± 0.128 V. If –Input is connected to 1.0 V the usable input range is 1.0 ± 0.128 V or 0.872 to 1.128 V. ±0.064 V When using the internal reference (1.024 V), the input range will be –Input ± 0.064V. If –Input is (-Input ± Vref/16) connected to 1.0 V the usable input range is 1.0 ± 0.064 V or 0.936 to 1.064 V. Page 10 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) The above options are dependent on the Vref setting. The table below shows examples with the Vref equal to 1.024 volts and 1.200 volts. The leading numeric value is dependent on the “Vref” setting in the “Reference” section. With Vref = 1.024V With Vref = 1.2V +/- 1.024V ( -Input +/- Vref ) +/- 1.200V ( -Input +/- Vref ) +/- 2.048V ( -Input +/- Vref*2 ) +/- 2.400V ( -Input +/- Vref*2 ) +/- 6.144 (-Input +/- 6*Vref) +/- 7.200 ( -Input +/- 6*Vref) +/- 0.512V ( -Input +/- Vref/2 ) +/- 0.600V ( -Input +/- Vref/2 ) +/- 0.256V ( -Input +/- Vref/4 ) +/- 0.300V ( -Input +/- Vref/4 ) +/- 0.128V ( -Input +/- Vref/8 ) +/- 0.150V ( -Input +/- Vref/8 ) +/- 0.064V ( -Input +/- Vref/16 ) +/- 0.075V ( -Input +/- Vref/16 ) The following options are available when Input Mode is set to Single-Ended. To simulate single ended operation, the negative input is connected to an internal reference value (Vssa or Vref). Depending on the application, you can select either Rail to Rail, Level Shift, or Bypass using the Buffer Mode parameter. See Buffer Mode parameter description for more details. An external reference may be used to provide a different operating range. The usable input range can be calculated with the applicable equation. Table 3 Single-Ended Input Range Options Input Range Internal Ref (External Ref) Description Vssa to 1.024 V (0 to Vref) When using the internal reference (1.024 V), the usable input voltage to the ADC is 0.0 to 1.024 Volts. Vssa to 2.048 V (0.0 to 2*Vref) When using the internal reference (1.024 V), the usable input voltage to the ADC is 0.0 to 2.048 Volts. This range requires that the input buffer gain be equal to 1. If a gain other than 1 is selected, the ADC will not operate properly Vssa to Vdda This mode is ratiometric of the supply voltage. The input range is Vssa to Vdda. An external reference should not be used for this setting. This range requires that the input buffer gain be equal to 1. If a gain other than 1 is selected, the ADC will not operate properly. Vssa to 6.144 V (Vssa to 6*Vref) When using the internal reference (1.024 V), the input range will be 0.0 to 6.144 V., but not exceeding maximum electrical input range. This mode can be used to measure the supply voltage. If you intend to measure the supply you must bypass the buffer. The table below shows the example with Vref = 1.024V and 1.2V. The leading numeric value will be dependent on the “Vref” setting in the “Reference” section. Document Number: 001-65192 Rev. ** Page 11 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet With Vref = 1.024V With Vref = 1.2V Vssa to 1.024V ( 0.0 to Vref ) Vssa to 1.200V ( 0.0 to Vref ) Vssa to 2.048V ( 0.0 to Vref*2 ) Vssa to 2.400V ( 0.0 to Vref*2 ) Vssa to Vdd Vssa to Vdd Vssa to 6.144 (0.0 to 6*Vref) Vssa to 7.200 (0.0 to 6*Vref) Note When selecting the Vss to Vdd option, the customizer will automatically select either the Vdda/4 or Vdda/3 reference. This selection is based on the value of Vdda entered in the design wide resources. Buffer Gain Selects the ADC input buffer gain. The ADC buffer has a finite gain bandwidth which affects settling time. Increasing the buffer gain reduces the available maximum sample rate. The maximum sample rate is the sample rate in Table 1 divided by the buffer gain. To achieve the highest signal to noise ratio, it is important to use the full range of the ADC. The input buffer can be used to amplify the input signal to make use of the full range of the ADC. Care should be taken to make sure the Buffer_Gain and ADC_Input_Range setting are compatible. Unbuffered Buffered Buffer Gain Description 1 Sets input buffer gain at 1. 2 Sets input buffer gain at 2. 4 Sets input buffer gain at 4. 8 Sets input buffer gain at 8. Page 12 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Buffer Mode Selects the ADC input buffer mode. The ADC has maximum sample rate when the buffer is used. The unbuffered modes have slightly reduced bandwidth. Buffer Mode Description Bypass Buffer Disables the input buffer gain. If selected, the buffer will be disabled to reduce the overall power consumption. The Buffer Gain parameter will not have any effect if this mode is selected. If this mode is selected then input impedance is reduced to less than 500 k . See the following diagram for specifics on range. Rail to Rail Sets the input buffer mode to rail to rail. See the following diagram for specifics on range. Level-Shift Sets the input buffer mode to Level-Shift. Both positive and negative input buffers will be used. Level-Shift mode allows you to go below the Vssa but not all the way to Vdda. See the following diagram for specifics on range. The following figures show the ADC range for all Buffer Modes. Reference Vref This parameter selects the ADC_DelSig reference voltage and configuration. The reference voltage sets the range of the ADC. ADC_Reference Description Internal Vref Use the internal 1.024-V reference (default) Internal Vref, bypassed on P0[3] * Use internal 1.024-V reference, and allow an external bypass capacitor to be connected on pin P0[3]. Document Number: 001-65192 Rev. ** Page 13 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) ADC_Reference PSoC® Creator™ Component Data Sheet Description Internal Vref, bypassed on P3[2] * Use internal 1.024-V reference, and allow an external bypass capacitor to be connected on pin P3[2]. External Vref on P0[3] Use external reference on pin P0[3]. See DC Characteristics section for allowable range. External Vref on P3[2] Use external reference on pin P3[2]. Internal Vdda/4 Use the internal Vdda/4 reference. Internal Vdda/3 Use the internal Vdda/3 reference. This option is valid only for PSoC 3 ES3 and PSoC 5 ES2 silicon or later. Selecting this option with PSoC 3 ES2 and PSoC5 ES1 silicon causes compilation error. * The accuracy and signal to noise ratio are highly dependent on the quality of the reference. The reference supplied to the ADC can be bypassed on either port P0[3] or port P3[2]. The use of an external bypass capacitor is recommended for resolutions of 14 bits and greater. Your chosen reference pin will be automatically configured to use this option. Refer to the following graphic/table for recommendations on bypass cap values. TBD: Graph of cap value versus noise. Noise versus cap value versus resolution. Bandwidth Vref value This parameter sets or displays the reference voltage used by the ADC. If the “Internal 1.024Volts” reference is used, the value 1.024 will be displayed. If the “Internal Vdda/3” or “Internal Vdda/4” reference option is selected, the value is derived from the Vdda setting in the design wide resource page. If an external reference is selected, the user may enter the reference used to ensure the counts to volts API work properly. The minimum and maximum allowed to be entered should be 0.9 to 1.3 volts respectively. The default will be 1.024 volts. When the selected reference is outside the range 0.9 to 1.3 volts, an error symbol at the end of Vref Value numerical drop down menu will alert the user that an error condition has occurred. Also compilation fails if Vref value exceeds the expected range of 0.9V to 1.3V. The table below shows the Vref value displayed when different reference options are selected. Reference selected Vref value displayed Comment Internal 1.024 Volts 1.024 Value not editable. Internal 1.024V Bypassed on P0.3 1.024 Value not editable. Internal 1.024V Bypassed on P3.2 1.024 Value not editable. External Vref on P0.3 1.024 Value is editable with a default value of 1.024 External Vref on P3.2 1.024 Value is editable with a default value of 1.024 Page 14 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Reference selected Vref value displayed Delta Sigma Analog to Digital Converter (ADC_DelSig) Comment Internal Vdda/4 1.250* This value is derived from the Vdda setting in the design wide resource. Value is not editable. *The example shown is for a Vdda of 5.0 volts. Internal Vdda/3 1.100** This value is derived from the Vdda setting in the design wide resource. Value is not editable. **The example shown is for a Vdda of 3.3 volts. Common Settings Hardware SOC (Start of Conversion) The ADC may be started by firmware with the ADC_StartConvert() function or by triggering with a hardware signal. Checking the Hardware SOC parameter enables an external pin to start conversion. When Hardware SOC is enabled the pin is displayed on the component; when not enabled, no pin is displayed. The conversion starts on the rising edge of the signal on the pin. Conversions continue until ADC_StopConvert() is called. By default, Hardware SOC is disabled. If a conversion is already in process, a Hardware SOC trigger is ignored. Clock Source The ADC can be clocked by a source internal to the ADC component, a source external to the component but internal to the chip using a standard clock component or UDB, or by a source external to the chip. The internal or external clock selection is made via a radio button. When Document Number: 001-65192 Rev. ** Page 15 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet external clock is enabled, a clock input pin is displayed on the ADC schematic symbol. External clocks must have 50-percent duty cycle, the internal clock is guaranteed by design to have the correct duty cycle. Clock stability is important for achieving low noise operation. One of the effects of jitter is substantial spreading of the signal. These are clearly shown in the following FFTs. The signal to noise ratio (SNR) of the ADC can be significantly improved with the use of an external clock. Figure 3: Noise versus Clock 16 bit 65536 Point FFT - Internal Clock, Fin=10 kHz 16 bit 65536 Point FFT - External Clock, Fin=10 kHz Low Power Charge-Pump Portions of the ADC_DelSig are powered by an internal charge pump which operates on a high frequency clock. When this option is selected, a lower frequency clock is routed to the internal charge pump, which can reduce power. This may save 100 to 300 µA, but will consume an additional clock resource. If selected, the ADC_Start and ADC_Stop functions will control this clock. By default, the Low Power Charge Pump is disabled. Page 16 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Enable_Vref_Vssa This parameter will allow you to connect the negative input of the ADC's reference Vssa to the analog global AGL[6]. For high accurate systems the Vref_Vssa can be connected to the external Vssa to eliminate any small difference between the on-chip Vssa and the off-chip Vssa. This small difference may cause a gain error in the ADC. This option is valid only for PSoC 3 ES3 and PSoC 5 ES2 silicon or later. Selecting this option with PSoC 3 ES2 and PSoC5 ES1 silicon causes compilation error. Vref_Vssa is an advanced feature that is useful when using an external reference supplied to the ADC. The Vref_Vssa connection can be routed through the analog routing fabric and brought out to a pin. This enables you to connect to an external reference and eliminate any offset in the reference supplied to the ADC due to I*R drops in the Vssa pin and bonding wire. The Vref_Vssa makes a direct connection to Analog Global Left 6 (AGL[6]) [See the analog routing diagram in the device data sheet for more information]. AGL[6] makes direct connections to pins P4[6], P4[2], P0[6] and P0[2]. For the best possible performance, you should ensure that Vref_Vssa is connected to one of these pins. Placing Vref_Vssa on another pin will cause extra routing resources to be consumed and extra resistance will be added in series with the connection. The manual analog routing system (MARS) components allow you to a add rule check that ensures only the specified pins can be used. By placing an Analog Resource Constraint on the Vref_Vssa net, only resources that make direct connections to that net can be used. If you place a pin on that net that is not directly connected to AGL[6], the tool will generate an error during the build process. The error will indicate that you have connected a resource to that net that has no direct connection to the pin and therefore cannot route. The following is an example: Placement Not applicable Document Number: 001-65192 Rev. ** Page 17 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Resources The ADC_DelSig uses a decimator, Delta-Sigma modulator, and a clock source. If an external reference or reference bypass is selected, P0[3] or P3[2] can be used for the external reference or bypass capacitor. API Memory (Bytes) Digital Blocks Resolution Datapaths Macro cells Status Registers Control Registers Counter7 Flash RAM Pins (per External I/O) 8-20 Bits 0 0 0 0 0 3984 13 - Application Programming Interface Application Programming Interface (API) routines allow you to configure the component using software. The following table lists and describes the interface to each function. The subsequent sections cover each function in more detail. By default, PSoC Creator assigns the instance name "ADC_DelSig_1" to the first instance of a component in a given design. You can rename the instance to any unique value that follows the syntactic rules for identifiers. The instance name becomes the prefix of every global function name, variable, and constant symbol. For readability, the instance name used in the following table is "ADC". Function Description void ADC_Start(void) Sets the initVar variable, calls the Init function, and then calls the Enable function. void ADC_Stop(void) Stop ADC conversions and power down. void ADC_SetBufferGain(uint8 gain) Select input buffer gain (1,2,4,8) void ADC_StartConvert(void) Start conversion. void ADC_StopConvert(void) Stop Conversions void ADC_IRQ_Enable(void) Enables interrupts at end of conversion. void ADC_IRQ_Disable(void) Disables interrupts. uint8 ADC_IsEndConversion(uint8 retMode) Returns a non-zero value if conversion is complete. int8 ADC_GetResult8(void) Returns an 8-bit conversion result, right justified. int16 ADC_GetResult16(void) Returns a 16-bit conversion result, right justified. int32 ADC_GetResult32(void) Returns a 32-bit conversion result, right justified. void ADC_SetOffset(int32 offset) Sets the offset used by the ADC_CountsTo_mVolts, Page 18 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Function Description ADC_CountsTo_uVolts, and ADC_CountsTo_Volts functions. void ADC_SelectConfiguration(uint8 config uint8 restart) Sets one of up to four ADC configurations. void ADC_SetGain(int32 adcGain) Sets the gain used by the ADC_CountsTo_mVolts, ADC_CountsTo_uVolts, and ADC_CountsTo_Volts functions. int32 ADC_CountsTo_mVolts(int32 adcCounts) Convert ADC counts to mV. Int32 ADC_CountsTo_uVolts(int32 adcCounts) Convert ADC counts to µV. float ADC_CountsTo_Volts(int32 adcCounts) Convert ADC counts to floating point volts. void ADC_Sleep(void) Stop ADC operation and saves the user configuration. void ADC_Wakeup(void) Restores and enables the user configuration. void ADC_Init(void) Initialize or restore the ADC per the Configure dialog settings. void ADC_Enable(void) Enable the ADC. void ADC_SaveConfig(void) Save the current configuration. void ADC_RestoreConfig(void) Restores the configuration. Global Variables Variable Description ADC_initVar Indicates whether the ADC has been initialized. The variable is initialized to 0 and set to 1 the first time ADC_Start() is called. This allows the component to restart without reinitialization after the first call to the ADC_Start() routine. If reinitialization of the component is required, then the ADC_Init() function can be called before the ADC_Start() or ADC_Enable() functions. ADC_offset The ADC_offset variable is used for offset calibration purpose. Initially this variable is set to zero. Application can modify it using ADC_SetOffset function. Affects only the ADC_CountsTo_Volts, ADC_CountsTo_mVolts, ADC_CountsTo_uVolts functions by subtracting the given offset. ADC_CountsPerVolt The ADC_countsPerVolt variable is used for gain calibration purpose. Initially this variable is calculated for default ADC configuration. The calculated value depends on resolution, input range and voltage reference. Application can modify it using ADC_SetGain() function. Affects only the ADC_CountsTo_Volts, ADC_CountsTo_mVolts, ADC_CountsTo_uVolts functions by supplying the correct conversion between ADC counts and the applied input voltage. ADC_convDone The ADC_convDone variable is used as the software flag for checking the ADC conversion in case of single sample conversion mode for resolutions above 16 bit. Document Number: 001-65192 Rev. ** Page 19 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet void ADC_Start(void) Description: Sets the initVar variable, calls the ADC_Init() function, and then calls the ADC_Enable() function. This function configures and powers up the ADC, but does not start conversions. By default the ADC is configured for Config1 unless the ADC_SelectConfiguration() function selects an alternate configuration. Parameters: None Return Value: None Side Effects: None void ADC_Stop(void) Description: Disables and powers down the ADC. Note This API is not recommended for use on PSoC 3 ES2 and PSoC 5 ES1 silicon. These devices have a defect that causes connections to several analog resources to be unreliable when not powered. The unreliability manifests itself in silent failures (e.g. unpredictably bad results from analog components) when the component utilizing that resource is stopped. It is recommended that all analog components in a design should be powered up (by calling the ADC_Start() APIs) at all times. Do not call the ADC_Stop() APIs. Parameters: None Return Value: None Side Effects: None void ADC_SetBufferGain(uint8 gain) Description: Sets the input buffer gain. Parameters: (uint8) gain: Input gain setting. See table below for valid gain constants. Gain Options ADC_BUF_GAIN_1X Set input buffer gain to 1. ADC_BUF_GAIN_2X Set input buffer gain to 2. ADC_BUF_GAIN_4X Set input buffer gain to 4. ADC_BUF_GAIN_8X Set input buffer gain to 8. Return Value: None Side Effects: None Page 20 of 38 Description Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) void ADC_StartConvert(void) Description: Forces the ADC to initiate a conversion. If in Single Sample mode, one conversion will be performed then the ADC will halt. If in one of the other three conversion modes, the ADC will run continuously. If the StartConvert function is called while the conversion is in progress, the next conversion start is queued and a new conversion will start after finishing the current conversion. If you want to start a new conversion without waiting for the current conversion to finish, then stop the current conversion by calling ADC_StopConvert(). After stopping the conversion, restart the conversion by calling ADC_StartConvert(). Parameters: None Return Value: None Side Effects: None void ADC_StopConvert(void) Description: Forces the ADC to stop all conversions. If the ADC is in the middle of the current conversion, the ADC will be reset and not provide a result for that partial conversion. Parameters: None Return Value: None Side Effects: None void ADC_IRQ_Enable(void) Description: Enables interrupts to occur at the end of a conversion. Global interrupts must also be enabled for the ADC interrupts to occur. To enable global interrupts, use the enable global interrupt macro "CYGlobalIntEnable;" in main.c, prior to when interrupts should occur. See Interrupt Service Routine section. Parameters: None Return Value: None Side Effects: Enables interrupts to occur. Reading the result will clear the interrupt. void ADC_IRQ_Disable(void) Description: Disables interrupts at the end of a conversion. Parameters: None Return Value: None Side Effects: None Document Number: 001-65192 Rev. ** Page 21 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet uint8 ADC_IsEndConversion(uint8 retMode) Description: Check for ADC end of conversion. This function provides the programmer with two options. In one mode this function immediately returns with the conversion status. In the other mode, the function does not return (blocking) until the conversion has completed. Parameters: (uint8) retMode: Check conversion return mode. See table below for options. Options Description ADC_RETURN_STATUS Immediately returns conversion result status. ADC_WAIT_FOR_RESULT Does not return until ADC conversion is complete. Return Value: (uint8) If a nonzero value is returned, the last conversion has completed. If the returned value is zero, the ADC is still calculating the last result. Side Effects: None int8 ADC_GetResult8(void) Description: This function will return the result of an 8-bit conversion. If the resolution is set greater than 8 bits, the LSB of the result will be returned. When the ADC is configured for 8-bit single ended mode, the ADC_GetResult16() function should be used instead. This function returns only signed 8-bit values. The maximum positive signed 8-bit value is 127, but in singled ended 8bit mode, the maximum positive value is 255. Parameters: None Return Value: (int8) The LSB of the last ADC conversion. Side Effects: None int16 ADC_GetResult16(void) Description: Returns a 16-bit result for a conversion with a result that has a resolution of 8 to 16 bits. If the resolution is set greater than 16-bits, it will return the 16 least significant bits of the result. When the ADC is configured for 16-bit single ended mode, the ADC_GetResult32() function should be used instead. This function returns only signed 16-bit result, which allows a maximum positive value of 32767, not 65535. Parameters: None Return Value: (int16) The 16-bit result of the last ADC conversion. Side Effects: None Page 22 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) int32 ADC_GetResult32(void) Description: Returns a 32-bit result for a conversion with a result that has a resolution of 8 to 20 bits. Parameters: None Return Value: (int32) Result of the last ADC conversion. Side Effects: None void ADC_SetOffset(int32 offset) Description: Sets the ADC offset which is used by the functions ADC_CountsTo_uVolts(), ADC_CountsTo_mVolts(), and ADC_CountsTo_Volts() to subtract the offset from the given reading before calculating the voltage conversion. Parameters: (int32) offset: This value is a measured value when the inputs are shorted or connected to the same input voltage. Return Value: None. Side Effects: Affects the ADC_CountsTo_uVolts(), ADC_CountsTo_mVolts(), and ADC_CountsTo_Volts() functions by subtracting the given offset. void ADC_SetGain(int32 adcGain) Description: Sets the ADC gain in counts per volt for the voltage conversion functions below. This value is set by default by the reference and input range settings. It should only be used to further calibrate the ADC with a known input or if an external reference is used. Parameters: (int32) adcGain: ADC gain in counts per volt. Return Value: None. Side Effects: Affects only the ADC_CountsTo_uVolts(), ADC_CountsTo_mVolts(), and ADC_CountsTo_Volts() functions by supplying the correct conversion between ADC counts and voltage. Document Number: 001-65192 Rev. ** Page 23 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet void ADC_SelectConfiguration(uint8 config uint8 restart) Description: Sets one of up to four ADC configurations. Before setting the new configuration, the ADC is stopped and powered down. After setting the new configuration, the ADC can be powered and conversion can be restarted depending up on the value of second parameter restart. If the value of this parameter is 1, then ADC will be restarted. If this value is zero, then user must call ADC_Start() and ADC_StartConvert() to restart the conversion. Parameters: (uint8) config: Configuration option between 1 and 4. (uint8) restart: Restart option. 1 means start the ADC and restart the conversion. 0 means do not start the ADC and conversion. Return Value: None. Side Effects: None int32 ADC_CountsTo_mVolts(int32 adcCounts) Description: Converts the ADC output to mV as a 32-bit integer. For example, if the ADC measured 0.534 V, the return value would be 534 mV. Parameters: (int32) adcCounts: Result from the ADC conversion. Return Value: (int32) Result in mV. Side Effects: None int32 ADC_CountsTo_uVolts(int32 adcCounts) Description: Converts the ADC output to µV as a 32-bit integer. For example, if the ADC measured – 0.02345 V, the return value would be –23450 µV. Parameters: (int32) adcCounts: Result from the ADC conversion. Return Value: (int32) Result in µV. Side Effects: None float ADC_CountsTo_Volts(int32 adcCounts) Description: Converts the ADC output to volts as a floating point number. For example, if the ADC measures a voltage of 1.2345 V, the returned result would be +1.2345 V. Parameters: (int32) adcCounts: Result from the ADC conversion. Return Value: (float) Result of the last ADC conversion. Side Effects: None Page 24 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) void ADC_Sleep(void) Description: The ADC_Sleep() function checks to see if the component is enabled and saves that state. Then it calls the ADC_Stop() function and calls ADC_SaveConfig() function to save the user configuration. Call the ADC_Sleep() function before calling the CyPmSleep() or the CyPmHibernate() function. Refer to the PSoC Creator System Reference Guide for more information about power management functions. Parameters: None Return Value: None Side Effects: Note If you put the ADC hardware to sleep using the CyPmSleep() function, then after coming out of sleep, ADC_Start() and ADC_StartConvert() need to be executed to restart conversions. void ADC_Wakeup(void) Description: The ADC_Wakeup() function calls the ADC_RestoreConfig() function to restore the user configuration. If the component was enabled before the ADC_Sleep() function was called, the ADC_Wakeup() function will re-enable the component. Parameters: None Return Value: None Side Effects: Calling the ADC_Wakeup() function without first calling the ADC_Sleep() or ADC_SaveConfig() function may produce unexpected behavior. void ADC_Init(void) Description: Initializes or restores the component parameters per the Configure dialog settings. You are not required to call this function if ADC_Start() is called. Parameters: None Return Value: None Side Effects: All registers will be reset to their initial values. This will reinitialize the component. void ADC_Enable(void) Description: Enables the clock and power for ADC. Parameters: None Return Value: None Side Effects: None Document Number: 001-65192 Rev. ** Page 25 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet void ADC_SaveConfig(void) Description: This function saves the component configuration. This will save non-retention registers. This function will also save the current component parameter values, as defined in the Configure dialog or as modified by appropriate APIs. This function is called by the ADC_Sleep() function. Parameters: None Return Value: None Side Effects: None. void ADC_RestoreConfig(void) Description: This function restores the component configuration. This will restore nonretention registers. This function will also restore the component parameter values to what they were prior to calling the ADC_Sleep() function. Parameters: None Return Value: None Side Effects: Calling this function without first calling the ADC_Sleep() or ADC_SaveConfig() function may produce unexpected behavior. DMA Information The DMA component can be used to transfer converted results from the ADC_DelSig register to RAM or another component, such as the Digital Filter Block (DFB). The DMA data request signal (DRQ) should be connected to EOC pin from ADC. The DMA Wizard can be used to configure DMA operation as follows: Name of DMA source / destination in DMA Wizard Direction DMA Req Signal DMA Req Type Description ADC_DelSig_DEC_SAMP_PTR source EOC Edge Receives 1 byte conversion result for input analog value that has a resolution of 8 bits. ADC_DelSig_DEC_SAMPM_PTR source EOC Edge Receives 2 byte conversion result for input analog value that has a resolution of 9-16 bits. ADC_DelSig_DEC_SAMPH_PTR source EOC Edge Receives 3 byte conversion result for input analog value that has a resolution of 17-20 bits. Sample Firmware Source Code PSoC Creator provides numerous example projects that include schematics and example code in the Find Example Project dialog. For component-specific examples, open the dialog from the Component Catalog or an instance of the component in a schematic. For general examples, Page 26 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) open the dialog from the Start Page or File menu. As needed, use the Filter Options in the dialog to narrow the list of projects available to select. Refer to the "Find Example Project" topic in the PSoC Creator Help for more information. Functional Description The Delta Sigma Channel is made up the following blocks: • A high input impedance, front-end buffer (with programmable gain) that can be bypassed (and powered down) when not required. • A fully differential programmable third-order switched capacitor modulator. • A downstream digital filtering option consisting of: A fourth-order Cascaded IntegratorComb (CIC) filter (also called the decimator). The post processing engine (cicdec4_pproc) optionally performs gain, offset and simple FIR filtering functions on the data as it leaves the CIC filter. • ANAIF - Analog interface Logic block consists of the register control for the input buffer and the modulator. The ANAIF also converts the 8-bit wide thermometer output from the modulator into 2's complement format, which is 4 bits wide. This 4-bit wide 2's complement code is sent to the decimator. Without an input buffer, a switched capacitor input stage would consume current to charge the capacitor during each cycle. In that case, the equivalent input resistance would be of the order of 1/fs*C, or 1/(3 MHz)(5 pF) = 66 k . Many sensor applications require a much higher impedance to achieve an accurate reading. Therefore, an input buffer is made a part of the Delta Sigma Channel. The input buffer must also deal with signals closer to ground in some applications and must work closer to the supply rail in others. Input buffer architecture comprises two single-ended buffers used to create a differential channel. Either buffer can be selected for the channel. When the channel operates in a single-ended mode, one of the inputs is connected to Ground Rail, and the corresponding buffer is bypassed. The buffers can be also be individually powered down. There are two main modes of operation for the buffer: • Level-Shifted Mode: Buffer output can be level shifted up from the input when the input is close to 0V input common mode voltage range. • Rail - Rail Mode: This mode is used when input is rail-to rail. Document Number: 001-65192 Rev. ** Page 27 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Figure 4: ADC Buffer Structure The switched capacitor implementation is shown in the Figure. A dynamic element matching (DEM) block shapes the errors due to mismatch in the switched capacitor DAC feedback of the modulator, when operating under 9-level quantization. When the buffer and modulator are correctly configured for a given application, the variable-level programmable quantizer (level 2, 3, or 9) in the modulator produces “the-quantized” bit-stream. This quantized bit-stream is 8 bits wide and in the thermometric format. The conversion of thermometer quantizer code into 2’s complement format, for use in decimator (Sinc4 and Sinc1), is performed in the ANAIF block. Figure 5: Switched Capacitor Delta Sigma Modulator Structure Page 28 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Registers Sample Registers The ADC results may be between 8 and 24 bits of resolution. The output is divided into three 8-bit registers. The CPU or DMA may access these register to read the ADC result. ADC_DEC_SAMP (ADC Output Data Sample Low Register) Bits 7 6 5 4 Value 3 2 1 0 2 1 0 2 1 0 Data[7:0] ADC_DEC_SAMPM (ADC Output Data Sample Middle Register) Bits 7 6 5 4 Value 3 Data[15:8] ADC_DEC_SAMPH (ADC Output Data Sample High Register) Bits 7 6 5 Value 4 3 Data[23:16] DC and AC Electrical Characteristics The following values indicate expected performance and are based on initial characterization data. Unless otherwise specified operating conditions are: • Operation in continuous sample mode • fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits • Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 • Unless otherwise specified, all charts and graphs show typical value Delta-Sigma ADC DC Specifications Parameter Description Conditions Min Typ Max Units Resolution 8 – 20 bits Number of channels, single ended – – No. of GPIO – Document Number: 001-65192 Rev. ** Page 29 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) Parameter Description PSoC® Creator™ Component Data Sheet Conditions Min Typ Max Units Number of channels, differential Differential pair is formed using a pair of GPIOs. – – No. of GPIO/2 – Monotonic Yes – – – – Ge Gain error Buffered, buffer gain = 1, – modulator gain = 1, 16-bit mode – ±0.2 % Gd Gain drift Buffered, buffer gain = 1, – modulator gain = 1, 16-bit mode – 50 ppm/° C Vos Input offset voltage Buffered – – ±0.1 mV TCVos ADC TC input offset voltage Temperature coefficient, input offset voltage – – 55 µV/°C VSSA – VDDA V Input voltage range, differential 1 unbuffered VSSA – VDDA V Input voltage range, differential, 1 buffered VSSA – VDDA – 1 V Input voltage range, single ended 1 PSRRb Power supply rejection ratio, 1 buffered Buffer gain = 1, 16-bit, Range = ±1.024 V 90 – – dB CMRRb Common mode rejection ratio, 1 buffered Buffer gain = 1, 16 bit, Range = ±1.024 V 85 – – dB INL20 Integral non linearity Range = ±1.024 V, unbuffered – – ±32 LSB DNL20 Differential non linearity Range = ±1.024 V, unbuffered – – ±1 LSB INL16 Integral non linearity Range = ±1.024 V, unbuffered – – ±2 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Input buffer used 10 – – M Rin_ADC16 ADC input resistance Input buffer bypassed, 16-bit, Range = ±1.024 V – 74 – k Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range = ±1.024 V – 148 – k 1 1 DNL16 Differential non linearity INL12 Integral non linearity DNL12 Differential non linearity 1 1 1 1 INL8 Integral non linearity DNL8 Differential non linearity Rin_Buff ADC input resistance 1 1 1 2 2 Based on device characterization (not production tested). 2 By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. Page 30 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Parameter Delta Sigma Analog to Digital Converter (ADC_DelSig) Description Conditions 1 Cin_G1 ADC input capacitance Vextref ADC external reference input voltage Min Typ Max Units Gain = 1 – 5 – pF Pins P0[3], P3[2] 0.9 – 1.3 V Current Consumption Current consumption, 20 bit 1 187 sps, unbuffered – – 1.25 mA Current consumption, 16 bit 1 48 ksps, unbuffered – – 1.2 mA Idd_12 Current consumption, 12 bit 1 192 ksps, unbuffered – – 1.4 mA Ibuff Buffer current consumption – – 2.5 mA Idd_20 Idd_16 Document Number: 001-65192 Rev. ** 1 Page 31 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Delta-Sigma ADC AC Specifications Parameter Description Conditions Startup time THD Total harmonic distortion 1 Min Typ Max Units – – 4 Samples Buffer gain = 1, 16 bit, Range = ±1.024 V – – 0.0032 % Range = ±1.024 V, unbuffered 7.8 – 187 sps Range = ±1.024 V, unbuffered – 40 – Hz Range = ±1.024 V, unbuffered 2 – 48 ksps Range = ±1.024 V, unbuffered – 11 – kHz 20-Bit Resolution Mode 1 SR20 Sample rate BW20 Input bandwidth at max sample rate 1 16-Bit Resolution Mode 1 SR16 Sample rate BW16 Input bandwidth at max sample rate SINAD16int Signal to noise ratio, 16-bit, internal 1 reference Range = ±1.024V, unbuffered 81 – – dB SINAD16ext Signal to noise ratio, 16-bit, external 1 reference Range = ±1.024 V, unbuffered 84 – – dB 4 – 192 ksps Range = ±1.024 V, unbuffered – 44 – kHz Range = ±1.024 V, unbuffered 66 – – dB 8 – 384 ksps Range = ±1.024 V, unbuffered – 88 – kHz Range = ±1.024 V, unbuffered 43 – – dB 1 12-Bit Resolution Mode SR12 Sample rate, continuous, high power Range = ±1.024 V, 1 unbuffered BW12 Input bandwidth at max sample rate SINAD12int Signal to noise ratio, 12-bit, internal 1 reference 1 8-Bit Resolution Mode SR8 Sample rate, continuous, high power Range = ±1.024 V, 1 unbuffered BW8 Input bandwidth at max sample rate SINAD8int Signal to noise ratio, 8-bit, internal 1 reference 1 Notes 1. Vssa to 6*Vbg range is used for direct measurement of Vdda power supply. Actual scale is limited to Vdda. 2. Total gain error is sum of ADC error and buffer error. 3. Total offset voltage error is sum of buffer Vos and ADC Vos 4. SNR definition 1 Based on device characterization (not production tested). Page 32 of 38 Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Delta-Sigma ADC Sample Rates, Range = ±1.024 V Resolution, Bits Continuous Multi-Sample Multi-Sample Turbo Min Max Min Max Min Max 8 8000 384000 1911 91701 1829 87771 9 6400 307200 1543 74024 1489 71441 10 5566 267130 1348 64673 1307 62693 11 4741 227555 1154 55351 1123 53894 12 4000 192000 978 46900 956 45850 13 3283 157538 806 38641 791 37925 14 2783 133565 685 32855 674 32336 15 2371 113777 585 28054 577 27675 16 2000 48000 495 11861 489 11725 17 500 12000 124 2965 282 6766 18 125 3000 31 741 105 2513 19 16 375 4 93 15 357 20 8 187.5 2 46 8 183 Figures Data collection is currently in progress. Document Number: 001-65192 Rev. ** Delta-sigma ADC INL at Maximum Sample Rate INL , LSBs Curre nt, mA Delta-sigma ADC IDD vs sps, Range = ±1.024 V Data collection is currently in progress. Page 33 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) Delta-sigma ADC Noise Histogram, 1000 Samples, 20Bit, 187 sps, Ext Ref, VIN = VREF/2, Range = ±1.024 V Data collection is currently in progress. Delta-sigma ADC Noise Histogram, 1000 samples, 16bit, 48 ksps, Int Ref, VIN = VREF/2, Range = ±1.024 V Data collection is currently in progress. Page 34 of 38 PSoC® Creator™ Component Data Sheet Delta-sigma ADC Noise Histogram, 1000 samples, 16bit, 48 ksps, Ext Ref, VIN = VREF/2, Range = ±1.024 V Data collection is currently in progress. Delta-sigma ADC Noise Histogram, 1000 samples, 12bit, 192 ksps, Int Ref, VIN = VREF/2, Range = ±1.024 V Data collection is currently in progress. Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Delta Sigma Analog to Digital Converter (ADC_DelSig) Delta-Sigma ADC RMS Noise vs. Input Range and Sample Rate, 20-bit, External Reference Data collection is currently in progress. This table will be updated in a future release. Input Voltage Range RMS Noise, Counts Sample rate, sps Single-Ended 0 to VREF 0 to VREF × 2 VSSA to VDDA Differential 0 to VREF × 6 ±VREF ±VREF/2 ±VREF/4 ±VREF/8 ±VREF/16 2.8 5.6 11.3 22.5 45 90 187.5 Delta-sigma ADC DNL vs Output Code, 16-bit, 48 ksps, 25 °C VDDA = 3.3 V Document Number: 001-65192 Rev. ** Page 35 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) PSoC® Creator™ Component Data Sheet Delta-sigma ADC INL vs Output Code, 16-bit, 48 ksps, 25 °C VDDA = 3.3 V Component Changes This section lists the major changes in the component from the previous version. Version 2.10 Description of Changes Reason for Changes / Impact Two differential input range ±0.128 V(–Input ± Vref/8) ±0.064 V(–Input ± Vref/16) names are changed. These input ranges have an error in their name. Note: When updating an existing project which uses older version than 2.0 with the version 2.10 of the ADC_DelSig, may result in a parameter evaluation failed error message. To fix the problem, open the Configure dialog, and then toggle the selection for Input mode. Click OK to close the dialog and then build the project. Two new reference options Internal Vdda/4 Internal Vdda/3 are added. The reference input for the PSoC3 ADC has a narrow range, 0.9 V to 1.3 V. This may cause the Vss to Vdda ratiometric range not to operate properly when Vdda is less than 3.6Volts. This new Vdda/3 reference will avoid this problem. Change in the reference value affects the input range list. Input range list updates based on the reference voltage selected. Error provider is added to Vref Value parameter. To warn the user if used Vref value exceeds the expected range 0.9V to 1.3V. ADC clock frequency is now dependent ADC clock frequency depends on the selected input range. on input range selection. ADC maximum clock frequency will differ based on the input range. If ADC clock frequency exceeds the maximum clock frequency for the selected input range, then error symbol will set on the clock frequency text box. Fixed an issue with offset calculation. Page 36 of 38 0 to 2*Vref single ended mode for resolutions 9, 10, 11, 13, 14 and 15 now works as expected. Document Number: 001-65192 Rev. ** PSoC® Creator™ Component Data Sheet Version Description of Changes Fixed an issue with DMA wizard tool generated code. Delta Sigma Analog to Digital Converter (ADC_DelSig) Reason for Changes / Impact DMA wizard tool uses correct ADC output register when resolution is above 8 bits. Added characterization data to datasheet Minor datasheet edits and updates 2.0 Changed the Input Range parameter: added 4 new input ranges: Vssa to 6*Vref ±6.144 V(–Input ± 6*Vref) ±0.125 V(–Input ± Vref/8) ±0.0625 V(–Input ± Vref/16) When updating an existing project with the 2.0 version of the ADC_DelSig, this change may result in a parameter evaluation failed error message. To fix the problem, open the Configure dialog, and then toggle the selection for Input mode. Click OK to close the dialog and then build the project. Note This change will likely break existing designs. Updated to support PSoC 3 ES2 or later and PSoC 5 ES1 or later. This version supports PSoC 3 ES2 or later and PSoC 5 ES1 or later. Older versions of the component will display an error message when used with newer versions of the silicon. Added Sleep/Wakeup and Init/Enable APIs. To support low power modes, as well as to provide common interfaces to separate control of initialization and enabling of most components. Added new parameters: Input Mode, and Buffer Mode. Removed the Power parameter and added new Conversion Mode "Single Sample." These new parameters were not present in the older versions of the ADC_DelSig component. When updating to version 2.0 of the component, the new parameters are given default values. The default value for the Input Mode parameter is "Differential." The Input Mode parameter drives the selection of the Input Range. Therefore, an updated component previously configured with a "single-ended" Input Range will get a default value of "Differential." Added DMA capabilities file to the component. This file allows the ADC_DelSig to be supported by the DMA Wizard tool in PSoC Creator. Added Keil function reentrancy support to the APIs. Add the capability for customers to specify individual generated functions as reentrant. Edited the Configure Dialog. Made Voltage Reference parameter editable. Added different configurations to support changing the configuration during run time. Dialog allows you to modify the voltage values when Vssa to Vdda input range is selected. Trim values are incorporated into the ADC implementation for the selected input ranges. Trim values will be used to adjust the Decimator gain to improve the performance of ADC. Added Constants to the header file for easier use. The ADC component now has Constants such as reference used, gain set, mode used, sample rate used, etc. so that you can use them in your applications. Document Number: 001-65192 Rev. ** Page 37 of 38 Delta Sigma Analog to Digital Converter (ADC_DelSig) Version Description of Changes PSoC® Creator™ Component Data Sheet Reason for Changes / Impact New optional connection has been added to the ADC DelSig component This can be used to connect the -ve input of modulator to AGL6. Charge pump power setting has been enabled depending on the clock frequency. There was a problem with 8-bit ADC range. The problem was due to not setting charge pump power setting bits with respect to ADC clock in the DSM_CR16 register. ADC code was modified to set these bits depending on the ADC clock frequency. Removed the SetPower API. The SetPower API was a non-functioning API. It was removed intentionally because it did not offer any value. If you had this function in your code, you need to remove it. © Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC® is a registered trademark, and PSoC Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 38 of 38 Document Number: 001-65192 Rev. **