RadHard 4 Mb FAST Async SRAM TID Report

JD Instruments LLC
14800 Central Ave SE
Albuquerque NM 87123
(505) 255-9182
TID-RLAT Test Report for Cypress 4Mb SRAMs
(CYRS1049DV33)
Fab Lot 4126444
Date: 23 Apr 2012
Revision: A
Purchase Order: Cypress 2150257
Prepared By:
JD Instruments
23 Apr 2012
Date
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed
to others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Executive Summary
Radiation Lot Acceptance Testing (RLAT) for Total Ionizing Dose (TID) was performed on 4Mb SRAMs
(CYRS1049DV33), fab lot 4126444. These parts showed very little change in measured parameters at any
radiation level. All parameters stayed well within spec sheet limits up to 350K rad(Si) and the lot passed RLAT
analysis using KTL statistics with Probability of Survival (Ps) of 99% and Confidence Level of 90%. In addition,
no memory failures were detected in any devices, even at the maximum radiation level. All irradiation and testing
was performed in accordance with MIL-STD 883H Method 1019.8 Condition A.
1.0 PART DESCRIPTION
Total Ionizing Dose (TID) Testing was performed by JD Instruments on one lot of 4Mb SRAMs
(CYRS1049DV33). A total of 14 devices were used for this testing. Twelve devices were irradiated and two
devices were reserved as control/reference. All parts were serialized by the manufacturer.
These devices have the architecture shown in Figure 1. This part is a pure static RAM with a power down
function to insure low current consumption when it is not enabled.
Figure 1. Functional Diagram for CYRS1049DV33
Devices were provided in 36 pin ceramic flat packages with pinout as shown in figure 2.
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Figure 2. 36 Pin Flat Package Pinout
Four devices were mounted to each bias board prior to being exposed to radiation. These devices were
arranged in a 2 X 2 matrix to minimize dose rate variation across the pattern. Figure 3 shows this pattern along
with measured dose rates. Dose rates were measured using a calibrated meter as detailed in Attachment A.
Measurements indicated less than +/-1% variation in dose rate across the exposure pattern.
Figure 3. DUT Pattern and Dose Rate
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Tests was performed using an Algorithmic Test Vector (ATV) system from JD Instruments as shown in
figure 4. This is a portable system containing many of the features found in larger main-frame test systems. For
this application it is particularly useful in that it collects data in both primitive error logs and also records summary
results in spreadsheet form, simplifying on-site understanding of results as the test proceeds.
Figure 4. ATV Test System used for TID Testing
All irradiations and tests were performed on these parts in static bias condition with Checkerboard pattern
loaded in memory and their maximum rated Vdd of 3.6V. Later functional and parametric testing was performed
with devices biased to their nominal voltages of Vdd=3.3V. Data retention was tested by lowering the Vdd to
2.0V.
0
0
All tests were performed at room temperature which was ~21 C (70 F). Devices were irradiated inside
lead/aluminum boxes as shown in figure 5. Testing was performed “in-situ” while the parts were inside the
lead/aluminum boxes after the co60 source had been lowered. Testing began within ~1 minute following the end
of each radiation step. All testing was completed and parts were again under irradiation within ~½ hour.
Figure 5. RLAT Devices being Irradiated in Lead/Aluminum Boxes at Co60 Facility
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Circuit schematics for the bias and test boards are presented in Appendix B.
Irradiations were performed to cumulative doses of 100K, 200K and 350K rad(Si). After parametric
measurements were made on all devices at the 350K rad(Si) level they were packed in dry ice and shipped to
0
0
DPACI for AC characterization. Temperature of devices shipped in dry ice was -77 C when packed and -66.8 C
0
when unpacked at DPACI (Note: shipping limit is < -60 C). Accept/reject analysis is based on measurements
made at the 350K rad(Si) level.
Irradiation exposures were performed in a cobalt-60 (Co60) room irradiator located on Kirtland AFB. All
testing was done in accordance with MIL-STD 883H Method 1019.8 Condition A. Testing was performed by H.
Jake Tausch of JD Instruments and Helmut Puchner of Cypress Semiconductor.
These parts showed very little change in measured parameters at any radiation. All parameters stayed well
within spec sheet limits up to 350K rad(Si).
2.0 Lot Acceptance Technique
Parameters were measured and recorded in an excel format spread sheet. The measured values at each
radiation step were analyzed using the Radiation Lot Acceptance Test (RLAT) “variables method” (see MILHDBK-814, Appendix Section 50, especially Table IXB).
In the RLAT variables method the average (Avg) and standard deviation (Std) of each parameter are
calculated for the group of parts being irradiated. A value is then calculated and compared to the part limits using
this average and standard deviation along with a one sided tolerance factor, KTL.
For parameters where the limit is higher than measured values the lot is acceptable if
Avg + KTL * Std < Limit
(eq. 1)
For parameters where the limit is lower than measured values the lot is acceptable if
Avg - KTL * Std > Limit
(eq. 2)
Values for KTL vary depending on sample size, Probability of Survival (Ps) and confidence level. For this
test, with a radiation sample size of 12, Ps of 0.99 and a confidence level of 0.9, the value for KTL was 3.372
(MIL-HDBK-814, Table IXB).
Figure 6 shows test results for one of the parameters that changed with radiation. This is a plot of Isb (CB)
(Stand-by power supply current when memory is loaded with a checkerboard pattern) vs radiation and is
illustrative of how parametric data is presented in the rest of this report. Note that checkerboard was the pattern
loaded into memory while the parts were being irradiated.
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
3-06
0.016
3-07
.
0.014
3-08
3-09
0.012
Isb (CB)
3-10
0.01
3-11
0.008
3-12
3-14
0.006
3-15
0.004
3-16
3-17
0.002
3-18
305
0
0
100000
200000
300000
400000
405
MaxLim
Dose rad(Si)
RLAT_Calc
Figure 6. Isb(CB) Variation with Radiation
First note that the limit is plotted as a solid, bold red line, 15mA in this case. Second, note that the
reference devices (SNs 305 and 405) are plotted as dotted lines with no symbols. Since the reference devices were
not irradiated then their value should remain the same across the plot. Measurements of the reference devices
provide an indication of repeatability of the test for the parameter being plotted. Each irradiated part is plotted as a
separate solid or dashed line with varying symbols. The RLAT calculation for this set of parts is shown as a bold
dashed line.
An RLAT value was calculated at each radiation step using the first equation described above.
Specifically:
RLAT_CALC = Avg + 3.532 * StdDev
The reference devices were not included in RLAT calculations.
The plot shows a gradual increase in supply current for cumulative doses up to 350K rad(Si). The lot
passed RLAT analysis for this parameter.
3.0 Measured Parameters and Results
The following parameters were measured and used for acceptance. Pass/Fail limits for each parameter are
listed with each parameter.
ON-SITE TESTS
1. Functional Write/Read over entire device (no bit failures)
2. Data Retention over entire memory (no bit failures)
a. Write with Vdd = 3.3V
b. Lower Vdd to 2V for 1 Sec
c. Read with Vdd= 3.3V
3. Isb
a. Checkerboard (15mA)
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
4.
5.
6.
7.
8.
9.
Apr 2012 TID RLAT Final Report
b. Checkerboard* (15mA)
c. Retention (CB) (15mA)
Input Leakage Current – IiL/Iih (1uA)
Output Leakage Current (Tri-Stated) – Iozl/Iozh (1uA)
Output High Voltage - Voh (min) (2.4V)
Output Low Voltage - Vol (max) (0.4V)
Vih (min) for proper operation (Less than 2.0V)
Vil (max) for proper operation (Greater than 0.8V)
PRE-/POST Irradiation Tests at DPACI
1. Taal – Address low to data valid (12nS)
2. Taah – Address high to data valid (12nS)
3. Tacel – CE* low to data valid (12nS)
4. Taceh – CE* high to data invalid (12nS)
5. Tdoel – OE* low to data valid (6nS)
6. Tdoeh – OE* high to data invalid (6nS)
7. Icc@83MHz – Power Supply Current when DUT is Operated (enabled) at 83MHz
4.0 RLAT Analysis Results
No memory bits on any device ever failed during this testing, either during functional or retention testing,
and are therefore not discussed further. Results of the other parameters are presented below.
4.1 Isb – Checkerboard, Checkerboard(Not) and Retention
Isb(CB) was shown previously and passed RLAT analysis. It is repeated here for ease of comparison to
other patterns.
3-06
0.016
.
3-07
0.014
3-08
0.012
3-09
Isb (CB)
3-10
0.01
3-11
0.008
3-12
3-14
0.006
3-15
0.004
3-16
3-17
0.002
3-18
305
0
0
100000
200000
300000
400000
405
MaxLim
Dose rad(Si)
RLAT_Calc
Figure 7. Isb(CB) Variation with Radiation
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
PAGE 7
CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Figure 8 shows Isb vs. radiation when memory is loaded with the complementary pattern (CB*). Note that
this current increase is slightly smaller than for the CB pattern. This difference in increase shows that there is a
slight pattern dependence in the radiation sensitivity for these parts. The increase for either pattern is well below
the parameter limit.
3-06
0.016
3-07
0.014
3-08
0.012
3-09
Isb (CB*)
3-10
0.01
3-11
0.008
3-12
3-14
0.006
3-15
0.004
3-16
3-17
0.002
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 8. Isb(CB*) Variation with Radiation
Figure 9 shows Idd-Retention vs. radiation. This was measured by loading memory with the
complementary checkerboard pattern (CB*) and reducing Vdd to 2.0V to put the part in retention conditions. Note
that this current is almost identical to that seen when the same pattern is loaded into memory and Vdd is at it’s
normal operating level. The increase in current is well below the parameter limit.
3-06
0.016
Idd Retention (CB*)
3-07
0.014
3-08
0.012
3-09
3-10
0.01
3-11
0.008
3-12
3-14
0.006
3-15
0.004
3-16
3-17
0.002
3-18
305
0
0
100000
200000
300000
400000
405
MaxLim
Dose rad(Si)
RLAT_Calc
Figure 9. Idd-retention(CB*) Variation with Radiation
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
4.2 Vih and ViL
Figures 10 and 11 show measurements and RLAT analysis for Vih and Vil testing.
3-06
2.5
3-07
3-08
2
3-09
3-10
1.5
3-11
Vih
3-12
3-14
1
3-15
3-16
0.5
3-17
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLin
RLAT_Calc
Figure 10. RLAT Results for Vih
1.4
3-06
3-07
1.2
3-08
3-09
1
3-10
3-11
0.8
Vil
3-12
3-14
0.6
3-15
0.4
3-16
3-17
0.2
3-18
305
0
0
100000
200000
300000
Dose rad(Si)
400000
405
MinLim
RLAT_Calc
Figure 11. RLAT Results for ViL
These parameter are measured by varying logic high and logic low voltages in a binary search sequence to
determine the voltage where the parts pass functional testing. The smallest step was ~25mV so there is some
granularity in the results. There was no detectable change in this parameter with increasing radiation and the lot
passes RLAT analysis for both parameters.
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
4.3 Voh and Vol
Voh and Vol were measured with load currents specified in the data sheet (Ioh = -4mA, Iol = 8mA). These
parameters did not show any change with radiation Both parameters easily pass RLAT analysis.
3-06
3.5
3-07
3
3-08
3-09
2.5
3-10
3-11
Voh
2
3-12
3-14
1.5
3-15
1
3-16
3-17
0.5
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MinLim
RLAT_Calc
Figure 12. RLAT Results for Voh
0.45
3-06
3-07
0.4
3-08
0.35
3-09
0.3
3-10
3-11
Vol
0.25
3-12
0.2
3-14
0.15
3-15
3-16
0.1
3-17
0.05
3-18
305
0
0
100000
200000
300000
Dose rad(Si)
400000
405
MaxLim
RLAT_Calc
Figure 13. RLAT Results for Vol
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
4.4 Iih and IiL
Iih and Iil are the input leakage currents when the inputs are biased to a logic high and logic low. Both
have a limit of 1uA. There was a slight increase in Iih, but both parameters easily pass RLAT analysis.
1.E-06
3-06
3-07
3-08
1.E-06
3-09
3-10
8.E-07
Iih
3-11
3-12
6.E-07
3-14
3-15
4.E-07
3-16
3-17
2.E-07
3-18
305
0.E+00
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 14. RLAT Results for Iih
1.2E-06
3-06
3-07
1.0E-06
3-08
3-09
3-10
8.0E-07
3-11
3-12
6.0E-07
Iil
3-14
3-15
4.0E-07
3-16
3-17
2.0E-07
3-18
305
0.0E+00
0
100000
200000
300000
Dose rad(Si)
400000
405
MaxLim
RLAT_Calc
Figure 15. RLAT Results for IiL
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
4.6 Iozh and IozL
Iozh and Iozl are the output leakage currents when devices are tri-stated and voltages equal to logic high
and logic low are applied to the outputs. Limits are 1uA for both parameters. As shown in Figures 16 and 17 both
parameters easily pass RLAT analysis. There was a slight increase in Iozh at 300K rad(Si), but not enough to
significantly affect the analysis.
1.2E-06
3-06
3-07
1.0E-06
3-08
3-09
3-10
8.0E-07
Ioz-h
3-11
3-12
6.0E-07
3-14
3-15
4.0E-07
3-16
3-17
2.0E-07
3-18
305
0.0E+00
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 16. RLAT Results for Iozh
1.2E-06
3-06
3-07
1.0E-06
3-08
3-09
8.0E-07
3-10
3-11
Ioz-l
6.0E-07
3-12
3-14
4.0E-07
3-15
3-16
2.0E-07
3-17
3-18
0.0E+00
305
0
100000
200000
300000
-2.0E-07
400000
405
MaxLim
Dose rad(Si)
RLAT_Calc
Figure 17. Results for IozL
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
4.7 AC Timing Measurements
A variety of timing measurements were made on these parts at DPACI, pre- and post-radiation. These
parameters are shown below in figures 18 thru 23. Note that none of the timing parameters showed any change
over radiation and all parameters easily passed RLAT analysis.
14
3-06
3-07
12
3-08
3-09
Taal (nS)
10
3-10
3-11
8
3-12
3-14
6
3-15
4
3-16
3-17
2
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 18. Address Low to Data Valid Access Time
14
3-06
3-07
12
3-08
3-09
Taah (nS)
10
3-10
3-11
8
3-12
3-14
6
3-15
4
3-16
3-17
2
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 19. Address High to Data Valid Access Time
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
14
3-06
3-07
12
3-08
3-09
Tacel (nS)
10
3-10
3-11
8
3-12
3-14
6
3-15
4
3-16
3-17
2
3-18
305
0
0
100000
200000
300000
400000
Dose rad(Si)
405
MaxLim
RLAT_Calc
Figure 20. CE* Low to Data Valid Access Time
14
3-06
3-07
12
3-08
3-09
Taceh (nS)
10
3-10
3-11
8
3-12
3-14
6
3-15
4
3-16
3-17
2
3-18
305
0
0
100000
200000
300000
Dose rad(Si)
400000
405
MaxLim
RLAT_Calc
Figure 21. CE* High to Data Invalid Time
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
7
3-06
3-07
6
3-08
3-09
Tdoel (nS)
5
3-10
3-11
4
3-12
3-14
3
3-15
2
3-16
3-17
1
3-18
305
0
405
0
100000
200000
300000
400000
Dose rad(Si)
MaxLim
RLAT_Calc
Figure 22. OE* Low to Data Valid Access Time
7
3-06
3-07
6
3-08
3-09
Tdoeh (nS)
5
3-10
3-11
4
3-12
3-14
3
3-15
2
3-16
3-17
1
3-18
305
0
405
0
100000
200000
300000
Dose rad(Si)
400000
MaxLim
RLAT_Calc
Figure 23. OE* High to Data Invalid Time
4.8 Idd@83MHz
Figure 24 shows the pre- and post-radiation operating current (Idd) when the devices are run at 83MHz.
Note that there is a slight increase in current with radiation. This increase is consistent with that seen in stand-by
currents as shown earlier. The increase doesn’t appear as pronounced here because of the much higher starting
(pre-rad) currents.
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
PAGE 15
CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
100
3-06
3-07
80
Idd@83MHz (mA)
3-08
3-09
60
3-10
3-11
3-12
40
3-14
3-15
3-16
20
3-17
3-18
0
MaxLim
0
100000
200000
300000
400000
RLAT_Calc
Dose rad(Si)
Figure 24. Idd When DUT is Operated at 83MHz, Enabled
5.0 Conclusions
This fab lot of CYRS1543AV18 devices showed no appreciable radiation induced change up to 350K
rad(Si). The lot passed RLAT analysis on all included parameters after the application of 99/90 KTL statistics.
This document contains information Property of Cypress Semiconductor and shall not be reproduced to other documents or disclosed to
others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Appendix A. Calibration Information
A.1 Test Equipment - Test stimulus and parametric measurements were provided by an
Algorithmic Test Vector (ATV) and a Parametric Work Station (PWS), both manufactured by JD
Instruments. Both units have calibration traceable to NIST.
A.2 Radiation Source – See letter below.
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others, or used for any purpose other than that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Appendix B. Board Circuit Schematics
Figure B1. Test Board, Schematic 1 of 2
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that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Figure B2. Test Board, Schematic 2 of 2
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that which is furnished without the prior written permission of Cypress Semiconductor.
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CYRS1049DV33 4MBit SRAM
Apr 2012 TID RLAT Final Report
Figure B3. Bias Board Schematic
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that which is furnished without the prior written permission of Cypress Semiconductor.
PAGE 20