AN86439 PSoC® 4 and PSoC Analog Coprocessor Using GPIO Pins.pdf

AN86439
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Author: Rajiv Badiger
Associated Project: Yes
Associated Part Family: PSoC 4, PSoC Analog Coprocessor
Software Version: PSoC Creator™ 3.3 SP2 or higher
Related Application Notes: For a complete list of the application notes, click here.
More code examples? We heard you.
To access an ever-growing list of hundreds of PSoC code examples, please visit our code examples web page.
You can also explore the PSoC 4 video library here.
®
AN86439 explains how to effectively use PSoC 4 and PSoC Analog Coprocessor GPIO pins with various use case
examples to demonstrate their features. Major topics in this application note include GPIO basics, configuration options,
mixed-signal use, interrupts, and low-power behavior.
Contents
1
2
3
4
5
6
Introduction ...............................................................2
PSoC Resources ......................................................2
2.1
PSoC Creator ..................................................3
2.2
Code Examples ...............................................4
2.3
PSoC Creator Help ..........................................5
2.4
Technical Support ............................................5
GPIO Pin Basics .......................................................6
3.1
Physical Structure of GPIO Pins ......................6
3.2
Pin Routing ......................................................9
3.3
Startup and Low-Power Behavior .................. 19
3.4
GPIO Interrupt ............................................... 20
Overvoltage-Tolerant (OVT) Pins ........................... 22
GPIO Pins in PSoC Creator.................................... 22
5.1
Pins Component Symbols.............................. 22
5.2
Pins Component Customizer ......................... 23
5.3
Pins Component Interrupts ............................ 25
5.4
Manual Pin Assignments ............................... 28
5.5
PSoC Creator APIs ........................................ 28
5.6
Debug Logic on GPIO Pins ............................ 29
5.7
Add Multiple GPIO Pins as a Logical Port...... 29
5.8
Represent Off-Chip Components................... 32
GPIO Tips and Tricks ............................................. 34
6.1
Toggle an LED ............................................... 35
6.2
Read an Input and Write to an Output ........... 36
6.3
Drive an Output from a Digital Logic Gate ..... 37
www.cypress.com
6.4
6.5
6.6
6.7
6.8
6.9
Using a Bidirectional Pin ................................ 38
Set the GPIO Input/Output Synchronization .. 40
Toggle GPIOs Faster with Data Registers ..... 45
Configure GPIO Output Enable Logic ............ 48
Pin Interrupt ................................................... 50
Configure GPIO Interrupt
Settings with Firmware .................................. 52
6.10
Using Both Analog and Digital on a GPIO ..... 54
6.11
Gang Pins for More Drive/Sink Current ......... 57
6.12
Control Register Handling in Deep-Sleep ...... 60
7
Related Application Notes ...................................... 63
8
Summary ................................................................ 63
9
About the Authors ................................................... 63
A
Appendix A: PSoC 4 and
PSoC Analog Coprocessor GPIO
Compared to PSoC 1, PSoC 3, and
PSoC 5LP GPIO ..................................................... 64
B
Appendix B: PSoC 4 Development Boards ............ 64
Document History............................................................ 65
Worldwide Sales and Design Support ............................. 66
Products .......................................................................... 66
®
PSoC Solutions ............................................................. 66
Cypress Developer Community....................................... 66
Technical Support ........................................................... 66
Document No. 001-86439 Rev. *D
1
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
1
Introduction
PSoC has a flexible general-purpose I/O (GPIO) architecture that provides more features than traditional MCUs.
PSoC GPIOs are controlled not only by configuring the registers in firmware, similar to traditional MCUs, but are also
driven by custom digital logic and analog block signals. This application note explains the basics of PSoC 4 and
PSoC Analog Coprocessor GPIO pins, and shows techniques for using them effectively for different functions.
This application note assumes that you are familiar with PSoC Creator™ and the PSoC 4 architecture. If you are new
to PSoC 4 or PSoC Analog Coprocessor, read AN79953 – Getting Started with PSoC 4 or AN211293 - Getting
Started with PSoC Analog Coprocessor respectively. If you are new to PSoC Creator, visit the PSoC Creator home
page. For information on device packages or GPIO specifications, see the PSoC 4 datasheet or PSoC Analog
1
Coprocessor datasheet. If you are already familiar with the device and PSoC Creator, you can jump to the section
GPIO Tips and Tricks.
1
Note References to ‘PSoC’ or ‘device’ henceforth refer to both PSoC 4 and PSoC Analog Coprocessor devices,
unless specified otherwise.
2
PSoC Resources
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design,
and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources,
see KBA86521 - How to Design with PSoC 3, PSoC 4, PSoC 5LP, and PSoC Analog Coprocessor. The following is
an abbreviated list for PSoC 4:


Overview: PSoC Portfolio, PSoC Roadmap

Datasheets describe and provide electrical
specifications for the PSoC 3, PSoC 4,
PSoC 5LP and PSoC Analog Coprocessor
device families.

CapSense Design Guide: Learn how to
design capacitive touch-sensing applications
with the PSoC 3, PSoC 4, PSoC 5LP, and
PSoC Analog Coprocessor families of
devices.

Product Selectors: PSoC 1, PSoC 3,
PSoC 4, PSoC 5LP, or PSoC Analog
Coprocessor. In addition, PSoC Creator
includes a device selection tool.
Development Kits:

CY8CKIT-040, CY8CKIT-041, CY8CKIT042, CY8CKIT-042-BLE, CY8CKIT-044,
CY8CKIT-046 and CY8CKIT-048 Pioneer
Kits are easy-to-use and inexpensive
development platforms. These kits
include
connectors
for
Arduino™
compatible shields and Digilent® Pmod™
daughter cards.

CY8CKIT-049 is a very low-cost
prototyping platform for sampling PSoC 4
devices.

CY8CKIT-001 is a common development
platform for all PSoC family devices.
®

Application Notes and Code Examples
cover a broad range of topics, from basic to
advanced level. Many of the application
notes include code examples.

Technical Reference Manuals (TRM)
provide detailed descriptions of the
architecture and registers in each of the
PSoC 3, PSoC 4, PSoC 5LP, and PSoC
Analog Coprocessor device families.
www.cypress.com

Document No. 001-86439 Rev. *D
The MiniProg3 device provides an interface
for flash programming and debug.
2
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
2.1
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and
firmware design of systems based on PSoC 3, PSoC 4, PSoC 5LP, and PSoC Analog Coprocessor. See Figure 1 –
with PSoC Creator, you can:
1.
2.
Drag and drop Components to build your
hardware system design in the main design
workspace
3.
Configure Components using configuration tools
4.
Explore the library of 100+ Components
Codesign your application firmware with the
PSoC hardware
5.
Review Component datasheets
Figure 1. PSoC Creator Features
www.cypress.com
Document No. 001-86439 Rev. *D
3
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
2.2
Code Examples
PSoC Creator includes a large number of code example projects.
These projects are available from the PSoC Creator Start Page,
as Figure 2 shows.
Figure 2. Code Examples in PSoC
Creator
Example projects can speed up your design process by starting
you off with a complete design, instead of a blank page. The
example projects also show how you can use PSoC Creator
Components for various applications. Code examples and
datasheets are included, as Figure 3 shows.
In the Find Code Example Project dialog shown in Figure 3,
you have several options:

Filter for examples based on device family (such as
PSoC 3, PSoC 4, PSoC Analog Coprocessor or PSoC 5LP);
category; or keyword

Select from the menu of examples offered based on the
Filter Options

Review the datasheet
Documentation tab)

Review the code example for the selection. You can copy
and paste code from this window to your project, which can
help speed up code development, or

Create a new project (and a new workspace, if needed)
based on the selection. This can speed up your design
process by starting you off with a complete, basic design.
You can then adapt that design to your application.
for
the
selection
(on
the
Figure 3. Code Example Projects with Sample Code
www.cypress.com
Document No. 001-86439 Rev. *D
4
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
2.3
PSoC Creator Help
Visit the PSoC Creator home page to download the latest version of PSoC Creator. Then, launch PSoC Creator and
navigate to the following items:
2.4

Quick Start Guide: Choose Help > Documentation > Quick Start Guide. This guide gives you the basics for
developing PSoC Creator projects.

System Reference Guide: Choose Help > System Reference Guides. This guide lists and describes the
system functions provided by PSoC Creator.

Component datasheets: Right-click a component and select “Open Datasheet.” Visit the PSoC 4 Component
Datasheets page for a list of all PSoC 4 Component datasheets.

Document Manager: PSoC Creator provides a document manager to help you to easily find and review
document resources. To open the document manager, choose the menu item Help > Document Manager.
Technical Support
If you have any questions, our technical support team is happy to assist you. You can create a support request on the
Cypress Technical Support page.
If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-5414736. Select option 8 at the prompt.
You can also use the following support resources if you need quick assistance.


Self-help
Local Sales Office Locations
www.cypress.com
Document No. 001-86439 Rev. *D
5
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3
GPIO Pin Basics
The PSoC GPIO pins offer the following features:







Analog and digital input and output capability
LCD segment drive support (not available in PSoC 4000)
CapSense® support
Interrupt on level, rising-edge, falling-edge, or both edges
Slew-rate control
Input threshold select (CMOS / LVTTL / 1.8-V CMOS)
Overvoltage-tolerant pins (available only in PSoC 4 BLE, PSoC 4 M-Series, and PSoC 4 L- Series) with hot-swap
capability
The GPIO functionality depends on the peripherals available in the PSoC 4 or PSoC Analog Coprocessor device. For
a side-by-side comparison of the features available in different PSoC 4 families, see Table1 in AN79953 – Getting
Started with PSoC 4. For features available in PSoC Analog Coprocessor, see AN211293 - Getting Started with
PSoC Analog Coprocessor.
3.1
Physical Structure of GPIO Pins
Figure 4 shows the pin connections with the resources in the PSoC device.
Figure 4. Simplified GPIO Block Diagram
Buffer
Digital
Input
Digital
Output
Digital Output
Driver
Pin
Analog
A detailed block diagram of the GPIO structure is available in the “I/O System” chapter of the PSoC 4 Architecture
TRM and PSoC Analog Coprocessor Architecture TRM. Each pin can act as an input or an output to the CPU and the
2
digital peripheral such as the Timer, PWM, or I C. It can also act as an analog pin for use with opamps and ADC. At
any given time, you can use a pin for only-digital input, only-digital output, only-analog pin, or even combinations of
these three. For example, if you enable both digital output and input, it provides a digital bidirectional pin. The input
buffer provides high impedance to the external input. It is configurable to CMOS, LVTTL, and 1.8-V CMOS (available
only in PSoC 4 BLE, PSoC 4 M-Series and PSoC 4 L-Series).
For the input threshold values, see the device datasheet.
www.cypress.com
Document No. 001-86439 Rev. *D
6
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
The digital output driver supports different drive modes and slew-rate control (see Figure 5).
Figure 5. Digital Output Driver
Vdd Vdd
Digital
Logic
Vdd
In
Slew
Control
PIN
Output
Enable
Drive
Mode
Slew-rate control is provided to reduce EMI and cross-talk. There are two options – Fast and Slow. Slew rate is set to
Fast by default. Use the Slow option when the signals are not speed-critical.
The circuit shown in Figure 5 supports eight drive modes in PSoC 4, as listed in Table 1.
Table 1. Drive Modes and Applications
#
Drive Mode
Application Examples
1
High-impedance Analog
Analog input/output
2
High-impedance Digital
Digital input
3
Resistive Pull-Up (~5 kΩ)
Interface to open-drain LOW input, such as the tachometer output from motors or a
switch connected to ground. It can also be used to drive LEDs.
4
Resistive Pull-Down (~5 kΩ)
Interface to an open-drain HIGH input or a switch connected to VDD. It can be used as
an output to interface LEDs in current-sink mode.
5
Open Drain, Drives Low
Provides high impedance in the HIGH state and a strong drive in the LOW state; this
configuration is used for I2C pins. This mode works in conjunction with an external pullup resistor.
6
Open Drain, Drives High
Provides strong drive in the HIGH state and high impedance in the LOW state. This
mode works in conjunction with an external pull-down resistor.
7
Strong Drive
CMOS output drive in both LOW and HIGH states
8
Resistive Pull-Up and
Resistive Pull-Down (~5 kΩ)
Adds a series resistor in both HIGH and LOW states
www.cypress.com
Document No. 001-86439 Rev. *D
7
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 6. Drive Modes
In
In
VDD
VDD
In
Pin
Out
Out
Pin
In
Out
Out
Pin
~5 k
~5k
Pin
Analog
Analog
Analog
1 . High-Impedance
Analog
2 . High-Impedance
Digital
3 . Resistive Pull Up
Analog
4 . Resistive Pull Down
VDD
In
In
VDD
~5k
In
Out
Pin
Out
In
VDD
Out
Out
Pin
Pin
~5k
Pin
Analog
Analog
5 . Open Drain,
Drives Low
6 . Open Drain,
Drives High
Analog
7 . Strong Drive
Analog
8 . Resistive Pull Up
& Pull Down
Note 1: The resistor values for pull-up and pull-down drive modes, shown in Figure 6, are approximate values; see
the device datasheet for resistor value specifications. Use an external resistor if a higher accuracy is required. In this
case, the pin must be configured as Open Drain Drive High or Open Drain Drive Low.
Note 2: At all times, avoid the device VDD getting powered from an external voltage at the pin through ESD clamp
diodes. This can happen if the PSoC 4 or PSoC Analog Coprocessor device is not powered and an external voltage
is applied at the GPIO or when an external voltage at the GPIO is greater than the device VDD. This is, however, not
applicable to the Overvoltage-Tolerant (OVT) Pins as there are no clamp diodes.
www.cypress.com
Document No. 001-86439 Rev. *D
8
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.2
Pin Routing
3.2.1
Digital Routing
A pin can be routed to different digital peripherals, such as the universal digital block (UDB), serial communication
block (SCB), timer/counter/pulse-width modulator (TCPWM) block, LCD driver, CAN block, interrupt controller, and
the data register which is read/written by the CPU. Figure 7 shows the routing for an input pin and Figure 8 shows the
routing for an output pin.
As shown in Figure 7 and Figure 8, peripherals are connected to the pins using the high-speed I/O matrix (HSIOM). It
multiplexes the signals from different peripherals to connect to a particular pin.
In PSoC, there are two routing possibilities: dedicated I/O routed through the HSIOM, and flexible routing using digital
system interconnect (DSI). DSI usage is not limited to routing the peripheral inputs and outputs to pins; it is also used
to route signals between digital resources. The Port Adapter connects the HSIOM and the DSI. It also provides
hardware to synchronize pin input and output signals.
Figure 7. Digital Pin Input Path
CAN(3)
SCB
HSIOM
From Input
Buffer
High
Speed
IO
Matrix
TCPWM
Port
Adapter(1)
DSI(1)
GPIO Edge
Detect
UDB(2)
Interrupt
Controller
CPU
(Pin State Reg)
1. not applicable to PSoC 4000, PSoC 4000S, PSoC 4100S, PSoC 4Axx
2. not applicable to PSoC 4000, PSoC 4000S, PSoC 4Axx, PSoC 4100, PSoC
4100S, PSoC 41xx-BL or PSoC 4100M
3. only available in PSoC 4200M and PSoC 4200L
2
SCB (I C, UART, and SPI) and TCPWM have dedicated routes to some I/Os. The flexible routing option is available
for UDB inputs and outputs, generating interrupts from the pins, and even for TCPWM. The LCD driver is present in
all I/Os of the PSoC parts (except PSoC 4000), with any I/O acting as a segment or a common driver for the LCD.
The GPIO Edge Detect block enables pin interrupts on rising-edge, falling-edge, and both edges. See the GPIO
Interrupt section for details.
www.cypress.com
Document No. 001-86439 Rev. *D
9
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 8. Digital Pin Output Path
CAN(4)
SCB
HSIOM
TCPWM
DSI(2)
Port
Adapter(2)
High
Speed
IO
Matrix
To Digital
Output
Driver
UDB(3)
LCD(1)
CPU
(Data Reg)
1. not applicable to PSoC 4000
2. not applicable to PSoC 4000, PSoC 4000S, PSoC 4100S, PSoC 4Axx
3. not applicable to PSoC 4000, PSoC 4000S, PSoC 4Axx, PSoC 4100, PSoC
4100S, PSoC 41xx-BL or PSoC 4100M
4. only available in PSoC 4200M and PSoC 4200L
Note: PSoC 4 has multiple ports with a maximum of 8 pins per port. For PSoC 4200L devices, Port 7 to Port 10 pins
do not have the port adapter; for other devices, Port 4 and higher ports do not have the port adapter. These ports
have the following restrictions:


Cannot be routed through the DSI; thus UDB-based digital signals cannot be routed to the pins of these ports

No input/output synchronization
Cannot be used for analog blocks such as SAR ADC, Opamp - Continuous Time Block mini (CTBm), and LowPower Comparator (applicable only to PSoC 4100 and PSoC 4200)
However, these ports are useful in the following ways:




As a GPIO controlled in firmware
Direct connection to TCPWM, SCB, or CAN
LCD and CapSense pins
Interrupts generation
Note: Pins of the PSoC device are shared for dedicated connections to different peripherals. To know the functions
possible at each pin, see the “Pinouts” section in the respective device datasheets.
www.cypress.com
Document No. 001-86439 Rev. *D
10
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.2.2
Analog Routing
GPIO pins configured in the High-Impedance Analog (HI-Z) mode are connected to the analog resources by direct
connections or through the analog switches and the analog mux (AMUX) bus, as Figure 9 to Figure 14 show.
Following are the key highlights of the analog routing in the PSoC 4000 parts shown in Figure 9:

All pins (except port 3) can connect to the AMUX buses, controlled by firmware. There are two buses:
AMUXBUS_A and AMUXBUS_B.



CapSense IDAC0 is connected to AMUXBUS_A, and IDAC1 is connected to AMUXBUS_B.
CapSense CMOD is connected to P0[4], and the shield tank capacitor is connected to P0[2].
Any pin can be used for the capacitive touch sensors (except Port 3) as the CapSense block connects to the
sensors using the AMUX bus.
Note: Place the CMOD capacitor close to the pin. See AN85951 - PSoC 4 CapSense Design Guide for layout
guidelines.
The following are the key highlights of analog routing in other PSoC 4 parts — see Figure 11 to Figure 15.

There are two AMUX buses. All pins have the capability to connect to AMUXBUS_A and AMUXBUS_B. AMUX
bus connection can be controlled by firmware or by using the DSI signal. Note that in the case of Port 4 and
higher port pins where the DSI connection is not available, AMUX can be connected only in firmware.

Direct connections are available for opamp inputs and outputs, which provide better performance due to lower
trace resistance and parasitic capacitance. Direct connections are also available for low-power comparator
(LPCOMP) inputs without switches.

There are dedicated pins for CapSense CMOD and the shield tank capacitor. See Figure 11 through Figure 15 to
know about the pins.


CapSense IDAC0 is connected to AMUXBUS_A; IDAC1 is connected to AMUXBUS_B.

AMUXBUS_A and AMUXBUS_B can be split using switches (marked in blue) as shown in figures 12 through 15.
This is useful if the AMUX buses are required for non-CapSense applications such as opamp/comparator input
and output routing along with CapSense in the system.

The SAR sequencer connects the SAR ADC input to:
Any pin can be used for the capacitive touch sensors as the CapSense block connects to the sensors using the
AMUX bus.




Port 2 in PSoC 4100, PSoC 4100S, PSoC 4200, PSoC 4100M, PSoC 4200M, and PSoC 4200L
Port 3 in PSoC 41xx-BL, PSoC 42xx-BL, and PSoC CY8C4Axx
CTBm outputs
Temperature sensor output
Multiplexing is done by controlling the switches shown in red in figures 11 through 15. Note that the SAR ADC can
also take the input from any pin using AMUXBUS without the sequencer.
Note: The opamp output is connected to a dedicated pin without any switches. If the connection to AMUX bus is
required, the AMUX switch associated with the dedicated pin is activated. This also allows other pins to act as opamp
output pins if the corresponding AMUX switches are activated.
Note: When the SAR ADC is operated with differential inputs in the sequencer mode, the positive input can only be
an even-numbered pin with the negative input as the adjacent odd-numbered pin. For example, in PSoC 4200, P2[0]
and P2[1] are pair pins with P2[0] as positive input and P2[1] as negative input. This is shown using rings
analog routing diagrams.
www.cypress.com
Document No. 001-86439 Rev. *D
in
11
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 9. PSoC 4000 Analog Routing Diagram
Port2
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P2[0]
Port1
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Port0
CapSense
Port3
P3[2]
P3[1]
P3[0]
AMUXBUS_B
source
shield
csh
cmod
CSIDAC1
AMUXBUS_A
CSD0
iout
Switch Control Legend
CSIDAC0
Firmware Controlled Switch
iout
Figure 10. PSoC 4000S Analog Routing Diagram
P0[0], P0[1], P0[2] and P0[3] are directly
connected to LPCOMP0 and LPCOMP1
inputs without switches.
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Port0
Switch Control Legend
Firmware Controlled Switch
AMUXBUS_A
AMUXBUS_B
LPCOMP0
P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]
CSIDAC1
iout
CSIDAC0
iout
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
CSD0
sense
shield
csh
shield_pad
LPCOMP1
vplus
vminus
P4[0]
P4[1]
P4[2]
P4[3]
cmod
vplus
vminus
Port4
Port3
Port2
www.cypress.com
Document No. 001-86439 Rev. *D
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
Port1
vref_ext
CapSense
12
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 11. PSoC 4200/PSoC 4100 Analog Routing Diagram
CTBm
SARMUX
Port1
Port2
P2[7]
P2[6]
P2[5]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P1[2] and P1[3] are directly connected to
OPAMP 0 and OPAMP 1 outputs, respectively,
without switches.
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[0], P0[1], P0[2] and P0[3] are directly
connected to LPCOMP0 and LPCOMP1
inputs without switches.
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
Port0
AMUXBUS_A
AMUXBUS_B
LPCOMP0
vplus
vminus
LPCOMP1
vplus
vminus
Port3
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
vminus
source
shield
csh
cmod
CSIDAC1
iout
Differential input
pairs
-
+
-
CSIDAC0
+
iout
OA1
OA0
TEMP0
10x
~
1x
1x
~
10x
Switch Control Legend
Firmware Only
Firmware + DSI
temp
Vssa_kelvin
SARADC0
Firmware + DSI +
SAR-Sequencer
vplus
vminus
ext_vref
Comp out to DSI
www.cypress.com
CAP
SENSE
P4[3]
P4[2]
P4[1]
P4[0]
Port4
sarbus0
sarbus1
vplus
CSD0
SAR
Comp out to DSI
Document No. 001-86439 Rev. *D
13
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 12. PSoC 4100S Analog Routing Diagram
Port0
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]
P1[0]
P1[1]
P1[2]
Port1
AMUXBUS_A
AMUXBUS_B
SARMUX
LPCOMP1
vplus
vminus
P4[3]
P4[2]
P4[1]
P4[0]
Port4
CTBm
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
Port3
Port2
LPCOMP0
vplus
vminus
P2[7]
P2[6]
P2[5]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
CSD0
TEMP0
source
shield
csh
temp
Vssa_kelvin
cmod
sarbus0
sarbus1
CSIDAC1
-
+
vminus
vplus
iout
-
CSIDAC0
+
iout
OA0
OA1
10x
~
1x
1x
~
10x
CAPSENSE
Differential input pairs
SAR
SARADC0
vplus
vminus
ext_vref
www.cypress.com
Comp out
Comp out
Document No. 001-86439 Rev. *D
Switch Control Legend
AMUX Splitter Firmware Only
Firmware Only
Firmware + SAR-Sequencer
14
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 13. PSoC 41xx-BL/PSoC 42xx-BL Analog Routing Diagram
P2[2] and P2[3] are
connected to OA0 and
OA1 OPAMP outputs
respectively
P1[2] and P1[3] are
connected to OA2 and
OA3 OPAMP outputs
respectively
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
CTBm
P2[7]
P2[6]
P2[5]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
CTBm
AMUXBUS_A
AMUXBUS_B
LPCOMP
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
LPCOMP1
vminus
vplus
LPCOMP0
vminus
vplus
P0[0], P0[1], P0[4] and
P0[5] are connected to
LPCOMP0 and
LPCOMP1 inputs
sarbus0
sarbus1
-
Comp out to DSI
iout
CSIDAC0
iout
CSIDAC1
CSD0
cmod
source
shield
csh
vplus
Differential input
pairs
CAPSENSE
temp
Vssa_kelvin
SARADC0
10x
1x
1x
Comp out to DSI
Comp out to DSI
TEMP0
SAR
+
OA2
~
10x
OA3
~
1x
1x
Comp out to DSI
-
+
OA0
~
10x
OA1
+
~
-
10x
-
+
vminus
Switch Control Legend
Firmware Only
Firmware + DSI
Firmware + DSI + SAR-Sequencer
AMUX Splitter - Firmware Only
ext_vref
AMUXBUS_B
AMUXBUS_A
P6[1]
P6[0]
Document No. 001-86439 Rev. *D
P5[1]
P5[0]
P4[1]
P4[0]
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
VREF
www.cypress.com
15
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 14. PSoC 4100M/PSoC 4200M Analog Routing Diagram
P1[2] and P1[3] are
connected to OA0 and
OA1 OPAMP outputs
respectively
P5[2] and P5[3] are
connected to OA2 and
OA3 OPAMP outputs
respectively
P5[5]
P5[4]
P5[3]
P5[2]
P5[1]
P5[0]
CTBm
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
CTBm
AMUXBUS_A
AMUXBUS_B
CAPSENSE
CSD1
csh
cmod
source
shield
CSIDAC3
iout
CSIDAC2
iout
LPCOMP
sarbus0
sarbus1
LPCOMP1
vminus
vplus
-
+
-
+
-
+
-
+
LPCOMP0
OA1
OA0
OA3
vminus
OA2
P0[0], P0[1], P0[2] and
P0[3] are connected to
LPCOMP0 and
LPCOMP1 inputs
~
10x
1x
~
1x
10x
10x
~
1x
~
1x
10x
vplus
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P7[2]
P7[1]
P7[0]
Comp out to DSI
Comp out to DSI
Comp out to DSI
Comp out to DSI
Differential input
pairs
CAPSENSE
TEMP0
Switch Control Legend
Firmware Only
CSD0
csh
cmod
source
shield
iout
vplus
CSIDAC0
iout
SARADC0
CSIDAC1
SAR
temp
Vssa_kelvin
Firmware + DSI
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
Firmware + DSI + SAR-Sequencer
AMUX Splitter - Firmware Only
vminus
ext_vref
Document No. 001-86439 Rev. *D
P3[7]
P3[6]
P3[5]
P3[4]
P3[3]
P3[2]
P3[1]
P3[0]
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
P2[7]
P2[6]
P2[5]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
www.cypress.com
16
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 15. PSoC 4200L Analog Routing Diagram
AMUXBUS_A
P1[7]
P1[6]
P1[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
~
sarbus1
sarbus0
10x
P5[7]
P5[6]
P5[5]
P5[4]
P5[3]
P5[2]
P5[1]
P5[0]
-
Comp out to DSI
1x
~
+
10x
CSD1
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
CAPSENSE
Differential input
pairs
Switch Control Legend
AMUX Splitter Firmware Only
Firmware + DSI + SAR-Sequencer
Firmware + DSI
Firmware Only
CSIDAC3
7-bit iout
P9[7]
P9[6]
P9[5]
P9[4]
P9[3]
P9[2]
P9[1]
P9[0]
iout 8-bit
P8[7]
P8[6]
P8[5]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P7[0]
P7[1]
P7[2]
P7[3]
P7[4]
P7[5]
P7[6]
P7[7]
LPCOMP
P0[2] and P0[3] are
connected to
LPCOMP1 inputs
LPCOMP1
vplus
vminus
vplus
CSD0
LPCOMP0
P0[0] and P0[1] are
connected
LPCOMP0 inputs
shield
source
cmod
csh
vminus
CSIDAC0
P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]
iout 7-bit
CAPSENSE
CSIDAC1
www.cypress.com
P5[2] and P5[3]
are connected to
OA2 and OA3
OPAMP outputs
respectively
CSIDAC2
8-bit iout
P11[0]
P11[1]
P11[2]
P11[3]
P11[4]
P11[5]
P11[6]
P11[7]
P4[0]
P4[1]
P4[2]
P4[3]
P4[4]
P4[5]
P4[6]
P4[7]
csh
cmod
source
shield
CTBm
OA2
1x
P12[0]
P12[1]
P6[0]
P6[1]
P6[2]
P6[3]
P6[4]
P6[5]
OA3
~
-
P10[0]
P10[1]
P10[2]
P10[3]
P10[4]
P10[5]
P10[6]
P10[7]
P1[2] and P1[3]
are connected to
OA0 and OA1
OPAMP outputs
respectively
+
Comp out to DSI
10x
CTBm
Comp out to DSI
1x
+
TEMP0
OA0
1x
-
Vssa_kelvin
temp
OA1
Comp out to DSI
SAR
vminus
vplus
SARADC0
~
-
VREF
P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]
10x
+
ext_vref
AMUXBUS_B
Document No. 001-86439 Rev. *D
17
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 16. PSoC CY8C4Axx Analog Routing Diagram
ARoute
CapSense
sarbus1
sarbus0
CTB1_Vout0
Differential input
pairs
Switch Control Legend
AMUX Splitter Firmware Only
Firmware + SAR-Sequencer
Firmware Only
CTB1_Vout1
Universal Analog Block
CTB1
External
reference
CTB0_Vout0
CTB0_Vout1
CTB0
Vref[3:0]
sar_aroute_vref
SARMUX
SAR ADC
sar_vminus
sar_vplus
sarbus0
sarbus1
Programmable Reference block
sar_vminus
sar_vplus
www.cypress.com
Document No. 001-86439 Rev. *D
18
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Note: The PSoC Creator IDE tool provides an analog routing diagram for a design similar to those illustrated in
Figure 9 through Figure 16. See the Analog tab in the .cydwr file of the project in PSoC Creator.
3.3
Startup and Low-Power Behavior
On reset/power-up, all GPIO pins start up in the high-impedance analog mode, that is, with the input buffer and
output driver disabled. These GPIO pins remain in this mode until the reset is released; then the initial operating
configuration of the associated registers of each GPIO pin is loaded during boot and takes effect at that time. During
run time, GPIOs can be configured by writing to the associated registers.
Note: In the PSoC 4000 parts (all parts except the 24-pin QFN), pin P1[6] is temporarily configured as XRES during
power-up until the device executes the start-up code. Do not pull this pin down during power-up as this keeps the
device in reset.
See KBA91258 – I/O System Restrictions in the PSoC 4000 Family for more information.
PSoC has up to four power modes. Table 2 shows the power mode availability in PSoC 4 families.
Table 2. Low Power Modes
Device
Sleep
Deep Sleep
Hibernate
Stop
PSoC 4000




PSoC 4000S




PSoC 4100/4200




PSoC 4100S




PSoC 4 BLE




PSoC 4 M




PSoC 4 L




PSoC Analog Coprocessor




In the Sleep mode, the GPIOs are active and can be actively driven by the peripherals; only the CPU is inactive in
2
this mode. In the Deep-Sleep mode, the pins driven by the Deep-Sleep peripherals such as I C, LCD driver, opamp,
2
and comparator are functional. The I C pins can wake the device up on an address match event. The segment LCD,
connected to the device pins, is periodically refreshed even in the Deep-Sleep mode.
The PSoC 4 parts (except PSoC 4000) have an additional feature that freezes the GPIOs in Deep-Sleep, Hibernate,
and Stop modes. Unfreezing of GPIOs also happens automatically when the low-power mode is exited. However,
note that the GPIOs driven by Deep-Sleep peripherals are active in Deep-Sleep mode and are not frozen.
In the case of Hibernate and Stop modes, wake-up happens with a device reset. This clears the GPIO configuration
and the pin state. To retain the pin state, use the CySysPmFreezeIo() and CySysPmUnfreezeIo() APIs. Note that
you do not need to call the CySysPmFreezeIo()function for Stop mode because it is automatically called when the
user invokes Stop mode using the CySysPmStop() API. However, you should call the CySysPmFreezeIo() API just
before the function call to enter the Hibernate mode. The GPIOs are unlocked with the call to API
CySysPmUnfreezeIo(). Call to this API is also required when the exit is made from the Stop mode. Note that the
Frozen pin states and configurations are not maintained on an external reset (XRES) event.
CySysPmFreezeIo() and CySysPmUnfreezeIo() are also useful in Deep-Sleep mode. An example of use of this
feature is shown in the Control Register Handling in Deep-Sleep section. UDB-based Components such as control
registers are not active and lose the data in Deep Sleep, Hibernate, and Stop modes. If the Control Register is driving
a pin, a glitch can occur when the PSoC device enters or exits these modes if the last state is a ‘1’. To avoid this
glitch, the GPIO should be frozen before entering a low-power mode.
For information on low-power modes, see AN86233 – PSoC 4 Low-Power Modes and Power Reduction Techniques.
www.cypress.com
Document No. 001-86439 Rev. *D
19
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.4
GPIO Interrupt
Figure 17 shows the signal path from HSIOM to the Interrupt Controller.
Figure 17. GPIO Interrupt Signal Routing
Interrupt Configuration
DSI
Port
Adapter(1)
From
HSIOM
GPIO Edge
Detect
Interrupt Source
Multiplexer
0
DSI(1)
1
Rising Edge
Detect (1)
1
To Interrupt
Controller
Fixed Function
0
Interrupt Select
(1) not applicable to PSoC 4000, PSoC 4000S, PSoC 4100S, PSoC 4Axx
At each of the 32 interrupt lines of the Interrupt Controller in the processor core, there is an Interrupt Source
Multiplexer. This multiplexer block selects the source of the interrupt and provides an option of rising-edge detection
or the direct connection to the Interrupt Controller. There are two sources of interrupts:
1.
Fixed-function source
2.
DSI source
The Interrupt Select line selects the DSI or the fixed-function source. The Interrupt Configuration selects the direct
connection or the rising-edge detection logic route to connect to the Interrupt Controller.
A fixed-function interrupt source has a fixed-interrupt vector; this means that the interrupt source has a dedicated
®
connection to one of the 32 interrupt lines of the Cortex M0 CPU. The interrupt source on this route is directly
connected to the Interrupt Controller. When the interrupt source is routed through the DSI, the vector selection is not
fixed. This routing also provides an option of rising-edge detection in addition to direct connection.
Note: The interrupt vector table is available in the Interrupts chapter of the Technical Reference Manual.
The use of Interrupt Source Multiplexer is not limited to the GPIO interrupts; it is also used for all other sources. To
®
know more about other interrupt source see the “Interrupt Sources” section of AN90799 - PSoC 4 Interrupts.
The GPIO interrupt, in addition to the resources present in the Interrupt Source Multiplexer, uses its own GPIO Edge
Detect block as Figure 17 shows.
The GPIO interrupt signal from the HSIOM is routed in the following ways:

Route 1: Fixed-function route through the GPIO Edge Detect block with the Interrupt Source Multiplexer
configured to direct connection

Route 2: DSI route through the GPIO Edge Detect block with the Interrupt Source Multiplexer configured to
rising-edge

Route 3: DSI route through the GPIO Edge Detect block with the Interrupt Source Multiplexer configured to direct
connection

Route 4: DSI route bypassing the GPIO Edge Detect block with the Interrupt Source Multiplexer configured to
rising-edge

Route 5: DSI route bypassing the GPIO Edge Detect block with the Interrupt Source Multiplexer configured to
direct connection
See Pins Component Interrupts to know how different routes are configured.
www.cypress.com
Document No. 001-86439 Rev. *D
20
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 18 shows the GPIO Edge Detect block. This block detects rising-edge, falling-edge, and both edges in the
incoming GPIO signal. Individual GPIO interrupt signals within a port are ORed together to generate a single interrupt
request. Thus, there is one interrupt vector for each port.
Figure 18. GPIO Edge Detect
Pin 0
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Edge Detector
Edge Detector
Edge Detector
Edge Detector
Edge Detector
To Interrupt
Source
Multiplexer
Edge Detector
Edge Detector
Edge Detector
As it is clear from Figure 18, when an interrupt is triggered, the interrupt source is required to be identified. PSoC 4
provides a status register to identify the interrupting pin. After reading the status register, it is important to clear it
whenever the GPIO Edge Detect logic is used to avoid the following:
1.
Single interrupt trigger and nonresponsive to further interrupts when the Interrupt Source Multiplexer is
configured to rising-edge. This scenario occurs if Route 2 is used.
2.
Repetitive interrupts for a single request when the Interrupt Source Multiplexer is configured to direct connection.
This scenario occurs if Route 1 or Route 3 is used.
When the GPIO interrupt takes the route without the GPIO Edge Detect block, there is no need to clear the interrupt.
However, when the rising-edge detection logic in the Interrupt Source Multiplexer is also bypassed, it results in a level
type interrupt (Route 5). In this case, the interrupt is triggered repeatedly as long as the pin signal is HIGH. Thus, it is
recommended to configure the Interrupt Source Multiplexer to a rising-edge interrupt when the GPIO Edge Detect
block is bypassed (Route 4).
Note: The GPIO interrupt logic continues to function in Sleep, Deep-Sleep, and Hibernate modes; thus, any pin can
be used as a wakeup source. A dedicated wakeup pin, P0[7], is available to wake the device from Stop mode in
PSoC 4200 / PSoC 4100, PSoC 4 M, and PSoC 4 L parts. For a PSoC 4 BLE device, the wakeup pin is P2[2].
3.4.1
Limitations in GPIO Interrupt
1. Port 4 and higher ports do not have a port adapter. Thus, pin interrupt via DSI routing is not possible for these
port pins.
2.
PSoC 4000 and PSoC 4100/PSoC 4200 have one interrupt vector for each port. PSoC 4 BLE does not have a
dedicated interrupt vector for the ports beyond Port 5, while PSoC 4 M does not have one for the ports beyond
Port 4. However, a common port interrupt vector is allocated, which gets triggered when any port interrupt
becomes active. See the Pins Component datasheet to understand how to use this common port interrupt.
An example project is shown in the Pin Interrupt section, which explains how to use the GPIO interrupt. To
understand interrupts in general, see the application note AN90799 – PSoC 4 Interrupts.
www.cypress.com
Document No. 001-86439 Rev. *D
21
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
4
Overvoltage-Tolerant (OVT) Pins
Pins P5[0] and P5[1] in PSoC 4 BLE, and Port 6 in PSoC 4 M are the OVT pins. For PSoC 4 L, Port 6 and Port 8
have OVT pins. These are similar to regular GPIOs with the following additional features:
1.
Overvoltage-tolerant: There are no ESD clamp diodes at the OVT pins. In addition, the GPIO-OVT cell has the
hardware to compare the I/O supply voltage (VDDIO) and the pin voltage. If the pin voltage exceeds the VDDIO
voltage, the output driver is disabled and the pin is tristated. This results in negligible current sink at the pin. Note
that during overvoltage conditions at the pin, the input buffer data will not be valid if the external source’s
specification of VOH and VOL do not match with the trip points of the input buffer.
2.
Provides better pull-down drive strength compared to a regular GPIO
3.
Serial Communication Block (SCB): When configured as I C and its lines routed to OVT pins, an SCB meets the
2
following I C specifications:
2
a)
Fast Mode Plus LOW-level output current (IOL) Specification
b)
Fast Mode and Fast Mode Plus hysteresis and minimum fall-time specifications
For more details on the I/O hardware, see the I/O System chapter of the Technical Reference Manual.
5
GPIO Pins in PSoC Creator
This section describes how to use PSoC Creator to configure and use GPIO pins.
5.1
Pins Component Symbols
The Pins Component is the recommended method for connecting internal PSoC resources to a physical pin. It allows
PSoC Creator to automatically place and route the signals within the PSoC device based on the chosen pin
configuration.
The standard Cypress Component Catalog contains four predefined GPIO configurations in the Ports and Pins class
of symbols: analog, digital bidirectional, digital input, and digital output. Drag one of these Components to the
schematic to add a pin to the project, as Figure 19 shows.
Figure 19. Pins Component Symbol Types in PSoC Creator
www.cypress.com
Document No. 001-86439 Rev. *D
22
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
5.2
Pins Component Customizer
Each Component in PSoC Creator comes with a customizer to configure the component. Figure 20 shows the Pin
Component Customizer, which is accessed by double-clicking the Component.
Figure 20. Pin Component Customizer
Table 3 describes some of the parameters in the Pin Component customizer. For details of all the parameters, see
the Pins Component datasheet.
Table 3. Pin Component Settings
Setting
General Tab > Type
Description
This setting configures the pin type. Possible options are:




Analog
Digital input with or without hardware (HW) connection
Digital output with or without HW connection and output enable
Bidirectional pin
When the digital input or output is configured with no HW connection, it means that the pin state is
controlled by the CPU. Note that more than one selection can be made at once. For example, a pin can
be configured for both analog and digital input at the same time.
General Tab > Drive
Mode
This setting configures the pin with one of the eight drive modes described in the GPIO Pin Basics
section. Figure 21 shows the drive mode options in the pin customizer.
General Tab > Initial
Drive State
The Initial drive state parameter sets the data register value. This value is reflected at the pin if it is
software-driven, given that the pin is set with an appropriate drive mode. If the pin is in the output mode
with HW connection enabled and Output enable disabled, the initial drive state acts as the enable
control. Setting the initial state to ‘1’ enables the pin, which is done as the default value by PSoC
Creator, as shown in Figure 21. If the pin is configured as input, initial drive state can still be useful. For
example, if resistive pull-up is required at the input pin, then the drive mode should be configured to
Resistive pull up with initial state as HIGH in order to turn on the pull-up path through the resistor.
Likewise, for resistive pull down, the initial drive state should be set to LOW to enable the pull-down
path.
Input Tab >
Threshold
CMOS and LVTTL input threshold setting is for an entire port. There are three options as Figure 22
shows. The “CMOS or LVTTL” option allows the PSoC Creator tool to select CMOS or LVTTL
depending on the threshold setting for other pins in the port.
Input Tab > Interrupt
This setting configures the GPIO Edge Detect block described in the GPIO Interrupt section. For more
details on this setting, refer to Pins Component Interrupts.
www.cypress.com
Document No. 001-86439 Rev. *D
23
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 21. Pin Drive Mode Setting and Initial Drive State
Figure 22. Pin Input Threshold Selection
www.cypress.com
Document No. 001-86439 Rev. *D
24
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
5.3
Pins Component Interrupts
The Interrupt parameter in the pin customizer configures the GPIO Edge Detect block described in the GPIO Interrupt
section.
Figure 23. Interrupt Configuration in PSoC Creator
The Pins Component symbol changes when interrupts are enabled, as Figure 24 shows.
Figure 24. Pins Component Symbol with Interrupts Enabled
Note that you can use only one Pin Component with each physical GPIO port if the interrupt is enabled. The reason
for this limitation is that all pin interrupts in a port are ORed together, as described in the GPIO Interrupt section.
Therefore, only one IRQ signal can be shown on the schematic per port. For example, consider two Pin Components
with interrupts enabled, as Figure 25 shows. These Components cannot be mapped to pins in the same physical port.
Figure 25. Two Pins Components with Interrupts Enabled
www.cypress.com
Document No. 001-86439 Rev. *D
25
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
PSoC Creator will not allow you to assign the two Components to the same port. The accepted method is to assign
multiple pins to the same component, as Figure 26 shows. This ensures that there is only one IRQ signal in the
schematic for that physical port. You can still assign each pin its own interrupt edge type. The only limitation is that
the pins must be contiguous in the same port. The interrupt source should be identified in the ISR; see the Pin
Interrupt section.
Figure 26. Multiple Pins in the Same Port with Interrupts Enabled
The IRQ of the Pin Component should be connected to the Interrupt Component. This routes the GPIO interrupt
signal to the interrupt controller. The Interrupt Component is in the Component catalog shown in Figure 27.
Figure 27. Interrupt Component in the Catalog
The Interrupt Component configures the Interrupt Source Multiplexer to either direct connection (shown as “level” in
the Interrupt Component customizer) or rising-edge. The GPIO interrupt architecture is described in the GPIO
Interrupt section along with the different routes available for the interrupt signal. Different routes are configured with
the help of the Pin Component and the Interrupt Component customizer settings summarized in Table 4.
www.cypress.com
Document No. 001-86439 Rev. *D
26
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Table 4. GPIO Interrupt Configurations
Schematic
www.cypress.com
Interrupt Setting in
Pin Component
Interrupt
Component
Setting
Route
Details
Rising-Edge or
Falling-Edge or Both
Edges
Level
Route 1
Interrupt on edges depending on the
Pin Component Setting. It uses a fixed
interrupt vector depending on the
selected port. In this configuration GPIO
interrupt status register should be
cleared; otherwise, interrupts are
triggered repeatedly on a single
interrupt request.
Rising-Edge or
Falling-Edge or Both
Edges
Rising-Edge
Route 2
Interrupt on edges depending on the
Pin Component Setting. In this
configuration GPIO interrupt should be
cleared; otherwise, interrupt is triggered
only once. Interrupt vector is not fixed.
Rising-Edge or
Falling-Edge or Both
Edges
Level
Route 3
This is similar to Route 1. However,
Route 3 is taken only if the interrupt
vector is forced on to a desired DSI
vector line. See the application note
AN90799 – PSoC 4 Interrupts to know
how to force the interrupt vector.
Disabled
Rising-Edge
Route 4
This configuration provides rising-edge
interrupt. In this case, there is no need
to clear the interrupt.
Disabled
Level
Route 5
This configuration provides Level
interrupt. Note that the interrupt is
triggered repeatedly as long as the pin
signal is high. In this case also, there is
no need to clear the interrupt.
Document No. 001-86439 Rev. *D
27
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
5.4
Manual Pin Assignments
You can use the Pins tab of the Design-Wide Resources (DWR) window to assign a Pins Component to a physical
pin. PSoC Creator automatically assigns pins if the user does not choose any but this may lead to a pin placement
that is more difficult to route on a PCB.
Figure 28 shows three assigned pins. The pins highlighted in dark blue are manually assigned and the pin highlighted
in light blue is automatically assigned. Selecting the Lock option prevents the pin from being reassigned by
PSoC Creator.
PSoC Creator makes it simple to reassign pins as needed, but you should consider pin selection before the boards
are designed.
Figure 28. Pin Assignment in DWR Window
Note: PSoC Creator can use the unused pin switches for routing the analog signals. This is configured using the
Unused Bonded I/O parameter in the System tab of the .cydwr file. See PSoC Creator Help for more details.
5.5
PSoC Creator APIs
Cypress provides a set of API functions that you can use to control GPIOs dynamically through firmware. The API for
the Pins Component enables access on both a Component-wide and per-pin basis. See the “API” section of the Pins
datasheet for more details.
Per-pin API functions, which are provided as part of cy_boot in the cypins.h file, are documented in the “Pins” section
of the PSoC Creator System Reference Guide (Help > Documentation > System Reference). You can use these
functions to control the configuration registers for each physical pin.
www.cypress.com
Document No. 001-86439 Rev. *D
28
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
5.6
Debug Logic on GPIO Pins
The PSoC 4 serial wire debug (SWD) pins are shared on the port pins. See the respective device datasheet for more
information on the debug port pins. The debug function, however, can be disabled and the pins can be used as
regular GPIOs by setting the “Debug Select” option to “GPIO” in the System tab of the DWR window as Figure 29
shows.
Figure 29. Debug Port Disabled
Note that disabling the debug interface does not affect the ability to program the device.
5.7
Add Multiple GPIO Pins as a Logical Port
In PSoC Creator, you can organize a group of as many as 36 pins into a logical port, which can then be referenced in
code by the port’s defined name. All the pins may be part of the same physical port, or they may form separate
physical ports. In the Pin Component customizer, set the Number of Pins required in a port. The pins appear in the
list below the field as Figure 30 shows. Each pin can be configured independently. Select [All Pins] to configure
every pin in the Component with the same settings.
Figure 30. One of Four Pins Configured as a Digital Input
www.cypress.com
Document No. 001-86439 Rev. *D
29
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
If the number of pins is configured to ‘4’ with three digital inputs and one digital output, the schematic symbol appears
as shown in Figure 31.
Figure 31. Pins Component in Port Configuration
There is an option to display the port with a bus instead of individual pin terminals. Select Display as Bus in the
Mapping tab of the pin configuration window to display the port as a bus, as Figure 32 shows. Note that all pins must
be of the same type to display as a bus.
Figure 32. Display as Bus Option
If the Number of Pins is configured to four digital outputs, the schematic symbol appears as shown in Figure 33.
Figure 33. Four Pins Displayed with Bus
www.cypress.com
Document No. 001-86439 Rev. *D
30
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
The pins with the bus terminal can be forced to map to adjacent pins by enabling Contiguous in the Mapping tab as
Figure 34 shows.
Figure 34. Contiguous Pin Placement Option
When you select Contiguous, PSoC Creator modifies the list of available pin options to match the port’s
configuration, as Figure 35 shows. When the Contiguous option is disabled, any pin can be selected. When the
Contiguous option is enabled, only adjacent pins can be selected as Figure 35 shows.
Figure 35. Pin Placement with Contiguous Disabled/Enabled
Contiguous Disabled
Contiguous Enabled
These features are described in more detail in the pin configuration window and the Pins Component datasheet.
www.cypress.com
Document No. 001-86439 Rev. *D
31
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
5.8
Represent Off-Chip Components
The Off-Chip Components Catalog provides a way to mix external and internal components on the same schematic,
as Figure 36 shows. This makes it possible to improve documentation and convey clearly how the internal schematic
fits in the entire design. Off-chip components serve the same function as comments in the code – they do not change
the functionality of the PSoC design but, instead, provide a clearer picture of the entire system.
Figure 36. Design with Off-Chip Components
External Connection
Internal Connection
Internal Connection
External Connection
In the design shown in Figure 36, PWM_1 and Opamp_1 are internal blocks of the device. These blocks are connected to the
external components using pins Pin_1 through Pin_4. Green and orange wires are the internal connections (green for digital
signals and orange for analog signals); whereas blue wires and components are external to the device. To make the
connections with the external components in the schematic, enable the “External Terminal” parameter in the Pin Component
customizer as Figure 37 shows. This brings out an additional terminal on the schematic as Figure 38 shows.
Figure 37. Enabling External Terminal
www.cypress.com
Document No. 001-86439 Rev. *D
32
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 38. Pin Component with Internal and External Terminal
External Terminal
Internal Terminal
The components, to connect to the external terminals on the schematic, are available in the Off-Chip tab in the
Components Catalog as Figure 39 shows.
Figure 39. Off-Chip Components Catalog
The components in this catalog cover those that are most likely to be connected to the pins of a PSoC device on the
board. These components consist of resistors, capacitors, transistors, inductors, switches, and others. Drag the
component and place it on the schematic as it is done in the case of internal components.
www.cypress.com
Document No. 001-86439 Rev. *D
33
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6
GPIO Tips and Tricks
This section provides practical examples of how to use GPIO pins. All these examples are included in the PSoC
Creator project provided with this application note.
Table 5. PSoC Creator Projects
#
Section
Project
PPSoC 4000,
4000S, 4100S,
CY8C4Axx
PSoC
41x7_BLE,
4100, 4100M
PSoC 4200,
4200M, 4200L,
42x7-BLE
1
Toggle an LED
Project01_ToggleLED



2
Read an Input and Write to an Output
Project02_ReadingPin



3
Drive an Output from a Digital Logic Gate
Project03_HWDrive
4
Using a Bidirectional Pin
Project04_BidirectionalPin


5
Set the GPIO Input/Output Synchronization
Project05_GPIOSynchronization


6
Toggle GPIOs Faster with Data Registers
Project06_FastGPIOUpdate


7
Configure GPIO Output Enable Logic
Project07_OutputEnable
8
Pin Interrupt
Project08_PinInterrupt



9
Configure GPIO Interrupt Settings with
Firmware
Project09_GPIOIntConfig



10
Using Both Analog and Digital on a GPIO
Project10_GPIOAnalogDigital


11
Gang Pins for More Drive/Sink Current
Project11_GangingPins

12
Control Register Handling in Deep-Sleep
Project12_ControlRegInDeepSleep




The Cypress development kits, listed in Appendix B: PSoC 4 Development Boards, can be used for testing these
projects.
www.cypress.com
Document No. 001-86439 Rev. *D
34
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.1
Toggle an LED
The simplest use of a GPIO is to set the output of a pin HIGH or LOW in firmware. This example demonstrates how
to set the output to toggle an LED using the Pins Component API.
1.
Place a Digital Output Pin Component in the project schematic.
2.
Name the Component “Pin_LED” and disable the hardware connection as Figure 40 shows.
Figure 40. Pin_LED Configuration
3.
Enable the external terminal to connect to the external components on the schematic.
4.
Assign it to a physical pin (this example uses P1[6]) in the Pins tab of the DWR window).
5.
Connect the physical pin to an LED. Note that the LED and resistor ‘R’ are off-chip components. The Top Design
schematic is shown in Figure 41.
www.cypress.com
Document No. 001-86439 Rev. *D
35
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 41. Toggle an LED Example Schematic
In main.c, use the Component API to set the output as follows:
for(;;)
{
/* Set LED output to logic HIGH */
Pin_LED_Write(1u);
/* Delay of 500 ms */
CyDelay(500u);
/* Set LED output state to logic LOW */
Pin_LED_Write(0u);
/* Delay of 500 ms */
CyDelay(500u);
}
6.
Build the project and program the PSoC 4 device.
The result is an LED blinking at a frequency of 1 Hz.
6.2
Read an Input and Write to an Output
This example demonstrates how to read from and write to a GPIO pin with the Component APIs. The output pin
drives the inverse of the input pin state.
1.
Place two pins in the project schematic—one Digital Input Pin and one Digital Output Pin with hardware
connection disabled—as Figure 42 shows.
Figure 42. Input and Output Example Schematic
2.
Assign the pins for Pin_Input and Pin_Output in the .cydwr window.
www.cypress.com
Document No. 001-86439 Rev. *D
36
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.
Use the Component APIs to set the state of Pin_Output based on Pin_Input as follows:
for(;;)
{
/* Set the output pin with an inverted value of input pin */
Pin_Output_Write(~Pin_Input_Read());
}
4.
Build the project and program the PSoC 4 device.
You can test this project by feeding a square wave from a signal generator to Pin_Input. The signal at Pin_Output will
be an inverted form of the signal at Pin_Input.
6.3
Drive an Output from a Digital Logic Gate
The previous example showed the use of the processor core to read a pin and set another pin with an opposite of the
read value. This example demonstrates the same task but with the use of configurable digital resources known as
Universal Digital Blocks (UDBs). In this example, an input pin signal is routed to a NOT gate and the output of the
NOT gate is routed to another pin. Follow these steps to create the project:
1.
Place two pins in the project schematic—one Digital Input Pin and one Digital Output Pin with hardware
connection enabled—as Figure 43 shows.
Figure 43. Input and Output Pins with HW Connection Enabled
2.
Place a NOT gate and connect to the pins as Figure 44 shows.
Figure 44. NOT Gate Connection
3.
Assign the pins for Pin_Input and Pin_Output in the .cydwr window.
4.
This project does not require any code. Build the project and program the PSoC 4 device.
Similar to the previous project, you can test this project by feeding a square wave from a signal generator to
Pin_Input. The signal at Pin_Output will be an inverted form of the signal at Pin_Input.
www.cypress.com
Document No. 001-86439 Rev. *D
37
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.4
Using a Bidirectional Pin
This example demonstrates the use of a pin in the bidirectional mode, that is, with both digital input and digital output
active. PSoC Creator provides a Pin Component in bidirectional configuration - “Digital Bidirectional Pin”.
2
This Pin Component, however, shows a single terminal for both input and output. Its use is limited to the I C SDA and
SCL lines. In many applications, it is useful to have two terminals – one for input and one for output. This can be done
by enabling both the Digital Input and Digital Output options in the Pin Component customizer. An example is shown
for configuring such a pin, where a switch is connected at the input side to pull the pin to logic LOW. This pin is
configured to resistive pull-up with logic ‘1’ driven continuously. To check the bidirectional pin status, the pin signal is
routed to another pin. Follow the steps below to create the project:
1.
Place a Digital Input Pin on the schematic.
2.
Enable Digital Output with Drive mode as Resistive pull up, as shown in Figure 45.
Figure 45. Pin_Bidirectional Configuration
Ensure that the Component looks like Figure 46 on the schematic.
Figure 46. Pin_Bidirectional on the Schematic
www.cypress.com
Document No. 001-86439 Rev. *D
38
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.
Connect a logic HIGH to drive the pin with resistive pull-up continuously as shown in Figure 47.
Figure 47. Logic HIGH to Pin_Bidirectional
4.
Now, the pin status is seen using another pin (Pin_Status) connected at the input side. Place a Digital Output Pin
and connect at the input buffer side of the Pin_Bidirectional as shown in Figure 48.
Figure 48. Pin_Status Connection to Pin_Bidirectional
With the external connections enabled, schematic looks like Figure 49.
Figure 49. Complete Schematic
5.
Assign the pins in the .cydwr window.
6.
The project does not require any user code. Build the project and program the PSoC 4 device.
The LED connected to Pin_Status shows the input buffer state of Pin_Bidirectional. When the switch is not pressed,
logic ‘1’ drives Pin_Bidirectional with a resistive pull-up. This turns OFF the LED (as the LED is connected in active
LOW mode). When the switch is pressed, strong logic ‘0’ appears at Pin_Bidirectional. This turns ON the LED. Thus,
this project demonstrates two drivers on the same pin (Pin_Bidirectional) – one internal (logic 1), and other external
(switch) with an input.
www.cypress.com
Document No. 001-86439 Rev. *D
39
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.5
Set the GPIO Input/Output Synchronization
For digital input and output signals, the GPIO provides synchronization with an internal clock, HFCLK, or a digital
signal as a clock in the PSoC 4 parts (except PSoC 4000). In addition, it provides the configuration for clock enable
and synchronization logic reset. Port adapter logic is used for input and output synchronization, as Figure 50 and
Figure 51 show.
Figure 50. Input Synchronization in PSoC 4
Selected
Reset
To DSI
From
Input Pin
2
PACFGx
IN SYNC[1:0]
00: Transparent
01: Single Sync
10: Double Sync
11: Reserved
Selected
Sync Clock
As Figure 50 shows, the input synchronization circuit provides the options of transparent, single sync, and double
sync.
Figure 51. Output Synchronization in PSoC 4
Selected
Reset
From
DSI
To Pin
2
Selected
Sync Clock
PACFGx
OUT SYNC[1:0]
00: Transparent
01: Single Sync
10: Clock
11: Clock Inverted
The output synchronization circuit provides the options of transparent, single sync, clock, and clock inverted, as
shown in Figure 51. Clock and clock inverted route the sync clock to the output pin. These are set in the Pins
Component customizer, as Figure 52 shows.
www.cypress.com
Document No. 001-86439 Rev. *D
40
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
The synchronizer clock can be configured as HFCLK, an external signal (from DSI), or one of the pin signals. The
synchronizer block reset signal can be an external signal (from DSI) or one of the pin signals. These are configured in
the Pins Component customizer from the Clocks tab, as Figure 53 shows.
For more information on the parameters in the Clocking tab of the Pins Component customizer, see the Pins
Component datasheet.
Figure 52. Sync Mode Setting
Figure 53. Clock Setting
Pin signals are synchronized using a combination of the UDB port adapter and GPIO blocks. Also, the clock is
common for all the pins of a port for internal clock synchronization. For more information, see the PSoC 4
Architecture TRM.
Note: The signals at Port 4 and higher port pins cannot be synchronized because these ports do not have a UDB port
adapter. Therefore, these port pins should always be used in the Transparent mode to avoid an error during build.
The next two examples demonstrate how to set the input/output synchronization.
www.cypress.com
Document No. 001-86439 Rev. *D
41
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.5.1
G P I O I n p u t S yn c h r o n i z a t i o n
1. Place one Digital Input Pin, two Digital Output Pins, and one Clock Component in the project schematic.
Configure them per Table 6.
Table 6. Components Configuration
Component
Digital Input Pin
Name
Pin_Input_DoubleSync
Configuration
Drive Mode: Resistive Pull-Up
Sync Mode: Double-Sync
In Clock (for input sync): External
Digital Output Pin
Pin_Output_LFCLK_1
Output Mode: Transparent
Digital Output Pin
Pin_Output_Transparent_1
Output Mode: Transparent
Clock
LFCLK
Clock Type: Existing
Source: LFCLK
2.
Connect the pins and add the Off-Chip Components, as Figure 54 shows.
Figure 54. GPIO Input Synchronization Example Schematic
Note: Clocks in PSoC 4 cannot be directly connected to a pin terminal, except for SYSCLK and LFCLK. See the
"Clocking System" section of the PSoC 4 Architecture TRM for more information.
3.
Assign the pins, and connect the Pin_Input_DoubleSync pin to a switch connected to GND.
4.
Build the project and program the PSoC 4 device.
When the button connected to Pin_Input_DoubleSync is pressed, the signal waveforms occur as Figure 55 shows.
The Pin_Output_Transparent_1 pin becomes LOW at the second rising edge of LFCLK because the input is doublesynchronized with LFCLK.
www.cypress.com
Document No. 001-86439 Rev. *D
42
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 55. Input/Output Signal Waveforms
6.5.2
G P I O O u t p u t S yn c h r o n i z a t i o n
1. Place one digital input pin, three digital output pins, and one Clock Component in the project schematic, as
Figure 56 shows, and configure them per Table 7.
Figure 56. GPIO Output Synchronization Example Schematic
www.cypress.com
Document No. 001-86439 Rev. *D
43
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Table 7. Pins Configuration
Component
Digital Input Pin
Name
Configuration
Pin_Input_Transparent
Drive Mode: Resistive Pull-Up
Sync Mode: Transparent
Digital Output Pin
Pin_Output_LFCLK_2
Output Mode: Transparent
Digital Output Pin
Pin_Output_SingleSync
Output Mode: Single-Sync
Out Clock (for output sync): External
Digital Output Pin
Pin_Output_Transparent_2
Output Mode: Transparent
Clock
LFCLK
Clock Type: Existing
Source: LFCLK
2.
Connect the pins as Figure 56 shows.
3.
Assign the pins, and connect the Pin_Input_Transparent to a switch connected to GND. Note that you cannot
select Port 4 and higher port pins for Pin_Output_SingleSync as they do not support synchronization.
4.
Build the project and program the PSoC 4 device.
Figure 57 shows the waveforms corresponding to a button press.
The Pin_Output_SingleSync pin becomes LOW at the next rising-edge of LFCLK because the output is synchronized
with LFCLK. The Pin_Output_Transparent_2 pin becomes LOW at the same time as the Input_Transparent pin
because there is no synchronization.
Figure 57. Input/Output Signal Waveform
www.cypress.com
Document No. 001-86439 Rev. *D
44
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.6
Toggle GPIOs Faster with Data Registers
The Component API is the easiest way to control GPIO pins; however, it is not the fastest way.
Take an example of writing logic ‘1’ to Pin_1 mapped to pin P5[2]. Here is the API function call:
Pin_1_Write(1);
The equivalent assembly code can be seen in the listing file (main.lst) in the Results tab of the project workspace.
mov
r0, #1
;load the value in r0
bl Pin_1_Write
;call Pin_1_Write
The assembly code of the Component API of the Pin_1_Write function can also be seen in the listing fileldr
r3, .L2
;load the address of Pin_1_DR into r3
ldr
r1, [r3]
;load the value of Pin_1_DR into r1
mov
r2, #251
;load 251 into r2 (value depends on location of pin
;in 8 bit wide port, in this case, Pin_1 is on port P5[2])
and r2, r1
;AND the values of r2 and r1 and load result back in r2
lsl
r0, r0, #2
;left shift r0 by two bits and load the result back in
;r0(this instruction is not present for the pin on LSB)
mov
r1, #4
;load value of 4 into r1 (depends on the location of
;pin in 8 bit wide port)
and
r0, r1
;and the value of r0(contains "value")and r1 and load
;the result in r0
orr
r0, r2
;r0
;or the value of r0 with r2 and load the result back in
str
r0, [r3]
;store the result back in Pin_1_DR
bx
lr
;return to calling function
This code takes 20 CPU cycles to write logic ‘1’ to Pin_1.
Alternatively, you can use the register definitions and masks in the <pin_name>.h file that is created for each Pins
Component to update the pins quickly.
The following statement sets logic ‘1’ at Pin_1 mapped to P5[2]. Pin_1_DR is the data register of Pin_1.
Pin_1_DR |= Pin_1_MASK
In the listing file (main.lst), the above instruction translates into an assembly code as follows:
www.cypress.com
Document No. 001-86439 Rev. *D
45
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
ldr
r3, .L3
;load the address of Pin_1_DR into r3
ldr
r1, [r3]
;load value of Pin_1_DR into r1
mov
r2, #4
;move value of 4 (Pin_1_MASK) into r2
orr
r2, r1
;Set the bit in Pin_1_DR
strb
r2, [r3]
;Store it back into Pin_1_DR
This code takes eight cycles as against 20 cycles used by the Component API.
The Component API had firmware overhead for the following actions, which are not required in direct register writes:



Function call
Checking the function argument to set the pin to logic ‘1’ or logic ‘0’
Return from the function
To set, reset, and read the pin using direct register writes, the following macros are provided in PSoC Creator:
Macro
Description
CY_SYS_PINS_SET_PIN(portDR, pin)
Sets the output value for the pin to logic HIGH
portDR is the address of the port data register
pin is the pin number (0 to 7)
CY_SYS_PINS_CLEAR_PIN(portDR, pin)
Clears the output value for the pin to logic LOW
portDR is the address of the port data register
pin is the pin number (0 to 7)
CY_SYS_PINS_READ_PIN(portPS, pin)
Reads the pin value
portPS is the address of the port status register
pin is the pin number (0 to 7)
Refer to the System Reference Guide (available from the PSoC Creator Help Menu) for more details on these
macros.
Follow these instructions to create a PSoC Creator project that can be used to compare the performance of the API
function call and direct register write:
1.
Place two digital output pins, with hardware connection disabled, in the project schematic and name them
“Pin_Test” and “Pin_Index,” as Figure 58 shows.
Figure 58. Toggle GPIOs with Data Registers Example Schematic
2.
Assign the pins in the .cydwr window.
www.cypress.com
Document No. 001-86439 Rev. *D
46
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.
Add the following code to the main.c file. The code sets Pin_Index HIGH and toggles Pin_Test using the
Component API. It then sets Pin_Index LOW and toggles Pin_Test using the data register (DR).
for(;;)
{
/* Set IndexPin */
Pin_Index_Write(1);
/********************* API Call ********************/
/* Set TestPin */
Pin_Test_Write(1u);
/* Clear TestPin */
Pin_Test_Write(0u);
/* do it again */
Pin_Test_Write(1u);
Pin_Test_Write(0u);
/***************************************************/
/* Clear IndexPin */
Pin_Index_Write(0);
/************* Direct Register Writes **************/
/* Set TestPin */
CY_SYS_PINS_SET_PIN(Pin_Test__DR, Pin_Test_SHIFT);
/* Clear TestPin */
CY_SYS_PINS_CLEAR_PIN(Pin_Test__DR, Pin_Test_SHIFT);
/* do it again */
CY_SYS_PINS_SET_PIN(Pin_Test__DR, Pin_Test_SHIFT);
CY_SYS_PINS_CLEAR_PIN(Pin_Test__DR, Pin_Test_SHIFT);
/***************************************************/
}
Note Pin_Test__DR is the address of the data register, whereas Pin_Test_DR is the value of the data
register. See the Pin Component .h file in the Source Files folder of the project workspace (in this case, Pin_Test.h)
to know about the macro for the data register address.
The code that writes to the data register is also portable similar to the API call, so that if the pin assignment changes
during development, you do not have to change the code.
www.cypress.com
Document No. 001-86439 Rev. *D
47
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
4.
Observe the waveform of the two pins using an oscilloscope, as shown in Figure 59.
Figure 59. Output Signals Waveform
A
C
B
D
A. Pin_Test_Write(1u)
B. Pin_Test_Write(0u)
C. CY_SYS_PINS_SET_PIN(Pin_Test__DR, Pin_Test_SHIFT)
D. CY_SYS_PINS_CLEAR_PIN(Pin_Test__DR, Pin_Test_SHIFT)
Figure 59 shows that a pin can toggle faster by directly writing to the data register, as opposed to calling the API
functions.
To know about coding techniques to achieve time efficiency, see the application note, AN89610 – PSoC 4 and PSoC
5LP ARM Cortex Code Optimization.
6.7
Configure GPIO Output Enable Logic
This example demonstrates how to configure and use the output enable logic of a GPIO pin. This project is applicable
only for PSoC 4200, PSoC 42xx_BL, PSoC 4200M, and PSoC 4200L parts.
1.
Place two Digital Output Pins in the project schematic.
2.
Open the configuration dialog for each pin and select the Output Enable option, as Figure 60 shows.
Figure 60. Output Enable Selection
www.cypress.com
Document No. 001-86439 Rev. *D
48
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
3.
Place a Control Register in the schematic.
4.
Configure the Control Register for two outputs, as Figure 61 shows.
Figure 61. Control Register Configured With Two Outputs
5.
Add one Logic Low ‘0’ Component.
6.
Connect the Logic Low to the pins and add the Off-Chip Components for the LEDs, as Figure 62 shows.
Figure 62. Control Register Driving Pins' Output Enable
7.
8.
Assign the pins and connect the pins to LEDs.
Add the following code to the main.c file.
uint8 count;
for(;;)
{
for(count = 0u; count < 4u; count++)
{
/* Set Control_Reg Value */
Control_Reg_Write(count);
/* Delay for 500ms */
CyDelay(500u);
}
}
9. Build the project and program the PSoC 4 device.
The result is the output of the two pins gated by the state of Control_Reg, which causes the LEDs to “count” to 3.
www.cypress.com
Document No. 001-86439 Rev. *D
49
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.8
Pin Interrupt
This example demonstrates how to use an interrupt generated from two pins in the same port, using the Component
APIs. These two pins can use only one IRQ terminal. Thus, the interrupt source must be identified in the ISR.
1.
Place two pins in the project schematic: one Digital Input Pin named “Pin_Button” and one Digital Output Pin
named “Pin_LED”.
2.
Set Pin_Button’s number of pins to 2, Drive mode as Resistive Pull Up, and Interrupt as Falling-Edge. This
exposes the IRQ terminal.
3.
Connect the Interrupt Component to the irq terminal as shown in Figure 63.
Figure 63. Pin Interrupt Example Schematic
4.
Assign the pins in the .cywdr window.
5.
Use the Component APIs to set the state of the LED Pin based on Pin_Button. Copy the following main.c code:
#define LED_ON (0u)
#define LED_OFF (1u)
/* The flag to enter ISR_Button */
uint8 isrFlag = 0u;
/* The LED state */
uint8 ledState = LED_OFF;
/* ISR for ISR_Button */
CY_ISR(INT_ISR_Button)
{
/* Set the flag */
isrFlag = 1u;
/* Check which pin caused interrupt by reading interrupt status register */
if(Pin_Button_INTSTAT & (0x01u << Pin_Button_SHIFT))
{
/* Triggered by Pin_Button_0 */
ledState = LED_OFF;
}
else
www.cypress.com
Document No. 001-86439 Rev. *D
50
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
{
/* Triggered by Pin_Button_1 */
ledState = LED_ON;
}
/* Clear interrupt */
Pin_Button_ClearInterrupt();
}
int main()
{
/* Start Pin ISR */
isr_Button_StartEx(INT_ISR_Button);
/* Enable global interrupt */
CyGlobalIntEnable;
for(;;)
{
/* Check the flag */
if(0u != isrFlag)
{
/* Clear the flag */
isrFlag = 0u;
/* Drive the LED with ledState. Led State is updated in ISR */
Pin_LED_Write(ledState);
}
/* Delay 1ms */
CyDelay(1u);
}
}
In the main.c code, CY_ISR(INT_ISR_Button) is the interrupt service routine for the pin interrupt.
6.
Build the project and program the PSoC 4 device.
The result is that the LED turns OFF when you press the button connected to Pin_Button_0 and turns ON when you
press the button connected to Pin_Button_1, but not when you release the buttons. (Note that the switch bounce in
the buttons may cause several interrupts on a single button press; see AN60024 – Switch Debouncer and Glitch
Filter with PSoC 3, PSoC 4, and PSoC 5LP for details).
In the main.c code, Pin_Button_INTSTAT and Pin_Button_SHIFT are the functions and constant macros provided by
the Pins Component. These are used to check which pin caused an interrupt.
The function Pin_Button_ClearInterrupt() clears the interrupt status register.
For more information on interrupts and writing interrupt handlers, see AN90799 – PSoC 4 Interrupts.
www.cypress.com
Document No. 001-86439 Rev. *D
51
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.9
Configure GPIO Interrupt Settings with Firmware
The GPIO interrupt is configured dynamically by writing to the two bits of the Interrupt Configuration register.


For PSoC 4000: GPIO_PRTx_INTR_CFG[2y+1:2y]
For other PSoC 4 parts: PRTx_INTCFG[2y+1:2y]
where “x” corresponds to the port number and “y” corresponds to the pin number (see Table 8). You can change the
configuration at any time to enable or disable pin interrupts.
Table 8. GPIO Interrupt Types and Bit Settings
PRTx_INTCFG [2y+1:2y]
Edge Type
Description
0
Disable
Interrupts disabled
1
Rising-Edge
Trigger on rising edge
2
Falling-Edge
Trigger on falling edge
3
Both Edges
Trigger on either edge
In this example, Pin_Button is configured with a rising-edge interrupt. Once the interrupt occurs, it is configured as a
falling-edge interrupt. An LED is toggled whenever the interrupt is triggered.
1.
Place a Digital Input Pin and a Digital Output Pin in the project schematic. Add the Off-Chip Components for the
LED and button, as Figure 64 shows.
Figure 64. Example Schematic
2.
Assign the pins to Pin_Button and Pin_LED in the cydwr window.
3.
Configure Pin_Button as a resistive pull-up pin and connect it to a button.
4.
Configure Pin_LED as a strong drive pin and connect it to an external LED.
5.
Add the following code to the main.c file. Note that instead of using the device register name, this project uses
Pin_Button__INTCFG, provided by PSoC Creator (in the cyfitter.h file) for interrupt configuration. You do not
need to worry about the exact register name in the selected device. This helps to port the project to a different
PSoC 4 device without changing anything in the code.
#define INTERRUPT_MASK 0x03
#define RISING_EDGE 0x01
#define FALLING_EDGE 0x02
int main()
{
/* Variable to save temporary data */
uint32 regVal = 0x00u;
/* Flag to switch interrupt type */
uint8 edgeFlag = 0x00u;
www.cypress.com
Document No. 001-86439 Rev. *D
52
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
for(;;)
{
/* Get value of port interrupt configuration register */
regVal = CY_GET_REG32(Pin_Button__INTCFG);
/* Clear the configuration bits for the Pin_Button.
Pin_Button_SHIFT is multiplied by 2 as two bits of the interrupt
configuration register sets the configuration for one pin */
regVal &= ~(INTERRUPT_MASK << (Pin_Button_SHIFT * 2));
if(edgeFlag)
{
/* Set P0[7] to GPIO interrupt rising-edge trigger.
Pin_Button_SHIFT is multiplied by 2 as two bits of the
interrupt configuration register sets the configuration for
one pin */
CY_SET_REG32(Pin_Button__INTCFG, regVal | (RISING_EDGE <<
(Pin_Button_SHIFT * 2)));
}
else
{
/* Set P0[7] to GPIO interrupt falling-edge trigger.
Pin_Button_SHIFT is multiplied by 2 as two bits of the
interrupt configuration register sets the configuration for
one pin */
CY_SET_REG32(Pin_Button__INTCFG, regVal | (FALLING_EDGE <<
(Pin_Button_SHIFT * 2)));
}
/* Toggle edgeFlag */
edgeFlag ^= 0x01u;
/* Wait for Interrupt */
while(!(CY_GET_REG32(Pin_Button__INTSTAT) & (0x01u <<
Pin_Button_SHIFT))) {;}
/* Clear interrupt */
CY_SET_REG32(Pin_Button__INTSTAT, (0x01u << Pin_Button_SHIFT));
/* Toggle LED */
Pin_LED_Write(~Pin_LED_Read());
}
}
6.
Build the project and program the PSoC 4 device.
The LED toggles whenever the button is pressed or released. When the button is pressed, the falling-edge triggers
the interrupt, and when it is released, the rising-edge triggers the interrupt.
The PSoC 4 Architecture TRM contains more information about the GPIO interrupt, including block diagrams and
functional descriptions. Another good resource is the application note AN90799 – PSoC 4 Interrupts.
www.cypress.com
Document No. 001-86439 Rev. *D
53
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.10
Using Both Analog and Digital on a GPIO
This example demonstrates how to configure and use a pin for analog and digital functions. In this example, an
output pin is controlled alternately by an IDAC and the firmware. When controlled by firmware, the LED blinks. When
controlled by the IDAC, the LED gradually brightens.
This type of multiplexing is useful when you need analog and digital functionality from a single pin. It can also reduce
the number of GPIOs used in a design.
You can use a hardware connection instead of firmware to control the digital output. See the description at the end of
this section for the required modifications to the project.
To configure the pin signal source, the HSIOM_PORT_SELx register is updated. Like the previous example, this
project uses the register name as defined in the Pins Component for easy portability across the PSoC 4 device family.
Follow these steps to create the schematic and firmware:
1.
Place an Analog Pin and a Current DAC in the schematic.
2.
Assign the Pins Component to a physical pin (this example uses P0[2]).
3.
Configure the pin with both Analog and Digital Output settings, as Figure 65 shows.
4.
Set the IDAC’s Polarity as Negative (Sink), as Figure 66 shows. Connect the IDAC to the analog terminal, as
Figure 67 shows.
5.
Build the project to create the necessary APIs.
Figure 65. LED Pin Configured as both Analog and Digital
www.cypress.com
Document No. 001-86439 Rev. *D
54
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 66. IDAC Setting
Figure 67. PSoC Creator Schematic of Analog and Digital Switching Scheme
6.
Add the following code to the main.c file and build the project again. Program the device with the hex file
generated. Note that in this code, the macros defined in the Pins Component and Cyfitter.h are used.
#define HSIOM_SW_GPIO 0x00
#define HSIOM_AMUX_BUS_A 0x06
int main()
{
uint32 i = 0u;
uint32 regVal = 0x00u;
/* Disable Input Buffer */
Pin_LED_INP_DIS |= (0x01u << Pin_LED_SHIFT);
/* Start IDAC */
IDAC_Start();
for(;;)
{
/* Get the current value of HSIOM_PORT_SEL0 register */
regVal = CY_GET_REG32(Pin_LED__0__HSIOM);
regVal &= ~Pin_LED__0__HSIOM_MASK;
/* Set LED Pin as GPIO controlled by firmware */
regVal = CY_SET_REG32(Pin_LED__0__HSIOM, regVal |(HSIOM_SW_GPIO <<
Pin_LED__0__HSIOM_SHIFT));
www.cypress.com
Document No. 001-86439 Rev. *D
55
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
/* Set LED Pin to Strong Drive Mode */
Pin_LED_SetDriveMode(Pin_LED_DM_STRONG);
for(i= 0u; i < 5u; i++)
{
/* Toggle LED with 100-ms delay */
Pin_LED_Write(0u);
CyDelay(100u);
Pin_LED_Write(1u);
CyDelay(100u);
}
/* Get the current value of HSIOM_PORT_SEL0 register */
regVal = CY_GET_REG32(Pin_LED__0__HSIOM);
regVal &= ~Pin_LED__0__HSIOM_MASK;
/* Connect LED Pin to AMUXBUS-A */
CY_SET_REG32(Pin_LED__0__HSIOM, regVal | (HSIOM_AMUX_BUS_A <<
Pin_LED__0__HSIOM_SHIFT));
/* Set LED Pin to High Impedance-Analog Drive Mode */
Pin_LED_SetDriveMode(Pin_LED_DM_ALG_HIZ);
for(i = 0u; i < 0x7fu; i++)
{
/* Adjust LED brightness */
IDAC_SetValue(i);
/* Delay 20 ms */
CyDelay(20u);
}
}
}
The result is an output that alternates control by the firmware and IDAC.
You can easily modify this project to use a hardware connection for the digital output instead of the firmware control.
To do so, in step 3, enable the HW connection in the pin configuration window. You can then wire a digital resource
to the pin. To select this digital resource as the pin output, set the pin as a DSI-controlled GPIO or a pin-specific
digital resource connection, using the HSIOM_PORT_SEL register. See the PSoC 4 Architecture TRM for more
details.
www.cypress.com
Document No. 001-86439 Rev. *D
56
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.11
Gang Pins for More Drive/Sink Current
To increase the total source or sink capabilities of the circuit, GPIO pins can be ganged (shorted together). This
example demonstrates driving a PWM signal with four GPIO pins. Note that the project is applicable only for
PSoC 4200, PSoC 42xx_BL, PSoC 4200M, and PSoC 4200L parts.
1.
Place and configure a PWM (TCPWM mode) and a Clock Component in the schematic.
2.
Place a single Digital Output Pins Component.
3.
Connect the Components as Figure 68 shows.
Figure 68. PWM Driven to Single Pin
4.
Open the pins configuration dialog and set the number of pins accordingly, as Figure 69 shows. This example
uses four GPIO pins. Set the Output Mode to Single-Sync and Out Clock to External, as Figure 70 and Figure
71 show.
Note: Synchronize the output to avoid different output signal delays for the different pins.
Figure 69. Configure Multiple Pins in the Component
www.cypress.com
Document No. 001-86439 Rev. *D
57
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 70. Output Mode Setting
Figure 71. Out Clock Setting
5.
(Optional) Set the pin mapping to Contiguous for easier PCB routing, as Figure 72 shows.
www.cypress.com
Document No. 001-86439 Rev. *D
58
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 72. Enable Contiguous Mapping
6.
Assign the Pins Component to physical pins.
7.
Place a Sync Component and connect the signal source (PWM, in this example) to each of the pin terminals via
the Sync Component. Place another Clock Component and set its source to High Frequency Clock (HFCLK).
Connect the out_clk terminal of the Pin Component and the Clock terminal of the Sync Component to the HFCLK.
It is important to select a high-frequency synchronization clock to reduce the difference in pin signal delays. The Sync
Component is required to synchronize the signal crossing from one clock domain to another. In this case, the PWM
output is going to cross from Clock (1 kHz) domain to HFCLK.
Figure 73. PWM Driving Four Pins
8.
Build the project and program the PSoC 4 device.
The output of the PWM is driven on all four GPIOs. The pins can be shorted externally on the PCB and connected to
the external circuit as needed.
www.cypress.com
Document No. 001-86439 Rev. *D
59
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
6.12
Control Register Handling in Deep-Sleep
This example demonstrates freezing of GPIO pins to avoid glitches at the output while using the low-power modes.
As an example, consider a Control Register driving a pin. When the device enters the Deep-Sleep mode, all I/Os are
frozen without any user intervention. When the device wakes up, all the I/Os are automatically restored to their
original configuration. However, the Control Register loses its data in the Deep-Sleep mode. It needs to be restored
before the I/Os are unfrozen. Otherwise, there is a glitch at the output. PSoC 4 provides alternate control for the user
to freeze and unfreeze the GPIOs in the form of CySysPmFreezeIo() and CySysPmUnfreezeIo() APIs. Follow
these steps to create the PSoC Creator project. Note that this project is applicable only for PSoC 4200,
PSoC 42xx_BL, PSoC 4200M, and PSoC 4200L.
1.
Place one Digital Input Pin, two Digital Output Pins, a Clock, a Control Register, and an Interrupt Component in
the schematic.
2.
Configure the Components per Table 9. Connect the Components as Figure 74 shows.
Table 9. Component Configurations
Component
Digital Input Pin
Name
Pin_Button
Configuration
Drive Mode: Resistive Pull-Up
Interrupt: Rising-Edge
Digital Output Pin
Pin_Clock
Default Configuration
Digital Output Pin
Pin_CtrlReg
Default Configuration
Clock
SYSCLK
Source: SYSCLK
Interrupt
isr_Buttton
Default Configuration
Control Register
Ctrl_Reg
Output: 1
Initial value: 1
Figure 74. Avoiding Glitch While Exiting Deep-Sleep
3.
Add the following code to the main.c file.
/* Set FREEZE_IO to 0x01 to avoid glitch by enabling the GPIO freeze */
/* else set it to 0 */
#define FREEZE_IO 0x01
/* The flag to enter ISR */
uint8 isrFlag = 0u;
CY_ISR(ISR_Handle)
{
www.cypress.com
Document No. 001-86439 Rev. *D
60
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
/* Set the flag */
isrFlag = 1u;
/* Clear pin interrupt */
Pin_Button_ClearInterrupt();
}
int main()
{
/* This variable is used as backup for Control register value */
uint8 ctrlRegVal = 0u;
/* Clear the flag */
isrFlag = 0u;
/* Start the ISR */
isr_Button_StartEx(ISR_Handle);
CyGlobalIntEnable;
/* Set Control register output as high */
Ctrl_Reg_Write(1u);
for(;;)
{
/* If freeze flag is set */
if(0u != isrFlag)
{
/* Clear isr flag set in GPIO Interrupt Handler */
isrFlag = 0u;
/* Rewrite the value */
Ctrl_Reg_Write(ctrlRegVal);
#if(FREEZE_IO)
/* Unfreeze I/O */
CySysPmUnfreezeIo();
#endif
}
/* Delay 200us */
CyDelayUs(200u);
/* Store the value of Control register */
ctrlRegVal = Ctrl_Reg_Read();
#if(FREEZE_IO)
/* Freeze I/O */
CySysPmFreezeIo();
#endif
/* Enter Deep-Sleep mode */
CySysPmDeepSleep();
}
}
To disable the freeze option, set FREEZE_IO to ‘0’. Build and program the device. When the button is pressed and
released, the glitch can be seen on Pin_CtrlReg as Figure 75 shows. To enable the freeze option, set FREEZE_IO to
‘1’. Build and program the device. In this case, I/O is frozen and no glitch is observed, as Figure 76 shows.
www.cypress.com
Document No. 001-86439 Rev. *D
61
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Figure 75. Output Signal Waveform (No Freeze I/O)
Wakeup
Enter Deep-Sleep
SYSCLK
Pin_CtrlReg
Pin_Button
Figure 76. Output Signal Waveform (Freeze I/O)
www.cypress.com
Document No. 001-86439 Rev. *D
62
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
7
Related Application Notes
AN79953 – Getting Started with PSoC 4
AN211293 – Getting Started with PSoC Analog Coprocessor
AN86233 – PSoC 4 Low-Power Modes and Power Reduction Techniques
AN60024 – Switch Debouncer and Glitch Filter with PSoC 3, PSoC 4, and PSoC 5LP
AN72382 – Using PSoC 3 and PSoC 5LP GPIO Pins
AN90799 – PSoC 4 Interrupts
AN2094 – PSoC 1 Getting Started with GPIO
AN89610 - PSoC® 4 and PSoC 5LP ARM Cortex Code Optimization
8
Summary
This application note explains the basic use cases of the GPIO modes in PSoC 4 and PSoC Analog Coprocessor
using the Pin Component in PSoC Creator.
9
About the Authors
Name:
Charles Cheng
Title:
Application Engineer
Background:
Charles is an application engineer in the Cypress Semiconductor Programmable Systems Division
focused on PSoC applications.
Name:
Rajiv Badiger
Title:
Application Engineer Staff
Background:
Rajiv is an application engineer in the Cypress Semiconductor Programmable Systems Division
focused on PSoC applications.
www.cypress.com
Document No. 001-86439 Rev. *D
63
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
A
Appendix A: PSoC 4 and PSoC Analog Coprocessor GPIO Compared to
PSoC 1, PSoC 3, and PSoC 5LP GPIO
The PSoC 4 and PSoC Analog Coprocessor GPIO are different from that of PSoC 1, PSoC 3, and PSoC 5LP; see
Table 10 for details.
Table 10. PSoC 4 and PSoC Analog Coprocessor GPIO Versus PSoC 1, PSoC 3, and PSoC 5LP GPIO
GPIO Features
PSoC 1
PSoC 3
PSoC 4 / PSoC Analog Coprocessor
PSoC 5LP
CapSense
√
√
√
√
LCD segment drive
√
√
√*
√
Eight drive modes
√
√
√
√
POR state configuration
×
√
×
√
Separate port DR and PS
×
√
√
√
Input/output synchronization
×
Bus_clk
HFCLK, External*
Bus_clk
* Not available in PSoC 4000
B
Appendix B: PSoC 4 Development Boards
You can test the PSoC Creator projects provided with this application note on the following Cypress development
boards.
Device Family
Development Board
PSoC 4000
CY8CKIT-040 PSoC 4000 Pioneer Development Kit
PSoC 4000S / 4100S
CY8CKIT-041 PSOC® 4 S-Series Pioneer Kit
PSoC 4200 / PSoC 4100
CY8CKIT-042 PSoC 4 Pioneer Kit
PSoC 4 CY8CKIT-049 4xxx Prototyping Kits
PSoC 42x7_BL
CY8CKIT-042-BLE Bluetooth Low Energy (BLE) Pioneer Kit
PSoC 4200M
CY8CKIT-044 PSoC 4 M-Series Pioneer Kit
PSoC 4200L
CY8CKIT-046 PSoC® 4 L-Series Pioneer Kit
PSoC Analog Coprocessor
CY8CKIT-048 PSoC Analog Coprocessor Pioneer Kit
www.cypress.com
®
®
®
®
Document No. 001-86439 Rev. *D
64
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Document History
Document Title: AN86439 - PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Document Number: 001-86439
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
4288100
CLSC
03/27/2014
New application note
*A
4381956
RJVB
05/16/2014
Updated for PSoC 4000
*B
4739860
RJVB
07/02/2015
Updated for PSoC 4 BLE and PSoC 4 M-Series
Updated component customizer screenshots
Added information on latency in GPIO update
Added example projects
Added Appendix B – PSoC 4 Development Boards
Updated information on GPIO architecture
*C
5054810
ASRI
01/05/2016
Updated for PSoC 4 L-Series
Added Figure 15. PSoC 4200L Analog Routing Diagram
Added section 6.4 to introduce Bidirectional Pin
Added an example project “Project04_BidirectionanlPin”
Updated Table 5. PSoC Creator Projects
Updated the projects to PSoC Creator 3.3
*D
5185171
ARVI
03/22/2016
Updated for PSoC 4000S, PSoC 4100S and PSoC Analog Coprocessor
Added Figure 10. PSoC 4000S Analog Routing Diagram
Added Figure 12. PSoC 4100S Analog Routing Diagram
Added Figure 16. PSoC CY8C4Axx Analog Routing Diagram
Updated Table 5. PSoC Creator Projects
Updated Appendix B: PSoC 4 Development Boards
www.cypress.com
Document No. 001-86439 Rev. *D
65
PSoC® 4 and PSoC Analog Coprocessor – Using GPIO Pins
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
®
®
ARM Cortex Microcontrollers
cypress.com/arm
cypress.com/psoc
Automotive
cypress.com/automotive
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
cypress.com/clocks
Cypress Developer Community
Interface
cypress.com/interface
Lighting & Power Control
cypress.com/powerpsoc
Memory
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
cypress.com/usb
Wireless/RF
cypress.com/wireless
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2014-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including
Spansion LLC (“Cypress”). This document, including any software or firmware included or referenced in this document (“Software”), is owned by
Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such
laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with
Cypress governing the use of the Software, then Cypress hereby grants you under its copyright rights in the Software, a personal, non-exclusive,
nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and reproduce the Software solely for
use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end
users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a
personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of Cypress’s patents that are infringed by the
Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum extent that is necessary for you
to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application
or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test
the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or
authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, lifesupport devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous
substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended
Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the
device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and Company shall and hereby does release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify and hold
Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related
to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or
registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other
names and brands may be claimed as property of their respective owners.
www.cypress.com
Document No. 001-86439 Rev. *D
66
Similar pages