CY24271: Rambus® XDR™ Clock Generator Datasheet.pdf

CY24271
Rambus® XDR™ Clock Generator
Rambus® XDR™ Clock Generator
Features
■
Quad (open drain) differential output drivers
Meets Rambus Extended Data Rate (XDR™) clocking
requirements
■
Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
■
Spread Aware™
■
25 ps typical cycle-to-cycle jitter
❐ 135 dBc/Hz typical phase noise at 20 MHz offset
■
2.5 V operation
100 or 133 MHz differential clock input
■
28-pin TSSOP package
■
■
300–800 MHz high speed clock support
■
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
/B Y P A S S
EN
EN
R egA
CLK0
C LK 0B
EN
R egB
CLK1
B ypass
MUX
C LK 1B
EN
R egC
PLL
R E F C L K ,R E F C L K B
CLK2
C LK 2B
EN
R egD
CLK3
C LK 3B
SCL
Cypress Semiconductor Corporation
Document Number: 001-00411 Rev. *F
•
SDA
ID 0
198 Champion Court
ID 1
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 20, 2016
CY24271
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
PLL Multiplier ............................................................... 4
Device ID and SMBus Device Address ....................... 4
Modes of Operation ..................................................... 5
SMBus Protocol ........................................................... 6
Input Clock Signal ....................................................... 6
SMBus Data Byte Definitions ...................................... 6
Absolute Maximum Conditions ....................................... 8
DC Operating Conditions ................................................. 8
DC Electrical Specifications ............................................ 9
Thermal Resistance .......................................................... 9
AC Operating Conditions ............................................... 10
AC Electrical Specifications .......................................... 11
Test and Measurement Setup ........................................ 12
Document Number: 001-00411 Rev. *F
Signal Waveforms .......................................................... 13
Jitter ................................................................................. 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Drawing and Dimension ................................. 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC®Solutions ....................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 2 of 19
CY24271
Pinouts
Figure 1. 28-pin TSSOP pinout
VD DP
VSS P
ISET
VSS
REFC LK
VDD C
V SSC
SC L
S DA
EN
ID0
ID 1
/BY PASS
CY24271
R EFC LKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
V SS
CLK2
CLK2B
VSS
CLK3
CLK3B
VD D
Pin Definitions
28-pin TSSOP
Name
I/O
1
Pin No.
VDDP
PWR
2.5 V power supply for phased lock loop (PLL)
Description
2
VSSP
GND
Ground
3
ISET
I
4
VSS
GND
5
REFCLK
I
Reference clock input (connect to clock source)
6
REFCLKB
I
Complement of reference clock (connect to clock source)
7
VDDC
PWR
2.5 V power supply for core
8
VSSC
GND
Ground
9
SCL
I
SMBus clock (connect to smbus)
10
SDA
I
SMBus data (connect to smbus)
11
EN
I
Output Enable (CMOS signal)
12
ID0
I
Device ID (CMOS signal)
13
ID1
I
Device ID (CMOS signal)
14
/BYPASS
I
REFCLK bypassing PLL (CMOS signal)
15
VDD
PWR
Power supply for outputs
16
CLK3B
O
Complement clock output
17
CLK3
O
Clock output
18
VSS
GND
19
CLK2B
O
20
CLK2
O
21
VSS
GND
Ground
22
VDD
PWR
Power supply for outputs
23
CLK1B
O
Complement clock output
24
CLK1
O
25
VSS
GND
Set clock driver current (external resistor)
Ground
Ground
Complement clock output
Clock output
Clock output
Ground
Document Number: 001-00411 Rev. *F
Page 3 of 19
CY24271
Pin Definitions (continued)
28-pin TSSOP
Name
I/O
26
Pin No.
CLK0B
O
Complement clock output
Description
27
CLK0
O
Clock output
28
VDD
PWR
Power supply for outputs
Functional Overview
PLL Multiplier
Table 1 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Default multiplier at power up is 4.
Table 1. PLL Multiplier Selection
Register
Frequency Multiplier
Output Frequency (MHz)
REFCLK = 100 MHz[1], REFSEL = 0 REFCLK = 133 MHz[1], REFSEL = 1
MULT2
MULT1
MULT0
0
0
0
3
300
400
0
0
1
4
400[2]
533[3]
0
1
0
5
500
667
0
1
1
6
600
800
1
0
0
8
800
1067[3]
1
0
1
9/2
450
600
1
1
0
15/2
750
1000[3]
1
1
1
15/4
375
500
Device ID and SMBus Device Address
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation. Table 2 shows the addresses for four
CY24271 devices on the same SMBus.
Table 2. SMBus Device Addresses for CY24271
XCG
Device
0
1
2
3
Operation
8-bit SMBus Device Address Including Operation
Hex Address
Write
D8
Read
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
Five Most Significant Bits
1
1
0
1
ID1
ID0
0
0
0
1
1
0
1
1
1
WR# / RD
0
1
0
1
0
1
0
1
Notes
1. Output frequencies shown in Table 1 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
2. Default PLL multiplier at power up.
3. Contact the factory if operation at these frequencies is required.
Document Number: 001-00411 Rev. *F
Page 4 of 19
CY24271
Modes of Operation
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 3 shows selection from one to all four of the outputs, the
Outputs Disabled Mode (EN = low), and Bypass Mode
(EN = high, /BYPASS = low). There is an option reserved for
vendor test. Disabled outputs are set to High Z.
At power up, the SMBus registers default to the last entry in
Table 3. The value at RegTest is 0. The values at RegA, RegB,
RegC, and RegD are all ‘1’. Thus, all outputs are controlled by
the logic applied to EN and /or BYPASS.
Table 3. Modes of Operation for CY24271
EN
/BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B
CLK1/CLK1B
CLK2/CLK2B
CLK3/CLK3B
High Z
High Z
High Z
High Z
X
REFCLK/
REFCLKB[4]
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
0
0
High Z
High Z
High Z
High Z
0
0
1
High Z
High Z
High Z
CLK/CLKB
0
1
0
High Z
High Z
CLK/CLKB
High Z
0
0
1
1
High Z
High Z
CLK/CLKB
CLK/CLKB
0
1
0
0
High Z
CLK/CLKB
High Z
High Z
0
0
1
0
1
High Z
CLK/CLKB
High Z
CLK/CLKB
0
0
1
1
0
High Z
CLK/CLKB
CLK/CLKB
High Z
H
0
0
1
1
1
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
0
1
0
0
0
CLK/CLKB
High Z
High Z
High Z
H
H
0
1
0
0
1
CLK/CLKB
High Z
High Z
CLK/CLKB
H
H
0
1
0
1
0
CLK/CLKB
High Z
CLK/CLKB
High Z
H
H
0
1
0
1
1
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
H
H
0
1
1
0
0
CLK/CLKB
CLK/CLKB
High Z
High Z
H
H
0
1
1
0
1
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
H
H
0
1
1
1
0
CLK/CLKB
CLK/CLKB
CLK/CLKB
High Z
H
0[5]
1[5]
1[5]
1[5]
1[5]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
L
X
H
X
1
X
X
X
X
H
L
0
X
X
X
H
H
0
0
0
H
H
0
0
H
H
0
0
H
H
0
H
H
0
H
H
H
H
H
H
H
X
X
X
X
X
Reserved for Vendor Test
Notes
4. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
5. Default mode of operation is at power up.
Document Number: 001-00411 Rev. *F
Page 5 of 19
CY24271
SMBus Protocol
The CY24271 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to RAMBUS standard to support
1.8, 2.5, and 3.3 volt devices. Time-out detection and packet
error protocol SMBus features are not supported.
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions on page 8 and AC Operating
Conditions on page 10.
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2 on page 7, provide a
reference voltage VTH at the REFCLKB pin. This determines the
proper trip point of REFCLK. For the range of VTH specified in
DC Operating Conditions on page 8, the outputs also meet the
DC and AC Operating Conditions tables.
SMBus Data Byte Definitions
Three data bytes are defined for the CY24271. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in Table 4 on page 6, Table 5
on page 6, and Table 6 on page 7. The upper five bits are the
revision numbers of the device and the lower three bits are the
ID numbers assigned to the vendor by Rambus.
Table 4. Command Code 80h [6]
Bit
Register
POD
Type
7
Reserved
0
RW
Reserved (no internal function)
Description
6
MULT2
0
RW
PLL Multiplier Select
5
MULT1
0
RW
4
MULT0
1
RW
3
RegA
1
RW
Clock 0 Output Select
2
RegB
1
RW
Clock 1 Output Select
1
RegC
1
RW
Clock 2 Output Select
0
RegD
1
RW
Clock 3 Output Select
Table 5. Command Code 81h [6]
Bit
Register
POD
Type
Description
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
1
RW
Reserved (must be set to ‘1’ for proper operation)
2
REFSEL
0
RW
Reference Frequency Select (reference Table 1 on page 4)
1
Reserved
0
RW
Reserved (must be set to ‘0’ for proper operation)
0
RegTest
0
RW
Reserved (must be set to ‘0’ for proper operation)
Reserved (no internal function)
Note
6. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 1 on page 4 for PLL multipliers and Table 3 on page 5 for clock output selections.
Document Number: 001-00411 Rev. *F
Page 6 of 19
CY24271
Table 6. Command Code 82h [7]
Bit
Register
POD
7
Device
Revision
Number
?
RO
?
RO
?
RO
?
RO
?
RO
0
RO
1
1
RO
0
0
RO
6
5
4
3
2
Vendor ID
Type
Description
Contact factory for Device Revision Number information.
RAMBUS assigned Vendor ID Code
Figure 2. Differential and Single-Ended Clock Inputs
Supply Voltage
REFCLKB
V TH
Input
REFCLK
Input
REFCLK
XDR Clock Generator
Differential Input
XDR Clock Generator
Single-ended Input
Note
7. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 1 on page 4 for PLL multipliers and Table 3 on page 5 for clock output selections.
Document Number: 001-00411 Rev. *F
Page 7 of 19
CY24271
Absolute Maximum Conditions
Parameter
VDD
VDDC
VDDP
VIN
Description
Clock Buffer Supply Voltage
Core Supply Voltage
PLL Supply Voltage
Input Voltage (SCL and SDA)
Input Voltage
(REFCLK/REFCLKB)
Input Voltage
TS
TA
TJ
ESDHBM
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
ESD Protection (Human Body
Model)
Condition
Relative to VSS
Relative to VSS
Relative to VSS
Non-functional
Functional
Functional
MIL-STD-883, Method 3015
Min
–0.5
–0.5
–0.5
–0.5
–0.5
Max
4.6
4.6
4.6
4.6
VDD + 1.0
Unit
V
V
V
V
V
–0.5
–65
0
–
2000
VDD + 0.5
150
70
150
–
V
°C
°C
°C
V
DC Operating Conditions
Min
Max
Unit
VDDP
Parameter
Supply Voltage for PLL
Description
2.5 V ± 5%
Condition
2.375
2.625
V
VDDC
Supply Voltage for Core
2.5 V ± 5%
2.375
2.625
V
VDD
Supply Voltage for Clock Buffers 2.5 V ± 5%
2.375
2.625
V
VIHCLK
Input High Voltage,
REFCLK/REFCLKB
0.6
0.95
V
VILCLK
Input Low Voltage,
REFCLK/REFCLKB
–0.15
+0.15
V
VIXCLK[8]
Crossing Point Voltage,
REFCLK/REFCLKB
200
550
mV
VIXCLK[8]
Difference in Crossing Point
Voltage, REFCLK/REFCLKB
–
150
mV
VIH
Input Signal High Voltage at ID0,
ID1, EN, and /BYPASS
1.4
2.625
V
VIL
Input Signal Low Voltage at ID0,
ID1, EN, and /BYPASS
–0.15
0.8
V
VIH,SM
Input Signal High Voltage at SCL
and SDA[9]
1.4
3.465
V
VIL,SM
Input Signal Low Voltage at SCL
and SDA
–0.15
0.8
V
VTH[10]
Input Threshold Voltage for
single-ended REFCLK
0.35
0.5 × VDD
V
VIH,SE
Input Signal High Voltage for
single-ended REFCLK
VTH + 0.3
2.625
V
VIL,SE
Input Signal Low Voltage for
single-ended REFCLK
–0.15
VTH – 0.3
V
TA
Ambient Operating Temperature
0
70
°C
Notes
8. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
9. This range of SCL and SDA input high voltage enables the 3.3 V, 2.5 V, or 1.8 V SMBus voltages to use CY24271.
10. Single-ended operation guaranteed only when 0.8 < (VIH,SE – VTH)/(VTH – VIL,SE) < 1.2.
Document Number: 001-00411 Rev. *F
Page 8 of 19
CY24271
DC Electrical Specifications
Parameter
Description
Min
Typ
Max
Unit
0.9
1.0
1.1
V
300
325
350
mV
0.85
–
–
V
0.98
1.0
1.02
V
Power Supply Current at 2.625 V, fref = 100 MHz, and fout = 300 MHz
–
–
85
mA
Power Supply Current at 2.625 V, fref = 133 MHz, and fout = 667 MHz
–
–
125
mA
Power Supply Current at 2.625 V, fref = 133 MHz, and fout = 800 MHz
–
–
130
mA
6.8
7.0
7.2
45
–
–
mA
[12]
VOX[11]
VCOS[11]
Differential output crossing point voltage
VOL,ABS
Absolute output low voltage at CLK[3:0], CLK[3:0]B[14]
VISET
Reference voltage for swing controlled current, IREF
IDD[11]
IDD[11]
IDD[11]
IOL/IREF
Output voltage swing (peak-to-peak single-ended)
Ratio of output low current to reference
[13]
current[15]
VOL,ABS[16]
IOL,ABS
Minimum current at
VOL,SDA
SDA output low voltage at test condition of
SDA output low current = 4 mA
–
–
0.4
V
IOL,SDA
SDA output low voltage at test condition of SDA voltage = 0.8 V
6
–
–
mA
IOZ
Current during High Z per pin at CLK[3:0], CLK[3:0]B
–
–
10
A
ZOUT
Output dynamic impedance when clock output signal is at
VOL = 0.9 V [17]
1000
–
–

Thermal Resistance
Parameter [18]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
28-pin TSSOP Unit
78
°C/W
17
°C/W
Notes
11. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
12. VOX is measured on external divider network.
13. VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.
14. VOL_ABS is measured at the clock output pins of the package.
15. IREF is equal to VISET/RRC.
16. Minimum IOL,ABS is measured at the clock output pin with RRC = 148 ohms or less.
17. ZOUT is defined at the output pins as (0.94 V – 0.90 V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.
18. These parameters are guaranteed by design and are not tested.
Document Number: 001-00411 Rev. *F
Page 9 of 19
CY24271
AC Operating Conditions
The AC operating conditions follow.
Parameter [19]
tCYCLE,IN
Description
Condition
REFCLK, REFCLKB input cycle REFSEL = 0, /BYPASS = High
time
REFSEL = 1, /BYPASS = High
/BYPASS = Low
[20]
Min
Max
Unit
9
11
ns
7
8
ns
4
–
ns
–
185
ps
tJIT,IN(cc)
Input Cycle to Cycle Jitter
tDCIN[21]
Input Duty Cycle
Over 10,000 cycles
40%
60%
tCYCLE
tRIN / tFIN
Rise and Fall Times
Measured at 20%–80% of input voltage for
REFCLK and REFCLKB inputs
175
700
ps
tRIN / tFIN
Rise and Fall Times Difference
–
150
ps
Modulation Index for triangular
modulation
–
0.6
%
Modulation Index for
non-triangular modulation
–
0.5[23]
%
fMIN[22]
Input Frequency Modulation
30
33
kHz
tSR,IN
Input Slew Rate (measured at
20%–80% of input voltage) for
REFCLK
1
4
V/ns
CIN,REF
Capacitance at REFCLK inputs
–
7
pF
CIN,CMOS
Capacitance at CMOS inputs
–
10
pF
fSCL
SMBus clock frequency input in
SCL pin
DC
100
kHz
pMIN
[22]
Notes
19. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
20. Jitter measured at crossing points and is the absolute value of the worst case deviation.
21. Measured at crossing points.
22. If input modulation is used; input modulation is allowed but not required.
23. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Document Number: 001-00411 Rev. *F
Page 10 of 19
CY24271
AC Electrical Specifications
The AC Electrical specifications follow.
Parameter [24]
tCYCLE
tJIT(cc)
Description
[25]
Clock Cycle time
Typ
Max
Unit
1.25
–
3.34
ns
–
25
40
ps
Jitter over 1-6 clock cycles at 638–800 MHz
–
25
30
ps
Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz
(In addition, device must not exceed
L(f) = 10log[1+(50x106/f)2.4] –138 for f = 1 MHz to 100 MHz
except for the region near f = REFCLK/Q where Q is the value of the
internal reference divider.)
–
–135
–128
dBC/Hz
533 MHz and faster output
–
–
TBD
Cycle-to-cycle duty cycle error at 400–635 MHz
–
25
40
ps
Cycle-to-cycle duty cycle error at 636–800 MHz
–
25
30
ps
tSKEW
Drift in tSKEW when ambient temperature varies between 0 °C and
70 °C and supply voltage varies between 2.375 V and 2.625 V.[27]
–
–
15
ps
DC
Long term average output duty cycle
45%
50
55%
tCYCLE
tEER,SCC
PLL output phase error when tracking SSC
–100
–
100
ps
tCR,tCF
Output rise and fall times at 400–800 MHz (measured at 20%–80%
of output voltage)
120
–
300
ps
tCR,CF
Difference between output rise and fall times on the same pin of the
single device (20%–80%) of 400–800 MHz[28]
–
–
100
ps
L20
tJIT(hper,cc)
Jitter over 1-6 clock cycles at 400–635 MHz
[26]
Min
Notes
24. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
25. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 800 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
26. Output short term jitter spec is the absolute value of the worst case deviation.
27. tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. tSKEW is the change in tSKEW when the
operating temperature and supply voltage change.
28. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.
Document Number: 001-00411 Rev. *F
Page 11 of 19
CY24271
Test and Measurement Setup
Figure 3. Clock Outputs
V TS
Measurement
CLK
R 1 Point
R2
Swing Current
Control
Differential Driver
ISET
VT
Z CH
RT
R3
V TS
Measurement
R 1 Point
VT
CLKB
R2
Z CH
RT
R3
Table 7. Example External Resistor Values and Termination
Voltages for a 50  Channel
Table 7. Example External Resistor Values and Termination
Voltages for a 50  Channel
Parameter
Value
Unit
Parameter
Value
Unit
RT
49.9

R1
39.2

RRC
200

R2
66.5

VTS
2.5V
V
R3
93.1

VT
1.2V
V
Document Number: 001-00411 Rev. *F
Page 12 of 19
CY24271
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4. Both rise and fall times are defined between
the 20% and 80% points of the voltage swing, with the swing
defined as VH–VL.
Figure 5 shows the definition of the output crossing point. The
nominal crossing point between the complementary outputs is
defined as the 50% point of the DC voltage levels. There are two
crossing points defined: Vx+ at the rising edge of CLK and Vx–
at the falling edge of CLK. For some waveforms, both Vx+ and
Vx– are below Vx,nom (for example, if tCR is larger than tCF).
Figure 4. Input and Output Waveforms
VH
80%
V (t)
20%
VL
tF
tR
Figure 5. Crossing Point Voltage
CLK
Vx+
Vx.nom
Vx-
CLKB
Document Number: 001-00411 Rev. *F
Page 13 of 19
CY24271
Jitter
requirements apply rising edges of the CLK signal. Figure 7 on
page 14 shows the definition of cycle-to-cycle duty cycle error
(tDC,ERR). Cycle-to-cycle duty cycle is defined as the difference
between tPW+ (high times) of adjacent differential clock cycles.
Equal requirements apply to tPW-, low times of the differential
click cycles.
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms. Figure 6
on page 14 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle jitter
is the difference between cycle times of adjacent cycles. Equal
Figure 6. Cycle-to-cycle Jitter
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles
Figure 7. Cycle-to-cycle Duty-cycle Error
CLK
CLKB
tPW-(i)
tCYCLE,(i)
tPW+(i)
tPW-(i+1)
tPW+(i+1)
tCYCLE,(i+1)
tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)
Document Number: 001-00411 Rev. *F
Page 14 of 19
CY24271
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY24271ZXC
28-pin TSSOP
Commercial, 0 °C to 70 °C
CY24271ZXCT
28-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY 24721
Z
X
C
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range:
C = Commercial
Pb-free
Package Type:
Z = 28-pin TSSOP
Base Device Part Number
Company ID: CY = Cypress
Document Number: 001-00411 Rev. *F
Page 15 of 19
CY24271
Package Drawing and Dimension
Figure 8. 28-pin TSSOP (4.40 mm Body) Z28.173/ZZ28.173 Package Outline, 51-85120
51-85120 *D
Document Number: 001-00411 Rev. *F
Page 16 of 19
CY24271
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
ESD
Electrostatic Discharge
°C
degree Celsius
PLL
Phase Locked Loop
Hz
hertz
TSSOP
Thin Shrunk Small Outline Package
kHz
kilohertz
XDR
Extended Data Rate
MHz
megahertz
Document Number: 001-00411 Rev. *F
Symbol
Unit of Measure
µA
microampere
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 17 of 19
CY24271
Document History Page
Document Title: CY24271, Rambus® XDR™ Clock Generator
Document Number: 001-00411
Rev.
ECN No.
Issue Date
Orig. of
Change
**
378263
See ECN
RGL
*A
492065
See ECN
*B
1333483
See ECN
*C
3162845
02/04/2011
BASH
Added Ordering Code Definitions under Ordering Information.
Updated Package Drawing and Dimension.
Added Acronyms and Units of Measure.
Updated to new template.
*D
4292206
02/26/2014
CINM
Updated Package Drawing and Dimension:
spec 51-85120 – Changed revision from *B to *C.
Updated to new template.
Completing Sunset Review.
*E
4581659
11/27/2014
AJU
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Drawing and Dimension:
spec 51-85120 – Changed revision from *C to *D.
*F
5279278
05/20/2016
PSR
Added Thermal Resistance.
Updated to new template.
Document Number: 001-00411 Rev. *F
Description of Change
New data sheet.
KKVTMP Replaced VSSC with VSS in all instances across the document.
Replaced VSSB with VSSC in all instances across the document.
Replaced SCLK with SCL in all instances across the document.
Replaced SDATA with SDA in all instances across the document.
Replaced BYPASSB with /BYPASS in all instances across the document.
Replaced VDDO with VDD in all instances across the document.
Replaced VSSO with VSS in all instances across the document.
Replaced VSSG with VSS in all instances across the document.
Updated Pin Definitions.
FGA / SFV Updated DC Electrical Specifications:
Added values for IDD parameter.
Page 18 of 19
CY24271
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
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cypress.com/arm
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cypress.com/powerpsoc
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2005-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-00411 Rev. *F
Revised May 20, 2016
Spread Aware is a trademark of Cypress Semiconductor Corporation. Rambus is a registered trademark, and XDR is a trademark, of Rambus Inc.
Page 19 of 19
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