CY7C1461KV33, CY7C1463KV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture Datasheet.pdf

CY7C1461KV33
CY7C1463KV33
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM
with NoBL™ Architecture
36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■
Supports up to 133 MHz bus operations with zero wait states
❐ Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow through operation
■
Byte write capability
■
3.3 V and 2.5 V I/O power supply
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock Enable (CEN) pin to enable clock and suspend operation
■
Synchronous self timed writes
■
Asynchronous Output Enable
■
CY7C1461KV33,
CY7C1463KV33
available
JEDEC-standard Pb-free 100-pin TQFP packages
■
Three chip enables for simple depth expansion
■
Automatic power down feature available using ZZ mode or CE
deselect
■
Burst capability – linear or interleaved burst order
■
Low standby power
The
CY7C1461KV33/CY7C1463KV33
are
3.3 V,
1M × 36/2M × 18 Synchronous Flow-Through Burst SRAMs
designed specifically to support unlimited true back-to-back read
and write operations without the insertion of wait states. The
CY7C1461KV33/CY7C1463KV33 is equipped with the advanced
NoBL logic required to enable consecutive read and write
operations with data being transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
in
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description
133 MHz
Unit
6.5
ns
× 18
150
mA
× 36
170
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-66681 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 7, 2016
CY7C1461KV33
CY7C1463KV33
Logic Block Diagram – CY7C1461KV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
BW C
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BW D
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
DQP C
DQP D
E
E
READ LOGIC
SLEEP
CONTROL
Document Number: 001-66681 Rev. *G
Page 2 of 23
CY7C1461KV33
CY7C1463KV33
Logic Block Diagram – CY7C1463KV33
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BW A
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW B
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP A
DQP B
E
E
READ LOGIC
SLEEP
CONTROL
Document Number: 001-66681 Rev. *G
Page 3 of 23
CY7C1461KV33
CY7C1463KV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ................................. 9
Linear Burst Address Table ......................................... 9
ZZ Mode Electrical Characteristics .............................. 9
Truth Table ...................................................................... 10
Partial Truth Table for Read/Write ................................ 11
Partial Truth Table for Read/Write ................................ 11
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
Neutron Soft Error Immunity ......................................... 12
Electrical Characteristics ............................................... 12
Document Number: 001-66681 Rev. *G
Capacitance .................................................................... 14
Thermal Resistance ........................................................ 14
AC Test Loads and Waveforms ..................................... 14
Switching Characteristics .............................................. 15
Switching Waveforms .................................................... 16
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC®Solutions ....................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 4 of 23
CY7C1461KV33
CY7C1463KV33
Pin Configurations
A
40
41
42
43
44
45
46
47
48
49
50
NC/72M
A
A
A
A
A
A
A
A
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document Number: 001-66681 Rev. *G
81
A
82
A
83
A
84
ADV/LD
VSS
90
85
VDD
91
OE
CE3
92
86
BWA
93
CEN
BWB
94
WE
BWC
95
88
BWD
96
CLK
CE2
97
89
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1461KV33
A
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
Figure 1. 100-pin TQFP pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 5 of 23
CY7C1461KV33
CY7C1463KV33
Pin Configurations (continued)
A
42
43
44
45
46
47
48
49
50
A
A
A
A
A
A
A
A
41
NC/72M
40
37
A0
VSS
36
A1
VDD
35
A
39
34
A
NC/144M
33
A
38
32
NC/288M
31
Document Number: 001-66681 Rev. *G
81
A
82
A
83
A
84
85
ADV/LD
OE
86
CEN
90
WE
VSS
91
88
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
97
96
CE1
CE2
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1463KV33
A
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
Figure 2. 100-pin TQFP pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 6 of 23
CY7C1461KV33
CY7C1463KV33
Pin Definitions
Pin Name
A0, A1, A
I/O
Description
Input-Synchronous Address Inputs. Used to select one of the address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB, Input-Synchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
BWC, BWD
WE
Input-Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-Synchronous Advance or Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After deselecting, drive ADV/LD LOW
to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select or deselect the device.
CE2
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select or deselect the device.
CE3
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select or deselect the device.
OE
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected.
CEN
Input-Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ
Input-Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non time critical sleep condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs
I/O-Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D]
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
I/O-Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
Power Supply
Power Supply Inputs to the Core of the Device.
VDD
VDDQ
I/O Power Supply
VSS
Ground
NC
N/A
Power Supply for I/O Circuitry.
Ground for the Device.
No Connects. Not internally connected to the die.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
Document Number: 001-66681 Rev. *G
Page 7 of 23
CY7C1461KV33
CY7C1463KV33
Pin Definitions (continued)
Pin Name
I/O
Description
NC/576M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/1G
N/A
Not Connected to the Die. Can be tied to any voltage level.
Functional Overview
The CY7C1461KV33/CY7C1463KV33 are synchronous flow
through burst SRAMs designed specifically to eliminate wait
states during Write-Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the clock enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized
and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If CEN is
active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the write
enable (WE). BWX can be used to conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when these conditions are satisfied at
clock rise:
■
CEN is asserted LOW
■
CE1, CE2, and CE3 are ALL asserted active
■
The write enable input signal WE is deasserted HIGH
■
ADV/LD is asserted LOW
The address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW for the device to
drive out the requested data. On the subsequent clock, another
operation (Read/Write/Deselect) can be initiated. When the
SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Document Number: 001-66681 Rev. *G
Burst Read Accesses
The CY7C1461KV33/CY7C1463KV33 have an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four reads without reasserting the address inputs.
ADV/LD must be driven LOW to load a new address into the
SRAM, as described in Single Read Accesses. The sequence of
the burst counter is determined by the MODE input signal. A
LOW input on MODE selects a linear burst mode, a HIGH selects
an interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX (or
a subset for byte write operations, see Truth Table on page 10
for details) inputs is latched into the device and the write is
complete. Additional accesses (read/write/deselect) can be
initiated on this cycle.
The data written during the write operation is controlled by BWX
signals. The CY7C1461KV33/CY7C1463KV33 provide byte write
capability that is described in the truth table. Asserting the (WE)
with the selected byte write select input selectively writes to only
the desired bytes. Bytes not selected during a byte write
operation remains unaltered. A synchronous self timed write
mechanism is provided to simplify the write operations. Byte
write capability is included to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1461KV33/CY7C1463KV33 are common I/O
devices, data must not be driven into the device when the
outputs are active. The OE can be deasserted HIGH before
presenting data to the DQs and DQPX inputs. This tri-states the
output drivers. As a safety precaution, DQs and DQPX are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Page 8 of 23
CY7C1461KV33
CY7C1463KV33
Burst Write Accesses
The CY7C1461KV33/CY7C1463KV33 have an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in the Single Write Accesses section.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BWX inputs
must be driven in each cycle of the burst write, to write the correct
bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. When in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, and CE3,
must remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1: A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
75
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-66681 Rev. *G
Page 9 of 23
CY7C1461KV33
CY7C1463KV33
Truth Table
The truth table for CY7C1461KV33/CY7C1463KV33 follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
Read Cycle (Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Write Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/Write Abort (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
Write Abort (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle (Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Notes
1. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BWX, and WE. See truth table for read or write.
3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
4. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is
inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document Number: 001-66681 Rev. *G
Page 10 of 23
CY7C1461KV33
CY7C1463KV33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1461KV33 is as follows. [8, 9]
Function (CY7C1461KV33)
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Write – No Bytes Written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
L
L
H
H
H
Write Byte B – (DQB and DQPB)
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1463KV33 is as follows. [8, 9]
Function (CY7C1463KV33)
WE
BWb
BWa
Read
H
X
X
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Notes
8. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects
are asserted, see truth table for details.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
Document Number: 001-66681 Rev. *G
Page 11 of 23
CY7C1461KV33
CY7C1463KV33
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
Ambient
Temperature
Storage Temperature ............................... –65 C to +150 C
Commercial
0 °C to +70 °C
Ambient Temperature with
Power Applied ......................................... –55C to +125 C
Industrial
Supply Voltage on VDD Relative to GND .....–0.5 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
–40 °C to +85 °C
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+10%
VDD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ Max* Unit
LSBU
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
VDD
Latch Up Current .................................................. > 200 mA
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
Output HIGH voltage
VOL
Output LOW voltage
Max
Unit
3.135
3.6
V
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
GND  VI  VDDQ, Output Disabled
–5
5
A
voltage[10]
Input HIGH
VIL
Input LOW voltage[10]
Input current of ZZ
IOZ
–
Min
for 3.3 V I/O, IOL = 8.0 mA
VIH
IX
Test Conditions
Output leakage current
for 3.3 V I/O
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-66681 Rev. *G
Page 12 of 23
CY7C1461KV33
CY7C1463KV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
IDD
ISB1
ISB2
ISB3
ISB4
Description
VDD operating supply current
Test Conditions
Min
Max
Unit
mA
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
× 18
–
150
× 36
–
170
Automatic CE power down
current – TTL inputs
VDD = Max,
Device Deselected,
VIN  VIH or VIN  VIL,
f = fMAX,
Inputs Switching
7.5 ns cycle,
133 MHz
× 18
–
85
× 36
–
90
Automatic CE Power down
current – CMOS inputs
VDD = Max,
Device Deselected,
VIN  0.3 V or
VIN > VDD – 0.3 V,
f = 0,
Inputs Static
7.5 ns cycle,
133 MHz
× 18
–
75
Automatic CE power down
current – CMOS inputs
VDD = Max,
Device Deselected,
VIN  0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX,
Inputs Switching
7.5 ns cycle,
133 MHz
× 18
Automatic CE power down
current – TTL inputs
VDD = Max,
Device Deselected,
VIN  VDD – 0.3 V or
VIN  0.3 V,
f = 0,
Inputs Static
7.5 ns cycle,
133 MHz
× 18
–
75
× 36
–
80
Document Number: 001-66681 Rev. *G
× 36
mA
mA
80
–
× 36
85
mA
90
mA
Page 13 of 23
CY7C1461KV33
CY7C1463KV33
Capacitance
In the following table, the capacitance parameters are listed.
Parameter [12]
Description
100-pin TQFP Unit
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/output capacitance
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test With Still Air (0 m/s)
methods and procedures for
With Air Flow (1 m/s)
measuring thermal impedance,
per EIA/JESD51.
With Air Flow (3 m/s)
35.36
°C/W
31.30
°C/W
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter [12]
JA
Description
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
JB
Thermal resistance
(junction to board)
–
28.86
°C/W
7.52
°C/W
28.89
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317 
Z0 = 50 
VT = 1.5 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V I/O Test Load
2.5 V
OUTPUT
GND
R = 351 
VT = 1.25 V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
 1 ns
2 V/ns
(b)
(c)
R = 1667 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
Z0 = 50 
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
GND
R = 1538 
(b)
10%
90%
10%
90%
 1 ns
2 V/ns
(c)
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66681 Rev. *G
Page 14 of 23
CY7C1461KV33
CY7C1463KV33
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
tPOWER[15]
–
133 MHz
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock Cycle Time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data Output Valid After CLK Rise
–
6.5
ns
tDOH
Data Output Hold After CLK Rise
2.5
–
ns
2.5
–
ns
–
3.8
ns
–
3.0
ns
0
–
ns
–
3.0
ns
[16, 17, 18]
tCLZ
Clock to Low Z
tCHZ
Clock to High Z [16, 17, 18]
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
OE LOW to Output Low Z
[16, 17, 18]
OE HIGH to Output High Z
[16, 17, 18]
Setup Times
tAS
Address Setup Before CLK Rise
1.5
–
ns
tALS
ADV/LD Setup Before CLK Rise
1.5
–
ns
tWES
WE, BWX Setup Before CLK Rise
1.5
–
ns
tCENS
CEN Setup Before CLK Rise
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.5
–
ns
tAH
Address Hold After CLK Rise
0.5
–
ns
tALH
ADV/LD Hold After CLK Rise
0.5
–
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
–
ns
tCENH
CEN Hold After CLK Rise
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 3 on page 14 unless otherwise noted.
15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 14. Transition is measured ± 200 mV from steady-state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 001-66681 Rev. *G
Page 15 of 23
CY7C1461KV33
CY7C1463KV33
Switching Waveforms
Figure 4. Read/Write Waveforms [19, 20, 21]
1
2
3
t CY C
4
5
6
7
8
9
A5
A6
A7
10
CLK
t CENS
t CENH
t CES
t CEH
t CH
t CL
CEN
CE
ADV/LD
WE
BW X
A1
ADDRESS
t AS
A2
A4
A3
t CDV
t AH
t DOH
t CLZ
DQ
D(A1)
t DS
D(A2)
Q(A3)
D(A2+1)
t OEV
Q(A4+1)
Q(A4)
t OELZ
W RITE
D(A1)
W RITE
D(A2)
D(A5)
Q(A6)
D(A7)
W RITE
D(A7)
DESELECT
t OEHZ
t DH
OE
COM M AND
t CHZ
BURST
W RITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
t DOH
W RITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 001-66681 Rev. *G
Page 16 of 23
CY7C1461KV33
CY7C1463KV33
Switching Waveforms (continued)
Figure 5. NOP, STALL, and DESELECT Cycles [22, 23, 24]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A5
t CHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
t DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 001-66681 Rev. *G
Page 17 of 23
CY7C1461KV33
CY7C1463KV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or REA D Only
High-Z
DON’T CA RE
Notes
25. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-66681 Rev. *G
Page 18 of 23
CY7C1461KV33
CY7C1463KV33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed
(MHz)
133
Ordering Code
CY7C1461KV33-133AXC
Package
Diagram
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
CY7C1463KV33-133AXC
CY7C1461KV33-133AXI
Industrial
Ordering Code Definitions
CY
7
C
14XX
K V33 - XXX A
X
X
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type:
A = 100-pin TQFP
Speed Grade: XXX = 133 MHz
V33 = 3.3 V VDD
Process Technology: K  65 nm
Part Identifier: 14XX = 1461 or 1463
1461 = FT, 1 M × 36 (36-Mbit)
1463 = FT, 2 M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66681 Rev. *G
Page 19 of 23
CY7C1461KV33
CY7C1463KV33
Package Diagram
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
Document Number: 001-66681 Rev. *G
Page 20 of 23
CY7C1461KV33
CY7C1463KV33
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 3. Units of Measure
CE
Chip Enable
CEN
Clock Enable
°C
degree Celsius
CMOS
Complementary Metal Oxide Semiconductor
MHz
megahertz
I/O
Input/Output
µA
microampere
NoBL
No Bus Latency
mA
milliampere
OE
Output Enable
mm
millimeter
SRAM
Static Random Access Memory
ms
millisecond
TQFP
Thin Quad Flat Pack
ns
nanosecond
WE
Write Enable
Document Number: 001-66681 Rev. *G
Symbol
Unit of Measure
pF
picofarad
V
volt
W
watt
Page 21 of 23
CY7C1461KV33
CY7C1463KV33
Document History Page
Document Title: CY7C1461KV33/CY7C1463KV33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 001-66681
Rev.
ECN No.
Issue Date
Orig. of
Change
*E
4680529
04/09/2015
PRIT
*F
4757974
05/07/2015
DEVM
*G
5298825
06/07/2016
PRIT
Document Number: 001-66681 Rev. *G
Description of Change
Changed status from Preliminary to Final.
Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
Added Industrial Temperature Range related information in all instances across
the document.
Updated Neutron Soft Error Immunity:
Updated details in “Typ” and “Max” columns corresponding to LSBU parameter.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Page 22 of 23
CY7C1461KV33
CY7C1463KV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66681 Rev. *G
Revised June 7, 2016
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
Page 23 of 23
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