CY8C24894 ® Automotive PSoC Programmable System-on-Chip™ ■ Automotive Electronics Council (AEC) qualified ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Two 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Automotive temperature range: –40 °C to +85 °C ■ ■ ■ ■ ■ Additional system resources 2 ❐ I C™ slave, master, or multimaster operation up to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable LVD ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ■ Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full-featured in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128-KB trace memory Advanced peripherals (PSoC® blocks) ❐ Six rail-to-rail analog PSoC blocks provide: • Up to 14-bit analog-to-digital converters (ADCs) • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) • Programmable filters and comparators ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse-width modulators (PWMs) • Cyclic redundancy check (CRC) and pseudo-random sequence (PRS) modules • Full- or half-duplex UART • SPI master or slave • Connectable to all general purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks • Capacitive sensing application capability Flexible on-chip memory ❐ 16-KB flash program storage, 1000 erase/write cycles ❐ 1-KB SRAM data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash Programmable pin configurations ❐ 25-mA sink, 10-mA drive on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs ❐ Up to 47 analog inputs on GPIOs ❐ Two 30-mA analog outputs on GPIOs ❐ Configurable interrupt on all GPIOs Logic Block Diagram Port 5 Port 7 System Bus Features Port4 Global Digital Interconnect Port 3 Port 2 Port 0 Analog Drivers Port 1 Global Analog Interconnect PSoC CORE SRAM 1K SROM Flash16K CPU Core (M8C) Interrupt Controller Sleep and Watchdog Clock Sources (Includes IMO and ILO) DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital 2 Decimator Clocks MACs Type2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Precision, programmable clocking ❐ Internal ±4% 24/48 MHz oscillator ❐ Internal low-speed, low-power oscillator for watchdog and sleep functionality ❐ Optional external oscillator, up to 24 MHz Errata: For information on silicon errata, see “Errata” on page 46. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation Document Number: 001-53754 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 12, 2015 CY8C24894 Contents PSoC Functional Overview .............................................. 3 The PSoC Core ........................................................... 3 The Digital System ...................................................... 3 The Analog System ..................................................... 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 56-Pin Part Pinout (with XRES pin) ............................ 8 Registers ........................................................................... 9 Register Conventions .................................................. 9 Register Mapping Tables ............................................ 9 Register Map Bank 0 Table: User Space ................. 10 Register Map Bank 1 Table: Configuration Space ... 11 Electrical Specifications ................................................ 12 Absolute Maximum Ratings ....................................... 13 Operating Temperature ............................................. 13 Document Number: 001-53754 Rev. *H DC Electrical Characteristics ..................................... 14 AC Electrical Characteristics ..................................... 27 Packaging Information ................................................... 35 Thermal Impedances ................................................. 35 Solder Reflow Specifications ..................................... 35 Tape and Reel Information ........................................ 36 Development Tool Selection ......................................... 37 Software .................................................................... 37 Development Kits ...................................................... 37 Evaluation Tools ........................................................ 37 Device Programmers ................................................. 38 Accessories (Emulation and Programming) .............. 38 Ordering Information ...................................................... 39 Ordering Code Definitions ......................................... 39 Acronyms ........................................................................ 40 Reference Documents .................................................... 40 Document Conventions ................................................. 41 Units of Measure ....................................................... 41 Numeric Conventions ................................................ 41 Glossary .......................................................................... 41 Errata ............................................................................... 46 Part Numbers Affected .............................................. 46 CY8C24x94 Errata Summary .................................... 46 Document History Page ................................................. 50 Sales, Solutions, and Legal Information ...................... 52 Worldwide Sales and Design Support ....................... 52 Products .................................................................... 52 PSoC® Solutions ...................................................... 52 Cypress Developer Community ................................. 52 Technical Support ..................................................... 52 Page 2 of 52 CY8C24894 The PSoC family consists of many programmable system-on-chips with on-chip controller devices. All PSoC family devices are designed to replace traditional microcontroller units (MCUs), system ICs, and the numerous discrete components that surround them. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of industrial, consumer, and communication applications. The Digital System The digital system is composed of four digital PSoC blocks. Each block is an 8-bit resource used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Figure 1. Digital System Block Diagram Port 7 Port 1 Port 2 To System Bus Digital Clocks From Core Port 0 To Analog System DIGITAL SYSTEM Digital PSoC Block Array 8 8 The PSoC Core Row 0 DBB00 DBB01 DCB02 4 DCB03 4 GIE[7:0] The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIOs. The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four-MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming of real-time embedded events. Program execution is timed and protected using the included sleep timer and watchdog timer (WDT). Port 3 GIO[7:0] Global Digital Interconnect Row Output Configuration The PSoC architecture, as illustrated in the Logic Block Diagram on page 1, is comprised of four main areas: PSoc Core, digital system, analog system, and system resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x94 devices can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. Port 5 Port 4 This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. Row Input Configuration PSoC Functional Overview 8 8 GOE[7:0] GOO[7:0] Digital peripheral configurations include those listed below. ■ PWMs (8- to 32-bit) ■ PWMs with Dead band (8- to 24-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ Full- or half-duplex 8-bit UART with selectable parity The PSoC device incorporates flexible internal clock generators, including a 24-MHz internal main oscillator (IMO) accurate to ±4% over temperature and voltage. The 24-MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32-kHz internal low-speed oscillator (ILO) is provided for the sleep timer and WDT. The clocks, together with programmable clock dividers (as system resources), provide the flexibility to integrate almost any timing requirement into the PSoC device. ■ SPI master and slave ■ I2C master, slave, or multimaster (implemented in a dedicated I2C block) ■ Cyclic redundancy checker/generator (16-bit) ■ Infrared Data Association (IrDA) ■ PRS generators (8- to 32-bit) PSoC GPIOs provide connection to the CPU, digital resources, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin is also capable of generating a system interrupt. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Memory encompasses 16 KB of flash for program storage, 1 KB of SRAM for data storage, and up to 2 KB of emulated EEPROM using the flash. Program flash has four protection levels on blocks of 64 bytes, allowing customized software IP protection. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Document Number: 001-53754 Rev. *H Page 3 of 52 CY8C24894 Figure 2. Analog System Block Diagram The analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below. ■ Filters (Two- and Four-pole band pass, low pass, and notch) ■ Amplifiers (up to two, with selectable gain to 48x) ■ Instrumentation amplifiers (one with selectable gain to 93x) ■ Comparators (up to two, with 16 selectable thresholds) ■ DACs (up to two, with 6- to 9-bit resolution) ■ Multiplying DACs (up to two, with 6- to 9-bit resolution) ■ High current output drivers (two with 30 mA drive) ■ 1.3-V reference (as a system resource) ■ DTMF Dialer ■ P 0 [6 ] P 0 [5 ] P 0 [4 ] P 0 [3 ] P 0 [2 ] P 0 [1 ] P 0 [0 ] P 2 [3 ] AGNDIn RefIn ADCs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta-sigma, or successive approximation register (SAR)) P 0 [7 ] Analog ■ A ll IO (E x c e p t P o r t 7 ) Mux Bus The Analog System P 2 [1 ] P 2 [6 ] P 2 [4 ] P 2 [2 ] P 2 [0 ] A C I 0 [1 :0 ] A C I 1 [1 :0 ] A r r a y In p u t C o n f ig u r a t io n B lo c k A rray AC B00 A C B 01 Modulators A SC 10 A SD 11 ■ Correlators ASD20 A SC 21 ■ Peak Detectors ■ Many other topologies possible A n a lo g R e f e r e n c e Analog blocks are arranged in a column of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure 2. In t e r f a c e t o D ig it a l S y s t e m R e fH i R e fL o AGND R e fe r e n c e G e n e ra to rs A G N D In R e fIn B andgap M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .) The Analog Multiplexer System The analog mux bus can connect to every GPIO pin in ports 0-5. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and ADCs. It can be split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: Document Number: 001-53754 Rev. *H ■ Track pad, finger sensing. ■ Chip-wide mux that allows analog input from up to 47 I/O pins. ■ Crosspoint connection between any I/O pin combination. Page 4 of 52 CY8C24894 Additional System Resources System resources provide additional capability useful for complete systems. Additional resources include a multiplier, decimator, LVD, and power-on reset (POR). Brief statements describing the merits of each resource follow. ■ ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. ■ ■ The decimator provides a custom hardware filter for digital signal processing applications including creation of DeltaSigma ADCs. The I2C module provides 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3-V voltage reference provides an absolute reference for the analog system, including ADCs and DACs. ■ Versatile analog multiplexer system. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have varying numbers of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet is shown in the highlighted row of the table. Table 1. PSoC Device Characteristics PSoC Part Number Digital I/O CY8C29x66[1] up to 64 CY8C28xxx up to 44 Digital Rows Digital Blocks Analog Inputs Analog Outputs 4 16 up to 12 4 up to 3 up to 12 up to 44 up to 4 Analog Columns Analog Blocks SRAM Size Flash Size 4 12 2K 32 K up to 6 up to 12 + 4[2] 1K 16 K CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K CY8C24x94[1] up to 56 1 4 up to 48 2 2 6 1K 16 K CY8C24x23A[1] up to 24 1 4 up to 12 2 2 6 256 4K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K CY8C22x45[1] up to 38 2 8 up to 38 0 4 6[2] 1K 16 K CY8C21x45[1] up to 24 1 4 up to 24 0 4 6[2] 512 8K CY8C21x34[1] up to 28 1 4 up to 28 0 2 4[2] 512 8K CY8C21x23 up to 16 1 4 up to 8 0 2 4[2] 256 4K [2,3] CY8C20x34 [1] CY8C20xx6 up to 28 0 0 up to 28 0 0 3 up to 36 0 0 up to 36 0 0 3[2,3] 512 8K up to 2 K up to 32 K Notes 1. Automotive qualified devices available in this group. 2. Limited analog functionality. 3. Two analog blocks and one CapSense® block. Document Number: 001-53754 Rev. *H Page 5 of 52 CY8C24894 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Code Generation Tools Technical Support The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. Development Tools C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) Document Number: 001-53754 Rev. *H Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Page 6 of 52 CY8C24894 Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Designing with PSoC Designer The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise Document Number: 001-53754 Rev. *H configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Page 7 of 52 CY8C24894 Pinouts The automotive CY8C24x94 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O. However, VSS, VDD, and XRES are not capable of digital I/O. 56-Pin Part Pinout (with XRES pin) Table 2. 56-Pin Part Pinout (QFN) Figure 3. CY8C24894 56-Pin PSoC Device 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QFN (Top View) I/O M P5[0] 30 I/O M P5[2] 31 I/O M P5[4] Type Name Pin No. Digital Analog 32 I/O M P5[6] 45 I/O I, M P0[0] 33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input 34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input 35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input 49 VDD Supply voltage Input P2[2], AI, M P2[0], AI, M P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M I2C SCL, M, P1[7] I2C SDA, M, P1[5] M, P1[3] I2C SCL, M, P1[1] VSS DNC DNC VDD P7[7] P7[0] I2C SDA, M, P1[0] M, P1[2] EXTCLK, M, P1[4] M, P1[6] 29 36 42 41 40 39 38 37 36 35 34 33 32 31 30 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P2[5], M P2[7], M P0[1], M, AI P0[3], M, AIO P0[5], M, AIO P0[7], M, AI VSS VDD P0[6], M, AI P0[4], M, AI P0[2], M, AI P0[0], M, AI P2[6], M, Ext. VRef P2[4], M, Ext. AGND Type Pin Name Description No. Digital Analog 1 I/O I, M P2[3] Direct switched capacitor block input 2 I/O I, M P2[1] Direct switched capacitor block input 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] 7 I/O M P3[7] 8 I/O M P3[5] 9 I/O M P3[3] 10 I/O M P3[1] 11 I/O M P5[7] 12 I/O M P5[5] 13 I/O M P5[3] 14 I/O M P5[1] 15 I/O M P1[7] I2C serial clock (SCL) 16 I/O M P1[5] I2C serial data (SDA) 17 I/O M P1[3] 18 I/O M P1[1] I2C SCL, ISSP SCLK[4] 19 Power VSS Ground connection 20 DNC Do not connect anything to this pin 21 DNC Do not connect anything to this pin 22 Power VDD Supply voltage 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C SDA, ISSP SDATA[4] 26 I/O M P1[2] 27 I/O M P1[4] Optional external clock (EXTCLK) input 28 I/O M P1[6] Analog column mux input 37 I/O M XRES Active high external reset with internal pull-down P4[0] 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output 41 I/O I, M P2[0] Direct switched capacitor block input 54 I/O I, M P0[1] Analog column mux input 42 I/O I, M P2[2] Direct switched capacitor block input 55 I/O M P2[7] 43 I/O M P2[4] External analog ground (AGND) input 56 I/O M P2[5] 44 I/O M P2[6] External voltage reference (VREF) input EP 50 Power Description Power Power VSS VSS Ground connection Exposed pad is not connected internally. Connect to circuit ground for best performance LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 4. These are the ISSP pins, which are not high Z when coming out of reset state. See the PSoC Technical Reference Manual for details. Document Number: 001-53754 Rev. *H Page 8 of 52 CY8C24894 Registers This section lists the registers of the automotive CY8C24x94 PSoC device family. For detailed register information, refer to the PSoC Technical Reference Manual. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the following table. The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set the user is in Bank 1. Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-53754 Rev. *H Note In the following register mapping tables, blank fields are Reserved and should not be accessed. Page 9 of 52 CY8C24894 Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B PRT7DR 1C RW PRT7IE 1D RW PRT7GS 1E RW PRT7DM2 1F RW DBB00DR0 20 # AMX_IN DBB00DR1 21 W AMUXCFG DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 30 ACB00CR3 31 ACB00CR0 32 ACB00CR1 33 ACB00CR2 34 ACB01CR3 35 ACB01CR0 36 ACB01CR1 37 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. Document Number: 001-53754 Rev. *H Addr (0,Hex) Access 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 RW RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) Access 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F DAC_D CPU_SCR1 CPU_SCR0 Addr (0,Hex) Access C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL RW # # Page 10 of 52 CY8C24894 Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW 11 RW 12 RW 13 RW 14 RW 15 RW 16 RW 17 RW 18 19 1A 1B PRT7DM0 1C RW PRT7DM1 1D RW PRT7IC0 1E RW PRT7IC1 1F RW DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW CMP_GO_EN DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW DCB02IN 29 RW DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 ACB00CR3 31 ACB00CR0 32 ACB00CR1 33 ACB00CR2 34 ACB01CR3 35 ACB01CR0 36 ACB01CR1 37 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and should not be accessed. Document Number: 001-53754 Rev. *H Addr (1,Hex) Access 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) Access 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW CPU_F DAC_CR CPU_SCR1 CPU_SCR0 Addr (1,Hex) Access C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R W W RW W RW RW RL RW # # Page 11 of 52 CY8C24894 Electrical Specifications This section presents the DC and AC electrical specifications of the automotive CY8C24x94 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com. Specifications are valid for –40 C TA 85 C and TJ 100 C, except where noted. Figure 4. Voltage versus CPU Frequency 5.25 lid ing Va rat n e io Op eg R VDD Voltage (V) 4.75 3.0 0 93 kHz 12 MHz 24 MHz CPU Frequency (nominal setting) Document Number: 001-53754 Rev. *H Page 12 of 52 CY8C24894 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 3. Absolute Maximum Ratings Symbol TSTG Description Storage temperature TBAKETEMP Bake temperature tBAKETIME TA VDD VIO VIO2 IMIO IMAIO ESD LU Min –55 Typ 25 – 125 Bake time See package label Ambient temperature with power applied –40 Supply voltage on VDD relative to VSS –0.5 DC input voltage VSS – 0.5 DC voltage applied to tri-state VSS – 0.5 Maximum current into any port pin –25 Maximum current into any port pin –50 configured as analog driver Electro static discharge voltage 2000 Latch-up current – Max +100 Units Notes C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 C ± 25 C. Time spent in storage at a temperature greater than 65 °C counts toward the FlashDR electrical specification in Table 16 on page 26. C – See package label 72 Hours – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 C V V V mA mA – – – 200 V mA Typ – – Max +85 +100 Human Body Model ESD. Operating Temperature Table 4. Operating Temperature Symbol Description TA Ambient temperature TJ Junction temperature Document Number: 001-53754 Rev. *H Min –40 –40 Units Notes C C The temperature rise from ambient to junction is package specific. See Table 28 on page 35. The user must limit the power consumption to comply with this requirement. Page 13 of 52 CY8C24894 DC Electrical Characteristics DC Chip Level Specifications Table 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 5. DC Chip-Level Specifications Symbol Description VDD Supply voltage Min 3.0 Typ – Max 5.25 IDD5 Supply current, IMO = 24 MHz, VDD = 5 V – 14 27 IDD3 Supply current, IMO = 24 MHz, VDD = 3.3 V – 8 14 ISB Sleep [5] (mode) current with POR, LVD, sleep timer, and WDT.[6] – 3 6.5 ISBH Sleep (mode) current with POR, LVD, sleep timer, and WDT at high temperature.[6] – 4 25 Units Notes V See DC POR and LVD specifications, Table 15 on page 25. mA Conditions are VDD = 5.0 V, TA = 25 C, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, Analog power = off. mA Conditions are VDD = 3.3 V, TA = 25 C, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, Analog power = off. A Conditions are with ILO active, VDD = 3.3 V, –40 C TA 55 C, Analog power = off. A Conditions are with ILO active, VDD = 3.3 V, 55 C < TA 85 C, Analog power = off. Notes 5. Errata: When the device is operating at 4.75 V to 5.25 V and the 3.3 V regulator is enabled, a short low pulse may be created on the DP signal line during device wake-up. The 15-20 μs low pulse of the DP line may be interpreted by the host computer as a deattach or the beginning of a wake-up. More details in “Errata” on page 46. 6. Standby current includes all functions (POR, LVD, WDT, sleep timer) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 001-53754 Rev. *H Page 14 of 52 CY8C24894 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 6. DC GPIO Specifications Symbol Description RPU Pull-up resistor RPD Pull-down resistor Min 4 4 Typ 5.6 5.6 Max 8 8 VOH High output level VDD – 1.0 – – VOL Low output level – – 0.75 IOH High level source current 10 – – IOL Low level sink current 25 – – VIL VIH VH IIL CIN Input low level Input high level Input hysterisis Input leakage (absolute value) Capacitive load on pins as input – 2.1 – – – – – 60 1 3.5 0.8 – – – 10 COUT Capacitive load on pins as output – 3.5 10 Document Number: 001-53754 Rev. *H Units Notes k k Also applies to the internal pull-down resistor on the XRES pin V IOH = 10 mA, VDD = 4.75 V to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. V IOL = 25 mA, VDD = 4.75 V to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200 mA maximum combined IOL budget. mA VOH VDD – 1.0 V, see the limitations of the total current in the note for VOH. mA VOL 0.75 V, see the limitations of the total current in the note for VOL. V VDD = 3.0 V to 5.25 V. V VDD = 3.0 V to 5.25 V. mV nA Gross tested to 1 A. pF Package and pin dependent. TA = 25 C. pF Package and pin dependent. TA = 25 C. Page 15 of 52 CY8C24894 DC Operational Amplifier Specifications Table 7 and Table 8 on page 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor (SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 7. 5-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high TCVOSOA Average input offset voltage Drift Input leakage current (Port 0 Analog Pins) IEBOA Input capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range All cases, except highest Power = high, Opamp bias = high GOLOA Open loop gain Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high VOLOWOA Low output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high ISOA Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high PSRROA Supply voltage rejection ratio Document Number: 001-53754 Rev. *H Min Typ Max Units – – – – – – 1.6 1.3 1.2 10 8 7.5 mV mV mV 7.0 20 4.5 35.0 – 9.5 V/C pA pF 0.0 0.5 – – VDD VDD – 0.5 V V 60 60 80 – – – – – – dB dB dB VDD – 0.2 VDD – 0.2 VDD – 0.5 – – – – – – V V V – – – – – – 0.2 0.2 0.5 V V V – – – – – – 65 400 500 800 1200 2400 4600 80 800 900 1000 1600 3200 6400 – A A A A A A dB Notes Gross tested to 1 A. Package and pin dependent. TA = 25 C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high Opamp bias), minimum is 60 dB. VSS VIN (VDD – 2.25 V) or (VDD – 1.25 V) VIN VDD. Page 16 of 52 CY8C24894 Table 8. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high TCVOSOA Average input offset voltage drift IEBOA Input leakage current (Port 0 analog pins) Input capacitance (Port 0 analog pins) CINOA Min Typ Max – – – – – – 1.65 1.32 – 7.0 20 4.5 10 8 – 35.0 – 9.5 VCMOA Common mode voltage range 0.2 – GOLOA Open loop gain Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low 60 60 80 – – – VDD – 0.2 VDD – 0.2 VDD – 0.2 – – – – – – V V V – – – – – – 0.2 0.2 0.2 V V V VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low VOLOWOA Low output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low Supply current ISOA (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high PSRROA Supply voltage rejection ratio – – – – – – 65 400 500 800 1200 2400 – 80 Units Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation mV mV mV µV/°C pA Gross tested to 1 µA. pF Package and pin dependent. TA = 25 °C. VDD – 0.2 V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at – dB low Opamp bias. For high – dB Opamp bias mode (except high – dB power, high Opamp bias), minimum is 60 dB. 800 900 1000 1600 3200 – – µA µA µA µA µA µA dB Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation VSS VIN (VDD – 2.25) or (VDD – 1.25 V) VIN VDD DC Low Power Comparator Specifications Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 9. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Document Number: 001-53754 Rev. *H Min 0.2 Typ – Max VDD – 1.0 Units V – – 10 2.5 55 55 A mV Notes Page 17 of 52 CY8C24894 DC Analog Output Buffer Specifications Table 10 and Table 11 on page 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 10. 5-V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB PSRROB Description Min Input offset voltage (absolute value) – Average input offset voltage drift – Common mode input voltage range 0.5 Output resistance Power = low – Power = high – High output voltage swing (load = 32 to VDD/2) Power = low 0.5 × VDD + 1.1 Power = high 0.5 × VDD + 1.1 Low output voltage swing (load = 32 to VDD/2) – Power = low – Power = high Supply current including opamp bias cell (no load) – Power = low – Power = high Supply voltage rejection ratio 53 CL Load capacitance VOHIGHOB VOLOWOB ISOB Document Number: 001-53754 Rev. *H – Typ 3 +6 – Max 12 – VDD – 1.0 Units mV µV/°C V 0.6 0.6 – – – – – – V V – – 0.5 × VDD – 1.3 0.5 × VDD – 1.3 V V 1.1 2.6 64 5.1 8.8 – mA mA dB – 200 pF Notes (0.5 × VDD – 1.3) VOUT (VDD – 2.3). This specification applies to the external circuit that is being driven by the analog output buffer. Page 18 of 52 CY8C24894 Table 11. 3.3-V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB PSRROB Description Min Input offset voltage (absolute value) – Average input offset voltage drift – Common mode input voltage range 0.5 Output resistance Power = low – Power = high – High output voltage swing (load = 1 Kto VDD/2) 0.5 × VDD + 1.0 Power = low 0.5 × VDD + 1.0 Power = high Low output voltage swing (load = 1 Kto VDD/2) Power = low – Power = high – Supply current including opamp bias cell (no load) Power = low – Power = high – Supply voltage rejection ratio 34 CL Load capacitance VOHIGHOB VOLOWOB ISOB Document Number: 001-53754 Rev. *H – Typ 3 +6 – Max 12 – VDD – 1.0 Units mV µV/°C V 1 1 – – – – – – V V – – 0.5 × VDD – 1.0 0.5 × VDD – 1.0 V V 0.8 2.0 64 2.0 4.3 – mA mA dB – 200 pF Notes (0.5 × VDD – 1.0) VOUT (0.5 × VDD + 0.9). This specification applies to the external circuit that is being driven by the analog output buffer. Page 19 of 52 CY8C24894 DC Analog Reference Specifications Table 12 and Table 13 on page 23 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C. These are for design guidance only. The guaranteed specifications are measured through the analog CT PSoC blocks. The power levels for AGND refer to the power of the analog CT PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the analog CT PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of the digital signal may appear on the AGND. Table 12. 5-V DC Analog Reference Specifications Reference ARF_CR [5:3] 0b000 Reference Power Settings RefPower = high Opamp bias = high Reference Description Min Typ Max Units VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.229 VDD/2 + 1.290 VDD/2 + 1.346 VAGND AGND VDD/2 VDD/2 – 0.038 VDD/2 + 0.040 V VREFLO Ref Low VDD/2 – Bandgap V VDD/2 V VREFHI Ref High VDD/2 + Bandgap VDD/2 – 1.356 VDD/2 – 1.295 VDD/2 – 1.218 VDD/2 + 1.220 VDD/2 + 1.292 VDD/2 + 1.348 VAGND AGND VDD/2 VDD/2 – 0.036 VDD/2 + 0.036 V VREFLO Ref Low VDD/2 – Bandgap V RefPower = medium VREFHI Opamp bias = high V AGND Ref High VDD/2 + Bandgap VDD/2 – 1.357 VDD/2 – 1.297 VDD/2 – 1.225 VDD/2 + 1.221 VDD/2 + 1.293 VDD/2 + 1.351 AGND VDD/2 VDD/2 – 0.036 VDD/2 + 0.036 V VREFLO Ref Low VDD/2 – Bandgap V RefPower = medium VREFHI Opamp bias = low VAGND Ref High VDD/2 + Bandgap VDD/2 – 1.357 VDD/2 – 1.298 VDD/2 – 1.228 VDD/2 + 1.219 VDD/2 + 1.293 VDD/2 + 1.353 AGND VDD/2 V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.036 VDD/2 – 1.359 VDD/2 – 1.299 VDD/2 – 1.229 VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.092 0.011 0.064 VAGND AGND P2[4] VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.031 0.007 0.056 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.078 0.008 0.063 V VAGND AGND P2[4] VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.031 0.004 0.043 V RefPower = medium VREFHI Opamp bias = high Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.073 0.006 0.062 V RefPower = high Opamp bias = low 0b001 Symbol RefPower = high Opamp bias = high RefPower = high Opamp bias = low P2[4] P2[4] VDD/2 P2[4] P2[4] P2[4] V V V – – AGND P2[4] Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.032 0.003 0.038 V RefPower = medium VREFHI Opamp bias = low Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.073 0.006 0.062 V AGND P2[4] Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) Document Number: 001-53754 Rev. *H P2[4] P2[4] P2[4] V VREFLO VREFLO P2[4] P2[4] V VAGND VAGND P2[4] VDD/2 P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.034 0.002 0.037 – – V Page 20 of 52 CY8C24894 Table 12. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b010 Reference Power Settings RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b011 Reference Description VREFHI Ref High VDD Min Typ Max Units VDD – 0.037 VDD – 0.007 VDD V VAGND AGND VDD/2 VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.029 V VREFHI Ref High VDD VDD – 0.034 VDD – 0.006 VDD V VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.036 V VAGND AGND VDD/2 VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.024 V RefPower = medium VREFHI Opamp bias = high V AGND Ref High VDD VDD – 0.032 VDD – 0.005 VDD V AGND VDD/2 VREFLO Ref Low VSS RefPower = medium VREFHI Opamp bias = low VAGND Ref High VDD AGND VDD/2 VREFLO Ref Low VSS VREFHI Ref High 3 × Bandgap 3.760 3.884 4.006 V VAGND AGND 2 × Bandgap 2.522 2.593 2.669 V VREFLO Ref Low Bandgap 1.252 1.299 1.342 V VREFHI Ref High 3 × Bandgap 3.766 3.887 4.010 V VAGND AGND 2 × Bandgap 2.523 2.594 2.670 V V RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b100 Symbol VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035 VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035 VSS VSS + 0.003 VSS + 0.022 VDD – 0.031 VDD – 0.005 VDD VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.035 VSS VSS + 0.003 VSS + 0.020 V V V V V V VREFLO Ref Low Bandgap 1.252 1.297 1.342 RefPower = medium VREFHI Opamp bias = high V AGND Ref High 3 × Bandgap 3.769 3.888 4.013 V AGND 2 × Bandgap 2.523 2.594 2.671 V V VREFLO Ref Low Bandgap 1.251 1.296 1.343 RefPower = medium VREFHI Opamp bias = low VAGND Ref High 3 × Bandgap 3.769 3.889 4.015 V AGND 2 × Bandgap 2.523 2.595 2.671 V VREFLO Ref Low Bandgap VREFHI Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) VAGND AGND 2 × Bandgap VREFLO Ref Low VREFHI Ref High VAGND AGND 2 × Bandgap 2.523 VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.523 – P2[6] RefPower = medium VREFHI Opamp bias = high Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.493 – P2[6] 2.588 – P2[6] RefPower = high Opamp bias = high RefPower = high Opamp bias = low 1.251 1.296 1.344 V 2.483 – P2[6] 2.582 – P2[6] 2.674 – P2[6] V 2.522 2.593 2.669 V 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.524 – P2[6] 2.600 – P2[6] 2.676 – P2[6] V 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.490 – P2[6] 2.586 – P2[6] 2.679 – P2[6] V 2.594 2.669 V 2.598 – P2[6] 2.675 – P2[6] V 2.682 – P2[6] V VAGND AGND 2 × Bandgap 2.523 2.594 2.670 V VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.523 – P2[6] 2.597 – P2[6] 2.675 – P2[6] V RefPower = medium VREFHI Opamp bias = low Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.494 – P2[6] 2.589 – P2[6] 2.685 – P2[6] V VAGND AGND 2 × Bandgap 2.523 2.595 2.671 V VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.522 – P2[6] 2.596 – P2[6] 2.676 – P2[6] V Document Number: 001-53754 Rev. *H Page 21 of 52 CY8C24894 Table 12. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] 0b101 Reference Power Settings RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b110 Reference Description Min Typ Max Units P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.354 V P2[4] P2[4] P2[4] – VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) VAGND AGND P2[4] VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.335 P2[4] – 1.294 P2[4] – 1.237 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.221 P2[4] + 1.293 P2[4] + 1.358 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.337 P2[4] – 1.297 P2[4] – 1.243 V RefPower = medium VREFHI Opamp bias = high Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.360 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.338 P2[4] – 1.298 P2[4] – 1.245 V RefPower = medium VREFHI Opamp bias = low Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.221 P2[4] + 1.294 P2[4] + 1.362 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.340 P2[4] – 1.298 P2[4] – 1.245 V RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b111 Symbol VREFHI Ref High 2 × Bandgap 2.513 2.593 2.672 V VAGND AGND Bandgap 1.264 1.302 1.340 V VREFLO Ref Low VSS VSS VSS + 0.008 VSS + 0.038 V VREFHI Ref High 2 × Bandgap 2.514 2.593 2.674 V VAGND AGND Bandgap 1.264 1.301 1.340 V V VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.028 RefPower = medium VREFHI Opamp bias = high V AGND Ref High 2 × Bandgap 2.514 2.593 2.676 V AGND Bandgap 1.264 1.301 1.340 V V VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.024 RefPower = medium VREFHI Opamp bias = low VAGND Ref High 2 × Bandgap 2.514 2.593 2.677 V AGND Bandgap 1.264 1.300 1.340 V VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.021 V VREFHI Ref High 3.2 × Bandgap 4.028 4.144 4.242 V VAGND AGND 1.6 × Bandgap 2.028 2.076 2.125 V VREFLO Ref Low VSS VSS VSS + 0.008 VSS + 0.034 V VREFHI Ref High 3.2 × Bandgap 4.032 4.142 4.245 V VAGND AGND 1.6 × Bandgap 2.029 2.076 2.126 V VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.025 V RefPower = medium VREFHI Opamp bias = high V AGND Ref High 3.2 × Bandgap 4.034 4.143 4.247 V AGND 1.6 × Bandgap 2.029 2.076 2.126 V VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.021 V RefPower = medium VREFHI Opamp bias = low VAGND Ref High 3.2 × Bandgap 4.036 4.144 4.249 V AGND 1.6 × Bandgap 2.029 2.076 2.126 V VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.019 V RefPower = high Opamp bias = high RefPower = high Opamp bias = low Document Number: 001-53754 Rev. *H Page 22 of 52 CY8C24894 Table 13. 3.3-V DC Analog Reference Specifications Reference ARF_CR [5:3] 0b000 Reference Power Settings RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b001 Reference Description Min Typ Max Units VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.200 VDD/2 + 1.290 VDD/2 + 1.365 VAGND AGND VDD/2 VDD/2 – 0.030 VDD/2 + 0.034 V VREFLO Ref Low VDD/2 – Bandgap V VREFHI Ref High VDD/2 + Bandgap VDD/2 – 1.346 VDD/2 – 1.292 VDD/2 – 1.208 VDD/2 + 1.196 VDD/2 + 1.292 VDD/2 + 1.374 VAGND AGND VDD/2 VDD/2 – 0.029 VDD/2 + 0.031 V VDD/2 VDD/2 V V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.349 VDD/2 – 1.295 VDD/2 – 1.227 V RefPower = medium VREFHI Opamp bias = high V AGND Ref High VDD/2 + Bandgap VDD/2 + 1.204 VDD/2 + 1.293 VDD/2 + 1.369 V AGND VDD/2 VDD/2 – 0.030 VDD/2 + 0.030 V VDD/2 VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.351 VDD/2 – 1.297 VDD/2 – 1.229 V RefPower = medium VREFHI Opamp bias = low VAGND Ref High VDD/2 + Bandgap V AGND VDD/2 VDD/2 + 1.189 VDD/2 + 1.294 VDD/2 + 1.384 VDD/2 – 0.032 VDD/2 VDD/2 + 0.029 RefPower = high Opamp bias = high RefPower = high Opamp bias = low 0b010 Symbol V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.353 VDD/2 – 1.297 VDD/2 – 1.230 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.105 0.008 0.095 V VAGND AGND P2[4] VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.035 0.006 0.053 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.094 0.005 0.073 V P2[4] P2[4] P2[4] P2[4] P2[4] P2[4] – VAGND AGND P2[4] VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.033 0.002 0.042 V – RefPower = medium VREFHI Opamp bias = high Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.094 0.003 0.075 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] – P2[6] – 0.035 P2[4] – P2[6] P2[4] – P2[6] + 0.038 V RefPower = medium VREFHI Opamp bias = low Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.095 0.003 0.080 V VAGND AGND P2[4] VREFLO Ref Low P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) RefPower = high Opamp bias = high RefPower = high Opamp bias = low VREFHI Ref High VDD VAGND AGND VDD/2 VREFLO Ref Low VSS VREFHI Ref High VDD VAGND AGND VDD/2 P2[4] P2[4] P2[4] – P2[4] – P2[6] – 0.038 P2[4] – P2[6] P2[4] – P2[6] + 0.038 V V VDD – 0.119 VDD – 0.005 VDD VDD/2 – 0.028 VDD/2 VDD/2 + 0.029 V VSS VSS + 0.004 VSS + 0.022 V VDD – 0.131 VDD – 0.004 VDD V VDD/2 – 0.028 VDD/2 VDD/2 + 0.028 V VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.021 V RefPower = medium VREFHI Opamp bias = high V AGND Ref High VDD VDD – 0.111 VDD – 0.003 VDD V AGND VDD/2 VDD/2 – 0.029 VDD/2 VDD/2 + 0.028 V VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.017 V RefPower = medium VREFHI Opamp bias = low VAGND Ref High VDD VDD – 0.128 VDD – 0.003 VDD V AGND VDD/2 VDD/2 – 0.029 VDD/2 VDD/2 + 0.029 V VREFLO Ref Low VSS VSS VSS + 0.002 VSS + 0.019 V Document Number: 001-53754 Rev. *H Page 23 of 52 CY8C24894 Table 13. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b011 All power settings. – Not allowed for 3.3 V. – – – – – – 0b100 All power settings. – Not allowed for 3.3 V. – – – – – – 0b101 RefPower = high Opamp bias = high VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.214 P2[4] + 1.291 P2[4] + 1.359 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.335 P2[4] – 1.292 P2[4] – 1.200 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.219 P2[4] + 1.293 P2[4] + 1.357 V RefPower = high Opamp bias = low 0b110 VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.335 P2[4] – 1.295 P2[4] – 1.243 V RefPower = medium VREFHI Opamp bias = high Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.222 P2[4] + 1.294 P2[4] + 1.356 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.337 P2[4] – 1.296 P2[4] – 1.244 V RefPower = medium VREFHI Opamp bias = low Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.224 P2[4] + 1.295 P2[4] + 1.355 V VAGND AGND P2[4] P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.339 P2[4] – 1.297 P2[4] – 1.244 V V RefPower = high Opamp bias = high RefPower = high Opamp bias = low VREFHI Ref High 2 × Bandgap 2.510 2.595 2.655 VAGND AGND Bandgap 1.276 1.301 1.332 V VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.031 V VREFHI Ref High 2 × Bandgap 2.513 2.594 2.656 V VAGND AGND Bandgap 1.275 1.301 1.331 V VREFLO Ref Low VSS VSS VSS + 0.004 VSS + 0.021 V RefPower = medium VREFHI Opamp bias = high V AGND Ref High 2 × Bandgap 2.516 2.595 2.657 V AGND Bandgap 1.275 1.301 1.331 V VREFLO Ref Low VSS VSS VSS + 0.003 VSS + 0.017 V RefPower = medium VREFHI Opamp bias = low VAGND Ref High 2 × Bandgap 2.520 2.595 2.658 V AGND Bandgap 1.275 1.300 1.331 V VSS VSS + 0.002 VSS + 0.015 V – – – – VREFLO 0b111 All power settings. – Not allowed for 3.3 V. Document Number: 001-53754 Rev. *H Ref Low VSS – – Page 24 of 52 CY8C24894 DC Analog PSoC Block Specifications Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 14. DC Analog PSoC Block Specifications Symbol Description RCT Resistor unit value (continuous time) CSC Capacitor unit value (switched capacitor) Min – – Typ 12.2 80 Max – – Units k fF Notes DC POR and LVD Specifications Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual for more information on the VLT_CR register. Table 15. DC POR and LVD Specifications Symbol Description VDD Value for PPOR Trip (negative ramp) VPPOR0[7] PORLEV[1:0] = 00b VPPOR1[7] PORLEV[1:0] = 01b VPPOR2[7] PORLEV[1:0] = 10b VPH0 VPH1 VPH2 PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VDD Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units Notes VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from watchdog. – – – 2.82 4.39 4.55 – – – V V V – – – 92 0 0 – – – mV mV mV 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02[8] 3.12 3.24 4.12 4.62 4.78[9] 4.87 4.96 V V V V V V V V Notes 7. Errata: When VDD of the device is pulled below ground just before power on, the first read from each 8K Flash page may be corrupted. This issue does not affect Flash page 0 because it is the selected page upon reset. More details in “Errata” on page 46. 8. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 9. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-53754 Rev. *H Page 25 of 52 CY8C24894 DC Programming Specifications Table 16 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 16. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5.0 Max 5.5 Units V VDDLV Low VDD for verify 3.0 3.1 3.2 V VDDHV High VDD for verify 5.1 5.2 5.3 V 3.0 – 5.25 V 15 – – – 30 0.8 – 0.2 mA V V mA – 1.5 mA – 0.75 V – VDD V – – – – – – – – Years VDDIWRITE Supply voltage for flash write operation IDDP VILP VIHP IILP Supply current during programming or verify – Input low voltage during programming or verify – Input high voltage during programming or verify 2.1 Input current when applying VILP to P1[0] or – P1[1] during programming or verify IIHP Input current when applying VIHP to P1[0] or – P1[1] during programming or verify VOLV Output low voltage during programming or – verify VOHV Output high voltage during programming or VDD – 1.0 verify FlashENPB Flash endurance (per block)[10, 11] 1,000 FlashENT Flash endurance (total)[11, 12] 256,000 FlashDR Flash data retention[11] 10 Notes This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to this device when it is executing internal flash writes Driving internal pull-down resistor. Driving internal pull-down resistor. Erase/write cycles per block. Erase/write cycles. Notes 10. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 11. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. 12. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. Document Number: 001-53754 Rev. *H Page 26 of 52 CY8C24894 AC Electrical Characteristics AC Chip-Level Specifications Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 17. AC Chip-Level Specifications Symbol F32K1 Description IMO frequency for 24 MHz (5 V nominal) IMO frequency for 24 MHz (3.3 V nominal) CPU frequency (5 V nominal) CPU frequency (3.3 V nominal) Digital PSoC block frequency (5 V nominal) Digital PSoC block frequency (3.3 V nominal) ILO frequency F32KU ILO untrimmed frequency FIMO245V FIMO243V FCPU1 FCPU2 FBLK5 FBLK3 tXRST DC24M DCILO Step24M Fout48M FMAX External reset pulse width 24 MHz duty cycle ILO duty cycle 24 MHz trim step size 48 MHz output frequency Maximum frequency of signal on row input or row output. SRPOWERUP Power supply slew rate tPOWERUP Time between end of POR state and CPU code execution tJIT_IMO[15] 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) Min 23.04[13] Typ 24 Max 24.96[13] Units Notes MHz Trimmed for 5 V operation using factory trim values. MHz Trimmed for 3.3 V operation using factory trim values. MHz SLIMO mode = 0. MHz SLIMO mode = 0. MHz Refer to the AC Digital Block Specifications. MHz Refer to the AC Digital Block Specifications. kHz This specification applies when the ILO has been trimmed. kHz After a reset and before the M8C processor starts to execute, the ILO is not trimmed. µs % % kHz MHz 4.75 V VDD 5.25 V MHz 22.08[13] 24 25.92[13] 0.090[13] 0.086[13] 0 24 12 48 24.96[13] 12.96[13] 49.92[13,14] 0 24 25.92[13,14] 15 32 64 5 – 100 10 40 20 – 46.08[13] – – 50 50 50 48 – – 60 80 – 49.92[13] 12.96[13] – – – 16 250 100 V/ms ms – – 200 900 1200 6000 ps ps – 200 900 ps VDD slew rate during power-up. Power-up from 0 V. N = 32 Notes 13. Accuracy derived from IMO with appropriate trim for VDD range. 14. See the individual user module datasheets for information on maximum frequencies for user modules. 15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 001-53754 Rev. *H Page 27 of 52 CY8C24894 AC GPIO Specifications Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 18. AC GPIO Specifications Symbol FGPIO tRISEF tFALLF tRISES tFALLS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12.96[16] 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode VDD = 4.5 to 5.25 V, 10% to 90% VDD = 4.5 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% Figure 5. GPIO Timing Diagram 90% G PIO Pin O utput Voltage 10% tRISEF TRiseF tRISES TRiseS tFALLF TFallF tFALLS TFallS Note 16. Specification derived from the accuracy of the Internal Main Oscillator (IMO) with appropriate trim for VDD range. Document Number: 001-53754 Rev. *H Page 28 of 52 CY8C24894 AC Operational Amplifier Specifications Table 19 and Table 20 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V. Table 19. 5-V AC Operational Amplifier Specifications Symbol tROA tSOA SRROA SRFOA BWOA ENOA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Rising slew rate (20% to 80%) (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling slew rate (20% to 80%) (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Min Typ Max Units – – – – – – 3.9 0.72 0.62 µs µs µs – – – – – – 5.9 0.92 0.72 µs µs µs 0.15 1.7 6.5 – – – – – – V/µs V/µs V/µs 0.01 0.5 4.0 – – – – – – V/µs V/µs V/µs 0.75 3.1 5.4 – – – – 100 – – – – MHz MHz MHz nV/rt-Hz Min Typ Max Units – – – – 3.92 0.72 µs µs – – – – 5.41 0.72 µs µs 0.31 2.7 – – – – V/µs V/µs 0.24 1.8 – – – – V/µs V/µs 0.67 2.8 – – – 100 – – – MHz MHz nV/rt-Hz Table 20. 3.3-V AC Operational Amplifier Specifications Symbol tROA tSOA SRROA SRFOA BWOA ENOA Description Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Rising slew rate (20% to 80%) (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling slew rate (20% to 80%) (10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Document Number: 001-53754 Rev. *H Page 29 of 52 CY8C24894 When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor. Figure 6. Typical AGND Noise with P2[4] Bypass nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 7. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 Document Number: 001-53754 Rev. *H 0.01 0.1 Freq (kHz) 1 10 100 Page 30 of 52 CY8C24894 AC Low Power Comparator Specifications Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 21. AC Low Power Comparator Specifications Symbol Description tRLPC LPC response time Min – Typ – Max 50 Units Notes s 50 mV overdrive comparator reference set within VREFLPC. AC Digital Block Specifications Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 22. AC Digital Block Specifications Function Description All Block input clock frequency functions VDD 4.75 V VDD < 4.75 V Timer Input clock frequency No capture, VDD 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Dead Kill pulse width Band Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD 4.75 V VDD < 4.75 V CRCPRS Input clock frequency (PRS VDD 4.75 V Mode) VDD < 4.75 V CRCPRS Input clock frequency (CRC Mode) SPIM Input clock frequency SPIS Transmitter Input clock (SCLK) frequency Width of SS_Negated between transmissions Input Clock Frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Min Typ Max Units – – – – 49.92[17] 25.92[17] MHz MHz – – – 50[18] – – – – 49.92[17] 25.92[17] 25.92[17] – MHz MHz MHz ns – – – 50[18] – – – – 49.92[17] 25.92[17] 25.92[17] – MHz MHz MHz ns 20 50[18] 50[18] – – – – – – ns ns ns – – – – 49.92[17] 25.92[17] MHz MHz – – – – – – 49.92[17] 25.92[17] 25.92[17] MHz MHz MHz – – 8.64[17] MHz – – 4.32[17] MHz 50[18] – – ns – – – – – – 49.92[17] 25.92[17] 25.92[17] MHz MHz MHz Notes The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode. The baud rate is equal to the input clock frequency divided by 8. Notes 17. Accuracy derived from IMO with appropriate trim for VDD range. 18. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-53754 Rev. *H Page 31 of 52 CY8C24894 Table 22. AC Digital Block Specifications (continued) Function Description Receiver Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Min Typ Max Units – – – – – – 49.92[17] 25.92[17] 25.92[17] MHz MHz MHz Notes The baud rate is equal to the input clock frequency divided by 8. AC External Clock Specifications Table 23 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 23. AC External Clock Specifications Symbol Description Min Typ Max Units FOSCEXT Frequency 0 – 24.24 MHz – High period 20.5 – – ns – Low period 20.5 – – ns – Power-up IMO to switch 150 – – s Notes AC Analog Output Buffer Specifications Table 24 and Table 25 on page 33 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 24. 5-V AC Analog Output Buffer Specifications Symbol Description tROB Rising settling time to 0.1%, 1 V step, 100pF load Power = low Power = high tSOB Falling settling time to 0.1%, 1 V step, 100pF load Power = low Power = high SRROB Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = low Power = high SRFOB Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = low Power = high BWOBSS Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high BWOBLS Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Document Number: 001-53754 Rev. *H Min Typ Max Units – – – – 2.5 2.5 s s – – – – 2.2 2.2 s s 0.65 0.65 – – – – V/s V/s 0.65 0.65 – – – – V/s V/s 0.8 0.8 – – – – MHz MHz 300 300 – – – – kHz kHz Notes Page 32 of 52 CY8C24894 Table 25. 3.3-V AC Analog Output Buffer Specifications Symbol Description tROB Rising settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high tSOB Falling settling time to 0.1%, 1 V step, 100 pF load Power = low Power = high SRROB Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = low Power = high SRFOB Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = low Power = high BWOBSS Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high BWOBLS Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min Typ Max Units – – – – 3.8 3.8 s s – – – – 2.6 2.6 s s 0.5 0.5 – – – – V/s V/s 0.5 0.5 – – – – V/s V/s 0.7 0.7 – – – – MHz MHz 200 200 – – – – kHz kHz Notes AC Programming Specifications Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 26. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tPRGH tPRGC Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Total flash block program time (tERASEB + tWRITE), hot Total flash block program time (tERASEB + tWRITE), cold Min 1 1 40 40 0 – – – – – – Typ – – – – – 10 40 – – – – Max 20 20 – – 8 40[19] 160[19] 45 50 100[19] 200[19] Units ns ns ns ns MHz ms ms ns ns ms ms Notes VDD 3.6 V 3.0 V VDD 3.6 V TJ 0 °C TJ 0 °C Note 19. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. Document Number: 001-53754 Rev. *H Page 33 of 52 CY8C24894 AC I2C Specifications Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 27. AC Characteristics of the I2C SDA and SCL Pins for VDD Symbol FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a stop and start condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100[20] 4.0 – Fast Mode Min Max 0 400[20] 0.6 – Units Notes kHz s 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – 1.3 0.6 0.6 0 100[21] 0.6 1.3 – – – – – – – s s s s ns s s – – 0 50 ns Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA tSUDATI2C tSPI2C tHDDATI2C tSUSTAI2C tHDSTAI2C tBUFI2C I2C_SCL tHIGHI2C S START Condition tLOWI2C tSUSTOI2C Sr Repeated START Condition P S STOP Condition Notes 20. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-53754 Rev. *H Page 34 of 52 CY8C24894 Packaging Information This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package and solder reflow peak temperatures. Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 9. 56-Pin (8 × 8 mm) QFN (Punched) 001-12921 *C Important Note ■ For information on the preferred dimensions for mounting QFN packages, see the following application note, Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. ■ Pinned vias for thermal conduction are not required for the low power PSoC device. Thermal Impedances Solder Reflow Specifications Table 28. Thermal Impedance per Package Package 56-pin QFN[23] Typical JA [22] 19 C/W Typical JC 1.7 C/W Table 29 shows the solder reflow temperature limits that must not be exceeded. Table 29. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 56-pin QFN 260 C 30 seconds Notes 22. TJ = TA + Power × JA. 23. To achieve the thermal impedance specified for the QFN package, refer to the application notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 001-53754 Rev. *H Page 35 of 52 CY8C24894 Tape and Reel Information Figure 10. 56-Pin (8 × 8 mm) QFN (Punched) Carrier Tape Drawing 51-51165 *C Table 30. Tape and Reel Specifications Package Cover Tape Width (mm) Hub Size (inches) Minimum Leading Empty Pockets 56-Pin QFN 13.1 7 42 Document Number: 001-53754 Rev. *H Minimum Trailing Empty Pockets 25 Standard Full Reel Quantity 2000 Page 36 of 52 CY8C24894 Development Tool Selection Software ■ Universal 110/220 power supply (12 V) PSoC Designer ■ European plug adapter At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. ■ USB 2.0 cable ■ Getting Started Guide ■ Development kit registration form PSoC Programmer Evaluation Tools Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. All evaluation tools can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. Development Kits All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes: ■ ICE-Cube unit ■ 28-pin PDIP emulation pod for CY8C29466-24PXI ■ 28-pin CY8C29466-24PXI PDIP PSoC device samples (two) ■ PSoC Designer software CD ■ ISSP cable ■ MiniEval socket programming and evaluation board ■ Backward compatibility cable (for connecting to legacy pods) Document Number: 001-53754 Rev. *H CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ Evaluation board with LCD module ■ MiniProg programming unit ■ 28-Pin CY8C29466-24PXI PDIP PSoC device sample (2) ■ PSoC Designer software CD ■ Getting Started Guide ■ USB 2.0 cable CY3210-24X94 Evaluation Pod (EvalPod) PSoC EvalPods are pods that connect to the ICE In-Circuit Emulator (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-24X94 provides evaluation of the CY8C24x94 PSoC device family. Page 37 of 52 CY8C24894 Device Programmers CY3207ISSP In-System Serial Programmer (ISSP) All device programmers can be purchased from the Cypress Online Store. The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ MiniEval Socket Programming and Evaluation Board ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample ■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ CY3207 Programmer Unit ■ PSoC ISSP Software CD ■ 110 ~ 240 V Power Supply, Euro-Plug Adapter ■ USB 2.0 Cable Accessories (Emulation and Programming) Table 31. Emulation and Programming Accessories Part # CY8C24894-24LFXA Pin Package 56-pin QFN Flex-Pod Kit[24] CY3250-24X94QFN Foot Kit[25] CY3250-56QFN-FK Adapter[26] AS-56-28-01ML-6 Notes 24. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 25. Foot kit includes surface mount feet that are soldered to the target PCB. 26. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at http://www.emulation.com. Document Number: 001-53754 Rev. *H Page 38 of 52 CY8C24894 Ordering Information XRES Pin Analog Outputs Analog Inputs Digital I/O Pins Analog Blocks Digital Blocks Temperature Range SRAM (Bytes) Flash (Bytes) Package Ordering Code Table 32. CY8C24x94 PSoC Device’s Key Features and Ordering Information 56-pin (8 × 8 mm) QFN, punched CY8C24894-24LFXA 16 K 1 K –40 C to +85 C 4 6 49 47 2 Yes 56-pin (8 × 8 mm) QFN, punched (tape and reel) CY8C24894-24LFXAT 16 K 1 K –40 C to +85 C 4 6 49 47 2 Yes Ordering Code Definitions CY 8 C 24 xxx-SPxx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LKX = QFN Pb-free AX = TQFP Pb-free BVX = VFBGA Pb-free Thermal Rating: A = Automotive –40 °C to +85 °C C = Commercial E = Automotive Extended –40 °C to +125 °C I = Industrial CPU Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 001-53754 Rev. *H Page 39 of 52 CY8C24894 Acronyms Table 33 lists the acronyms that are used in this document. Table 33. Acronyms Used in this Datasheet Acronym AC Description Acronym alternating current MIPS Description million instructions per second ADC analog-to-digital converter PCB printed circuit board AEC Automotive Electronics Council PDIP plastic dual in-line package API application programming interface PLL phase-locked loop CPU central processing unit POR power-on reset CRC CT cyclic redundancy check PPOR precision POR continuous time PSoC® Programmable System-on-Chip DAC digital-to-analog converter PWM pulse-width modulator DC direct current or duty cycle QFN quad flat no leads dual-tone multi-frequency RMS root mean square EEPROM DTMF electrically erasable programmable read-only memory SAR successive approximation register EXTCLK external clock GPIO general purpose I/O SC SCL / SCLK serial clock SDA serial data SLIMO slow IMO I2C inter-integrated circuit ICE in-circuit emulator IDE integrated development environment SMP ILO internal low-speed oscillator SOIC IMO internal main oscillator I/O switched capacitor SPI switch mode pump small-outline integrated circuit serial peripheral interface input/output SRAM static random-access memory IrDA Infrared Data Association SROM supervisory read-only memory ISSP in-system serial programming TQFP thin quad flat pack LCD liquid crystal display UART universal asynchronous receiver transmitter LED light-emitting diode USB universal serial bus LPC low power comparator WDT watchdog timer LVD low voltage detect XRES external reset MCU microcontroller unit Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) PSOC(R) 1 - Getting Started With Flash & E2PROM – AN2015 (001-40459) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 001-53754 Rev. *H Page 40 of 52 CY8C24894 Document Conventions Units of Measure The following table lists the units of measure that are used in this document. Table 34. Units of Measure Symbol C dB fF KB kHz k MHz A s V mA ms mV Unit of Measure degree Celsius decibel femtofarad 1024 bytes kilohertz kilohm megahertz microampere microsecond microvolt milliampere millisecond millivolt Symbol mVPP nA ns nV % pA pF ps rt-Hz V W Unit of Measure millivolts peak-to-peak nanoampere nanosecond nanovolt ohm percent picoampere picofarad picosecond root hertz volt watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital converter (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation. Application programming interface (API) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 001-53754 Rev. *H Page 41 of 52 CY8C24894 Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog converter (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital converter (ADC) performs the reverse operation. Document Number: 001-53754 Rev. *H Page 42 of 52 CY8C24894 Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at the VDD suppy voltage and pulled high with resistors. The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 001-53754 Rev. *H Page 43 of 52 CY8C24894 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power-on reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied value. modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a known state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 001-53754 Rev. *H Page 44 of 52 CY8C24894 Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code, operating from flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital PSoC blocks. User modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-53754 Rev. *H Page 45 of 52 CY8C24894 Errata This section describes the errata for the CY8C24x94 device. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number CY8C24x94 CY8C24x94 Errata Summary The following table defines the errata applicability to available devices. Items Part Number 1. The DP line of the USB interface may pulse low when the PSoC device wakes from sleep causing an unexpected wake-up of the host computer. CY8C24x94 2. Invalid Flash reads may occur if Vdd is pulled to -0.5 V just before power on. CY8C24x94 3. PMA Index Register fails to auto-increment with CPU_Clock set to SysClk/1 (24 MHz). CY8C24x94 4. The Internal Main Oscillator (IMO) frequency parameter (FIMO245V) may increase over a period of time during usage in the field and exceed the maximum spec limit of 24.96 MHz. CY8C24x94 1. The DP line of the USB interface may pulse low when the PSoC device wakes from sleep causing an unexpected wake-up of the host computer. ■ PROBLEM DEFINITION When the device is operating at 4.75 V to 5.25 V and the 3.3 V regulator is enabled, a short low pulse may be created on the DP signal line during device wake-up. The 15-20 µs low pulse of the DP line may be interpreted by the host computer as a deattach or the beginning of a wake-up. ■ TRIGGER CONDITION(S) The bandgap reference voltage used by the 3.3 V regulator decreases during sleep due to leakage. Upon device wake up, the bandgap is reenabled and after a delay for settling, the 3.3 V regulator is enabled. On some devices the 3.3 V regulator that is used to generate the USB DP signal may be enabled before the bandgap is fully stabilized. This can cause a low pulse on the regulator output and DP signal line until the bandgap stabilizes. In applications where Vdd is 3.3 V, the regulator is not used and therefore the DP low pulse is not generated. ■ WORKAROUND To prevent the DP signal from pulsing low, keep the bandgap enabled during sleep. The most efficient method is to set the No Buzz bit in the OSC_CR0 register. The No Buzz bit keeps the bandgap powered and output stable during sleep. Setting the No Buzz bit results in nominal 100 µA increase to sleep current. Leaving the analog reference block enabled during sleep also resolves this issue because it forces the bandgap to remain enabled. An example for disabling the No Buzz bit is listed below. Assembly M8C_SetBank1 or reg[OSC_CR0], 0x20 M8C_SetBank0 C OSC_CR0 |= 0x20; Document Number: 001-53754 Rev. *H Page 46 of 52 CY8C24894 2. Invalid Flash reads may occur if Vdd is pulled to -0.5 V just before power on. ■ PROBLEM DEFINITION When Vdd of the device is pulled below ground just before power on, the first read from each 8K Flash page may be corrupted. This issue does not affect Flash page 0 because it is the selected page upon reset. ■ TRIGGER CONDITION(S) When Vdd is pulled below ground before power on, an internal Flash reference may deviate from its nominal voltage. The reference deviation tends to result in the first Flash read from that page returning 0xFF. During the first read from each page, the reference is reset resulting in all future reads returning the correct value. A short delay of 5 µs before the first real read provides time for the reference voltage to stabilize. ■ WORKAROUND To prevent an invalid Flash read, a dummy read from each Flash page must occur before use of the pages. A delay of 5 µs must occur after the dummy read and before a real read. The dummy reads occurs as soon as possible and must be located in Flash page 0 before a read from any other Flash page. An example for reading a byte of memory from each Flash page is listed below. Placed it in boot.tpl and boot.asm immediately after the ‘start:’ label. // dummy read from each 8K Flash page // page 1 mov A, 0x20 // MSB mov X, 0x00 // LSB romx // wait at least 5 µs mov X, 14 loop1: dec X jnz loop1 Document Number: 001-53754 Rev. *H Page 47 of 52 CY8C24894 3. PMA Index Register fails to auto-increment with CPU_Clock set to SysClk/1 (24 MHz). ■ PROBLEM DEFINITION When the device is operating at 4.75 to 5.25 V and the CPU_Clock is set to SysClk/1 (24 MHz), the USB PMA Index Register may fail to increment automatically when used in an OUT endpoint configuration at Full-Speed. When the application program attempts to use the bReadOutEP() function the first byte in the PMA buffer is always returned. ■ TRIGGER CONDITION(S) An internal flip-flop hold problem associated with Index Register increment function. All reads of the associated RAM originate from the first byte. The hold problem has no impact on other circuits or functions within the device. ■ WORKAROUND To make certain that the index register properly increments, set the CPU_Clock to SysClk/2 (12 MHz) during the read of the PMA buffer. An example for the clock adjustment method is listed below. PSoC Designer™ 4.3 User Module workaround: PSoC Designer Release 4.3 and subsequent releases includes a revised full-speed USB User Module with the revised firmware work-around included (see example below). ;; ;; 24 MHz read PMA workaround ;; M8C_SetBank1 mov A, reg[OSC_CR0] push A and A, 0xf8 ;clear the clock bits (briefly chg the cpu_clk to 3 MHz) or A, 0x02 ;will set clk to 12Mhz mov reg[OSC_CR0],A ;clk is now set at 12 MHz M8C_SetBank0 .loop: mov A, reg[PMA0_DR] ; Get the data from the PMA space mov [X], A ; save it in data array inc X ; increment the pointer dec [USB_APITemp+1] ; decrement the counter jnz .loop ; wait for count to zero out ;; ;; 24MHz read PMA workaround (back to previous clock speed) ;; pop A ;recover previous reg[OSC_CR0] value M8C_SetBank1 mov reg[OSC_CR0],A ;clk is now set at previous value M8C_SetBank0 ;; ;; end 24Mhz read PMA workaround Document Number: 001-53754 Rev. *H Page 48 of 52 CY8C24894 4. The Internal Main Oscillator (IMO) frequency parameter (FIMO245V) may increase over a period of time during usage in the field and exceed the maximum spec limit of 24.96 MHz. ■ PROBLEM DEFINITION When the device has been operating at 4.75 V to 5.25 V for a cumulatively long duration in the field, the IMO Frequency may slowly increase over the duration of usage in the field and eventually exceed the maximum spec limit of 24.96 MHz. This may affect applications that are sensitive to the max value of IMO frequency, such as those using UART communication and result in a functional failure. ■ TRIGGER CONDITION(S) Very long (cumulative) usage of the device in the operating voltage range of 4.75V to 5.25V, with the IMO clock running continuously, could lead to the degradation. Higher power supply voltage and lower ambient temperature are worst-case conditions for the degradation. ■ WORKAROUND Operating the device with the power supply voltage range of 3.0 V to 3.6 V, would avoid the degradation of IMO Frequency beyond the max spec limit of 24.96 MHz. ■ FIX STATUS A new revision of the silicon, with a fix for this issue, is expected to be available from August 1st 2015. Document Number: 001-53754 Rev. *H Page 49 of 52 CY8C24894 Document History Page Document Title: CY8C24894 Automotive PSoC® Programmable System-on-Chip™ Document Number: 001-53754 Revision ECN Orig. of Change Submission Date ** 2715097 MASJ 06/08/09 New data sheet. *A 2782580 BTK 10/09/09 Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of some sections to improve consistency. Improved formatting of the register tables. Added clarifying comments to some electrical specifications. Fixed all AC specifications to conform to a ±4% or ±8% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Improved and edited content in Development Tool Selection section. Improved the bookmark structure. Changed FlashENT, VCMOA, the DC POR and LVD specifications, and the DC Analog Reference specifications according to MASJ directives. Added TXRST, DC24M, and 3.3 V DC Operational Amplifier specifications. *B 2822792 BTK / AESA 12/07/09 Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the footnotes of Table 16, “DC Programming Specifications,” on page 26. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Added “Contents” on page 2. *C 2888007 NJF 03/30/10 Updated Cypress website links. Removed reference to PSoC Designer 4.4 in PSoC Designer Software Subsystems Updated The Analog System. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings. Updated AC Chip-Level Specifications. Updated Packaging Information. Removed Third Party Tools and Build a PSoC Emulator into your Board. Updated links in Sales, Solutions, and Legal Information. *D 3272922 BTK/NJF 06/02/11 Updated Figure 8 on page 34 to improve clarity. Updated wording, formatting, and notes of the AC Digital Block Specifications table to improve clarity. Added VDDP, VDDLV, and VDDHV electrical specifications to give more information for programming the device. Updated Solder Reflow Specifications to give more clarity. Updated the jitter specifications. Updated PSoC Device Characteristics table. Updated the F32KU electrical specification. Updated note for RPD electrical specification. Updated note for the TSTG electrical specification to add more clarity. Added Tape and Reel Specifications section. Added CL electrical specification. Updated DC Analog Reference Specifications. Changed “NC” pins on the device to “DNC” pins. Corrected information about the exposed pad to clarify that it is not internally connected. *E 3990974 STHA Description of Change 05/06/2013 Added Errata. Document Number: 001-53754 Rev. *H Page 50 of 52 CY8C24894 Document History Page (continued) Document Title: CY8C24894 Automotive PSoC® Programmable System-on-Chip™ Document Number: 001-53754 Revision ECN Orig. of Change *F 4074455 STHA Submission Date Description of Change 07/23/2013 Added Errata footnotes (Note 5, 7). Updated Electrical Specifications: Updated DC Electrical Characteristics: Updated DC Chip Level Specifications: Added Note 5 and referred the same note in “Sleep Mode” in description of ISB parameter in Table 5. Updated DC POR and LVD Specifications: Added Note 7 and referred the same note in VPPOR0, VPPOR1, VPPOR2 parameters in Table 15. Updated to new template. *G 4398714 KUK 06/05/2014 Removed CY3280-24X94 Universal CapSense Controller Board section. Removed reference to obsolete spec 001-14503 from Reference Documents. *H 4684557 PSI 03/12/2015 Updated Errata. Document Number: 001-53754 Rev. *H Page 51 of 52 CY8C24894 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53754 Rev. *H Revised March 12, 2015 Page 52 of 52 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.