CY8C29466, CY8C29666 ® Automotive PSoC Programmable System-on-Chip™ Features ■ Automotive Electronics Council (AEC) Q100 qualified ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Two 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Automotive temperature range: –40 °C to +85 °C ■ ■ ■ ■ Advanced peripherals (PSoC® blocks) ❐ 12 rail-to-rail analog PSoC blocks provide: • Up to 14-bit analog-to-digital converters (ADCs) • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) • Programmable filters and comparators ❐ 16 digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse width modulators (PWMs) • Cyclic redundancy check (CRC) and pseudo-random sequence (PRS) modules • Full- or half-duplex UART • SPI master or slave • Connectable to all general purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ■ Additional system resources 2 ❐ Inter-Integrated Circuit (I C™) slave, master, or multimaster operation up to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low-voltage detection (LVD) ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ■ Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Logic Block Diagram Port 7 Port 6 Port 5 Port 4 Port 2 Port 1 Port 0 with Analog Drivers PSoC CORE System Bus Global Digital Interconnect Precision, programmable clocking ❐ Internal ±5% 24- and 48-MHz oscillator ❐ High accuracy 24 MHz with optional 32.768 kHz crystal and phase-locked loop (PLL) ❐ Optional external oscillator, up to 24 MHz ❐ Internal low-speed, low-power oscillator for watchdog and sleep functionality SRAM 256 Bytes Global Analog Interconnect SROM Flash 16 KB CPU Core (M8C) Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Flexible on-chip memory ❐ 32 KB flash program storage, 1000 erase/write cycles ❐ 2 KB SRAM data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash DIGITAL SYSTEM ANALOG SYSTEM Digital Block Array Programmable pin configurations ❐ 25 mA sink, 10 mA drive on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open drain drive modes on all GPIOs [1] ❐ Up to 12 analog inputs on GPIOs ❐ Four 30 mA analog outputs on GPIOs ❐ Configurable interrupt on all GPIOs Port 3 Digital Clocks Multiply Accum. Analog Block Array POR and LVD Decimator I2 C System Resets Analog Ref. Analog Input Muxing Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Note 1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the PSoC Technical Reference Manual for more details Cypress Semiconductor Corporation Document Number: 001-12899 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 17, 2015 CY8C29466, CY8C29666 Contents PSoC Functional Overview .............................................. 3 The Digital System ...................................................... 3 The Analog System ..................................................... 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 7 PSoC Designer Software Subsystems ........................ 7 Designing with PSoC Designer ....................................... 8 Select User Modules ................................................... 8 Configure User Modules .............................................. 8 Organize and Connect ................................................ 8 Generate, Verify, and Debug ....................................... 8 Pinouts .............................................................................. 9 28-Pin Part Pinout ...................................................... 9 48-Pin Part Pinout ..................................................... 10 Registers ......................................................................... 11 Register Conventions ................................................ 11 Register Mapping Tables .......................................... 11 Electrical Specifications ................................................ 14 Absolute Maximum Ratings ....................................... 15 Operating Temperature ............................................. 15 Document Number: 001-12899 Rev. *H DC Electrical Characteristics ..................................... 16 AC Electrical Characteristics ..................................... 30 Packaging Information ................................................... 40 Thermal Impedances ................................................. 41 Capacitance on Crystal Pins ..................................... 41 Solder Reflow Specifications ..................................... 41 Tape and Reel Information ........................................ 42 Development Tool Selection ......................................... 44 Software .................................................................... 44 Development Kits ...................................................... 44 Evaluation Tools ........................................................ 44 Device Programmers ................................................. 45 Accessories (Emulation and Programming) .............. 45 Ordering Information ...................................................... 46 Ordering Code Definitions ......................................... 46 Reference Information ................................................... 47 Acronyms .................................................................. 47 Reference Documents ............................................... 47 Document Conventions ............................................. 48 Glossary .................................................................... 48 Document History Page ................................................. 53 Sales, Solutions, and Legal Information ...................... 55 Worldwide Sales and Design Support ....................... 55 Products .................................................................... 55 PSoC® Solutions ...................................................... 55 Cypress Developer Community ................................. 55 Technical Support ..................................................... 55 Page 2 of 55 CY8C29466, CY8C29666 PSoC Functional Overview The PSoC programmable system-on-chip family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global buses allow all the device resources to be combined into a complete custom system. The automotive PSoC CY8C29x66 family can have up to three I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIOs. The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four million instructions per second (MIPS), 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included sleep timer and watchdog timer (WDT). ■ PWMs (8- to 32-bit) ■ PWMs with deadband (8- to 24-bit) ■ Counters (8- to 32-bit) ■ Timers (8- to 32-bit) ■ Full- or half-duplex 8-bit UART with selectable parity ■ SPI master and slave ■ I2C master, slave, or multimaster (implemented in a dedicated I2C block) ■ Cyclic redundancy checker/generator (16-bit) ■ Infrared Data Association (IrDA) ■ PRS generators (8- to 32-bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 1. Digital System Block Diagram Port7 Port5 Port6 Row Input Configuration Digital PSoC Block Array Row0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 Row Input Configuration Row Input Configuration Row Input Configuration 8 Row1 DBB10 DBB11 DCB12 4 DCB13 4 Row2 DBB20 DBB21 DCB22 4 DCB23 4 Row3 DBB30 DBB31 DCB32 4 DCB33 4 GIE[7:0] GIO[7:0] Global Digital Interconnect 8 Row Output Configuration Document Number: 001-12899 Rev. *H DIGITAL SYSTEM Row Output Configuration The digital system is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include those listed here. To Analog System Row Output Configuration The Digital System Port0 Row Output Configuration PSoC GPIOs provide connection to the CPU, digital resources, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt. Port1 Port2 To System Bus Digital Clocks From Core Memory includes 32 KB of flash for program storage and 2 KB of SRAM for data storage. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software intellectual property (IP) protection. The PSoC device incorporates flexible internal clock generators, including a 24-MHz internal main oscillator (IMO) accurate to ±5% over temperature and voltage. A low power 32-kHz internal low-speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is desired, the 32.768-kHz external crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24-MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. Port3 Port4 GOE[7:0] GOO[7:0] Page 3 of 55 CY8C29466, CY8C29666 The analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are as follows: ■ ADCs (up to four, with 6- to 14-bit resolution, selectable as incremental, delta-sigma, or successive approximation register (SAR)) Figure 2. Analog System Block Diagram P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] AGNDIn RefIn The Analog System P2[3] P2[6] ■ Filters (two- and four-pole band pass, low pass, and notch) ■ Amplifiers (up to four, with selectable gain up to 48x) ■ Instrumentation amplifiers (up to two, with selectable gain up to 93x) ■ Comparators (up to four, with 16 selectable thresholds) ■ DACs (up to four, with 6- to 9-bit resolution) ■ Multiplying DACs (up to four, with 6- to 9-bit resolution) ■ High current output drivers (four with 30-mA drive) ■ 1.3-V reference (as a system resource) ■ DTMF Dialer ■ Modulators ■ Correlators ■ Peak Detectors ACB00 ACB01 ACB02 ACB03 ■ Many other topologies possible ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22 ASC23 Analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure 2. P2[4] P2[1] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-12899 Rev. *H Page 4 of 55 CY8C29466, CY8C29666 Additional System Resources ■ System resources, some of which have been previously listed, provide additional capability useful for complete systems. Additional resources include a multiplier, decimator, LVD, and power-on reset (POR). Brief statements describing the merits of each system resource are given below: ■ ■ ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multiplier with 32-bit accumulate to assist in both general math as well as digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of delta-sigma ADCs. The I2C module provides 0 to 400 kHz communication over two wires. Slave, master, and multimaster modes are all supported. ■ LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3-V voltage reference provides an absolute reference for the analog system, including ADCs and DACs. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in Table 1. Table 1. PSoC Device Characteristics PSoC Part Number Digital I/O CY8C29x66[2] up to 64 CY8C28xxx up to 44 Digital Rows Digital Blocks Analog Inputs Analog Outputs 4 16 up to 12 4 up to 3 up to 12 up to 44 up to 4 Analog Columns Analog Blocks SRAM Size Flash Size 4 12 2K 32 K up to 6 up to 12 + 4[3] 1K 16 K CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16 K CY8C24x94[2] up to 56 1 4 up to 48 2 2 6 1K 16 K CY8C24x23A[2] up to 24 1 4 up to 12 2 2 6 256 4K CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K CY8C22x45[2] up to 38 2 8 up to 38 0 4 6[3] 1K 16 K CY8C21x45[2] up to 24 1 4 up to 24 0 4 6[3] 512 8K CY8C21x34[2] up to 28 1 4 up to 28 0 2 4[3] 512 8K CY8C21x23 up to 16 1 4 up to 8 0 2 4[3] 256 4K [3,4] CY8C20x34 [2] CY8C20xx6 up to 28 0 0 up to 28 0 0 3 up to 36 0 0 up to 36 0 0 3[3,4] 512 8K up to 2 K up to 32 K Notes 2. Automotive qualified devices available in this group. 3. Limited analog functionality. 4. Two analog blocks and one CapSense® block. Document Number: 001-12899 Rev. *H Page 5 of 55 CY8C29466, CY8C29666 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. CYPros Consultants For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Application Notes Solutions Library Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Document Number: 001-12899 Rev. *H Page 6 of 55 CY8C29466, CY8C29666 Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration ■ Extensive user module catalog ■ Integrated source-code editor (C and assembly) ■ Free C compiler with no size restrictions or time limits ■ Built-in debugger ■ In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Document Number: 001-12899 Rev. *H Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Page 7 of 55 CY8C29466, CY8C29666 Designing with PSoC Designer The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Document Number: 001-12899 Rev. *H Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Page 8 of 55 CY8C29466, CY8C29666 Pinouts The automotive CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O. However, VSS, VDD, and XRES are not capable of digital I/O. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Type Digital Analog I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I Power I/O I/O I/O I/O 14 Power Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input P1[7] P1[5] P1[3] P1[1] I2C serial clock (SCL) I2C serial data (SDA) VSS 15 I/O P1[0] 16 17 18 19 I/O I/O I/O P1[2] P1[4] P1[6] XRES 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O Input I I I I/O I/O I Power Description P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Figure 3. CY8C29466 28-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] Direct switched capacitor block input Direct switched capacitor block input Ground connection P2[5] AI, P2[3] AI, P2[1] Vss I2C SCL, P1[7] I2C SDA, P1[5] Crystal input (XTALin), I2C serial clock (SCL), ISSP-SCLK[5] Ground connection Crystal output (XTALout), I2C serial data (SDA), ISSP-SDATA[5] P1[3] XTALin, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VREF P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], I2C SDA, XTALout Optional external clock (EXTCLK) input. Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage LEGEND: A = Analog, I = Input, and O = Output. Note 5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details. Document Number: 001-12899 Rev. *H Page 9 of 55 CY8C29466, CY8C29666 48-Pin Part Pinout Table 3. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Type Digital Analog I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 24 Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] VSS P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Power VSS 25 I/O P1[0] 26 27 28 29 30 31 32 33 34 35 I/O I/O I/O I/O I/O I/O I/O I/O I/O Input P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD I I I I/O I/O I Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Figure 4. CY8C29666 48-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] Direct switched capacitor block input Direct switched capacitor block input P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] Ground connection Vss P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C serial clock (SCL) I2C serial data (SDA) Crystal input (XTALin), I2C serial clock (SCL), ISSP-SCLK[6] Ground connection I2C SDA, P1[5] P1[3] XTALin, I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VREF P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], I2C SDA, XTALout Crystal output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[6] Optional external clock (EXTCLK) input Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage LEGEND: A = Analog, I = Input, and O = Output. Note 6. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details. Document Number: 001-12899 Rev. *H Page 10 of 55 CY8C29466, CY8C29666 Registers Register Conventions Register Mapping Tables This section lists the registers of the automotive CY8C29x66 PSoC device. For detailed register information, refer to the PSoC Technical Reference Manual. The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, bank 0 and bank 1. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set to ‘1’, the user is in bank 1. The register conventions specific to this section are listed in the following table. Table 4. Abbreviations Convention R Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Description Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Document Number: 001-12899 Rev. *H Page 11 of 55 CY8C29466, CY8C29666 Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0, Hex) Access Name 00 RW DBB20DR0 01 RW DBB20DR1 02 RW DBB20DR2 03 RW DBB20CR0 04 RW DBB21DR0 05 RW DBB21DR1 06 RW DBB21DR2 07 RW DBB21CR0 08 RW DCB22DR0 09 RW DCB22DR1 0A RW DCB22DR2 0B RW DCB22CR0 0C RW DCB23DR0 0D RW DCB23DR1 0E RW DCB23DR2 0F RW DCB23CR0 10 RW DBB30DR0 11 RW DBB30DR1 12 RW DBB30DR2 13 RW DBB30CR0 14 RW DBB31DR0 15 RW DBB31DR1 16 RW DBB31DR2 17 RW DBB31CR0 18 DCB32DR0 19 DCB32DR1 1A DCB32DR2 1B DCB32CR0 1C DCB33DR0 1D DCB33DR1 1E DCB33DR2 1F DCB33CR0 DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Document Number: 001-12899 Rev. *H Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RL # # Page 12 of 55 CY8C29466, CY8C29666 Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) Access Name 00 RW DBB20FN 01 RW DBB20IN 02 RW DBB20OU 03 RW 04 RW DBB21FN 05 RW DBB21IN 06 RW DBB21OU 07 RW 08 RW DCB22FN 09 RW DCB22IN 0A RW DCB22OU 0B RW 0C RW DCB23FN 0D RW DCB23IN 0E RW DCB23OU 0F RW 10 RW DBB30FN 11 RW DBB30IN 12 RW DBB30OU 13 RW 14 RW DBB31FN 15 RW DBB31IN 16 RW DBB31OU 17 RW 18 DCB32FN 19 DCB32IN 1A DCB32OU 1B 1C DCB33FN 1D DCB33IN 1E DCB33OU 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and should not be accessed. Document Number: 001-12899 Rev. *H Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 RDI3RI C8 RDI3SYN C9 RDI3IS CA RDI3LT0 CB RDI3LT1 CC RDI3RO0 CD RDI3RO1 CE CF GDI_O_IN D0 GDI_E_IN D1 GDI_O_OU D2 GDI_E_OU D3 D4 D5 D6 D7 D8 D9 DA DB DC OSC_GO_EN DD OSC_CR4 DE OSC_CR3 DF OSC_CR0 E0 OSC_CR1 E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 BDG_TR EA ECO_TR EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FLS_PR1 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R W W RW W RL RW # # Page 13 of 55 CY8C29466, CY8C29666 Electrical Specifications This section presents the DC and AC electrical specifications of the automotive CY8C29x66 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by visiting http://www.cypress.com. Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Refer to Table 21 on page 30 for the electrical specifications of the internal main oscillator (IMO) using slow IMO (SLIMO) mode. Figure 5. Voltage versus CPU Frequency Figure 6. IMO Frequency Trim Options 5.25 5.25 lid ing Va rat n pe io O eg R SLIMO Mode = 0 SLIMO Mode = 1 SLIMO Mode = 0 4.75 VDD Voltage (V) VDD Voltage (V) 4.75 SLIMO Mode = 1 3.0 3.6 3.0 0 0 93 kHz 12 MHz CPU Frequency (nominal setting) Document Number: 001-12899 Rev. *H 24 MHz 6 MHz 12 MHz 24 MHz IMO Frequency Page 14 of 55 CY8C29466, CY8C29666 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ 25 – 125 TBAKETEMP Bake temperature tBAKETIME TA VDD VIO VIOZ IMIO IMAIO ESD LU Bake time See package label Ambient temperature with power applied –40 Supply voltage on VDD relative to VSS –0.5 DC input voltage VSS – 0.5 DC voltage applied to tri-state VSS – 0.5 Maximum current into any port pin –25 Maximum current into any port pin configured –50 as analog driver Electrostatic discharge voltage 2000 Latch-up current – Max +100 Units Notes °C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Time spent in storage at a temperature greater than 65 °C counts toward the FlashDR electrical specification in Table 20 on page 29. C – See package label 72 Hours – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 °C V V V mA mA – – – 200 V mA Human body model ESD. Operating Temperature Table 8. Operating Temperature Symbol Description TA Ambient temperature TJ Junction temperature Document Number: 001-12899 Rev. *H Min –40 –40 Typ – – Max +85 +100 Units Notes °C °C The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 41. The user must limit the power consumption to comply with this requirement. Page 15 of 55 CY8C29466, CY8C29666 DC Electrical Characteristics DC Chip-Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 9. DC Chip-Level Specifications Symbol Description VDD Supply voltage Min 3.00 Typ – Max 5.25 IDD Supply current – 8 14 IDD3 Supply current – 5 9 IDDP Supply current when IMO = 6 MHz using SLIMO mode. – 2 3 ISB Sleep (mode) current with POR, LVD, sleep timer, WDT, and ILO active. – 4 25 ISBXTL Sleep (mode) current with POR, LVD, sleep timer, WDT, ILO, and 32-kHz crystal oscillator active. Reference voltage (bandgap) – 4 27 1.28 1.3 1.32 VREF Units Notes V See DC POR and LVD Specifications on page 28. mA Conditions are 5.25 V, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. mA Conditions are VDD = 3.3 V, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. mA Conditions are VDD = 3.3 V, CPU = 3 MHz, 48 MHz disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. A Conditions are with internal low speed oscillator, VDD = 3.3 V, –40 °C TA 85 °C. A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. VDD = 3.3 V, –40 °C TA 85 °C. V Trimmed for appropriate VDD. DC General Purpose I/O Specifications Table 10 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 10. DC GPIO Specifications Symbol Description Pull-up resistor RPU Pull-down resistor RPD Min 4 4 Typ 5.6 5.6 Max 8 8 VOH High output level VDD – 1.0 – – VOL Low output level – – 0.75 IOH High-level source current 10 – – IOL Low-level sink current 25 – – VIL VIH Input low level Input high level – 2.1 – – 0.8 Document Number: 001-12899 Rev. *H Units Notes k k Also applies to the internal pull-down resistor on the XRES pin. V IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. V IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. mA VOH VDD –1.0 V, see the limitations of the total current in the note for VOH mA VOL 0.75 V, see the limitations of the total current in the note for VOL V VDD = 3.0 to 5.25. V VDD = 3.0 to 5.25. Page 16 of 55 CY8C29466, CY8C29666 Table 10. DC GPIO Specifications (continued) Symbol Description VH Input hysteresis IIL Input leakage (absolute value) CIN Capacitive load on pins as input COUT Capacitive load on pins as output Min – – – Typ 60 1 3.5 Max – – 10 – 3.5 10 Units Notes mV nA Gross tested to 1 A. pF Package and pin dependent. TA = 25 °C. pF Package and pin dependent. TA = 25 °C. DC Operational Amplifier Specifications Table 11 and Table 12 on page 18 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The operational amplifier is a component of both the analog CT PSoC blocks and the analog SC PSoC blocks. The guaranteed specifications are measured in the analog CT PSoC block. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Power = high and Opamp bias = high settings are not allowed together for 3.3 V VDD operation. Table 11. 5-V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA CINOA Description Input offset voltage (absolute value) Average input offset voltage drift Input leakage current (Port 0 analog pins) Input capacitance (Port 0 analog pins) Min – – – – Typ 1.6 4.0 200 4.5 Max 10 23.0 – 9.5 Units mV V/°C pA pF VCMOA Common-mode voltage range All cases, except highest Power = high, Opamp bias = high Common-mode rejection ratio 0.0 0.5 60 – – – VDD VDD – 0.5 – V V dB 80 VDD – 0.01 – – – – – – 0.01 dB V V – – – – – – 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – A A A A A A dB CMRROA GOLOA VOHIGHOA VOLOWOA ISOA PSRROA Open loop gain High output voltage swing (internal signals) Low output voltage swing (internal signals) Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Supply voltage rejection ratio Document Number: 001-12899 Rev. *H Notes Gross tested to 1 A. Package and pin dependent. TA = 25 °C. This specification is measured through the analog output buffer and therefore includes the limitations imposed by the characteristics of the analog output buffer. VSS VIN (VDD – 2.25) or (VDD – 1.25 V) VIN VDD Page 17 of 55 CY8C29466, CY8C29666 Table 12. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Min Typ Max Units – 1.4 10 mV Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. TCVOSOA Average input offset voltage drift – 7.0 40.0 V/°C IEBOA Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 A. CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent. TA = 25 °C. VCMOA Common-mode voltage range 0 – VDD V CMRROA Common-mode rejection ratio 60 – – dB GOLOA Open loop gain 80 – – dB VOHIGHOA High output voltage swing (internal signals) VDD – 0.01 – – V VOLOWOA Low output voltage swing (internal signals) – – 0.01 V ISOA PSRROA Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high – – – – – – 150 300 600 1200 2400 – 200 400 800 1600 3200 – A A A A A – Supply voltage rejection ratio 54 80 – dB This specification is measured through the analog output buffer and therefore includes the limitations imposed by the characteristics of the analog output buffer. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation. VSS VIN (VDD – 2.25) or (VDD – 1.25 V) VIN VDD DC Low-Power Comparator Specifications Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 13. DC Low-Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low-power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Document Number: 001-12899 Rev. *H Min 0.2 Typ – Max VDD – 1 Units V – – 10 2.5 40 30 A mV Notes Page 18 of 55 CY8C29466, CY8C29666 DC Analog Output Buffer Specifications Table 14 and Table 15 on page 20 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 14. 5-V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input offset voltage (absolute value) Average input offset voltage drift Common-mode input voltage range Output resistance Power = low Power = high VOHIGHOB High output voltage swing (load = 32 to VDD/2) Power = low Power = high VOLOWOB Low output voltage swing (load = 32 to VDD/2) Power = low Power = high ISOB Supply current including bias cell (no load) Power = low Power = high PSRROB Power supply rejection ratio CL Load capacitance Document Number: 001-12899 Rev. *H Min – – 0.5 Typ 3.2 5.5 – Max 18 26.0 VDD – 1.0 Units mV V/°C V – – – – 1 1 0.5 × VDD + 1.3 0.5 × VDD + 1.3 – – – – V V – – – – 0.5 × VDD – 1.3 0.5 × VDD – 1.3 V V – – 40 – 1.1 2.6 64 – 2 5 – 200 mA mA dB pF Notes This specification applies to the external circuit driven by the analog output buffer. Page 19 of 55 CY8C29466, CY8C29666 Table 15. 3.3-V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB PSRROB CL Description Input offset voltage (absolute value) Power = low Power = high Average input offset voltage drift Power = low Power = high Common-mode input voltage range Output resistance Power = low Power = high High output voltage swing (load = 1 k to VDD/2) Power = low Power = high Low output voltage swing (load = 1 k to VDD/2) Power = low Power = high Supply current including bias cell (no load) Power = low Power = high Power supply rejection ratio Load capacitance Document Number: 001-12899 Rev. *H Min Typ Max Units – – 3.2 6.0 20.0 25.0 mV mV – – 0.5 8.0 12.0 – 32.0 41.0 VDD – 1.0 V/°C V/°C V – – – – 10 10 0.5 × VDD + 1.0 0.5 × VDD + 1.0 – – – – V V – – – – 0.5 × VDD – 1.0 0.5 × VDD – 1.0 V V – – 60 – 0.8 2.0 64 – 1 5 – 200 mA mA dB pF Notes High power setting is not recommended. This specification applies to the external circuit driven by the analog output buffer. Page 20 of 55 CY8C29466, CY8C29666 DC Analog Reference Specifications Table 16 and Table 17 on page 25 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local AGND buffer. Reference control power can be set to medium or high unless otherwise noted. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of the digital signal may appear on the AGND. Table 16. 5-V DC Analog Reference Specifications Reference ARF_CR[5:3] Reference Power Settings Symbol Reference Description Min RefPower = High Opamp bias = High VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.228 VAGND AGND VDD/2 VDD/2 – 0.078 RefPower = High Opamp bias = Low 0b000 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Typ Max Unit VDD/2 + 1.290 VDD/2 + 1.352 VDD/2 – 0.007 VDD/2 + 0.063 V V VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.336 VDD/2 – 1.295 VDD/2 – 1.250 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.224 V VAGND AGND VDD/2 VDD/2 – 0.056 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 – 0.005 VDD/2 + 0.043 VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.338 VDD/2 – 1.298 VDD/2 – 1.255 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.226 V V VAGND AGND VDD/2 VDD/2 – 0.057 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 – 0.006 VDD/2 + 0.044 VREFLO Ref Low VDD/2 – Bandgap VDD/2 – 1.337 VDD/2 – 1.298 VDD/2 – 1.256 V VREFHI Ref High VDD/2 + Bandgap VDD/2 + 1.226 V VDD/2 VDD/2 – 0.047 VDD/2 + 1.294 VDD/2 + 1.359 VDD/2 – 0.004 VDD/2 + 0.035 VDD/2 – Bandgap VDD/2 – 1.338 VDD/2 – 1.299 V VAGND AGND VREFLO Ref Low Document Number: 001-12899 Rev. *H VDD/2 – 1.258 V V Page 21 of 55 CY8C29466, CY8C29666 Table 16. 5-V DC Analog Reference Specifications(continued) Reference ARF_CR[5:3] Reference Power Settings Symbol Reference RefPower = High Opamp bias = High VREFHI Ref High RefPower = High Opamp bias = Low 0b001 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b010 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Description P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) Min Typ Max Unit P2[4] + P2[6] – 0.085 P2[4] + P2[6] – 0.016 P2[4] + P2[6] + 0.044 V P2[4] P2[4] VAGND AGND VREFLO Ref Low P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – 0.022 P2[4] – P2[6] + P2[4] – P2[6] + 0.010 0.055 V VREFHI Ref High P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – 0.077 P2[4] + P2[6] – 0.010 P2[4] + P2[6] + 0.051 V P2[4] P2[4] P2[4] P2[4] – VAGND AGND VREFLO Ref Low P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – 0.022 P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 V VREFHI Ref High P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – 0.070 P2[4] + P2[6] – 0.010 P2[4] + P2[6] + 0.050 V VAGND AGND P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] – P2[6] – 0.022 P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 V VREFHI Ref High P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] – 0.070 P2[4] + P2[6] – 0.007 P2[4] + P2[6] + 0.054 V P2[4] P2[4] P2[4] P2[4] VAGND AGND VREFLO Ref Low P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VREFHI Ref High VDD VAGND AGND P2[4] VDD/2 P2[4] P2[4] P2[4] – P2[6] – 0.022 P2[4] – P2[6] + P2[4] – P2[6] + 0.002 0.032 – – V VDD – 0.037 VDD – 0.009 VDD V VDD/2 – 0.061 VDD/2 – 0.006 VDD/2 + 0.047 V VREFLO Ref Low VSS VSS VSS + 0.007 VSS + 0.028 V VREFHI Ref High VDD VDD – 0.039 VDD – 0.006 VDD V VAGND AGND VDD/2 – 0.049 VDD/2 – 0.005 VDD/2 + 0.036 V VDD/2 VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.019 V VREFHI Ref High VDD VDD – 0.037 VDD – 0.007 VDD V VAGND AGND VDD/2 – 0.054 VDD/2 – 0.005 VDD/2 + 0.041 V VDD/2 VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.024 V VREFHI Ref High VDD VDD – 0.042 VDD – 0.005 VDD V VDD/2 – 0.046 VDD/2 – 0.004 VDD/2 + 0.034 V VSS VSS + 0.004 VSS + 0.017 V VAGND AGND VREFLO Ref Low Document Number: 001-12899 Rev. *H VDD/2 VSS Page 22 of 55 CY8C29466, CY8C29666 Table 16. 5-V DC Analog Reference Specifications(continued) Reference ARF_CR[5:3] Reference Power Settings Symbol Reference RefPower = High Opamp bias = High VREFHI Ref High 3 × Bandgap RefPower = High Opamp bias = Low 0b011 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b100 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Description Min Typ Max Unit 3.788 3.891 3.986 V VAGND AGND 2 × Bandgap 2.500 2.604 2.699 V VREFLO Ref Low Bandgap 1.257 1.306 1.359 V VREFHI Ref High 3 × Bandgap 3.792 3.893 3.982 V 2 × Bandgap 2.518 2.602 2.692 V Bandgap 1.256 1.302 1.354 V VAGND AGND VREFLO Ref Low VREFHI Ref High 3 × Bandgap 3.795 3.894 3.993 V VAGND AGND 2 × Bandgap 2.516 2.603 2.698 V VREFLO Ref Low Bandgap 1.256 1.303 1.353 V VREFHI Ref High 3 × Bandgap 3.792 3.895 3.986 V VAGND AGND 2 × Bandgap 2.522 2.602 2.685 V VREFLO Ref Low Bandgap 1.255 1.301 1.350 V VREFHI Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.495 + P2[6] 2.586 + P2[6] 2.657 + P2[6] V VAGND AGND 2.502 2.604 2.719 V VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.531 – P2[6] 2.611 – P2[6] 2.681 – P2[6] V VREFHI Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.500 + P2[6] 2.591 + P2[6] 2.662 + P2[6] V 2 × Bandgap VAGND AGND 2.519 2.602 2.693 V VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.530 – P2[6] 2.605 – P2[6] 2.666 – P2[6] V VREFHI Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.503 + P2[6] 2.592 + P2[6] 2.662 + P2[6] V 2 × Bandgap VAGND AGND 2.517 2.603 2.698 V VREFLO Ref Low 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2.529 – P2[6] 2.606 – P2[6] 2.665 – P2[6] V VREFHI Ref High 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2.505 + P2[6] 2.594 + P2[6] 2.665 + P2[6] V VAGND AGND 2.525 2.602 2.685 V VREFLO Ref Low 2.528 – P2[6] 2.603 – P2[6] 2.661 – P2[6] V Document Number: 001-12899 Rev. *H 2 × Bandgap 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) Page 23 of 55 CY8C29466, CY8C29666 Table 16. 5-V DC Analog Reference Specifications(continued) Reference ARF_CR[5:3] Reference Power Settings Symbol Reference RefPower = High Opamp bias = High VREFHI Ref High VAGND AGND VREFLO Ref Low VREFHI Ref High RefPower = High Opamp bias = Low 0b101 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b110 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b111 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Description Min Typ Max Unit P2[4] + 1.222 P2[4] + 1.290 P2[4] + 1.343 V P2[4] P2[4] P2[4] – P2[4] – Bandgap (P2[4] = VDD/2) P2[4] – 1.331 P2[4] – 1.295 P2[4] – 1.254 V P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.226 P2[4] + 1.293 P2[4] + 1.347 V P2[4] + Bandgap (P2[4] = VDD/2) P2[4] VAGND AGND P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] P2[4] – 1.331 P2[4] – 1.298 P2[4] – 1.259 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.227 P2[4] + 1.294 P2[4] + 1.347 V VAGND AGND P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – Bandgap (P2[4] = VDD/2) P2[4] P2[4] – 1.331 P2[4] – 1.298 P2[4] – 1.259 V VREFHI Ref High P2[4] + Bandgap (P2[4] = VDD/2) P2[4] + 1.228 P2[4] + 1.295 P2[4] + 1.349 V VAGND AGND P2[4] P2[4] P2[4] – VREFLO Ref Low P2[4] – 1.332 P2[4] – 1.299 P2[4] – 1.260 V VREFHI Ref High VAGND AGND P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap 2.535 2.598 2.644 V Bandgap 1.227 1.305 1.398 V V VREFLO Ref Low VSS VSS VSS + 0.009 VSS + 0.038 VREFHI Ref High 2 × Bandgap 2.530 2.598 2.643 V VAGND AGND Bandgap 1.244 1.303 1.370 V V VREFLO Ref Low VSS VSS VSS + 0.005 VSS + 0.024 VREFHI Ref High 2 × Bandgap 2.532 2.598 2.644 V VAGND AGND Bandgap 1.239 1.304 1.380 V VREFLO Ref Low VSS VSS VSS + 0.006 VSS + 0.026 V VREFHI Ref High 2 × Bandgap 2.528 2.598 2.645 V Bandgap 1.249 1.302 1.362 V VSS VSS + 0.004 VSS + 0.018 V 4.155 4.234 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 3.2 × Bandgap 4.041 1.6 × Bandgap 1.998 2.083 2.183 V VSS VSS + 0.010 VSS + 0.038 V 4.153 4.236 V VAGND AGND VREFLO Ref Low VSS VREFHI Ref High 3.2 × Bandgap 4.047 1.6 × Bandgap 2.012 2.082 2.157 V VSS VSS + 0.006 VSS + 0.024 V VAGND AGND VREFLO Ref Low VREFHI Ref High 3.2 × Bandgap 4.049 4.154 4.238 V VAGND AGND 1.6 × Bandgap 2.008 2.083 2.165 V VREFLO Ref Low VSS VSS + 0.006 VSS + 0.026 V VREFHI Ref High 3.2 × Bandgap 4.047 4.154 4.238 V VAGND AGND 1.6 × Bandgap 2.016 2.081 2.150 V VREFLO Ref Low VSS VSS + 0.004 VSS + 0.018 V Document Number: 001-12899 Rev. *H VSS VSS VSS Page 24 of 55 CY8C29466, CY8C29666 Table 17. 3.3-V DC Analog Reference Specifications Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b000 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low RefPower = High Opamp bias = High Symbol Reference Description Min Typ Max Unit VDD/2 + BandGap VDD/2 + 1.225 VDD/2 + 1.292 VDD/2 + 1.361 V VDD/2 VDD/2 – 0.067 VDD/2 – 0.002 VDD/2 + 0.063 V VREFHI Ref High VAGND AGND VREFLO Ref Low VDD/2 – BandGap VDD/2 – 1.35 VDD/2 – 1.293 VDD/2 – 1.210 V VREFHI Ref High VDD/2 + BandGap VDD/2 + 1.218 VDD/2 + 1.294 VDD/2 + 1.370 V VAGND AGND VDD/2 VDD/2 – 0.038 VDD/2 – 0.001 VDD/2 + 0.035 V VREFLO Ref Low VDD/2 – BandGap VDD/2 – 1.329 VDD/2 – 1.296 VDD/2 – 1.259 V VREFHI Ref High VDD/2 + BandGap VDD/2 + 1.221 VDD/2 + 1.294 VDD/2 + 1.366 V VAGND AGND VDD/2 VDD/2 – 0.050 VDD/2 – 0.002 VDD/2 + 0.046 V VREFLO Ref Low VDD/2 – BandGap VDD/2 – 1.331 VDD/2 – 1.296 VDD/2 – 1.260 V VREFHI Ref High VDD/2 + BandGap VDD/2 + 1.226 VDD/2 + 1.295 VDD/2 + 1.365 V VAGND AGND VDD/2 VDD/2 – 0.028 VDD/2 – 0.001 VDD/2 + 0.025 V VREFLO Ref Low VDD/2 – BandGap VDD/2 – 1.329 VDD/2 – 1.297 VDD/2 – 1.262 V VREFHI Ref High P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.098 0.018 0.055 V VAGND AGND VREFLO Ref Low P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + = VDD/2, P2[6] = 0.055 0.013 0.086 VREFHI Ref High P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + = VDD/2, P2[6] = 0.082 0.011 0.050 0.5 V) P2[4] P2[4] P2[4] P2[4] – V 0.5 V) RefPower = High Opamp bias = Low V 0.5 V) VAGND AGND VREFLO Ref Low VREFHI Ref High VAGND AGND VREFLO Ref Low VREFHI Ref High VAGND AGND VREFLO Ref Low P2[4] P2[4] P2[4] P2[4] P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + = VDD/2, P2[6] = 0.037 0.006 0.054 – V 0.5 V) 0b001 RefPower = Med Opamp bias = High P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + = VDD/2, P2[6] = 0.079 0.012 0.047 V 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = P2[4] P2[4] P2[4] – P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.038 0.006 0.057 V P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.080 0.008 0.055 V 0.5 V) RefPower = Med Opamp bias = Low P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.032 0.003 0.042 – V 0.5 V) Document Number: 001-12899 Rev. *H Page 25 of 55 CY8C29466, CY8C29666 Table 17. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b010 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Symbol Reference Description Min Typ Max Unit VDD – 0.06 VDD – 0.010 VDD V VDD/2 – 0.05 VDD/2 – 0.002 VDD/2 + 0.040 V VREFHI Ref High VAGND AGND VREFLO Ref Low Vss Vss Vss + 0.009 Vss + 0.056 V VREFHI Ref High VDD VDD – 0.060 VDD – 0.006 VDD V VAGND AGND VDD/2 – 0.028 VDD/2 – 0.001 VDD/2 + 0.025 V VREFLO Ref Low Vss Vss Vss + 0.005 Vss + 0.034 V VREFHI Ref High VDD VDD – 0.058 VDD – 0.008 VDD V VAGND AGND VDD/2 – 0.037 VDD/2 – 0.002 VDD/2 + 0.033 V VREFLO Ref Low Vss Vss Vss + 0.007 Vss + 0.046 V VREFHI Ref High VDD VDD – 0.057 VDD – 0.006 VDD V VAGND AGND VDD/2 – 0.025 VDD/2 – 0.001 VDD/2 + 0.022 V VDD VDD/2 VDD/2 VDD/2 VDD/2 VREFLO Ref Low 0b011 All power settings. Not allowed for 3.3 V – – – Vss – Vss + 0.004 – Vss + 0.030 – V – 0b100 All power settings. Not allowed for 3.3 V – – – – – – – VREFHI Ref High P2[4] + 1.213 P2[4] + 1.291 P2[4] + 1.367 V VAGND AGND P2[4] P2[4] P2[4] V VREFLO Ref Low P2[4] – BandGap (P2[4] = VDD/2) P2[4] – 1.333 P2[4] – 1.294 P2[4] – 1.208 V VREFHI Ref High P2[4] + BandGap (P2[4] = VDD/2) P2[4] + 1.217 P2[4] + 1.294 P2[4] + 1.368 V P2[4] P2[4] P2[4] V RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b101 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Vss P2[4] + BandGap (P2[4] = VDD/2) P2[4] VAGND AGND VREFLO Ref Low P2[4] – BandGap (P2[4] = VDD/2) P2[4] – 1.320 P2[4] – 1.296 P2[4] – 1.261 V VREFHI Ref High P2[4] + BandGap (P2[4] = VDD/2) P2[4] + 1.217 P2[4] + 1.294 P2[4] + 1.369 V VAGND AGND P2[4] P2[4] P2[4] V VREFLO Ref Low P2[4] – BandGap (P2[4] = VDD/2) P2[4] – 1.322 P2[4] – 1.297 P2[4] – 1.262 V VREFHI Ref High P2[4] + BandGap (P2[4] = VDD/2) P2[4] + 1.219 P2[4] + 1.295 P2[4] + 1.37 V P2[4] P2[4] P2[4] V P2[4] – 1.324 P2[4] – 1.297 P2[4] – 1.262 V VAGND AGND VREFLO Ref Low Document Number: 001-12899 Rev. *H P2[4] P2[4] P2[4] P2[4] – BandGap (P2[4] = VDD/2) Page 26 of 55 CY8C29466, CY8C29666 Table 17. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High RefPower = High Opamp bias = Low 0b110 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low 0b111 Symbol Reference VREFHI Ref High VAGND AGND Description Min Typ Max Unit 2 × BandGap 2.507 2.598 2.698 V BandGap 1.203 1.307 1.424 V Vss Vss + 0.012 Vss + 0.067 V VREFLO Ref Low Vss VREFHI Ref High 2 × BandGap 2.516 2.598 2.683 V VAGND AGND BandGap 1.241 1.303 1.376 V VREFLO Ref Low Vss Vss Vss + 0.007 Vss + 0.040 V VREFHI Ref High 2 × BandGap 2.510 2.599 2.693 V VAGND AGND BandGap 1.240 1.305 1.374 V VREFLO Ref Low Vss Vss Vss + 0.008 Vss + 0.048 V VREFHI Ref High 2 × BandGap 2.515 2.598 2.683 V BandGap 1.258 1.302 1.355 V Vss – Vss + 0.005 – Vss + 0.03 – V – VAGND AGND VREFLO Ref Low – – All power settings. Not allowed for 3.3 V. Vss – DC Analog PSoC Block Specifications Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 18. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switch cap) Document Number: 001-12899 Rev. *H Min – – Typ 12.2 80 Max – – Units k fF Notes Page 27 of 55 CY8C29466, CY8C29666 DC POR and LVD Specifications Table 19 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 19. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Min Typ Max Units PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b – – – 2.82 4.39 4.55 – – – V V V PPOR hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b – – – 92 0 0 – – – mV mV mV 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98[7] 3.08 3.20 4.08 4.57 4.74[8] 4.82 4.91 V V V V V V V V VDD value for PPOR trip (negative ramp) VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Notes Notes 7. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 8. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-12899 Rev. *H Page 28 of 55 CY8C29466, CY8C29666 DC Programming Specifications Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 20. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5.0 Max 5.5 Units V VDDLV Low VDD for verify 3.0 3.1 3.2 V VDDHV High VDD for verify 5.1 5.2 5.3 V 3.0 – 5.25 V 10 – – – 30 0.8 – 0.2 mA V V mA – 1.5 mA – 0.75 V – VDD V – – – – – – – – Years VDDIWRITE Supply voltage for flash write operation IDDP VILP VIHP IILP Supply current during programming or verify – Input low voltage during programming or verify – Input high voltage during programming or verify 2.1 Input current when applying VILP to P1[0] or – P1[1] during programming or verify IIHP Input current when applying VIHP to P1[0] or – P1[1] during programming or verify VOLV Output low voltage during programming or – verify VOHV Output high voltage during programming or VDD – 1.0 verify FlashENPB Flash endurance (per block)[9, 10] 1,000 FlashENT Flash endurance (total)[10, 11] 512,000 FlashDR Flash data retention 15 Notes This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to this device when it is executing internal flash writes. Driving internal pull-down resistor. Driving internal pull-down resistor. Erase/write cycles per block. Erase/write cycles. Notes 9. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 10. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. 11. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. Document Number: 001-12899 Rev. *H Page 29 of 55 CY8C29466, CY8C29666 AC Electrical Characteristics AC Chip-Level Specifications Table 21 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40°C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 21. AC Chip-Level Specifications Symbol FIMO24 Description IMO frequency for 24 MHz Min 22.8[12] Typ 24 Max 25.2[12] Units MHz FIMO6 IMO frequency for 6 MHz 5.5[12] 6 6.5[12] MHz FCPU1 CPU frequency (5 V nominal) 0.089[12] – 25.2[12] MHz FCPU2 CPU frequency (3.3 V nominal) 0.089[12] – 12.6[12] MHz FBLK5 0 – 50.4[12,13] MHz 0 – 25.2[12,13] MHz F32K1 Digital PSoC block frequency (5 V VDD nominal) Digital PSoC block frequency (3.3 V VDD nominal) ILO frequency 15 32 64 kHz F32KU ILO untrimmed frequency 5 – 100 kHz F32K2 ECO frequency – 32.768 – kHz FPLL PLL frequency – 23.986 – MHz tPLLSLEW tPLLSLEWLOW tOS tOSACC PLL lock time PLL lock time for low gain setting ECO startup to 1% ECO startup to 100 ppm 0.5 0.5 – – – – 250 300 10 50 500 600 ms ms ms ms tXRST DC24M DCILO Step24M Fout48M FMAX External reset pulse width 24 MHz duty cycle ILO duty cycle 24 MHz trim step size 48 MHz output frequency Maximum frequency of signal on row input or row output. Power supply slew rate Time between end of POR state and CPU code execution 10 40 20 – 45.6 [12] – – 50 50 50 48.0 – – 60 80 – 50.4 [12] 12.6[12] s % % kHz MHz MHz – – – 16 250 100 V/ms ms FBLK33 SRPOWERUP tPOWERUP Notes Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 5 on page 14. SLIMO mode = 0. Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 5 on page 14. SLIMO mode = 1. 4.75 V VDD 5.25 V. SLIMO mode = 0. 3.0 V VDD 3.6 V. SLIMO mode = 0. Refer to AC Digital Block Specifications on page 35. Refer to AC Digital Block Specifications on page 35. This specification applies when the ILO has been trimmed. After a reset and before the M8C processor starts to execute, the ILO is not trimmed. Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. Refer to Figure 7 on page 31. Refer to Figure 8 on page 31. Refer to Figure 9 on page 31. The ECO frequency is within 100 ppm of its final value by the end of the tOSACC period. Correct operation assumes a properly loaded 1-µW maximum drive level, 32.768-kHz crystal. VDD slew rate during power up. Power up from 0 V. Notes 12. Accuracy derived from IMO with appropriate trim for VDD range. 13. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-12899 Rev. *H Page 30 of 55 CY8C29466, CY8C29666 Table 21. AC Chip-Level Specifications (continued) Symbol tJIT_IMO[14] tJIT_PLL[14] Description 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) PLL cycle-to-cycle jitter (RMS) PLL long term N cycle-to-cycle jitter (RMS) PLL period jitter (RMS) Min – Typ 200 Max 700 Units ps Notes – 300 900 ps N = 32 – – – 100 200 300 400 800 1200 ps ps ps N = 32 – 100 700 ps Figure 7. PLL Lock Timing Diagram PLL Enable tPLLSLEW T PLLSLEW 24 MHz FPLL PLL Gain 0 Figure 8. PLL Lock for Low Gain Setting Timing Diagram PLL Enable tPLLSLEWLOW T PLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 9. External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz TtOS OS F32K2 Note 14. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 001-12899 Rev. *H Page 31 of 55 CY8C29466, CY8C29666 AC GPIO Specifications Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 22. AC GPIO Specifications Symbol FGPIO tRISEF tFALLF tRISES tFALLS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12.6[15] 18 18 – – Units MHz ns ns ns ns Notes Normal strong mode VDD = 4.75 to 5.25 V, 10% - 90% VDD = 4.75 to 5.25 V, 10% - 90% VDD = 3 to 5.25 V, 10% - 90% VDD = 3 to 5.25 V, 10% - 90% Figure 10. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISEF tRISES tFALLF tFALLS Note 15. Accuracy derived from IMO with appropriate trim for VDD range. Document Number: 001-12899 Rev. *H Page 32 of 55 CY8C29466, CY8C29666 AC Operational Amplifier Specifications Table 23 and Table 24 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog CT PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V. Table 23. 5-V AC Operational Amplifier Specifications Symbol Description tROA Rising settling time to 0.1% for a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high tSOA Falling settling time to 0.1% for a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high SRROA Rising slew rate (20% to 80%) of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high SRFOA Falling slew rate (80% to 20%) of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high BWOA Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high ENOA Noise at 1 kHz (Power = medium, Opamp bias = high) Min Typ Max Units – – – – – – 3.9 0.72 0.62 s s s – – – – – – 5.9 0.92 0.72 s s s 0.15 1.7 6.5 – – – – – – V/s V/s V/s 0.01 0.5 4.0 – – – – – – V/s V/s V/s 0.75 3.1 5.4 – – – – 100 – – – – MHz MHz MHz nV/rt-Hz Min Typ Max Units – – – – 3.92 0.72 s s – – – – 5.41 0.72 s s 0.31 2.7 – – – – V/s V/s 0.24 1.8 – – – – V/s V/s 0.67 2.8 – – – 100 – – – MHz MHz nV/rt-Hz Notes Table 24. 3.3-V AC Operational Amplifier Specifications Symbol Description tROA Rising settling time to 0.1% of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high tSOA Falling settling time to 0.1% of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high SRROA Rising slew rate (20% to 80%) of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high SRFOA Falling slew rate (80% to 20%) of a 1-V step (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high BWOA Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) ENOA Document Number: 001-12899 Rev. *H Notes Page 33 of 55 CY8C29466, CY8C29666 When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor. Figure 11. Typical AGND Noise with P2[4] Bypass nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 12. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 Document Number: 001-12899 Rev. *H 0.01 0.1 Freq (kHz) 1 10 100 Page 34 of 55 CY8C29466, CY8C29666 AC Low-Power Comparator Specifications Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 25. AC Low-Power Comparator Specifications Symbol tRLPC Description LPC response time Min – Typ – Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC. AC Digital Block Specifications Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 26. AC Digital Block Specifications Function All functions Timer Counter Dead Band CRCPRS (PRS Mode) Description Block input clock frequency VDD 4.75 V VDD < 4.75 V Input clock frequency No capture, VDD 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Input clock frequency No enable input, VDD 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD 4.75 V VDD < 4.75 V Input clock frequency VDD 4.75 V VDD < 4.75 V Input clock frequency CRCPRS (CRC Mode) SPIM Input clock frequency SPIS Transmitter Input clock (SCLK) frequency Width of SS_Negated between transmissions Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Min Typ Max Units Notes – – – – 50.4[17] 25.2[17] MHz MHz – – – 50[16] – – – – 50.4[17] 25.2[17] 25.2[17] – MHz MHz MHz ns – – – 50[16] – – – – 50.4[17] 25.2[17] 25.2[17] – MHz MHz MHz ns 20 50[16] 50[16] – – – – – – ns ns ns – – – – 50.4[17] 25.2[17] MHz MHz – – – – – – 50.4[17] 25.2[17] 25.2[17] MHz MHz MHz – – 8.4[17] – – 4.2[17] 50[16] – – – – – – – – 50.4[17] 25.2[17] 25.2[17] MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. MHz The input clock is the SPI SCLK in SPIS mode. ns The baud rate is equal to the input MHz clock frequency divided by 8. MHz MHz Notes 16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). 17. Accuracy derived from IMO with appropriate trim for VDD range. Document Number: 001-12899 Rev. *H Page 35 of 55 CY8C29466, CY8C29666 Table 26. AC Digital Block Specifications (continued) Function Receiver Description Input clock frequency VDD 4.75 V, 2 stop bits VDD 4.75 V, 1 stop bit VDD < 4.75 V Min Typ Max Units – – – – – – 50.4[18] 25.2[18] 25.2[18] Notes The baud rate is equal to the input MHz clock frequency divided by 8. MHz MHz AC Analog Output Buffer Specifications Table 27 and Table 28 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 27. 5-V AC Analog Output Buffer Specifications Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1-V step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1-V step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1-V step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1-V step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min Typ Max Units – – – – 4 4 s s – – – – 3.4 3.4 s s 0.5 0.5 – – – – V/s V/s 0.55 0.55 – – – – V/s V/s 0.8 0.8 – – – – MHz MHz 300 300 – – – – kHz kHz Min Typ Max Units – – – – 4.7 4.7 s s – – – – 4 4 s s 0.36 0.36 – – – – V/s V/s 0.4 0.4 – – – – V/s V/s 0.7 0.7 – – – – MHz MHz 200 200 – – – – kHz kHz Notes Table 28. 3.3-V AC Analog Output Buffer Specifications Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1-V step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1-V step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1-V step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1-V step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Notes Note 18. Accuracy derived from IMO with appropriate trim for VDD range. Document Number: 001-12899 Rev. *H Page 36 of 55 CY8C29466, CY8C29666 AC External Clock Specifications Table 29 and Table 30 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 29. 5-V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency 0.093 – 24.6 MHz – High period 20.6 – 5300 ns – Low period 20.6 – – ns – Power-up IMO to switch 150 – – s Min Typ Max Units Notes Table 30. 3.3-V AC External Clock Specifications Symbol Description FOSCEXT Frequency with CPU clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. FOSCEXT Frequency with CPU clock divide by 2 or greater 0.093 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. – High period with CPU Clock divide by 1 41.7 – 5300 ns – Low period with CPU Clock divide by 1 41.7 – – ns – Power-up IMO to switch 150 – – s Document Number: 001-12899 Rev. *H Page 37 of 55 CY8C29466, CY8C29666 AC Programming Specifications Table 31 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 31. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tPRGH tPRGC Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Total flash block program time (tERASEB + tWRITE), hot Total flash block program time (tERASEB + tWRITE), cold Min 1 1 40 40 0 – – – – – Typ – – – – – 10 40 – – – Max 20 20 – – 8 40[19] 160[19] 45 50 100[19] Units ns ns ns ns MHz ms ms ns ns ms – – 200[19] ms Notes VDD 3.6 3.0 VDD 3.6 TJ 0 °C TJ 0 °C Note 19. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information. Document Number: 001-12899 Rev. *H Page 38 of 55 CY8C29466, CY8C29666 AC I2C Specifications Table 32 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus-free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100[20] 4.0 – Fast Mode Min Max 0 400[20] 0.6 – Units Notes kHz s 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – 1.3 0.6 0.6 0 100[21] 0.6 1.3 – – – – – – – s s s s ns s s – – 0 50 ns Figure 13. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA tSUDATI2C tSPI2C tHDDATI2C tSUSTAI2C tHDSTAI2C tBUFI2C I2C_SCL tHIGHI2C S START Condition tLOWI2C tSUSTOI2C Sr Repeated START Condition P S STOP Condition Notes 20. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-12899 Rev. *H Page 39 of 55 CY8C29466, CY8C29666 Packaging Information This section illustrates the packaging specifications for the automotive CY8C29x66 PSoC device, along with the thermal impedances and solder reflow for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 14. 28-Pin (210-Mil) SSOP 51-85079 *F Document Number: 001-12899 Rev. *H Page 40 of 55 CY8C29466, CY8C29666 Figure 15. 48-Pin (300-Mil) SSOP 51-85061 *F Thermal Impedances Capacitance on Crystal Pins Table 33. Thermal Impedances per Package Typical JA Package Table 34. Typical Package Capacitance on Crystal Pins [22] Package Package Capacitance 28-pin SSOP 94 °C/W 28-pin SSOP 2.8 pF 48-pin SSOP 69 °C/W 48-pin SSOP 3.3 pF Solder Reflow Specifications Table 35 shows the solder reflow temperature limits that must not be exceeded. Table 35. Solder Reflow Specifications Package Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 28-pin SSOP 260 °C 30 seconds 48-pin SSOP 260 °C 30 seconds Note 22. TJ = TA + Power × JA . Document Number: 001-12899 Rev. *H Page 41 of 55 CY8C29466, CY8C29666 Tape and Reel Information Figure 16. 28-Pin SSOP Carrier Tape Drawing 51-51100 *D Document Number: 001-12899 Rev. *H Page 42 of 55 CY8C29466, CY8C29666 Figure 17. 48-Pin SSOP Carrier Tape Drawing 51-51104 *E Table 36. Tape and Reel Specifications Package Cover Tape Width (mm) Hub Size (inches) Minimum Leading Empty Pockets 28-Pin SSOP 48-Pin SSOP 13.3 25.5 7 4 42 32 Document Number: 001-12899 Rev. *H Minimum Trailing Empty Pockets 25 19 Standard Full Reel Quantity 1000 1000 Page 43 of 55 CY8C29466, CY8C29666 Development Tool Selection This section presents the development tools available for the CY8C29x66 family. Software Evaluation Tools PSoC Designer All evaluation tools can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ Evaluation board with LCD module ■ MiniProg programming unit ■ 28-pin CY8C29466-24PXI PDIP PSoC device sample (2) Development Kits ■ PSoC Designer software CD All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. ■ Getting Started guide ■ USB 2.0 cable CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes: ■ ICE-Cube unit ■ 28-pin PDIP emulation pod for CY8C29466-24PXI ■ 28-pin CY8C29466-24PXI PDIP PSoC device samples (two) ■ PSoC Designer software CD ■ ISSP cable ■ MiniEval socket programming and evaluation board ■ Backward compatibility cable (for connecting to legacy pods) ■ Universal 110/220 power supply (12 V) ■ European plug adapter ■ USB 2.0 cable ■ Getting Started guide ■ Development kit registration form Document Number: 001-12899 Rev. *H CY3210-29X66 Evaluation Pod (EvalPod) PSoC EvalPods are pods that connect to the ICE (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-29X66 provides evaluation of the CY8C29x66 PSoC device family. Page 44 of 55 CY8C29466, CY8C29666 Device Programmers CY3207ISSP In-System Serial Programmer (ISSP) All device programmers can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes: ■ CY3207 programmer unit ■ MiniProg programming unit ■ PSoC ISSP software CD ■ MiniEval socket programming and evaluation board ■ 110 ~ 240-V power supply, Euro-Plug adapter ■ 28-pin CY8C29466-24PXI PDIP PSoC device sample ■ USB 2.0 cable ■ PSoC Designer software CD ■ Getting Started guide ■ USB 2.0 cable Accessories (Emulation and Programming) Table 37. Emulation and Programming Accessories Part Number Pin Package Pod Kit[23] Foot Kit[24] Adapter[25] CY8C29466-24PVXA 28-pin SSOP CY3250-29XXX CY3250-28SSOP-FK AS-28-28-02SS-6ENP-GANG CY8C29666-24PVXA 48-pin SSOP CY3250-29XXX CY3250-48SSOP-FK AS-48-48-01SS-6-GANG Notes 23. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 24. Foot kit includes surface mount feet that can be soldered to the target PCB. 25. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are available at http://www.emulation.com. Document Number: 001-12899 Rev. *H Page 45 of 55 CY8C29466, CY8C29666 Ordering Information The following table lists the automotive CY8C29x66 PSoC devices’ key package features and ordering codes. Flash (KB) RAM (KB) Temperature Range Digital PSoC Blocks Analog PSoC Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin CY8C29466-24PVXA CY8C29466-24PVXAT 32 32 2 2 –40 °C to +85 °C –40 °C to +85 °C 16 16 12 12 24 24 12[26] 12[26] 4 4 Yes Yes CY8C29666-24PVXA CY8C29666-24PVXAT 32 32 2 2 –40 °C to +85 °C –40 °C to +85 °C 16 16 12 12 44 44 12[26] 12[26] 4 4 Yes Yes Package Ordering Code Table 38. CY8C29x66 Automotive PSoC Device Key Features and Ordering Information 28-pin (210-Mil) SSOP 28-pin (210-Mil) SSOP (tape and reel) 48-pin (300-Mil) SSOP 48-pin (300-Mil) SSOP (tape and reel) Ordering Code Definitions CY 8 C 29 xxx-SPxx Package type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LTX = QFN Pb-free AX = TQFP Pb-free Thermal Rating: A = Automotive -40 °C to +85 °C C = Commercial E = Automotive Extended -40 °C to +125 °C I = Industrial CPU speed: 24 MHz Part number Family code Technology code: C = CMOS Marketing code: 8 = PSoC Company ID: CY = Cypress Note 26. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the PSoC Technical Reference Manual for more details Document Number: 001-12899 Rev. *H Page 46 of 55 CY8C29466, CY8C29666 Reference Information Acronyms The following table lists the acronyms that are used in this document. Table 39. Acronyms Used in this Datasheet Acronym Description Acronym Description AC alternating current LVD low-voltage detect ADC analog-to-digital converter MAC multiply accumulate AEC Automotive Electronics Council MCU microcontroller unit API application programming interface MIPS million instructions per second CMOS complementary metal oxide semiconductor PCB printed circuit board CPU central processing unit PDIP plastic dual-in-line package CRC cyclic redundancy check PGA programmable gain amplifier CT continuous time PLL phase-locked loop DAC digital-to-analog converter POR power-on reset DC direct current PPOR precision POR DTMF dual-tone multi-frequency PRS pseudo-random sequence ECO external crystal oscillator PSoC® Programmable System-on-Chip EEPROM electrically erasable programmable read-only memory PWM pulse-width modulator GPIO general-purpose I/O RTC real time clock I/O input/output SAR successive approximation register ICE in-circuit emulator SC switched capacitor IDE integrated development environment SLIMO slow IMO I2C inter-integrated circuit SPI serial peripheral interface ILO internal low-speed oscillator SRAM static random-access memory IMO internal main oscillator SROM supervisory read-only memory IP intellectual property SSOP shrink small-outline package IrDA infrared data association UART universal asynchronous receiver transmitter ISSP in-system serial programming USB universal serial bus LCD liquid crystal display WDT watchdog timer LED light-emitting diode XRES external reset LPC low power comparator Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Understanding Data Sheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Document Number: 001-12899 Rev. *H Page 47 of 55 CY8C29466, CY8C29666 Document Conventions Units of Measure The following table lists the units of measure that are used in this document. Table 40. Units of Measure Symbol dB C fF kHz k MHz µA µs µV µW mA mm ms mV Unit of Measure decibel degree Celsius femto-farad kilohertz kilohm megahertz microampere microsecond microvolt microwatt milliampere millimeter millisecond millivolt Symbol mVpp nA ns nV ppm % pF ps pA rt-Hz V W Unit of Measure millivolts peak-to-peak nanoampere nanosecond nanovolt ohm parts per million percent picofarad picosecond pikoampere root hertz volt watt Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. analog-to-digital converter (ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation. Application programming interface (API) A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. Document Number: 001-12899 Rev. *H Page 48 of 55 CY8C29466, CY8C29666 Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler A program that translates a high level language, such as C, into machine language. configuration space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. debugger A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition. digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. digital-to-analog converter (DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital converter (ADC) performs the reverse operation. Document Number: 001-12899 Rev. *H Page 49 of 55 CY8C29466, CY8C29666 Glossary (continued) duty cycle The relationship of a clock period high time to its low time, expressed as a percent. emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency The number of cycles or events per unit of time, for a periodic function. gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at the VDD supply voltage and pulled high with resistors. The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode. ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (ISR) A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the flash, SRAM, and register space. master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. Document Number: 001-12899 Rev. *H Page 50 of 55 CY8C29466, CY8C29666 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal The reference to a circuit containing both analog and digital techniques and components. modulator A device that imposes a signal on a carrier. noise 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. oscillator A circuit that may be crystal controlled and is used to generate a clock frequency. parity A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. port A group of pins, usually eight. power-on reset (POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied value. modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. register A storage device with a specific capacity, such as a bit or byte. reset A means of bringing a system back to a known state. See hardware reset and software reset. ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. Document Number: 001-12899 Rev. *H Page 51 of 55 CY8C29466, CY8C29666 Glossary (continued) shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code, operating from flash. stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level analog and digital PSoC blocks. User modules also provide high level API (Application Programming Interface) for the peripheral function. user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. VDD A name for a power net meaning "voltage drain". The most positive power supply signal. Usually 5 V or 3.3 V. VSS A name for a power net meaning "voltage source." The most negative power supply signal. watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. Document Number: 001-12899 Rev. *H Page 52 of 55 CY8C29466, CY8C29666 Document History Page Document Title: CY8C29466, CY8C29666 Automotive PSoC® Programmable System-on-Chip™ Document Number: 001-12899 Revision ECN Orig. of Change Submission Date Description of Change ** 772096 HMT See ECN New silicon, new document (Revision **). *A 2697720 VIVG/ PYRS 04/24/09 Updated template Content edits *B 2769233 BTK 09/25/09 Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of some sections for added clarity. Improved formatting of the register tables. Added clarifying comments to some electrical specifications. Changed TRAMP specification per MASJ input. Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block connections. Updated the Development Tool Selection section. Improved the bookmark structure. Edited FIMO6, TERASEB, TWRITE, TRSCLK, TFSCLK, VIHP, VPPORxR, and 5 V RefLo specifications according to MASJ input. Removed ‘TM’ from Programmable System-on-Chip in the title. *C 2822792 BTK/ AESA 12/07/2009 Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the footnotes for the DC Programming Specifications table. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Added “Contents” on page 2. *D 2888007 NJF 03/30/2010 Updated Cypress website links. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings Updated Packaging Information. Updated Ordering Code Definitions. Removed Third Party Tools and Build a PSoC Emulator into your Board. Updated Development Kits and Evaluation Tools. Updated links in Sales, Solutions, and Legal Information. *E 2987146 BTK 07/19/2010 Updated Pinouts section to add 48-pin package. Updated Packaging Information section to add 48-pin package. Updated Development Tool Selection section to add 48-pin package development tool information. Updated Ordering Information section to add new 48-pin package product. Moved Acronyms section to the end of the document. Added part number CY8C29666 to the title. *F 3111512 BTK/NJF 07/25/2011 Updated I2C timing diagram to improve clarity. Updated wording, formatting, and notes of the AC Digital Block Specifications table to improve clarity. Added VDDP, VDDLV, and VDDHV electrical specifications to give more information for programming the device. Updated solder reflow temperature specifications to give more clarity. Updated the jitter specifications. Updated PSoC Device Characteristics table. Updated the F32KU electrical specification. Updated note for RPD electrical specification. Updated note for the TSTG electrical specification to add more clarity. Added Tape and Reel Information section. Added CL electrical specification. Updated Analog Reference specifications. Updated VOSOA, TCVOSOA, VOSOB, and TCVOSOB electrical specifications. *G 3543452 KAUL 03/06/2012 Updated Tape and Reel Information under Packaging Information. Document Number: 001-12899 Rev. *H Page 53 of 55 CY8C29466, CY8C29666 Document Title: CY8C29466, CY8C29666 Automotive PSoC® Programmable System-on-Chip™ Document Number: 001-12899 Revision ECN Orig. of Change Submission Date *H 4690138 KUK 03/17/2015 Document Number: 001-12899 Rev. *H Description of Change Updated Electrical Specifications: Updated DC Electrical Characteristics: Updated DC Analog Reference Specifications: Updated description. Updated Packaging Information: spec 51-85079 – Changed revision from *E to *F. spec 51-85061 – Changed revision from *E to *F. Updated Tape and Reel Information: spec 51-51100 – Changed revision from *C to *D. spec 51-51104 – Changed revision from *D to *E. Updated to new template. Completing Sunset Review. Page 54 of 55 CY8C29466, CY8C29666 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12899 Rev. *H Revised March 17, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 55 of 55