CY3210-27x43 EvalPod Schematic.pdf

5
4
3
2
1
VCC
Be aware when
measuring current that
this resistor may need
to be removed.
R1
D1
VCC
C1
C2
C3
3528
0603
0.1 uFd
0603
+
0.1 uFd
VCC
10 uFd 16v
0603
1206
U1
LED Green
R2
OCD_DE
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
31
27
32
26
33
24
34
23
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
37
20
38
19
39
18
40
17
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
48
9
49
8
50
7
51
6
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
44
13
45
12
46
11
47
10
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
SMP
16
SMP
P5_0
P5_1
P5_2
P5_3
35
22
36
21
P5_0
P5_1
P5_2
P5_3
TV1
TV2
TV3
TV4
1
25
29
30
NC1
NC2
NC3
NC4
OCD_DE
OCD_DO
14
15
OCDE
OCDO
OCD_HCLK
OCD_CCLK
42
43
HCLK
CCLK
OCD_RESET
41
XRES
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
52
5
53
4
54
3
55
2
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
0603
56.2
C4
R3
1K
NO LOAD
P0_[0:7]
0603
0603
VCC
R4
OCD_DO
D
56
1K
VDD
D
P1
P3_7
P3_5
P3_3
P3_1
P4_7
P4_5
P4_3
P4_1
P5_3
P5_1
0603
NO LOAD
U2
VCC
R6
OCD_CCLK
0603
56.2
VCC
C7
0603
XRES
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
24
4
25
3
26
2
27
1
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
SMP
9
SMP
GND2
C8
0.1 uFd
R7
1K
NO LOAD
0603
0603
19
OCD_RESET
8
7
6
5
4
3
2
1
C9
330 pFd
R8
1K
15
13
16
12
17
11
18
10
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
20
8
21
7
22
6
23
5
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_[0:7]
RECEPTACLE 10x1
C
P2
P3_6
P3_4
P3_2
P3_0
P4_6
P4_4
P4_2
P4_0
P5_2
P5_0
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
RECEPTACLE 10x1
CY8C27002-24PVI
28 DIP Socket
B
0603
0603
14
P3
P1_[0:7]
R9
OCD_HCLK
0603
B
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
1
2
3
4
5
6
7
8
9
10
VSS
R5
1K
0603
0603
28
C6
C
28
56.2
1
2
3
4
5
6
7
8
9
10
C10
56.2
R10
1K
RJ45 Right Angle
NO LOAD
0603
0603
NOTE: RJ45 pinout assumes a
straight-through connector
will be used.
VCC
P1_[0:7]
C11
0603
A
TP1
TP-43R
0.1 uFd
J1
TP2
TP-43R
PCB:
PCA:
VCC
PDCR-9310 REV*A
121R-31000 REV*A
A
CYPRESS SEMICONDUCTOR © 2005
1
2
3
4
5
OCD_RESET
P1_1
P1_0
Title
CY8C27002 28 PDIP Module
TP3
TP-43R
HDR 1x5
Programming header
Size
B
Test points
Date:
5
4
3
2
Document Number
REF-13445
Monday, May 22, 2006
Rev
*A
Sheet
1
1
of
1
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