CE95277 Delta Sigma ADC in Single-Ended Mode with PSoC 3/PSoC 5LP.pdf

CE95277 – Delta Sigma ADC in Single-Ended
Mode with PSoC® 3/PSoC 5LP
Objective
This code example demonstrates how to use the Delta Sigma ADC (ADC_DelSig) Component to take samples of an analog
input and send those samples to a PC application over RS-232 via the UART Component.
Overview
This code example implements a simple data collection system using the ADC_DelSig and UART Components. The ADC
continuously samples an analog input. The resulting samples can be sent to a PC over a UART connection a single sample at
a time or continuously. Emulated data, which is simply an incrementing number, can also be sent over the UART connection to
test the communication. The UART is used to create an RS-232 connection to a terminal program on a PC. The terminal program
is used to send commands to get the ADC sample data and read the resulting responses.
PSoC Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device for your design and quickly and
effectively integrate it into your design. For a comprehensive list of resources, see KBA86521 – How to Design with PSoC 3,
PSoC 4, and PSoC 5LP. The following is an abbreviated list:


Overview: PSoC Portfolio, PSoC Roadmap

Product Selector Guides: PSoC 1, PSoC 3, PSoC 4,
or PSoC 5LP. In addition, PSoC Creator™ includes a
device selection tool.
Technical Reference Manuals (TRMs): Provide
detailed descriptions of the architecture and registers
in the PSoC 5LP device family.

Development Kits:

Datasheets: Describe and provide electrical
specifications for the PSoC 5LP device family

CapSense® Design Guide: Learn how to design
capacitive touch-sensing applications with the
PSoC 5LP family of devices.

Application Notes and Code Examples: Cover a
broad range of topics, from basic to advanced level.
Many application notes include code examples.

CY8CKIT-001 is a common development platform
for all PSoC devices.

CY8CKIT-050 is a development platform targeted
at analog-intensive designs for PSoC 5LP.

CY8CKIT-030 is a development platform targeted
at analog intensive designs for PSoC 3.

CY8CKIT-059 is a rapid prototyping kit for PSoC
5LP.

CY8CKIT-002 features the MiniProg3 device, which
provides an interface for flash programming and
debugging.
PSoC Creator
PSoC Creator is a free, Windows based Integrated Design Environment (IDE). It enables you to design system hardware and
firmware concurrently based on PSoC 3, PSoC 4, and PSoC 5LP (see Figure 1). With PSoC Creator, you can do the following:
1.
Drag and drop Components to build your hardware
system design in the main design workspace.
3.
Configure Components using configuration tools.
4.
Explore the library of 100+ Components.
2.
Codesign your application firmware with the PSoC
hardware.
5.
Review Component datasheets.
www.cypress.com
Document No. 001-95277 Rev.**
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Figure 1. PSoC Creator Features
Requirements
Tool: PSoC Creator 3.1 or later
Programming Language: C (GCC 4.7.3)
Associated Parts: PSoC 3 and PSoC 5LP parts
Related Hardware: CY8CKIT-059, CY8CKIT-001, CY8CKIT-050, CY8CKIT-030
www.cypress.com
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Design
Figure 2. PSoC Creator Schematic of Code Example
The code example uses the ADC_DelSig Component to sample the analog input and the UART Component to transmit the
sampled data to the PC over RS-232. See Figure 2 for details on the design schematic.
All firmware for the code example is implemented in main.c. The firmware performs the following functions:
1.
Starts the ADC and UART Components.
2.
Checks for ADC end of conversion. Stores the latest result if conversion is complete.
3.
Checks for UART input.

'C' or 'c' received: Transmits the last sample via the UART.
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP



'S' or 's' received: Continuously transmits samples as they are completed.
'X' or 'x' received: Stops continuously transmitting samples.
'E' or 'e' received: Transmits a dummy byte of data.
Hardware Setup
Connect a voltage source to P0[0] on the kit. If P0[0] is not available, you can change the Vin pin in the Design-Wide Resources
file (CE95277.cywdr). If a voltage source is not available, you can test the UART connection using the emulated data by sending
‘e’ or ‘E’ over the terminal connection. The ADC is configured to accept a voltage input from 0V up to VDD of the part. Do not
exceed VDD of the part.
This code example is targeted at the CY8CKIT-059. If you are using this kit, then no external hardware connections are needed
to allow UART communication. If you are using a different hardware platform, you may need to connect the UART Tx (P12[7])
and Rx (P12[6]) to an RS-232 interface.
If you are not using the CY8CKIT-059, then you may also need to target a different PSoC device. To do so, right-click the project
in the Workspace Explorer and select Device Selector. Select the appropriate PSoC device for your hardware platform.
Software Setup
To interface with the UART on the PSoC device, a terminal emulator application is needed. HyperTerminal and PuTTY are
examples of valid options. Open up a connection to the COM port number that the PC gives to the PSoC device when it
enumerates. Make sure the settings in the software COM port match the settings for the UART Component, detailed in Parameter
Settings.
Components
Table 1 lists the PSoC Creator Components used in this example, as well as their hardware resources.
Table 1. PSoC Creator Components
Component or User Module
Hardware Resources
DelSig ADC
DelSig ADC
Full UART
UDBs (3 Datapath Cells, 58 macrocells, 2 Status Cells, 2 Control Cells, 2 interrupts)
Analog Pin (Vin)
P0[0]
Digital Input Pin (Rx_1)
P12[6]
Digital Output Pin (Tx_1)
P12[7]
Parameter Settings
Table 2 describes the component settings used to implement the project functionality.
Table 2. Parameter Settings
Component
Non-default Parameter Settings
Sampling Mode: Continuous
Resolution: 8 Bit
DelSig ADC
Samples per Second: 10000
Input Range: Vssa to 6.144 V (0.0 to 6*Vref)
Reference: Internal 1.024 V
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Component
Non-default Parameter Settings
Baud Rate: 115200
Date Bits: 8
UART
Parity: None
Stop Bits: 1
Flow Control: None
Analog Pin (Vin)
High Impedance Analog
Digital Input Pin (Rx_1)
High Impedance Digital, Hardware Connection
Digital Output Pin (Tx_1)
Strong Drive, Hardware Connection
Design-Wide Resources
Figure 3 shows the pin selections for the code example.
Figure 3. Pin Selections
Operation
1.
Connect the board to the PC using the USB connector of the KitProg. On the CY8CKIT-059, this is the PCB-USB
connector.
2.
Program the example project to the board. In PSoC Creator, go to the Debug Menu and Select Program. In the dialog
that appears, connect to the KitProg associated with the Kit being used.
3.
Connect an external voltage to the PSoC 5LP target device on P0[0]
4.
Open a terminal emulator on the PC and connect to the virtual COM port, enumerated as a part of KitProg
5.
Type character “C” or “c” in the terminal emulator to receive one sample of ADC data.
6.
Type character “S” or “s” in the terminal emulator to receive continuous samples of ADC data.
7.
Type character “X” or “x” in the terminal emulator to stop receiving ADC samples.
8.
Type character “E” or “e” in the terminal emulator to receive one emulated sample of data. This data will increment
by 1 each time an emulated sample is requested.
www.cypress.com
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Related Documents
Table 3 lists the relevant application notes, code examples, knowledge base articles, device datasheets, and Component
datasheets.
Table 3. Related Documents
Application Notes
Description
AN84783
Accurate Measurement Using PSoC 3 and
PSoC 5LP Delta-Sigma ADCs
Shows how to increase the accuracy of DelSig measurements
AN61102
PSoC 3 and PSoC 5LP – ADC Data
Buffering Using DMA
Describes how to buffer data from the DelSig using DMA
AN58304
PSoC 3 and PSoC 5LP – Pin Selection for
Analog Designs
Provides an overview of analog routing in PSoC 3/5LP and
recommendations for pin selection
AN58827
PSoC 3 and PSoC 5LP Internal Analog
Routing Considerations
Shows how to choose the best routes for analog-sensitive designs
AN68403
PSoC 3 and PSoC 5LP Analog Signal
Chain Calibration
Shows how to calibrate the analog signal chain in PSoC 3/5LP
Code Examples
CE95271
Delta Sigma ADC in Differential Mode with PSoC 3/5LP
CE95273
Delta Sigma ADC in Single-Ended Mode Using DMA and VDAC with PSoC 3/5LP
CE95299
Delta Sigma ADC Using 16 Multiplexed Single-Ended Inputs with PSoC 3/5LP
CE95302
Delta Sigma ADC and I2C Slave with PSoC 3/5LP
CE95388
UART Receive with PSoC 3/4/5LP
CE95389
UART Transmit with PSoC 3/4/5LP
PSoC Creator Component Datasheets
Description
ADC_DelSig
Details the use of the ADC_DelSig Component
UART
Details the use of the UART Component
Device Documentation
PSoC 3 Datasheets
PSoC 3 Technical Reference Manuals
PSoC 4 Datasheets
PSoC 4 Technical Reference Manuals
PSoC 5LP Datasheets
PSoC 5LP Technical Reference Manuals
Development Kit (DVK) Documentation
PSoC 3 and PSoC 5LP Kits
PSoC 4 Kits
www.cypress.com
Document No. 001-95277 Rev.**
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Document History
Document Title: CE95277 - Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
Document Number: 001-95277
Revision
ECN
**
4753338
www.cypress.com
Orig. of
Change
TDU
Submission
Date
10/05/2015
Description of Change
New spec
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Delta Sigma ADC in Single-Ended Mode with PSoC® 3/PSoC 5LP
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© Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under
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Use may be limited by and subject to the applicable Cypress software license agreement.
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Document No. 001-95277 Rev.**
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