Data sheet, Rev. 2.1, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Power Management & Drives N e v e r s t o p t h i n k i n g 6ED003L06-F Integrated 3 Phase Gate Driver 6ED003L06-F Revision History: Previous Version: Page 11 9 2009-07 2.0 Subjects (major changes since last revision) VIT Hys changed Corrected RthJA Fig3 Æ Fig13 Rev. 2.1 Edition 2006-01 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 7/28/09. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Datasheet 2 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Table of Contents: 1 1.1 Overview ........................................................................................................................................4 Features ........................................................................................................................................ 4 1.2 Description ................................................................................................................................... 4 2 2.1 Pin Configuration and Description..............................................................................................5 Description ................................................................................................................................... 5 2.1.1 /HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 2, 3, 4, 5, 6, 7)................. 5 2.1.2 EN (Gate driver enable, Pin 10)................................................................................................... 6 2.1.3 /FAULT (Fault feedback, Pin 8) ................................................................................................... 6 2.1.4 ITRIP and RCIN (Over-current detection function, Pin 9, 11) .................................................. 6 2.1.5 VCC, VSS and COM (Low side supply, Pin 1, 12,13) ................................................................ 6 2.1.6 VB1,2,3 and VS1,2,3 (High side supplies, Pin 18, 20, 22, 24, 26, 28)....................................... 7 2.1.7 LO1,2,3 and HO1,2,3 (Low and High side outputs, Pin 14, 15, 16, 19, 23, 27)........................ 7 3 3.1 Electrical parameters....................................................................................................................9 Absolute Maximum Ratings ........................................................................................................ 9 3.2 Required Operation Conditions................................................................................................ 10 3.3 Operating Range ........................................................................................................................ 10 3.4 Static Logic function Table ....................................................................................................... 11 3.5 Static Parameters....................................................................................................................... 11 3.6 Dynamic Parameters.................................................................................................................. 13 4 Timing Diagrams .........................................................................................................................14 5 5.1 Package........................................................................................................................................17 Package Drawing ....................................................................................................................... 17 5.2 Reference PCB for thermal resistance .................................................................................... 18 Datasheet 3 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 1 Overview 1.1 Features • Thin-film-SOI-technology • Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology • Maximum blocking voltage +600V • Power supply of the high side drivers via boot strap • Separate control circuits for all six drivers • CMOS and LSTTL compatible input (negative logic) • Signal interlocking of every phase to prevent cross-conduction • Detection of over-current and under-voltage supply • 'shut down' of all switches during error conditions • externally programmable delay for fault clear after over current detection PG-DSO28-17 1.2 Description The device 6ED003L06-F is a full bridge driver to control power devices like MOS-transistors or IGBTs in 3phase systems with a maximum blocking voltage of +600V. Based on the used SOI-technology there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch up may occur at all temperature and voltage conditions. Figure 1: Typical Application The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down to 3.3V logic. The device includes an under-voltage detection unit with hysterese characteristic and an over-current detection. The over-current level is adjusted by choosing the resistor value and the threshold DC-Bus 5V / 3.3V VCC VCC HIN1,2,3 LIN1,2,3 FAULT EN HIN1,2,3 LIN1,2,3 FAULT VB1,2,3 HO1,2,3 To Load VS1,2,3 RRCIN CRCIN EN RCIN ITRIP VSS LO1,2,3 COM RNTC VSS level at pin ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut-down off all six switches. An error signal is provided at the FAULT open drain output pin. The blocking time after overcurrent can be adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore, the resistor RRCIN is optional. The minimum output current can be given with 120mA for pull-up and 250mA for pull down. Because of system safety reasons a 380ns interlocking time has been realised. The function of input EN can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1). There are parasitic diode structures between pins VCC and VBx due to the monolithic setup of the IC, but external bootstrap diodes are still mandatory. Datasheet 4 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 2 Pin Configuration and Description Figure 2: Pin Configuration of 6ED003L06-F Table 1: Pin Description Symbol Description VCC Low side power supply VSS Logic ground /HIN1,2,3 High side logic input (negative logic) /LIN1,2,3 Low side logic input (negative logic) /FAULT Indicates over-current and under-voltage (negative logic, open-drain output) EN Enable I/O functionality (positive logic) ITRIP Analog input for over-current shutdown, activates FAULT and RCIN to VSS RCIN external RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR) COM Low side gate driver reference VB1,2,3 High side positive power supply HO1,2,3 High side gate driver output VS1,2,3 High side negative power supply LO1,2,3 Low side gate driver output nc Not Connected 2.1 Description Datasheet 2.1.1 /HIN1,2,3 and /LIN1,2,3 (Low side and high side control pins, Pin 2, 3, 4, 5, 6, 7) These pins are active low and they are responsible for HO1,2,3 and LO1,2,3 out-of-phase 5 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver • Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the supply voltage condition returns in the normal operation range (please refer to VCC pin description for more details). commutation. The schmitt-trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3V controller outputs. • Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and RCIN input is released (please refer to ITRIP pin). ≈ 50Ω Figure 3: Input pin structure An internal pull-up resistor of about 75 kΩ is prebiases the input during supply start-up and a zener clamp is provided for pin protection purposes. Input schmitt-trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 4 and Figure 7. Figure 5: /Fault pin structure 2.1.4 ITRIP and RCIN (Over-current detection function, Pin 9, 11) 6ED003L06-F provides an over-current detection function by connecting the ITRIP input with the motor current feedback. The ITRIP comparator threshold (typ 0.46V) is referenced to VSS ground. A input noise filter (typ: tITRIPMIN = 210 ns) prevents the driver to detect false over-current events. Figure 4: Input filter timing diagram Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault feedback at /FAULT pin. It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1us. RCIN input/output pin is used to determine the reset time of the fault condition. As soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 6.0V, the fault condition releases and the driver returns operational following /HIN and /LIN inputs. Please refer to AN-GateDriver-6ED003L06-1 for details on setting RCIN time constant. The 6ED003L06-F provides additionally an antishoot through prevention capability which avoids the simultaneous on-state of two gate drivers of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When two inputs of a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe state. Please refer to the application note AN-Gatedrive6ED003L06-1 for a detailed description. A minimum deadtime insertion of typ 380ns is also provided, in order to reduce cross-conduction of the external power switches. 2.1.2 2.1.5 VCC, VSS and COM (Low side supply, Pin 1, 12,13) VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is referenced to COM ground.COM ground is floating respect to VSS ground with a recommended range of operation of +/-2.5V. A back-to-back zener structure protects grounds from noise spikes. EN (Gate driver enable, Pin 10) The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW logic level. The internal structure of the pin is the same as Figure 3 made exception of the switching levels of the Schmitt-Trigger, which are here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. 2.1.3 /FAULT (Fault feedback, Pin 8) /Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 3). The pin is active (i.e. forces LOW voltage level) when one of the following conditions occur: Datasheet The under-voltage circuit enables the device to operate at power on when a typical supply voltage VCCUV+ = 12 V is present. 6 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 10.4 V. This prevents the external power switches from critically low gate voltage levels during on-state and therefore from excessive power dissipation. area as a function of the supply voltage. Details on bootstrap supply section and transient immunity can be found in application note ANGateDriver-6ED003L06-1. 2.1.7 LO1,2,3 and HO1,2,3 (Low and High side outputs, Pin 14, 15, 16, 19, 23, 27) Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs (/LIN1,2,3), while high side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs (/HIN1,2,3). In particular, after an under-voltage condition of the VBS supply, a falling /HIN edge is necessary to turn-on the respective high side output, while after a undervoltage condition of the VCC supply, the low side outputs switch to the state of their respective inputs. 2.1.6 VB1,2,3 and VS1,2,3 (High side supplies, Pin 18, 20, 22, 24, 26, 28) VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver stage can be supplied by bootstrap topology connected to VCC. Under-voltage detection operates with a rising supply threshold of typical VBSUV+ = 12 V and a falling threshold of VCCUV- = 10.4 V. Please refer to Figure 11 of the datasheet for device operating Datasheet 7 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver BIAS NETWORK / VDD2 INPUT NOISE FILTER HIN1 LIN1 INPUT NOISE FILTER HIN2 INPUT NOISE FILTER LIN2 INPUT NOISE FILTER HIN3 INPUT NOISE FILTER LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR UVDETECT GateDrive HO1 VS1 VB2 BIAS NETWORK - VB2 DEADTIME & SHOOT-THROUGH PREVENTION LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR UVDETECT GateDrive HO2 VS2 DEADTIME & SHOOT-THROUGH PREVENTION VB3 BIAS NETWORK / VB3 LATCH HV LEVEL-SHIFTER + REVERSE-DIODE COMPA RATOR INPUT NOISE FILTER LIN3 VB1 BIAS NETWORK - VB1 DEADTIME & SHOOT-THROUGH PREVENTION UVDETECT GateDrive HO3 VS3 >1 INPUT NOISE FILTER EN VCC UVDETECT DELAY VSS / COM LEVELSHIFTER GateDrive LO1 DELAY VSS / COM LEVELSHIFTER GateDrive LO2 DELAY VSS / COM LEVELSHIFTER GateDrive LO3 INPUT NOISE FILTER ITRIP S VDD2 Q SET DOMINANT LATCH R IRCIN RCIN COM FAULT VSS >1 Figure 6: Block diagram Datasheet 8 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 3 Electrical parameters 3.1 Absolute Maximum Ratings All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C) Symbol Min. Max. Unit High side offset voltage(Note 1) VCC-VBS6 600 V High side offset voltage (tp<500ns, Note 1) VCC -VBS 50 - High side offset voltage(Note 1) VCC - 6 620 High side offset voltage (tp<500ns, Note 1) VCC - 50 - VBS High side floating supply voltage (VB vs. VS) -1 20 VHO High side output voltage (VHO vs. VS) -0.5 VB + 0.5 VCC Low side supply voltage (internally clamped) -1 20 VS VB Definition VCCOM Low side supply voltage (VCC vs. VCOM) -0.5 25 VCOM Gate driver ground -5.7 5.7 VLO Low side output voltage (VLO vs. VCOM) -0.5 VCCOM +0.5 VIN Input voltage LIN,HIN,EN,ITRIP tp <10µs -1.0 10 15 VFLT FAULT output voltage -0.5 VCC + 0.5 VRCIN RCIN output voltage -0.5 VCC + 0.5 Power dissipation (to package) Note 2 - 1.0 W Thermal resistance (junction to ambient, device mounted on PCB see Fig.13) - 70 K/W TJ Junction temperature - 125 °C TS Storage temperature -40 150 PD RthJA dVs/dt offset voltage slew rate 50 V/ns Note :The minimal value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VCC, HINx, LINx, FAULT, EN, RCIN, ITRIP, VSS, COM, LOx) and pins connected inside each high side itself (VBx, HOx, VSx) is guaranteed up to 1.5kV (Human Body Model). Note 1 : Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by design / characterization. External bootstrap diode is mandatory. Refer to application note. Note 2: Consistent power dissipation of all outputs Datasheet 9 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 3.2 Required Operation Conditions All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C) Symbol VB VCCOM Definition High side offset voltage (Note 1) Low side supply voltage (VCC vs. VCOM) Min. Max. Unit 11.1 620 V 10 25 Note 1 : Logic operational for VB (VB vs. VSS) > 11,1V 3.3 Operating Range All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. (TA=25°C) Symbol VS Definition High side floating supply offset voltage Min. Max. Unit VCC -VBS0.5 550 V -0.5 550 VBCC High side floating supply offset voltage (VB vs. VCC, statically, Note 1, Note 2) VBS High side floating supply voltage (VB vs. VS) 13 17.5 VHO High side output voltage (VHO vs. VS) 0 VBS VLO Low side output voltage (VLO vs. VCOM) 0 20 VCC Low side supply voltage 13 17.5 VCOM Low side ground voltage -2.5 2.5 VIN Logic input voltages LIN,HIN,EN,ITRIP 0 5 VFLT FAULT output voltage 0 VCC VRCIN RCIN input voltage 0 VCC tIN Pulse width for ON or OFF (Note 3) 1 - µs TA Ambient temperature -40 95 °C Note 2 : All input pins (/HINx, /LINx) and EN, ITRIP pin are internally clamped with a 10.5V zener diode. Note 3 : In case of input pulse width at /LINx and /HINx below 1µ the input pulse can not be transmitted properly Datasheet 10 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 3.4 Static Logic function Table VCC VBS RCIN ITRIP ENABLE FAULT LO1,2,3 HO1,2,3 <VCCUV- X X X X 0 0 0 15V <VBSUV- X 0V 5V High imp /LIN1,2,3 0 15V 15V < 3.3V ↓ 0V 5V 0 0 0 15V 15V X > VIT,TH+ 5V 0 0 0 15V 15V > 5.8V 0V 5V High imp /LIN1,2,3 /HIN1,2,3 15V 15V > 5.8V 0V 0V High imp 0 0 3.5 Static Parameters VCC = VBS = 15V unless otherwise specified. (TA=25°C) Symbol 1 Definition Min. Typ. Max. Unit V Test Conditions VIH Logic "0" input voltage (LIN,HIN) 1.7 2.1 2.4 VIL Logic "1" input voltage (LIN,HIN) 0.7 0.9 1.1 VEN,TH+ EN positive going threshold 1.9 2.1 2.3 VEN,TH- EN negative going threshold 1.1 1.3 1.5 VIT,TH+ ITRIP positive going threshold 360 460 540 mV VIT,HYS ITRIP input hysteresis 45 70 VRCIN,TH RCIN positive going threshold - 6.0 7.5 V VRCIN,HYS RCIN input hysteresis - 2.5 - VOH Output voltage (high level, VCC-VO or VBSVO) - 0.8 1.4 IO = 20mA VOL Output voltage (low level, VO-VCOM or VO-VS) - 0.2 0.6 IO = -20mA VCCUV+ VBSUV+ VCC and VBS supply undervoltage positive going threshold 11.0 12 12.8 VCCUVVBSUV- VCC and VBS supply undervoltage negative going threshold 9.5 10.4 11.0 VCCUVH VBSUVH VCC and VBS supply undervoltage lockout hysteresis 1.2 1.6 - ILVS+ High side leakage current betw. VS and VSS - 1 5 µA VS = 600V ILVS+1 High side leakage current betw. VS and VSS - 30 - µA Tj=125°C, VS = 600V ILVS-1 High side leakage current between VSx and VSy (x=1,2,3 and y=1,2,3) - 30 - Tj=125°C VSx - VSy =600V Not subject of production test, verified by characterisation Datasheet 11 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Symbol Definition Min. Typ. Max. Unit Test Conditions IQBS1 Quiescent VBS supply current (VB only) - 300 500 HO=low IQBS2 Quiescent VBS supply current (VB only) - 360 550 HO=high IQCC1 Quiescent VCC supply current (VCC only) - 0.6 1 mA VLIN=float. IQCC2 Quiescent VCC supply current (VCC only) - 1.1 1.6 mA VLIN=0V, VHIN=5V, IQCC3 Quiescent VCC supply current (VCC only) - 0.9 1.6 mA VLIN=5V, VHIN=0V 9.0 10.6 13 V IIN=4mA µA VLIN=5V VIN,CLAMP Input clamp voltage (/HIN, /LIN, EN, ITRIP) (Note 1) ILIN+ Input bias current - 52 100 ILIN- Input bias current - 110 200 VLIN=0V IHIN+ Input bias current - 52 100 VHIN=5V IHIN- Input bias current - 110 200 VHIN=0V 70 120 VITRIP=5V 69 120 VENABLE=5V IITRIP+ Input bias current (ITRIP=high) IEN+ Input bias current (EN=high) - IRCIN Input bias current RCIN (internal current source) IO+ Mean output current for load capacity charging in range from 3V(20%) to 6V(40%) 120 142 - IO- Mean output current for load capacity discharging in range from 12V(80%) to 9V(60%) 250 410 - RON,RCIN RCIN low on resistance of the pull down transistors - 47 100 RON,FLT FAULT low on resistance of the pull down transistors - 54 100 2.8 VRCIN = 2 V mA CL=10nF CL=10nF Ω VRCIN=0.5V VFAULT=0.5V Note 1: There is an additional power dissipation for input voltages above the clamping voltage. In series to clamping diode there is a limiting resistor of 55Ω (see also Fig.3) Datasheet 12 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 3.6 Dynamic Parameters VCC = VBS =15V, VS = VSS = VCOM, unless otherwise specified. (TA=25°C) Symbol Definition Min. Typ. Max. Unit Test Condition ns VLIN/HIN=0V ton Turn-on propagation delay 400 620 800 toff Turn-off propagation delay 400 610 800 VLIN/HIN=5V tr Turn-on rise time (CL=1nF) - 76 130 VLIN/HIN=0V tf Turn-off fall time (CL=1nF) - 26 45 VLIN/HIN=5V Shutdown propagation delay ENABLE - 780 1000 VEN=0 Shutdown propagation delay ITRIP 400 765 1000 Input filter time ITRIP 155 210 380 - 450 700 tEN tITRIP tITRIPMIN VITRIP=1V tFLT Propagation delay ITRIP to FAULT tFILIN Input filter time at LIN for turn on and off and input filter time at HIN for turn on only 120 270 - VLIN/HIN=0V& 5V tFILIN1 Input filter time at HIN for turn off (Note 1) 100 220 - VHIN = 5V tFILIN2 Input filter time at HIN for turn off (Note 1) - 400 - VHIN = 5V tFILEN Input filter time EN 300 485 - Fault clear time at RCIN after ITRIPfault, (CRCin=1nF) 1.0 2.3 3.0 ms VLIN/HIN = 0 & 5V VITRIP=0V Dead time 150 380 - ns VLIN/HIN = 0 & 5V tFLTCLR DT MTON Matching delay ON, max(ton)-min(ton), ton are applicable to all 6 driver outputs - 70 150 external dead time>500ns MTOFF Matching delay OFF, max(toff)min(toff), toff are applicable to all 6 driver outputs - 90 150 external dead time>500ns PM Output pulse width matching. PwinPWout 12 100 PWin>1µs Note 1 : Because of internal signal processing and safety aspects the output HO at short turn off pulses shows the behaviour according to figure 4. For proper work of the driver the input pulses must not fall below the recommended input width tIN of 1µs. The short signal range is not subject to production test and is not guaranteed. Datasheet 13 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 4 Timing Diagrams tFILIN tFILIN LIN HIN LIN on off on off high HO LO LO a) tFILIN1 low tFILIN2 toff,HINx HIN toff,HINx < tFILIN1 high HO b) HIN toff,HINx toFILIN1 < toff,HINx < tFILIN2 HO c) HIN toff,HINx toff,HINx > tFILIN2 HO Figure 7: Timing of short pulse suppression Figure 8: Timing of internal deadtime Datasheet 14 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Figure 9: Enable delay time definition Figure 10: Input to output propagation delay times and switching times definition Figure 11: Operating Areas Datasheet 15 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver Figure 12: ITRIP-timing Datasheet 16 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 5 Package 1.27 0.1 0.35 +0.15 2) 8˚ MAX. 7.6 -0.2 1) 0.4 +0.8 10.3 ±0.3 0.2 28x 28 0.35 x 45˚ 0.23 +0.09 2.65 MAX. 2.45 -0.2 0.2 -0.1 5.1 Package Drawing 15 1 18.1 -0.4 1) 14 Index Marking 1) 2) Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.05 max. per side Footprint for Reflow soldering e = 1.27 A = 9.73 L = 1.67 B = 0.65 B e L A HLG05506 Datasheet 17 Rev. 2, Dec 2008 6ED003L06-F Integrated 3 Phase Gate Driver 5.2 Reference PCB for thermal resistance Figure 13: PCB Reference layout Dimensions 80.0 × 80.0 × 1.5 mm³ λtherm [W/m⋅K] Material FR4 0.3 Metal (Copper) 70µm 388 Datasheet 18 Rev. 2, Dec 2008