INFINEON SDA9205-2

Triple 8-Bit Analog-to-Digital-Converter
SDA 9205-2
Preliminary Data
CMOS IC
Features
Three equivalent CMOS A/D converters on chip
30-MHz sample rate
8-bit resolution
No external sample & hold required
On-chip input buffer for each analog channel
Internal clamping circuits for each of the ADCs
Different digital output multiplex formats:
– 3 independent unmultiplexed 8-bit outputs
– Multiplexed formats compatible to inputs of all
Siemens Featureboxes and Siemens TV-SAM
– CCIR 656 output format
● Overflow and underflow outputs
●
●
●
●
●
●
●
P-LCC-68-1
Type
Ordering Code
Package
SDA 9205-2
Q67100-H5069
P-LCC-68-1 (SMD)
General Description
The SDA 9205-2 is a single monolithic IC containing three separate 8-bit analog to digital converters
for video (YUV) applications. It utilizes an advanced VLSI 1.2 µm CMOS process providing 30-MHz
sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several
control inputs, compatible to inputs of all Siemens Featureboxes, Siemens TV-SAM, and CCIR 656
output format.
The ADCs have no missing codes over the full operating temperature range of 0 to + 70 °C.
Operation is from + 5 V DC-power supply.
Semiconductor Group
1
01.94
SDA 9205-2
Pin Configuration
(top view)
Semiconductor Group
2
SDA 9205-2
Pin Definitions and Functions
Pin No.
Symbol
Function
63 to 2
C7 to C0
Digital outputs of ADC C (port C) C0 least significant bit
3
VQGNDC
Output stages supply ground of port C
4
UFLC
Underflow data output of ADC C
5
OFLC
Overflow data output of ADC C
6
OENC
Output enable of port C
7
DTC
Binary/two’s complement output port C
8/9/11/17
CONT3CONT0
Control inputs for different digital output multiplex formats –
refer to logic table
10
VREFHC
Reference voltage high of ADC C (+ 2.5 V)
12
VCCC
Analog positive supply voltage of ADC C (+5 V)
13
VAGNDC
Analog ground of ADC C
14
VREFLC
Reference voltage low of ADC C (+ 5 V)
15
AINC
Analog voltage input of ADC C
16
VREFHB
Reference voltage high of ADC B (+ 2.5 V)
18
VCCB
Analog positive supply voltage of ADC B (+ 5 V)
19
VAGNDB
Analog ground of ADC B
20
VREFLB
Reference voltage low of ADC B (+ 0.5 V)
21
AINB
Analog voltage input of ADC B
22
VREFHA
Reference voltage high of ADC A (+ 2.5 V)
23
VCCA
Analog positive supply voltage of ADC A (+ 5 V)
24
VAGNDA
Analog ground of ADC A
25
AINA
Analog voltage input of ADC A
26
VREFLA
Reference voltage low of ADC A (+ 0.5 V)
27/29
TEST
Factory use only, connect to 0 V
28
DTA
Binary/two’s complement output of port A
30
CLAMP
Clamp input for all three channels
31
UFLA
Underflow data output of ADC A
32
OFLA
Overflow data output of ADC A
33
VQGNDA
Output stages supply ground of port A
34 to 41
A7 to A0
Digital outputs of ADC A (port A) A0 least significant bit
42
OENA
Output enable of port A
43
VDDQA
Output stages supply voltage of port A
Semiconductor Group
3
SDA 9205-2
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Function
44
OENB
Output enable of port B
45
UFLB
Underflow data output of ADC B
46
OFLB
Overflow data output of ADC B
47
VQGNDB
Output stages supply ground of port B
48 to 55
B7 to B0
Digital outputs of ADC B (port B) B0 least significant bit
56
VDDQB
Output stages supply voltage of port B
57
CLK
Clock input
58
VDGND
Digital ground
59
FSY
Format sync input
60
DTB
Binary/two’s complement output of port B
61
VDD
Digital positive supply voltage (+ 5 V)
62
VDDQC
Output stages supply voltage of port C
Semiconductor Group
4
SDA 9205-2
Circuit Description
Analog to Digital Converter
The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters.
They are two step converters with a coarse comparator block and two fine comparator blocks each
using pipeline architecture for high speed sampling performance. During the first clock cycle, the
coarse comparator samples and determines 4 MSBs and one of the fine comparator blocks
samples the input voltage. During the second clock cycle this fine comparator block makes its
decision for the 4 LSBs. So the coarse comparator block makes its decisions at each clock cycle,
the fine comparator blocks make the comparison alternating every two clock cycles.
The converter uses the redundancy principle to correct fine conversion. The sample and hold
function has been distributed in each comparator due to the two step conversion principle.
Clamping
An internal clamping circuit is provided in each of three analog channels. The analog pins AINA,
AINB, AINC are switched simultaneously to on chip generated clamping levels by an active high
pulse on pin 30 (CLAMP).
Clamping Levels
Analog Channel
Dual Code
Components
AINA
00010000
(Y)
AINB, AINC
10000000
(U, V)
Semiconductor Group
5
SDA 9205-2
The external clamping capacitance is loaded by on chip current sources (typ. 200 µA) during
clamping. So the loading time depends on the values of Cext cl.
The loading time for a complete loading cycle is 1200 CLK pulses typical (44 µs with 27 MHz CLK
and Cext cl = 10 nF) as shown in figure 1.
Cext cl = 10 nF, RS = 50 Ω
Figure 1
Typical Clamp Timing Diagram
Semiconductor Group
6
SDA 9205-2
Digital Signal Processing
The digital signal processing block performs averaging of sampled data. The α, β, γ 8-bit busses
represent the results of DSP function with input data from a, b, c, 8-bit busses. A special DSP
function in combination with a special output coding format is defined by four control pins
CONT0 … CONT3 (see Output Coding).
Figure 2
Interfaces of ADC-, DSP- and Output Coding Block
Semiconductor Group
7
SDA 9205-2
The following DSP functions are available
(1.0)
αn = an – 3
(1.1)
αn = 1/2 (an – 4 + an – 3)
(2.0)
βn = bn – 3
(2.1)
βn = 1/2 (bn – 4 + bn – 3)
(2.2)
β4n = 1/4 (b4n – 5 + b4n – 4 + b4n – 3 + b4n – 2n), β4n – 3,2,1
(2.3)
ADC A
n = sampling point
ADC B
β8n = 1/8 (b8n – 7 + b8n – 6 + ..... + b8n),
β8n – 7,6,5,4,3,2,1
arbitrarily
arbitrarily
(2.0)
γn = c n – 3
(2.1)
γn = 1/2 (cn – 4 + cn – 3)
(2.2)
γ4n = 1/4 (c4n – 5 + c4n – 4 + c4n – 3 + c4n – 2)
γ4n – 3,2,1
arbitrarily
(2.3)
γ8n = 1/8 (c8n – 7 + c8n – 6 + ..... + c8n)
γ8n – 7,6,5,4,3,2,1
arbitrarily
ADC C
Averaged results are rounded to eight bits (X ≤ 0.5 → 0; X > 0.5 → 1)
A group delay of 0.5 CLK cycles exists between DSP (1.0, 2.0) and the other DSP functions.
Semiconductor Group
8
SDA 9205-2
Figure 3
DSP Function
Detailed function of DSP block is shown in figure 3.
Semiconductor Group
9
SDA 9205-2
Output Coding
Eight different digital output multiplex formats are available. They are selectable via four control
lines CONT0 … CONT3. These multiplexed formats perform combinations of DSP functions of the
several converters (A, B, C).
DSP functions – output coding combinations
Format
DSP
CONT3
CONT2
CONT1
CONT0
8:8:8
1.0 + 2.0
1.1 + 2.1
0
0
0
0
0
0
0
1
8:4:4
1.0 + 2.0
1.1 + 2.1
0
0
0
0
1
1
0
1
8:2:2
1.0 + 2.0
1.1 + 2.2
0
0
1
1
0
0
0
1
8:1:1
1.0 + 2.0
1.1 + 2.3
0
0
1
1
1
1
0
1
4:8:8
1.0 + 2.0
1.1 + 2.1
1
1
0
0
0
0
0
1
4:4:4
1.0 + 2.0
1.1 + 2.1
1
1
0
0
1
1
0
1
4:2:2
1.0 + 2.0
1.1 + 2.2
1
1
1
1
0
0
0
1
4:1:1
1.0 + 2.0
1.1 + 2.3
1
1
1
1
1
1
0
1
Semiconductor Group
10
SDA 9205-2
The digital output data are synchronized by the FSY signal. The first high of FSY defines the first
output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1,
4:1:1 the first and the second) output format byte after FSY had gone high does not contain valid
data. Timing of FSY, CLK and output data is shown in figure 4 with output format 4:1:1.
Figure 4
Semiconductor Group
11
SDA 9205-2
Format 8:8:8
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
0
0
0
0
1.1 + 2.1
0
0
0
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 71
α 61
α 51
α 41
α 31
α 21
α 11
α 01
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 73
α 63
α 53
α 43
α 33
α 23
α 13
α 03
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 75
α 65
α 55
α 45
α 35
α 25
α 15
α 05
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 77
α 67
α 57
α 47
α 37
α 27
α 17
α 07
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
β 71
β 61
β 51
β 41
β 31
β 21
β 11
β 01
β 72
β 62
β 52
β 42
β 32
β 22
β 12
β 02
β 73
β 63
β 53
β 43
β 33
β 23
β 13
β 03
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
β 75
β 65
β 55
β 45
β 35
β 25
β 15
β 05
β 76
β 66
β 56
β 46
β 36
β 26
β 16
β 06
β 77
β 67
β 57
β 47
β 37
β 27
β 17
β 07
C
C7
C6
C5
C4
C3
C2
C1
C0
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
γ 71
γ 61
γ 51
γ 41
γ 31
γ 21
γ 11
γ 01
γ 72
γ 62
γ 52
γ 42
γ 32
γ 22
γ 12
γ 02
γ 73
γ 63
γ 53
γ 43
γ 33
γ 23
γ 13
γ 03
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
γ 75
γ 65
γ 55
γ 45
γ 35
γ 25
γ 15
γ 05
γ 76
γ 66
γ 56
γ 46
γ 36
γ 26
γ 16
γ 06
γ 77
γ 67
γ 57
γ 47
γ 37
γ 27
γ 17
γ 07
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
Semiconductor Group
12
SDA 9205-2
Format 8:4:4
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
0
0
1
0
1.1 + 2.1
0
0
1
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 71
α 61
α 51
α 41
α 31
α 21
α 11
α 01
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 73
α 63
α 53
α 43
α 33
α 23
α 13
α 03
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 75
α 65
α 55
α 45
α 35
α 25
α 15
α 05
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 77
α 67
α 57
α 47
α 37
α 27
α 17
α 07
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
β 72
β 62
β 52
β 42
β 32
β 22
β 12
β 02
γ 72
γ 62
γ 52
γ 42
γ 32
γ 22
γ 12
γ 02
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
β 76
β 66
β 56
β 46
β 36
β 26
β 16
β 06
γ 76
γ 66
γ 56
γ 46
γ 36
γ 26
γ 16
γ 06
C
C7
C6
C5
C4
C3
C2
C1
C0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T*
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
*
T … Tristate
Semiconductor Group
13
SDA 9205-2
Format 8:2:2
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
0
1
0
0
1.1 + 2.2
0
1
0
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 71
α 61
α 51
α 41
α 31
α 21
α 11
α 01
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 73
α 63
α 53
α 43
α 33
α 23
α 13
α 03
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 75
α 65
α 55
α 45
α 35
α 25
α 15
α 05
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 77
α 67
α 57
α 47
α 37
α 27
α 17
α 07
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
γ 70
γ 60
T
T
T
T
β 50
β 40
γ 50
γ 40
T
T
T
T
β 30
β 20
γ 30
γ 20
T
T
T
T
β 10
β 00
γ 10
γ 00
T
T
T
T
β 74
β 64
γ 74
γ 64
T
T
T
T
β 54
β 44
γ 54
γ 44
T
T
T
T
β 34
β 24
γ 34
γ 24
T
T
T
T
β 14
β 04
γ 14
γ 04
T
T
T
T
C
C7
C6
C5
C4
C3
C2
C1
C0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T*
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
*
T … Tristate
Semiconductor Group
14
SDA 9205-2
Format 8:1:1
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
0
1
1
0
1.1 + 2.3
0
1
1
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 71
α 61
α 51
α 41
α 31
α 21
α 11
α 01
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 73
α 63
α 53
α 43
α 33
α 23
α 13
α 03
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 75
α 65
α 55
α 45
α 35
α 25
α 15
α 05
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 77
α 67
α 57
α 47
α 37
α 27
α 17
α 07
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
γ 70
γ 60
T
T
T
T
β 70
β 60
γ 70
γ 60
T
T
T
T
β 50
β 40
γ 50
γ 40
T
T
T
T
β 50
β 40
γ 50
γ 40
T
T
T
T
β 30
β 20
γ 30
γ 20
T
T
T
T
β 30
β 20
γ 30
γ 20
T
T
T
T
β 10
β 00
γ 10
γ 00
T
T
T
T
β 10
β 00
γ 10
γ 00
T
T
T
T
C
C7
C6
C5
C4
C3
C2
C1
C0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T*
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
*
T … Tristate
Semiconductor Group
15
SDA 9205-2
Format 4:8:8
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
1
0
0
0
1.1 + 2.1
1
0
0
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
β 71
β 61
β 51
β 41
β 31
β 21
β 11
β 01
β 72
β 62
β 52
β 42
β 32
β 22
β 12
β 02
β 73
β 63
β 53
β 43
β 33
β 23
β 13
β 03
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
β 75
β 65
β 55
β 45
β 35
β 25
β 15
β 05
β 76
β 66
β 56
β 46
β 36
β 26
β 16
β 06
β 77
β 67
β 57
β 47
β 37
β 27
β 17
β 07
C
C7
C6
C5
C4
C3
C2
C1
C0
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
γ 71
γ 61
γ 51
γ 41
γ 31
γ 21
γ 11
γ 01
γ 72
γ 62
γ 52
γ 42
γ 32
γ 22
γ 12
γ 02
γ 73
γ 63
γ 53
γ 43
γ 33
γ 23
γ 13
γ 03
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
γ 75
γ 65
γ 55
γ 45
γ 35
γ 25
γ 15
γ 05
γ 76
γ 66
γ 56
γ 46
γ 36
γ 26
γ 16
γ 06
γ 77
γ 67
γ 57
γ 47
γ 37
γ 27
γ 17
γ 07
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
Semiconductor Group
16
SDA 9205-2
Format 4:4:4
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
1
0
1
0
1.1 + 2.1
1
0
1
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
β 72
β 62
β 52
β 42
β 32
β 22
β 12
β 02
β 72
β 62
β 52
β 42
β 32
β 22
β 12
β 02
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
β 76
β 66
β 56
β 46
β 36
β 26
β 16
β 06
β 76
β 66
β 56
β 46
β 36
β 26
β 16
β 06
C
C7
C6
C5
C4
C3
C2
C1
C0
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
γ 72
γ 62
γ 52
γ 42
γ 32
γ 22
γ 12
γ 02
γ 72
γ 62
γ 52
γ 42
γ 32
γ 22
γ 12
γ 02
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
γ 76
γ 66
γ 56
γ 46
γ 36
γ 26
γ 16
γ 06
γ 76
γ 66
γ 56
γ 46
γ 36
γ 26
γ 16
γ 06
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
Semiconductor Group
17
SDA 9205-2
Format 4:2:2
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
1
1
0
0
1.1 + 2.2
1
1
0
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
C
C7
C6
C5
C4
C3
C2
C1
C0
β 70
β 60
β 50
β 40
β 30
β 20
β 10
β 00
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
γ 70
γ 60
γ 50
γ 40
γ 30
γ 20
γ 10
γ 00
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
β 74
β 64
β 54
β 44
β 34
β 24
β 14
β 04
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
γ 74
γ 64
γ 54
γ 44
γ 34
γ 24
γ 14
γ 04
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
Semiconductor Group
18
SDA 9205-2
Format 4:1:1
DSP Function
bit number
Coding
CONT3
CONT2
CONT1
CONT0
1.0 + 2.0
1
1
1
0
1.1 + 2.3
1
1
1
1
DSP
bus
α 70
time index
Port
Bit
Data
A
A7
A6
A5
A4
A3
A2
A1
A0
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 70
α 60
α 50
α 40
α 30
α 20
α 10
α 00
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 72
α 62
α 52
α 42
α 32
α 22
α 12
α 02
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 74
α 64
α 54
α 44
α 34
α 24
α 14
α 04
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
α 76
α 66
α 56
α 46
α 36
α 26
α 16
α 06
B
B7
B6
B5
B4
B3
B2
B1
B0
β 70
β 60
γ 70
γ 60
T
T
T
T
β 70
β 60
γ 70
γ 60
T
T
T
T
β 50
β 40
γ 50
γ 40
T
T
T
T
β 50
β 40
γ 50
γ 40
T
T
T
T
β 30
β 20
γ 30
γ 20
T
T
T
T
β 30
β 20
γ 30
γ 20
T
T
T
T
β 10
β 00
γ 10
γ 00
T
T
T
T
β 10
β 00
γ 10
γ 00
T
T
T
T
C
C7
C6
C5
C4
C3
C2
C1
C0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T*
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Time Index
*
T … Tristate
Semiconductor Group
19
SDA 9205-2
Output Coding for Binary/Two’s Complement Mode
Binary or two’s complement output coding is selectable for each separate output port (A, B, C) via
control inputs DTA, DTB, DTC. This coding is independent from selected formats (8:8:8, 8:4:4,
8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1).
Table 1
Output Coding for Formats 8:8:8, 8:4:4, 8:2:2, 8:1:1, 4:8:8, 4:4:4, 4:2:2, 4:1:1
Table 1 is valid for VREFL = 0.5 V and VREFH = 2.5 V
Step
VIN
Converter
A
VIN
Converter
B, C
OFL UFL Binary
Bit
Bit
Output
76543210
Two’s
Complement
76543210
Underflow
0
1
.
.
.
.
254
255
Overflow
< VCA – 0.125 V
VCA – 0.125 V
VCA – 0.117 V
.
.
.
.
VCA + 1.867 V
VCA + 1.875 V
> VCA + 1.875 V
< VCB, C – 1 V
VCB, C – 1 V
VCB, C – 0.992 V
.
.
.
.
VCB, C + 0.992 V
VCB, C + 1 V
> VCB, C + 1 V
0
0
0
.
.
.
.
.
0
1
10000000
10000000
10000001
.
.
.
.
01111110
01111111
01111111
1
0
0
.
.
.
.
.
0
0
00000000
00000000
00000001
.
.
.
.
11111110
11111111
11111111
VCA = ext. clamping level during CLAMP high pulse at Cext cl on channel AINA.
VCB, C = ext. clamping level during CLAMP high pulse at Cext cl on channel AINB and AINC.
In output format 4:2:2 a special suppression of code 0 and code 255 is provided in the binary output
mode.
Semiconductor Group
20
SDA 9205-2
Table 2
Output Coding for Format 4:2:2
Table 2 is valid for VREFL = 0.5 V and VREFH = 2.5 V
Step
VIN
Converter
A
VIN
Converter
B, C
OFL UFL Binary
Bit
Bit
Output
76543210
Two’s
Complement
76543210
Underflow
0
1
2
.
.
253
254
255
Overflow
< VCA – 0.125 V
VCA – 0.125 V
VCA – 0.117 V
.
.
.
.
VCA + 1.867 V
VCA + 1.875 V
> VCA + 1.875 V
< VCB, C – 1 V
VCB, C – 1 V
VCB, C – 0.992 V
.
.
.
.
VCB, C + 0.992 V
VCB, C + 1 V
> VCB, C + 1 V
0
0
0
0
.
.
0
0
0
1
10000000
10000000
10000001
10000010
1
0
0
.
.
.
0
0
0
0
00000001
00000001
00000001
00000010
.
.
11111101
11111110
11111110
11111110
VCA = ext. clamping level during CLAMP high pulse at Cext cl on channel AINA.
VCB, C = ext. clamping level during CLAMP high pulse at Cext cl on channel AINB and AINC.
Semiconductor Group
21
SDA 9205-2
Block Diagram
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
Supply voltages1)
VCC, VDD
Input voltage range all inputs
VI
Ambient temperature
Storage temperature
1)
22
max.
6.5
V
– 0.3
VCC + 0.3
V
TA
0
70
°C
Tstg
– 55
125
°C
All voltage values are with respect to network ground terminal
Semiconductor Group
Unit
SDA 9205-2
Characteristics
VDD = 5 V ± 5 %, VCC = 5 V ± 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V
fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Power Requirements
Analog supply voltage
VCC
4.75
5
5.25
V
Pins 12, 18, 23
Digital supply voltage
VDD
4.75
5
5.25
V
Pin 61
Output stage supply
voltage
VDDQ
4.75
5
5.25
V
Pins 43, 56, 62
Analog supply current
ICC
160
mA
Sum of all VCC pins
Digital supply current
IDD
20
mA
Sum of all VDD pins
Output stages supply
current
IDDQ
40
mA
Sum of all VDDQ pins
Supply voltage
differential
VCC – VDD
– 0.25
0.25
V
Supply voltage
differential
VDDQ – VDD – 0.25
0.25
V
Reference voltage high
VREFH
2.5
V
Pins 10, 16, 22
Reference voltage low
VREFL
0.5
V
Pins 14, 20, 26
Reference current
IREF
8
mA
Pins 10, 16, 22
Reference ladder
resistance
RREF
250
Ω
each
Input range
VI
2
Vpp
Single-ended,
DC-15 MHz
Analog input
capacitance
CI
5
pF
AINA, AINB, AINC,
each
Required ext clamp
capacitance
Cext cl
10
nF
AINA, AINB, AINC,
each
Required signal source
resistance
RS
Analog input current
IAIN
Reference Inputs
0.4
Analog Inputs
Semiconductor Group
5
23
200
Ω
100
nA
AINA, AINB, AINC,
each
SDA 9205-2
Characteristics (cont’d)
VDD = 5 V ± 5 %, VCC = 5 V ± 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V
fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Digital Inputs
L-input voltage
H-input voltage
VIL
VIH
0
2.0
Input current
II
– 10
0.8
5
VDD
V
V
10
µA
VI = 0 V, VCC
0.4
V
V
ISINK = 1.6 mA
ISOURCE = 400 mA
20
µA
VQ = 0 V, VCC
30
MSPS
Digital Outputs
L-output voltage
H-output voltage
VQL
VQH
2.4
High impedance state
output current
IQZ
– 20
Performance
Sampling rate
27
Full power bandwidth
(– 3 dB)
BW
Diff. linearity (D.C.)
DNLE
Int. linearity (D.C.)
INLE
10
Clamping level accuracy CLA
MHz
± 0.5
LSB
± 0.5
±1
LSB
±1
±3
LSB
Gain error
GE
±3
LSB
Differential gain1)
DG
3
%
fI = 3.6/4.4 MHz
AIN = 1/10 FSR2 )
Differential phase1)
DP
Signal-to-noise ratio
4.4 MHz sinus
αS/N
3
42
46
degree
dB
without harmonics
4:1:1 mode DSP 1.0
4.4 MHz fundamental
4.4 MHz fundamental
4.4 MHz fundamental
Harmonic Distorsion
2./4. order
3. order
5./6. order
– 40
– 40
– 46
dB
dB
dB
Supply voltage rejection
2.5
%FSR/V2)
1)
2)
Sample test
Full scale range (FSR) = 2 V as specified
Semiconductor Group
24
SDA 9205-2
Characteristics (cont’d)
VDD = 5 V ± 5 %, VCC = 5 V ± 5 %, VREFH = 2.5 V, VREFL = 0.5 V, VGND = 0 V
fCLK = 27 MHz, all specifications min (TA) to max (TA) unless otherwise noted
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
ns
CL = 15 pF
max.
Timing (see figure 5)
Output data delay time
tQD
Output data hold time
tQH
6
ns
CL = 15 pF
CLK pulse width
tWH; tWL
10
ns
CL = 15 pF
CLK rise time
tTLH
5
ns
CL = 15 pF
CLK fall time
tTHL
5
ns
CL = 15 pF
Input data setup time
tSU
7
ns
CL = 15 pF
Input data hold time
tIH
6
ns
CL = 15 pF
Clamp input pulse width
tCi
10
CLK
cycles
1 nF ext. clamp cap.
25
Figure 5
Timing Diagram Port A, B, C
Semiconductor Group
25
SDA 9205-2
Sample output data-delay is shown on format 8:8:8 with DSP function 1.0 + 2.0
Figure 6
Diagram of Complete Timing
There is a delay of 9 clock cycles between sampling of an analog input signal and the corresponding
digital output signal.
Semiconductor Group
26
SDA 9205-2
Figure 7
Typ. SNR (without harmonics) versus Analog Frequency (411 Mode DSP 1.0)
References
Figure 8
Blocking the SDA 9205-2
Capacitors: 100 nF - Ceramic
10 nF - Tantal
47 µF - Elko
Semiconductor Group
27
SDA 9205-2
VCC
VDD
Grounding
Figure 8 (cont’d)
Blocking the SDA 9205-2
Semiconductor Group
28
SDA 9205-2
Chip Capacitors 100 nF (as near as possible to the socket)
Figure 8 (cont’d)
Blocking the SDA 9205-2
Semiconductor Group
29
SDA 9205-2
Figure 9
Application Circuit 1 (4:1:1 Format, for Siemens Featurebox)
Semiconductor Group
30
SDA 9205-2
Figure 10
Application Circuit 2 (4:1:1 Format, for General Application)
Semiconductor Group
31
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