LIN-Transceiver LDO TLE 6285 Target Data Sheet 1 Overview 1.1 Features • • • • • • • • • • • • • • • • • Single-wire transceiver, suitable for LIN protocol Transmission rate up to 20 kBaud Compatible to LIN specification Compatible to ISO 9141 functions Very low current consumption in sleep mode Control output for voltage regulator Short circuit proof to ground and battery Overtemperature protection Output voltage 5V, tolerance £ ± 2 % 150 mA output current capability Low-drop voltage Overtemperature protection Reverse polarity protection Short-circuit proof Adjustable reset threshold Wide temperature range Suitable for use in automotive electronics P-DSO-16-4 Type Ordering Code Package TLE 6285 G on request P-DSO-16-4 1.2 Description The TLE 6285 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. In order to reduce the current consumption the TLE 6285 offers a sleep operation mode. In this mode a voltage regulator can be controlled in order to minimize the current consumption of the whole application (VR in sleep mode <1µA!). The on-chip voltage regulator (VR) is designed for this application but it is also possible to use an external Version 1.02 1 2002-05-15 Target Data TLE 6285 voltage regulator. A wake-up caused by a message on the bus enables the voltage regulator and sets the RxD output low until the device is switched to normal operation mode. To achieve proper operation of the µC, the device supplies a reset signal. The reset delay time is selected application specific by an external capacitor. The reset threshold is adjustable. The IC is based on the Smart Power Technology SPT® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE 6285 is designed to withstand the severe conditions of automotive applications. Version 1.02 2 2002-05-15 Target Data TLE 6285 1.3 Pin Configuration (top view) GND 1 16 GND INHI 2 15 RD RO 3 14 RTh VCCO 4 13 VBAT INHO 5 12 BUS RxD 6 11 TxD ENLIN 7 10 VCCI GND 8 9 GND P-DSO-16-4 GND 1 INHI 2 RO 3 VCCO Leadframe 16 GND 15 RD 14 RTh 4 13 VBAT INHO 5 12 BUS RxD 6 11 TxD ENLIN 7 10 VCCI GND 8 9 GND Chip: Voltage Regulator Chip: Transceiver P-DSO-16-4 Figure 1 Version 1.02 Pinout 3 2002-05-15 Target Data TLE 6285 1.4 Pin Definitions and Functions: Pin No. Symbol Function 1,8,9,16 GND Ground; place to cooling tabs to improve thermal behavior 2 INHI Inhibit Voltage Regulator Input; TTL compatible, HIGH active (HIGH switches the VR on); connect to VBAT if not needed 3 RO Reset Output; open collector output connected to the output via a resistor of 20kW 4 VCCO 5V Output; connected to GND with 22µF capacitor, ESC<3W 5 INHO Inhibit LIN Output; to control a voltage regulator 6 RxD Receive Data Output; internal 30kW pull up to Vs, LOW in dominat state 7 ENLIN Enable LIN Input; integrated 30kW pull down, transceiver in normal operation mode when HIGH 10 VCCI 5V Supply Input; VCC input to supply the LIN transceiver 11 TxD Transmit Data Input; internal 30kW pull up to Vs, LOW in dominant state 12 BUS LIN BUS Output/Input; internal 30kW pull up to Vs, LOW in dominant state 13 VBAT Battery Supply Input; a reverse current protection diode is required, block GND with 100nF ceramic capacitor and 22µF capacitor 14 RTh Reset Threshold; internal defined typical 4.6V, adjustable down to 3.5V according to the voltage level on this pin; connect to GND if not needed 15 RD Reset delay; connected to ground via external delay capacitor Version 1.02 4 2002-05-15 Target Data TLE 6285 1.5 Functional Block Diagram VBAT 13 30 k9 Bus Output Stage Mode Control Driver 5 INHO 10 VCCI 7 ENLIN 11 TxD 6 RxD 5 GND 30 k9 12 Temp.Protection Receiver TLE 6259 G TLE 4299 VBat I13 4Q VCCO Current and Saturation Control BandGapReference INHI INH2 RSO RRO Inhibit Control SO SI 3RO RO Reference Reset Control R RADJ Th 14 1,8,9,16 15 Figure 2 Version 1.02 D GND RD GND AEB03104 Block Diagram 5 2002-05-15 Target Data TLE 6285 2 Circuit Description The TLE 6285 is a single-wire transceiver combined with a LDO. It is a chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6285 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed for sleep mode applications but it is also possible to use an external voltage regulator. Start Up Power Up Normal Mode ENLIN INHO VCC ON high high ENLIN ENLIN low high Stand-By ENLIN (VCC high ON) ENLIN INHO RxD VCC low high low1) ON high3) Sleep Mode Wake Up t > tWAKE ENLIN INHO VCC low floating OFF2) 1) 2) 3) Figure 3 2.1 after wake-up via bus ON when INHO not connected to INHI after start up Operation Mode State Diagram Operation Modes In order to reduce the current consumption the TLE 6285 offers a sleep operation mode. This mode is selected by switching the enable input EN low (see figure 3, state diagram). In the sleep mode a voltage regulator can be controlled via the INHO output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus automatically enables the voltage regulator by switching the INHO output high. In parallel the wake-up is indicated by setting the RxD output low. When entering the normal mode this wake-up flag is reset and the RxD output is released to transmit the bus data. Version 1.02 6 2002-05-15 Target Data TLE 6285 In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE6285 can be set in normal operation mode without a wake-up via the communication bus. 2.2 LIN Transceiver The LIN Transceiver has already a pull up resistor of 30kW as termination implemented. There is also a diode in this path, to protect the circuit from feedback of voltages from the bus line to the power supply. To configure the TLE 6285 as a master node, an additional external termination resistor of 1kW is required. To avoid reverse currents from the bus line into the battery supply line in case of an unpowered node, it is also recommended to place a diode in series to the external pull up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1nF in the master node (see figure 6, application circuit). An capacitor of 10µF at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. 2.3 Input Capacitor The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 W in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values ³ 22 mF and an ESR of £ 5 W within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted. 2.4 Voltage regulator The 6285 incorporates a PNP based very low drop linear voltage regular. It regulates the output voltage to VCC = 5 V for an input voltage range of 5.5 V £ VI £ 45 V. The control circuit protects the device against potential caused by damages overcurrent and overtemperature. The internal control circuit achieves a 5 V output voltage with a tolerance of ± 2% in the temperature range of Tj = – 40 to 150 °C. The device includes a power on reset and an under voltage reset function with adjustable reset delay time and adjustable reset switching threshold as well as a sense control/early warning function. The device includes an inhibit function to disable it when the ECU is not used for example while the motor is off. The reset logic compares the output voltage VCC to an internal threshold. If the output voltage drops below this level, the external reset delay capacitor CD is discharged. When VD is lower than VLD, the reset output RO is switched Low. If the output voltage drop is Version 1.02 7 2002-05-15 Target Data TLE 6285 very short, the VLD level is not reached and no reset-signal is asserted. This feature avoids resets at short negative spikes at the output voltage e.g. caused by load changes. As soon as the output voltage is more positive than the reset threshold, the delay capacitor is charged with constant current. When the voltage reaches VUD the reset output RO is set High again. The reset threshold is either the internal defined VRT voltage (typical 4.6 V) or can be lowered by a voltage level at the RTh input down to 3.5 V. The reset delay time and the reset reaction time are defined by the external capacitor CD. The reset function is active down to VI = 1 V. The device is capable to supply 150 mA. For protection at high input voltage above 25 V, the output current is reduced (SOA protection). 2.5 Reset The power on reset feature is necessary for a defined start of the microprocessor when switching on the application. For the reset delay time after the output voltage of the regulator is above the reset threshold, the reset signal is set High again. The reset delay time is defined by the reset delay capacitor CD at pin RD (refer to figure 4 and 5). The under-voltage reset circuitry supervises the output voltage. In case VQ decreases below the reset threshold the reset output is set LOW after the reset reaction time. The reset LOW signal is generated down to an output voltage VCC to 1 V. Both the reset reaction time and the reset delay time is defined by the capacitor value. The power on reset delay time is defined by the charging time of an external delay capacitor CD. CD = (td ´ ID) / DV With CD td DV DV ID [1] reset delay capacitor reset delay time = VUD, typical 1.8 V for power up reset = VUD – VLD typical 1.35 V for undervoltage reset charge current typical 6.5 mA For a delay capacitor CD =100 nF the typical power on reset delay time is 28 ms. The reset reaction time tRR is the time it takes the voltage regulator to set reset output LOW after the output voltage has dropped below the reset threshold. It is typically 1 ms for delay capacitor of 100 nF. For other values for CD the reaction time can be estimated using the following equation: tRR = 10 ns / nF ´ CD [2] The reset output is an open collector output with a pull-up resistor of typical 20 kW to Q. An external pull-up can be added with a resistor value of at least 5.6 kW. Version 1.02 8 2002-05-15 Target Data TLE 6285 In addition the reset switching threshold can be adjusted by an external voltage divider. The feature is useful for microprocessors which guarantee safe operation down to voltages below the internally set reset threshold of 4.65 V typical. If the internal used reset threshold of typical 4.65 V is used, the pin RADJ has to be connected to GND. If a lower reset threshold is required by the system, a voltage divider defines the reset threshold VRth between 3.5 V and 4.60 V: VRth = VRADJ TH ´ (R1 + R2) / R2 [3] VRADJ TH is typical 1.36 V. Version 1.02 9 2002-05-15 Target Data TLE 6285 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. -0.3 6 V -0.3 40 V -20 32 V -20 40 V t<1s -0.3 VCC V 0 V < VCC < 5.5 V Voltages Supply voltage Battery supply voltage Bus input voltage Bus input voltage Logic voltages at EN, TxD, RxD Input voltages at INH VCC VS Vbus Vbus VI + 0.3 VINH -0.3 VS V + 0.3 Output current at INH Reset output voltage Reset delay voltage Output voltage Vcc INHIBIT voltage Reset Threshold voltage Reset Threshold current Electrostatic discharge voltage at Vs, Bus Electrostatic discharge voltage IINH VR VD VQ VINH VTh ITh VESD 1 mA – 0.3 7 V – 0.3 7 V – 0.3 7 V – 40 45 V – 0.3 7 V – 10 10 mA -4 4 kV human body model (100 pF via 1.5 kW) VESD -2 2 kV human body model (100 pF via 1.5 kW) Tj -40 150 °C Temperatures Junction temperature Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Version 1.02 10 2002-05-15 Target Data TLE 6285 3.2 Operating Range Parameter Supply voltage Battery Supply Voltage Junction temperature Symbol VCC VS Tj Limit Values Unit Remarks min. max. 4.5 5.5 V 6 20 V – 40 150 °C – Thermal Shutdown (junction temperature) Thermal shutdown temp. Thermal shutdown hyst. TjSD DT 150 170 190 °C – 10 – K Rthj-a Rthj-a – 185 K/W – – 70 K/W – Thermal Resistances Junction ambient LIN Junction ambient Vreg Version 1.02 11 2002-05-15 Target Data TLE 6285 3.3 Electrical Characteristics 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Remarks Current Consumption LIN Current consumption ICC 0.5 1.5 mA recessive state; VTxD = VCC Current consumption IS 0.5 1.0 mA recessive state; VTxD = VCC Current consumption ICC 0.7 2.0 mA dominant state; VTxD = 0 V Current consumption IS 0.7 1.5 mA dominant state; VTxD = 0 V Current consumption IS 20 30 µA sleep mode; Tj = 25 °C Current consumption IS 20 40 µA sleep mode Current Consumption Vreg Current consumption; Iq = II – IQ Iq – 65 105 mA Inhibit ON; IQ £ 1 mA, Tj < 85 °C Current consumption; Iq = II – IQ Iq – 65 100 mA Inhibit ON; IQ £ 1 mA, Tj = 25 °C Current consumption; Iq = II – IQ Iq – 170 500 mA Inhibit ON; IQ = 10 mA Current consumption; Iq = II – IQ Iq – 0.7 2 mA Inhibit ON; IQ = 50 mA Current consumption; Iq = II – IQ Iq – – 1 mA VINHI = 0 V; Tj = 25 °C -0.7 -0.4 mA VRD = 0.8 x VCC, mA VRD = 0.2 x VCC, Receiver Output R´D HIGH level output current LOW level output current Version 1.02 IRD,H IRD,L 0.4 12 0.7 2002-05-15 Target Data TLE 6285 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. 0.44 x VS 0.48 x VS Unit Remarks max. Bus receiver V -8 V < Vbus < Vbus,dom 0.56 x VS V Vbus,rec < Vbus < 20 V 0.04 x VS 0.06 x VS mV Vbus,hys = Vbus,rec - Vbus,dom 0.55 x VS 0.70 x VS V 2.9 0.7 x V Receiver threshold voltage, recessive to dominant edge Vbus,rd Receiver threshold voltage, dominant to recessive edge Vbus,dr 0.52 x VS Receiver hysteresis Vbus,hys 0.02 x VS Vwake 0.40 x VS HIGH level input voltage threshold VTD,H TxD input hysteresis VTD,hys VTD,L wake-up threshold voltage Transmission Input T´D LOW level input voltage threshold TxD pull up current recessive state VCC 300 600 mV 0.3 x 2.1 V dominant state -80 µA VTxD < 0.3 Vcc VS V VTxD = VCC 1.5 V VTxD = 0 V; 125 mA Vbus,short = 13.5 V mA VCC = 0 V, VS = 0 V, Vbus = -8 V, Tj < 85 °C VCC = 0 V, VS = 0 V, Vbus = 20 V, Tj < 85 °C VCC ITD -150 -110 Bus transmitter Bus recessive output voltage Vbus,rec 0.9 x VS Bus dominant output voltage Vbus,dom 0 Bus short circuit current Ibus,sc 40 85 Leakage current -100 Bus pull up resistance Version 1.02 Ibus,lk Rbus -350 20 13 5 20 mA 30 47 kW 2002-05-15 Target Data TLE 6285 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. 2.8 0.7 x Unit Remarks Enable input (pin ENLIN) HIGH level input voltage threshold VEN,on LOW level input voltage threshold VEN,off EN input hysteresis VEN,hys REN EN pull down resistance V normal mode V low power mode VCC 0.3 x 2.2 VCC 300 600 mV 15 30 60 kW 0.5 1.0 V IINHO = - 0.15 mA 5.0 µA sleep mode; VINHO = 0 V Inhibit output (pin INHO) HIGH level drop voltage DVINH = VS - VINH DVINH Leakage current IINH,lk - 5.0 Output voltage VQ 4.90 5.00 5.10 V 1 mA £ IQ £ 100 mA; 6 V £ VI £ 16 V Output voltage VQ 4.85 5.00 5.15 V IQ £ 150 mA; 6 V £ VI £ 16 V Current limit IQ Vdr D VQ D VQ 250 400 500 mA – – 0.22 0.5 V IQ = 100 mA1) – 5 30 mV IQ = 1 mA to 100 mA – 10 25 mV VI = 6 V to 28 V; IQ = 1 mA Power Supply Ripple rejection PSRR – 66 – dB fr = 100 Hz; Vr = 1 VSS; IQ = 100 mA Output voltage VQ 4.90 5.00 5.10 V 5 mA £ IQ £ 150 mA; 6 V £ VI £ 28 V Output voltage VQ 4.90 5.00 5.10 V 6 V £ VI £ 32 V; IQ = 100 mA; Tj = 100 °C Vcc Output (pin Vcco) Drop voltage Load regulation Line regulation Version 1.02 14 2002-05-15 Target Data TLE 6285 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. Unit Remarks max. Reset Generator (pins RO,RD) Switching threshold Reset pull up Reset low voltage External reset pull up Delay switching threshold Switching threshold Reset delay low voltage Charge current Reset delay time Reset reaction time Reset adjust switching threshold Vrt RRO VR 4.50 4.60 4.80 V – 10 20 40 kW – – 0.17 0.40 V VQ < 4.5 V; internal RRO; IR = 1 mA VR ext VDT VST VD Ich td trr VRADJ TH 5.6 – – kW Pull up resistor to Q 1.5 1.85 2.2 V – 0.40 0.50 0.60 V – – – 0.1 V VQ < VRT 4.0 8.0 12.0 mA VD = 1 V 17 28 35 ms CD = 100 nF 0.5 1.2 3.0 ms CD = 100 nF 1.26 1.36 1.44 V VQ > 3.5 V Inhibit Input (pin INHI) Inhibit OFF voltage range VINH – – 0.8 V VQ off – – V VQ on 3 5 mA VINHI = 5 V 0.5 2 mA VINHI = 0 V OFF Inhibit ON voltage range High input current Low input current VINH ON 3.5 IINH ON – IINH OFF – Note: The reset output is low within the range VQ = 1 V to VQ,rt 1) Drop voltage = Vi – VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 6 V input) Version 1.02 15 2002-05-15 Target Data TLE 6285 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kW; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Remarks Dynamic Transceiver Characteristics falling edge slew rate Sbus(L) -3 -2.0 -1 V/µs 80% > Vbus > 20% Cbus= 3.3 nF; Tambient < 85 °C; VCC = 5 V; VS = 13.5 V rising edge slew rate Sbus(H) 1 1.5 3 V/µs 20% < Vbus < 80% Cbus= 3.3 nF; VCC = 5 V; VS = 13.5 V Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) 2 5 10 µs Cbus = 3.3nF; VCC = 5 V; VS = 13.5 V CRxD = 20 pF Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) 2 5 10 µs Cbus = 3.3 nF; VCC = 5 V; VS = 13.5 V CRxD = 20 nF Propagation delay TxD LOW to bus td(L),T 1 4 µs VCC = 5 V Propagation delay TxD HIGH to bus td(H),T 1 4 µs VCC = 5 V Propagation delay bus dominant to RxD LOW td(L),R 1 4 µs VCC = 5V; CRxD = 20pF Propagation delay bus recessive to RxD HIGH td(H),R 1 4 µs VCC = 5 V; CRxD = 20 pF Receiver delay symmetry tsym,R tsym,T twake -2 2 µs tsym,R = td(L),R - td(H),R -2 2 µs tsym,T = td(L),T - td(H),T 200 µs Transmitter delay symmetry Wake-up delay time Version 1.02 30 16 100 2002-05-15 Target Data TLE 6285 4 Diagrams VI < trr t VQ VQ, rt dV ID, ch = dt CD VD t VDU VDRL trd trr t VRO t Power-ON Reset Figure 4 Version 1.02 Overtemperature Voltage Drop at Input Undervoltage Secondary Load Bounce Spike AET03066 Time Response, Watchdog with High-Frequency Clock 17 2002-05-15 Target Data TLE 6285 Typical Performance Characteristics Output Voltage VQ versus Temperature Tj AED01671 5.2 VQ Output Voltage VQ versus Input Voltage VI AED01808 12 VQ V 5.1 V 10 V Ι = 13.5 V 5.0 8 4.9 6 4.8 4 4.7 2 4.6 -40 0 40 80 0 120 C 160 Tj Version 1.02 RL = 50 Ω 0 2 4 6 8 V 10 VΙ 18 2002-05-15 Target Data TLE 6285 Charge Current Ich versus Temperature Tj Drop Voltage Vdr versus Output Current IQ AED03108 12 ID µA VDR AED02929 400 mV 10 125 ˚C 300 8 VI = 13.5 V VD = 1 V 25 ˚C 250 6 200 150 4 100 2 50 0 -40 0 40 80 0 120 ˚C 160 0 50 100 150 mA 200 Tj IQ Switching Voltage Vdt and Vst versus Temperature Tj Reset Adjust Switching Threshold VRADJTH versus Temperature Tj AED01804 3.2 VD V 2.8 AED03109 1.5 V VRADJTH 1.4 V Ι = 13.5 V 2.4 1.3 VUD 2.0 1.2 1.6 1.2 1.1 0.8 VLD 1.0 0.4 0 -40 0 40 80 0.9 -40 120 C 160 40 80 120 ˚C 160 Tj Tj Version 1.02 0 19 2002-05-15 Target Data TLE 6285 Sense Threshold Vsi versus Temperature Tj Output Current Limit IQ versus Input Voltage VI AED02933 1.6 VSi AED03110 350 Ι Q mA V 300 1.5 Sense Output High 250 1.4 Sense Output Low Tj = 25 C 200 1.3 150 Tj = 125 C 1.2 100 1.1 50 1.0 -40 0 40 80 0 120 ˚C 160 0 10 20 30 Tj VΙ Current Consumption Iq versus Output Current IQ Iq Current Consumption Iq versus Output Current IQ AED02931 1.0 mA Iq 4 0.6 3 0.4 2 0.2 1 0 10 20 30 40 0 mA 60 IQ Version 1.02 AED02932 5 mA 0.8 0 40 V 50 0 50 100 150 mA 200 IQ 20 2002-05-15 Target Data TLE 6285 5 Application Vbat LIN bus master node 13 VBAT 22 µF 100 nF 1k 12 5 RO 3 ENLIN 7 RxD 6 Bus TxD 11 INHO VCCI 10 TLE 6285 G 2 VCCO INHI µP GND 100 nF 100 nF 5V 4 R1 15 RD GND RTh 1,8,9,16 CD 22 µF 14 R2 100 nF ECU 1 slave node 13 VBAT 22 µF 100 nF 12 5 RO 3 ENLIN 7 RxD 6 Bus TxD 11 INHO VCCI 10 TLE 6285 G 2 VCCO INHI µP GND 100 nF 100 nF 5V 4 R1 15 CD Figure 5 Version 1.02 RD GND RTh 1,8,9,16 100 nF 22 µF 14 R2 ECU X Application Circuit 21 2002-05-15 Target Data TLE 6285 6 Package Outlines P-DSO-16-4 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm Version 1.02 22 2002-05-15 Target Data TLE 6285 Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 München © Infineon Technologies AG1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Version 1.02 23 2002-05-15