8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED AD9641 D D C SYNC SYNCSYNC+ DUT_CSB SP1 PDWN 7 9 10 22 23 24 KP_VDDIO AVDD DRVDD DVDD_KP33 VINVIN+ 28 VIN 29 26 1 3 6 AVDD_CLK 8 32 27 AVDD_PIPE 30 31 AVDD_FL 19 5 CLKN 4 CLKP 21 AVDD_REF CLKCLK+ DUT_SCLK DVDD 12 16 18 DRVDD DUT C104 0.1UF C107 0.1UF C101 0.1UF C103 1UF C121 1UF C122 1UF SCLK VIP U101 DOUT_N DOUT_P AD9641_PRELIM SDIO SYNC SYNC_N SYNC_P CSB MODE PDWN VCM NC_KPI 14 15 DATADATA+ 20 DUT_SDIO 25 VCM 2 DGND R106 100 KP_ICELL DNI C109 0.1UF PAD 11 13 17 AVDD SYNC- PAD DGND DGND C SYNC+ C110 0.1UF AGND C111 0.1UF C112 0.1UF C115 0.1UF C116 0.1UF C117 1UF C118 1UF C119 0.1UF C120 0.1UF AGND VCM C105 0.1UF AGND B B SYNC J101 1 R101 0 2 3 4 5 AGND R105 49.9 DNI DNI 2.0K R102 AVDD C123 SP1 1 2 SYNC 0.1UF R103 2.0K AVDD P102 SPARE P101 PDWN AGND 1 2 PDWN DNI AGND AGND A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 1 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS 2 3 4 6 5 CR202 A C AGND DATE APPROVED A C D 261 PGND DESCRIPTION POWER VIN R201 D 1 SK33A-TP CR201 A C N PJ-202A 10UF C201 P 1 2 3 F201 1 2 1.1A CR203 P201 REV FL201 BNX016-01 E212 1 2 3P3V_DIGITAL 10UF N C231 100MHZ 0.1UF C232 P AGND P202 DGND 1 2 3 4 5 6 10UF C233 100MHZ 0.1UF C234 P DRVDD N Z5.531.3625.0 E213 1 2 DGND DGND E214 1 2 AGND E215 1 2 P P203 4.7UF 100MHZ E205 1 2 E210 R204 100K U206 ADP2108AUJZ-1.8-R7 DNI AGND 1 VIN 1.00K R222 3 A 5 SW 4 EN FB GND 2 DNI 1 L201 L202 DNI DNI 2.2UH 2.2UH C213 10UF DNI 2 PAD TO EVALUATE SHARING OF AVDD AND DVDD GROUND PLANE TIES 4.7UF DNI SS GND1 PAD B E207 1 2 C230 OPTIONAL SWITCHING POWER SUPPLY 4.7UF C229 C212 1UF C228 C211 10UF JP204 1 2 0 0.01UF ADP1706ARDZ-1.8-R7 U205 1 EN 7 SENSE 3 5 IN OUT 4 6 IN2 OUT2 8 JP203 1 2 0 100MHZ 100MHZ AGND AVDD DNI 2 PAD AGND E206 1 2 100MHZ E201 1 2 DNI SS GND1 PAD AGND 4.7UF JP202 1 2 0 4.7UF C226 JP201 1 2 0 CR206 A C C225 CR205 A C C210 10UF 100MHZ Z5.531.3425.0 ADP1706ARDZ-1.8-R7 U204 1 EN 7 SENSE 3 5 IN OUT 4 6 IN2 OUT2 8 DGND B 3P3V_ANALOG N 100MHZ C227 C209 0.01UF C207 4.7UF C208 GND 2 3P3V_DIGITAL 10UF BYP E208 1 2 E216 1 2 P E204 1 2 AGND 1 2 3 4 DNI 0.1UF C240 ADP1713AUJZ-3.3-R7 5 0.01UF OUT 10UF 100MHZ U203 1 IN 3 EN 4 1 5V_SUPPORT N DNI AGND C TP201 100MHZ 0.1UF C238 4.7UF C206 2 0.01UF 4.7UF C204 C205 GND AGND 3P3V_ANALOG C237 BYP C 10UF N E202 1 2 C239 OUT ADP1713AUJZ-3.3-R7 5 100MHZ 1 IN 3 EN 4 E203 1 2 VIN C236 U202 CR204 A C C235 100MHZ 0.1UF P AVDD DRVDD 100MHZ AGND RS201 0 RS202 0 DNI RS203 0 DNI RS204 0 DNI RS210 0 DNI RS211 0 DNI DGND 2 DGND C215 10UF 100MHZ E209 1 2 DNI C214 10UF E211 1 AGND AGND DNI DNI DNI RS205 0 RS206 0 DNI RS207 0 DNI RS208 0 DNI RS209 0 DNI 100MHZ 2 DGND A AGND AGND 100MHZ AGND C216 10UF DNI AN A LOG DEV CES AGND THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 2 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED ANALOG INPUT D C303 PASSIVE PATH AMP_IN+ AMP_OUT+ DNI R309 0 DNI 3 DNI 6 DNI AGND R304 49.9 DNI R305 R306 0 0 1 4 ADT1-1WT+ T301 SEC T303 3 4 ETC1-1-13 T302 3 6 T304 0.1UF 2 AGND DNI VCM L301 82NH R314 36 0.1UF SHARE PADS AGND 0 VIN- AGND C306 R307 0 33 R313 36 C301 0.1UF 1 4 ADT1-1WT+ DNI R310 0 R319 R316 R320 33 0 R312 0 VIN+ R318 49.9 DNI C AGND C304 AMP_IN- AMP_OUT- LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER 8.2PF 1 DNI PRI 4 DNI J302 C 1 PRI DNI AGND 5 AGND 2 VCM 2 3 4 5 DNI R315 8.2PF R308 0 AGND R317 49.9 C302 R301 49.9 2 3 4 5 R311 0 C305 ETC1-1-13 0 3 0 SEC R303 SHARE PADS 5 AIN R302 AGND DNI 1 J301 1 8.2PF D AGND NOTE: CUTS REQ'D FOR 2ND TRANSF USE B B A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 3 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED ACTIVE PATH 3P3V_ANALOG D P C404 0.1UF N AGND D C405 10UF AGND THESE RLCS ARE PLACE HOLDERS... PLACE CORRECT VALUES & COMPONENTS... C401 R401 40.2 AMP_IN+ PRI SEC C406 0 1 VIP2 2 VIP1 3 VIN1 4 R405 AMP_IN- 4 3 ETC1-1-13 AGND 0 0.1UF R408 11 10 PD_N_A 12 DNI ENBL GND ADL5562_PRELIM R402 40.2 VCOM 9 PAD DNI DNI R411 1.00K C407 DNI DNI L405 82NH C408 0.1UF DNI C410 5PF C409 5PF 0 DNI VCM 120NH DNI R410 1.00K DNI C403 0.1UF AGND 3P3V_ANALOG 1JP401 2 JPR0402 120NH 0.1UF 0 DNI R409 VIN2 0 R406 C402 AMP_OUT+ VCC VOP VON L403 L401 U401 5 6 7 8 0 DNI R404 0.1UF 13 14 15 16 PAD 5 1 T401 R403 AGND DNI R412 DNI 0 L406 DNI VCM DNI 82NH L402 L404 DNI AMP_OUT- 0.1UF 120NH 120NH DNI DNI DNI AGND AGND R407 1.1K P401 PD_N_A C 1 2 C AGND B B A A AN A LOG DEV CES THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 4 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV OUT0_N 3 49.9 1 2 3 C508 4 5 0.33UF 6 7 8 9 C511 0.47UF 10 3.3V_PLL2 11 C512 12 0.1UF DNI C507 0.1UF C R506 0 C510 DNI C509 0.001UF TBD0402 0.001UF R507 AGND REFA REFA_N REFB REFB_N LF1_EXT_CAP OSC_CTRL OSC_IN OSC_IN_N LF2_EXT_CAP LDO_PLL2 VDD3_VCO LDO_VCO AGND 0 R525 REFCLK+ ADN4661BRZ R526 DNI OUT3_N AGND OUT3 R511 100 GND C AGND 100 C AGND R517 R518 10K 10K AGND 3.3V_OUT_2-5 1 J501 3.3V_OUT_2-5 USB_CSB2 CYP_SCLK CYP_SDI CYP_SDO 3.3V_OUT_2-5 OUT4_N OUT4 1.8V_OUT_0-5 L506 DRVDD B 1.8V_OUT_0-5 3.3V_PLL2 1UH L503 E501 1 2 3.3V_PLL1 1UH 45OHMS C533 CLK0.1UF R549 DNI 0 R550 DNI 3P3V_DIGITAL L504 E502 1 2 3.3V_OUT_0-1 1UH L505 45OHMS 1UH 3.3V_OUT_2-5 CLK_OUTREFCLK2- AGND REFCLK2+ A R551 REFCLK1- 0 R552 REFCLK1+ SCHEMATIC REFCLK- 0 R527 DNI REFCLK+ R553 DNI 0 R554 DNI AN A LOG DEV CES REFCLK2X+ THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. REFCLK2X- IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, 0 <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> OF ANALOG DEVICES. OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 6 DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS 7 AGND 2 TP505 0 8 A 200 NC7WZ16P6X 0 NC 4 3 5 6 GND 4 R514 A C CR501 CR502 10UF 0 REFCLK- 0 10K R545 DIN 200 TP503 3P3V_ANALOG DNI R534 10K R544 AGND 7 8 Y2 6 0 R524 0.1UF REF CLK U503 Y1 10UF C527 0 0 DNI 0 DNI R532 R547 0 0 R531 R548 CLK_IN+ C531 0.1UF DOUT_POS DOUT_NEG 1 1 TP504 R513 VCC 1 A1 3 A2 R540 24.9 3P3V_ANALOG 2 STATUS0/SP0 STATUS1/SP1 1.8V_OUT_0-5 OUT2 OUT2_N 3.3V_OUT_2-5 OUT3 OUT3_N EEPROM_SEL PDB RESETB U300 5 13 14 15 16 17 18 19 20 21 22 23 24 AGND 0 C530 36 35 34 33 32 31 30 29 28 27 26 25 3 AGND A STATUS_0_I2C_SP0 STATUS_1_I2C_SP1 VDD_1_8_OUT_2_3 OUT2 OUT2_N VDD3_OUT_2_3 OUT3 OUT3_N EEPROM_SEL PD_N RESET_N REF_TEST R543 100 2 R523 VCC TP502 10UF C534 AGND AGND 0.1UF 10UF C526 0 R541 DNI CR503 DNI DNI 1 AGND 3.3V_OUT_0-1 1UH L502 0.1UF DNI R538 DNI 49.9 R530 AGND C519 3.3V_REF 1 DNI 0.1UF 2 3 4 5 4 0.1UF 1 3 AGND 10UF C525 C523 J506 1 4 AGND DNI C524 0 2 SEC 0.1UF 0 AGND PRI 3.3V_OUT_0-1 R539 24.9 C528 C529 AGND CLK_OUT- 1UH L501 R542 DNI CLK R537 AGND 0.1UF C521 OUT2_N 5 4 3 2 0.1UF DNI T503 MABA-007159-000000 5 1 T502 ADT1-1WT+ 3 6 J503 1 R521 200 3.3V_REF CLK+ 0 49.9 2 3 4 5 C532 R522 0.1UF 0 CLK_OUT+ DNI R533 0 R528 DNI C522 J505 1 DNI R529 B DNI R519 SYNCB 10K 3.3V_REF CLK_IN- KP_ICELL DNI C516 0.1UF 0.1UF AD9524_PRELIM 0 R508 PASSIVE CLOCK KP_ICELL 0.1UF CLK_OUT+ OUT2 1 U501 DNI LAYOUT: SMA'S SHOULD BE 540 MILS CENTER TO CENTER LAYOUT: SHARE PADS WITH ACTIVE CLOCK PATH R'S C518 O4N OUT4_N PAD VDD3_CP LDO_PLL1 PLL1_OUT REF_SEL ZD_IN_N ZD_IN VDD_1_8_OUT_0_1 49.9 R505 C520 DNI SYNC_N VDD3_REF CS_N_SDA SCLK_SCL SDIO SDO OUT5_N OUT5 VDD3_OUT_4_5 OUT4_N OUT4 VDD_1_8_OUT_4_5 0.1UF AGND R509 0.1UF 49.9 60-800MHZ C506 R503 4DNI 5 AGND C504 D 1 2 3 C513 0.47UF 5 4 3 2 AGND R515 VCXO_CTRL R604 VC OUT+ OUTGND VCC DNI OUT0 OUT0_N VDD3_OUT_0_1 OUT1 OUT1_N R502 1K 0.1UF C505 Y501 R520 200 10K 0.1UF AGND 1 0.1UF PAD 48 3.3V_PLL1 47 46 45 44 43 42 1.8V_OUT_0-5 41 OUT0 40 OUT0_N 39 38 37 3.3V_REF 0.33UF C503 3.3V_PLL1 6 C514 0.1UF R501 C502 CLK_IN- SI04 1 0.1UF C515 TP501 49.9 D C501 CLK_IN+ OUT4 100 J502 1 O4 10K PECL/CML/LVDS CLK CIRCUITRY C517 OUT0 10K R516 R510 APPROVED DATE DNI R512 ACTIVE CLOCK PATH DESCRIPTION 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 5 1 OF 6 8 6 7 2 3 4 5 1 REVISIONS REV DESCRIPTION DATE APPROVED R603 1.1K C601 0.1UF DGND R626 1.1K 5 DGND 1 DNI TP604 Y1 FPGA_SDIO 3 A2 Y2 4 D DNI ADG734BRUZ 1 6 1 A1 DUT_SDIO 10 SA SB 9 7 D 8 3P3V_DIGITAL IN CYP_SDO U603 R606 GND 100K R602 10K R601 CYP_SDI R605 1.1K U601 NC7WZ07P6X VCC 2 SA 4 SB D 3P3V_DIGITAL 3 DU603 DRVDD IN DRVDD ADG734BRUZ DNI FAST_SPI_EN 2 0 DNI TP601 DGND DNI DNI C602 0.1UF LAYOUT: PLACE C705 NEAR DUT R607 CYP_SDIO 3P3V_DIGITAL 0 DNI DNI 1 DGND KP_VDDIO R608 0 C603 0.1UF Y1 6 CYP_CSB 3 A2 Y2 4 R612 10K R610 GND NC7WZ16P6X 2 DGND DGND 15 NC15 6 GND 5 VSS R613 R616 0 0 DNI DNI R614 R617 0 0 DGND ADG734BRUZ DGND DNI TP603 1 DUT_SCLK SPI & FPGA CONN. FPGA_SCLK 100K 1 A1 13 D U603 DUT_CSB VCC CYP_SCLK 11 DGND 1 12 SA 14 SB 18 D U603 TP602 NOTE: THIS SYMBOL IS DRAWN GIVEN INPUT 1 LOGIC DNI IN DNI DNI ADG734BRUZ IN 20 ADG734BRUZ DNI C FPGA_CSB R615 10K DNI 19 SA 17 SB U602 5 100K DGND R611 10K R609 C604 0.1UF DGND VDD FAST_SPI_EN DRVDD U603 16 DGND C LAYOUT: ROUTE ALL TRACES TO THE TYCO CONN ON TOP OF BOARD R618 0 0 B TP608 1 1 TP609 1 FAST_SPI_EN CYP_SDO CYP_SDI CYP_SCLK R620 DNI 0 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 SYNC- REFCLK2X- A DGND 6469169-1 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DNI DNI DNI P602 P602 P602 DGND TP610 TP611 1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 1 DNI TP612 1 FPGA_SCLK FPGA_CSB FPGA_SDIO B DGND PLUG HEADER D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PLUG HEADER P601 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 BG10 DNI P602 DGND P601 PLUG HEADER P601 PLUG HEADER REFCLK2X+ PLUG HEADER REFCLK1- C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 DNI DNI P602 P602 P601 REFCLK1+ DNI PLUG HEADER SYNC+ 1 TP607 PLUG HEADER CYP_CSB2 TP606 DNI D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 PLUG HEADER R628 CYP_CSB2 CYP_CSB B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DNI DNI PLUG HEADER 1 10K DNI USB_CSB2 R627 TP605 DNI PLUG HEADER DNI A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 PLUG HEADER 3P3V_DIGITAL PLUG HEADER P601 P601 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 REFCLK2- REFCLK2+ A LAYOUT: TYCO SPACING IS THE WIDER SPACING PER THE ALTERA BD LAYOUT: PLACE THESE R'S NEAR DUT R624 DATA+ 0 AN A LOG DEV CES R625 DATA- 0 THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS, SCHEMATIC <DRAWING_TITLE_HEADER> AD9641 CUSTOMER EVAL BD. DESIGN VIEW <DESIGN_VIEW> DRAWING NO. REV 9641CE01 B OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. SIZE PTD ENGINEER THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS OWNED OR CONTROLLED BY OWNED ANALOG DEVICES. 8 7 6 5 4 3 <PTD_ENGINEER> 2 D SCALE NONE SHEET 6 1 OF 6