AN2041 Understanding PSoC 1 Switched Capacitor Analog Blocks.pdf

AN2041
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Author: Dave Van Ess
Associated Project: Yes
Associated Part Family: CY8C29x66, CY8C28xxx, CY8C27x43,
CY8C24x23A,CY8C24x94
®
Software Version: PSoC Designer™ 5.2
Related Application Notes: For a complete list of the application notes, click here.
®
AN2041 explains the operation of PSoC 1's versatile switched capacitor analog blocks, and provides practical
examples of their use. Switched capacitor (SC) blocks are one of the two key components of PSoC 1's analog
functionality, and can be reconfigured to perform many useful functions. This application note also explains the
theory and application of these switched capacitor analog blocks.
Contents
Introduction .......................................................................2
Moving Charge ..................................................................2
Active Switched Cap Circuits ............................................3
Theme and Variation .........................................................3
Non-Inverting Amplifier .................................................4
Comparator ..................................................................4
Integrator ......................................................................5
Differentiator .................................................................6
Additional Switched Cap References ...........................6
Comparator as 2-bit ADC .............................................7
Real Analog-to-Digital Conversion ...............................7
Switched Capacitor PSoC Blocks .....................................8
Type C Switched Capacitor Blocks ..............................8
Type C Switched Cap Block Parameters......................9
Type D Switched Capacitor Blocks ..............................9
Type D Switched Cap Block Parameters.................... 10
SC Blocks and PSoC 1 Architecture ............................... 11
PSoC 1 SCBlock User Module ........................................ 11
www.cypress.com
Additional Applications .................................................... 12
Summary ......................................................................... 15
Related Application Notes ............................................... 16
Appendix A: Control Registers for a Type C Switched
Capacitor Block ............................................................... 17
Appendix B: Control Registers for a Type D Switched
Capacitor Block ............................................................... 17
Appendix C: A Input Multiplexer Connections ................. 17
Appendix D: C Input Multiplexer Connections ................. 18
Appendix E: B Input Multiplexer Connections ................. 18
Appendix F: C Code: 2-Bit ADC Example Project ........... 19
Appendix G: SC-Block Applications Cook Book .............. 21
Worldwide Sales and Design Support ............................. 28
Document No. 001-40440 Rev. *F
1
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Introduction
Analog circuit design involves the use of resistors,
capacitors, and integrated active devices. It is the nature
of integrated circuitry that small, accurate resistors are
harder and more expensive to build than small, accurate
capacitors. Because making capacitors is easier and
cheaper, techniques are developed to use capacitors to
build accurate analog circuitry. These techniques have led
to the use of switched capacitor (SC) architectures. These
architectures control the movement of charge between
capacitors with the precise timing of switches, instead of
relying on resistors. Switched capacitor analog blocks are
made up of a set of switched capacitors surrounding an
opamp. The switched capacitors allow configuration of the
block in many different modes, including as a comparator,
amplifier, integrator, differentiator, ADC, and more. This
application note provides the following:


A brief tutorial on switched capacitor techniques.


Examples of practical circuits using these blocks.
A detailed description of the switched capacitor PSoC
blocks.
Information on quick settings for a particular
application – Appendix G: SC-Block Applications
Cook Book
In the case of the switched capacitor, current is moved by
charging and discharging the capacitor. When the Φ1
switch is closed and the Φ2 switch is open, the capacitor
charges to the full potential. The equation of the charge
stored is shown in Equation 2.
q  CV
Equation 2
When the Φ1 switch is opened and Φ2 switch is closed, all
of this stored charge moves to the ground node. For each
precise sequential pair of switch closures, a quantum of
charge is moved. If these switches are controlled at the
frequency fs, the charge quanta also move at this
frequency. Equation 3 shows the current due to the
repetitive movement of charge across the switched
capacitor.
i  q / t  f s q  f sCV
Equation 3
Unlike in the case of the resistor, this current is not a
continuous movement of charge. The charge moves in
clumps (quanta). This is not a problem for a sampled
system where the signal is sampled at the end of each
sample cycle. The following equation shows that a
switched capacitor is equivalent to a resistor when they
have equivalent ratios of voltage drop against delivered
current. We can then replace a series resistor with a
parallel switched capacitor.
V
1
R
i
f sC
Moving Charge
Equation 4
Analog circuit design is all about controlling the movement
of charge between voltage nodes. Figure 1 shows charge
movement using a resistor and using a switched capacitor.
In the case of the resistor, current flow is created by the
voltage differential across the resistance. In the case of
the capacitor, current flow is created by electron
accumulation from the higher voltage node and discharge
into the lower voltage node.
The equivalent resistance is inversely proportional to the
capacitance and the switching frequency. The relative
value of the resistance may be altered, merely by
changing the switching frequency. The larger “C” is, the
larger the charge quanta. This results in more current and
a smaller equivalent resistance. Making “f s” bigger causes
more quanta to be transferred per unit time. This results in
a higher current and a lower effective resistance.
Figure 1. Two Methods for Moving Charge
The timing requirements for Φ1 and Φ2are
V
i
V
f1
q(t)
R
f2
q(t)
C
Equation 1 shows the current flow from a voltage potential
to ground through the resistor, a manipulation of Ohm’s
law, as shown in Figure 1. This current is a linear,
continuous movement of charge.
i
V
R
www.cypress.com

Never close the Φ1 and Φ2 switches at the same
time.

Give the Φ1 switch time to open before closing the Φ2
switch.

Give the Φ2 switch time to open before closing the Φ1
switch.

When selecting a sampling rate, allow enough time for
the circuitry to fully charge and discharge in the
allotted phase cycle.
Equation 1
Document No. 001-40440 Rev. *F
2
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 4. Configuration During Φ2 Phase
Active Switched Cap Circuits
f1
Simply moving charge is useful, but most circuits require
gain. Figure 2 shows a simple architecture for a fixed gain
amplifier. It consists of an opamp, an input capacitor (CA),
a feedback capacitor (CF), and five switches.
CF
q=Vin CA
Figure 2. Switched Cap Fixed Gain Inverting Amplifier
Vin
f1
CF
Vout
f1
f2
f1
CA
Equation 5 defines the amount of charge needed to excite
the input capacitor to the input voltage Vin.
f2
Vin
f1
CA
f2
f2
Vout
q  VinC A
Equation 5
f1
Figure 3 shows that three switches are closed during the
Φ1 phase.
This charge will take the only available path: through the
feedback capacitor. Therefore, the feedback capacitor
receives the same charge transfer. Equation 6 describes
the output voltage change due to this charge transfer.
Vout  
Figure 3. Configuration During Φ1 Phase
f1
CF
f2
Vin
0V
CA
f2
Gain 
0V
Vout
C
 A
Vin
CF
Equation 7
The result is an inverting amplifier with a gain set by the
ratio of its two capacitors.
Vout
f1
During Φ1 phase, the opamp is configured as a follower.
The opamp’s negative feedback drives the voltage at the
inverting input towards ground. The voltage will not be
exactly ground, because all opamps have input offset error
(Voffset). The input side of CA is pulled to ground, as is the
output side of CF. The offset voltage is added to both
capacitors. This removes the effect that this offset error
may have on the output during the charge transfer phase.
Because this offset removal happens without intervention
during the acquisition phase, it is known as an “autozero”
adjustment.
For a transition period between the phases, all of the
switches are open. This period is brief and the charge
stored on the capacitors does not change. This transition
period is known as “dead band”.
Figure 4 shows the configuration of the switches and the
flow of current during Φ2 phase.
www.cypress.com
Equation 6
Equation 7 combines Equation 5 and Equation 6 to
produce the transfer function for this amplifier.
V offset
f1
q
CF
Note that the output voltage is only correct at the end of
Φ2 phase. The output voltage will be near ground (at
Voffset) during Φ1 phase. For this reason, the sampling of
switched cap circuit outputs muse be timed properly.
The phase Φ2, in this case, is also referred to as signal
acquisition phase as the input capacitor acquires the input
signal. Phase Φ1 is referred to as charge transfer phase
as the charge acquired by input capacitor is transferred to
output.
Theme and Variation
The switched cap topology can be modified to achieve
more useful configurations. Some of these are described
below.
Note that in the explanation to all the below circuits,
following assumptions are made:
1.
Zero input offset voltage
2.
Mentioned voltages are referenced to analog ground
(AGND).
Document No. 001-40440 Rev. *F
3
Understanding PSoC® 1 Switched Capacitor Analog Blocks
3.
The current direction is drawn assuming input voltage
is greater than AGND value (which is same as
opamp’s non-inverting terminal voltage). If the input
voltage is less than AGND, the current direction is
reversed.
Figure 7. Non-Inverting Amplifier in Φ2 Phase
f1
Charges to
Vin x (CA/CF)
Non-Inverting Amplifier
Initially, Figure 5 appears to be an exact copy of Figure 2.
A closer examination shows that the input switches have
swapped phase. That is, Φ1 is now the signal acquisition
phase and Φ2 is the charge transfer phase. This
configuration creates a non-inverting amplifier.
CF
-
Discharges
through CF
Vin
+
+
+
f2
f1
CA
f1
Vout
Vout = Vin x CA/CF
f2
Figure 5. Switched Cap Non-Inverting Amplifier
f1
CF
Vin
Thus, the output voltage is proportional to the input rather
than inversely proportional. The result is a positive gain
amplifier with a gain defined in Equation 8.
f1
CA
f1
f2
Gain 
Vout
Vout C A

Vin CF
Equation 8
Figure 8 shows the modification that allows the correct
phasing for both positive and negative gain operation. A
multiplexer controls the input switching phase through a
“Sign” select signal.
f2
In this configuration, the input capacitor CA acquires Vin
during the acquisition phase Φ1 as shown in Figure 6.
Figure 8. Switched Cap Selectable Polarity Amplifier
f1
Figure 6. Non-Inverting Amplifier in Φ1 Phase
CF
f1
f2
Discharged
CF
CA
f2
f1
Vin
Charged to Vin
CA
Vin
+
+
+
f1
f2
-
f1
f2
f1
Vout
Sign
Vout
Vout = 0V
For the rest of these examples the “Sign” is assumed to be
positive, that is, the CA acquires Vin during Φ1 and moves
back to zero during Φ2.
Comparator
The charge needed to pull the input back to ground during
the transfer phase Φ2 moves in the opposite direction to
that of the first example shown in Figure 4. Charge moving
to Vout is likewise in the opposite direction as shown in
Figure 7.
www.cypress.com
Building a comparator using SC block is relatively easy.
Figure 9 shows a modification where the switch in series
with the feedback capacitor is removed.
Document No. 001-40440 Rev. *F
4
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 9. Switched Capacitor Comparator
Figure 12. Switched Capacitor Integrator
f1
f1
CF
CA
f2
f1
Vin
f2
Vout
CA
f1
Vin
Sign
This change removes the capacitor from the feedback
loop, effectively setting the capacitor value to zero.
Equation 8 states that the amplifier’s gain is the ratio of the
two capacitors. If the feedback capacitor is removed then
the gain is infinite and the amplifier acts like a comparator.
See Figure 10 and Figure 11 for current path, capacitor
and output voltage during Φ1 and Φ2 phase.
Figure 10. Comparator in Φ1 Phase
See Figure 13 and Figure 14 for integrator circuit in action.
Figure 13. Integrator in Φ1 Phase
Vin
+
+
+
f2
CF
CA charges to
Vin
f1
Vin
-
f2
assume sign is
positive
CA
+
+
+
+
-
Vout
Vout = 0V
Sign
assume sign is
positive
During Φ1 phase, input capacitor CA charges to input
voltage, whereas, feedback capacitor CF holds on to its
charge.
Figure 11. Comparator in Φ2 Phase
f1
Figure 14. Integrator in Φ2 Phase
CA
f2
-
f1
CF accumulates
charges
Vout
-
Vin
+
+
+
Vin
Sign
assume sign is
positive
CA discharges
through CF
Vout = HIGH if Vin < AGND
= LOW if Vin > AGND
f2
CA
f1
Vin
f2
Integrator
Integrators and differentiators can also be constructed
using SC blocks. Figure 12 shows that removing the
switch from CF to ground, prevents the charge on the
feedback capacitor from being removed during the
acquisition phase while still allowing the transfer of the
input charge.
www.cypress.com
CF
+
+
+
f1
f2
Vout
Vout = 0V
Sign
f1
No path for CF to
discharge
CA
f1
Vout
Sign
f1
CA charges
to Vin
f2
Sign
assume sign is
positive
Vout
Vout = VCF
During Φ2 phase, input capacitor CA discharges through
CF, thus transferring all its charge to CF.
Document No. 001-40440 Rev. *F
5
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Equation 9 defines its operation.
Vout  Vout z 1  Vin
CA
CF
Equation 9
Figure 17. Differentiator in Φ2 Phase
Manipulating Equation 9 results in the transfer function
shown in Equation 10.
Gain 
During Φ1 phase, input capacitor acquires input voltage
present at that particular instant, in this case, V in(T). The
feedback capacitor CF is discharged.
Vout C A
1
1 C 

  fs A 
Vin CF (1  z 1 ) s  CF 
f1
CF charges to
Δ*CA / CF
CF
Equation 10
CA charges to
Vin(T) + Δ
Equation 9 and Equation 10 state that this circuit is an
adjustable integrator whose gain can be varied by
changing the capacitor ratios or adjusting the sampling
frequency.
f2
f1
CA
Vin (T)+Δ
+
+
+
-
Vout
Differentiator
A differentiator may be created using a switched cap
block. Figure 15 shows that the analog input is
permanently connected to the input capacitor. This
topology makes the feedback capacitor behave like a
resistor and the input capacitor behave like a series
capacitor.
Figure 15. Switched Capacitor Differentiator
f1
CF
f2
f1
CA
Vout = Δ*CA / CF
During Φ2, let us assume that the input voltage changes
by Δ. This results in an increase in charge on the input
capacitor CA by Δ * CA. The same amount of charge is
transferred to CF as the current path is same. This gives
voltage across the feedback capacitor as Δ*CA/CF. Thus
the output voltage is proportional to the change in an input
voltage over time.
The differentiator operation can
modeled as given in equation 11.
Vin
V
Vout
in
be

 Vin z 1  C A  VoutCF
mathematically
Equation 11
Manipulating Equation 11 results in the transfer function
shown in Equation 12.
Figure 16 and Figure 17 shows the Differentiator operation
in Φ1 and Φ2.
Figure 16. Differentiator in Φ1 Phase
CF
CA is charged
to Vin(T)
CA
Vin(T)
+
+
+
-
 1 CA 
Vout
C

  1  z 1 A   s
Vin
CF
 f s CF 


Equation 12
Equation 12 shows that this is an adjustable gain
differentiator.
f1
CF is
discharged
Gain 
Additional Switched Cap References
f2
So far, all the examples have the input voltage referenced
to analog ground. Analog ground may be a convenient
reference point but others are also possible. Figure 18
shows a standard circuit with an improved reference
selection.
f1
Vout
Vout = 0V
www.cypress.com
Document No. 001-40440 Rev. *F
6
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 18. Improved Switched Cap Reference Selection
f1
CF

Less than Vref-
These four states make this circuit a 2-bit analog-to-digital
converter (ADC).
f2
Real Analog-to-Digital Conversion
CA
Sign
f1
f1
Vin
Vout
Vref+
Vref-
f2
Slight modification of the reference selection allows this
circuit to function as an analog to digital modulator. This
modification allows the output of the switched cap block to
control the reference selection, creating feedback and
creating a digital signal that can be measured to determine
the size of the analog input. Figure 20 shows that a
comparator is added to the output and is connected to the
reference selection mux.
ARefMux
Figure 20. Analog to Digital Modulator
ARefMux allows the selection of two other references
besides analog ground. Equation 13 defines the output
voltage for a switched cap amplifier given different
reference configurations. The equations are for the cases
where the reference is analog ground, Vref+ or Vref-.
Vout
Vout
Vout
Equation 13
f1
CA
f1
Vout
f2
With proper control of ARefMux, it is possible to determine
if Vin is:
Less than Vref+ but greater than ground
Less the ground but greater than Vref-
www.cypress.com
Vout
Vref+
Vref-
f2
Selecting the proper ARefMux value allows the output of
the comparator to determine the reference voltage. The
relationship is:

The reference is set to Vref+ when the comparator is
high (positive output value).

The reference is set to Vref- when comparator is low
(negative output value).
The switches around the feedback capacitor are
configured to make an integrator. The comparator control
causes a reference, with the same polarity as the V out, to
be subtracted from the input. This negative feedback
causes Vout to move back towards zero.
Equation 14 describes Vout, given the following conditions:
ARefMux
Greater than Vref+
Reset
ARefMux
Figure 19. Poor Man’s 2-bit Switched Cap ADC



f2
f1
Vin
Combining the comparator in Figure 9 with the reference
selection in Figure 18, results in a comparator with
multiple compare points, as shown in Figure 19. This kind
of comparator can be used as a simple 2 bit ADC.
Vref+
Vref-
CA
Sign
Comparator as 2-bit ADC
Vin
CF
C
 A Vin
CF
C
 A (Vin  Vref  )
CF
C
 A (Vin  Vref  )
CF
Sign
f1



The initial condition of Vout is zero.
The switch cycle is preformed “n” times.
Vout is greater than zero (comparator is high) “a” of
those times.
Vout 
CA
C
C
nVin  A aVref   A (n  a)Vref 
CF
CF
CF
Equation 14
Given that the references are of equal but opposite
polarity, solving for Vin results in the following equation.
Document No. 001-40440 Rev. *F
7
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Vin  Vref
2a  n  1 V
n
n
out

CF
; Vref  Vref   Vref 
CA

Equation 15
Vin is a function of Vref and Vout. As stated earlier, the
negative feedback causes Vout to move back towards
ground every cycle. This makes Vout less than (CA/CF)*Vref.
As “n” becomes larger, the contribution of Vout to
Equation 15 becomes negligible. This allows a simpler
Equation 16.

C
1
 2a   1
Vin  Vref 
 1 ;  Vout F  Vref  0  Equation 16
CA n
 n
 n

switch cycles. The range is -Vref (a = 0) to +Vref (a=n), and
the resolution is 2Vref/n. Longer the period (larger “n”) the
better the resolution of voltage measurement.
Switched Capacitor PSoC Blocks
The architecture previously discussed is quite versatile. It
allows many different functions merely by altering the
circuit’s switch closures. This architecture is used as the
basis for the SC blocks in the PSoC microcontroller and is
implemented with Type C and Type D switched capacitor
blocks.
Vin is not dependent on the ratio of the two capacitors. It is
only the ratio of “a” and “n”, and a function of V ref.
Measuring Vin is just a function of counting the number of
times the comparator is high (“a”) during a sequence of “n”
Type C Switched Capacitor Blocks
Figure 21 shows the Type C switched capacitor block. A larger copy of this diagram along with a map of the Control registers
for the block is in Appendix A. The canonical version of Figure 21 may be found in the PSoC 1 Technical Reference Manual
under Analog System > Switched Capacitor PSoC Block section.
Figure 21. Type C Switched Capacitor Block Architecture
f1 *AutoZero (9)
BQTAP
Fcap (1)
Ccap (10)
0,1,…,30,31 C
16,32 C
C Inputs
f2 +!AutoZero (9))
* FSW1 (12)
f1
ACMux (5)
f1
A Inputs
RefHi
RefLo
AGND
ARefMux (11)
Acap(4)
0,1,…,30,31 C
* FSW0
(13)
f2
AutoZero (9)
f1 *
!AutoZero (9)
f2
Asign (3)
Modulation
Inputs
Mod Bit Control
OUT
(7) AnalogBus * f2
ABUS
Power
(15)
Bcap (6)
0,1,…,30,31 C
(Comparator)
CBUS
f2
B Inputs
BMuxSC
(14)
www.cypress.com
f2
f1
Document No. 001-40440 Rev. *F
f1
CBUS
Driver
(8)
8
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 21 is similar to the architecture shown in
Figure 18, with the following additions:

A programmable CCap capacitor connects to the
summing node of the opamp inverting input.

A programmable BCap switched capacitor connects
to the summing node of the opamp inverting input.

An AnalogBus switch connects the opamp’s output to
an analog buffer.

A CompBus switch connects the comparator to the
digital blocks.
The BCap acts similar to the ACap except that it only
samples its input on Φ2 and is always referenced to
ground. It is generally used for multiple input amplifiers.
The CCap primarily benefits filter design.
Type C Switched Cap Block Parameters
PSoC 1’s switched cap blocks are most easily configured
using the user module interface in the PSoC Designer
IDE. There are 15 different parameters for a type C
switched cap block user module.
The parameters with descriptions of their operations are
given as follows:
1.
2.
FCap
A 1-bit field to set the value of FCap to either 16 or 32
units. Each unit of capacitance is approximately 50 fF.
ClockPhase
A 1-bit field that, when set, swaps the Φ1 and Φ2
phases. It is primarily used to match the input signal
sampling when input is taken from another SC block.
This is important as the output of a switched capacitor
is valid only during Φ2 phase and not on Φ1 phase, the
acquisition phase.
3.
ASign
A 1-bit field to set the gain of the block to either
positive or negative.
4.
ACap
A 5-bit field to set the value of ACap from 0 to 31
capacitance units.
5.
ACMux
A 3-bit field to select the inputs to the ACap and the
CCap. Appendix C and Appendix D show the
connection options.
6.
BCap
A 5-bit field to set the value of BCap from 0 to 31
capacitance units.
7.
AnalogBus
A 1-bit field that, when set, connects the output to an
analog buffer. This buffer can be used to drive pins or
other analog resources in the part.
www.cypress.com
8.
CompBus
A 1-bit field that, when set, connects the comparator
output to the data inputs of PSoC 1’s digital blocks.
9.
AutoZero
A 1-bit field that, when set, forces an autozero during
the Φ1signal acquisition phase.
10. CCap
A 5-bit field to set the value of CCap from 0 to 31
capacitance units.
11. ARefMux
A 2-bit field to select the voltage potential that the A
input is referenced to. It can be AGND, Vref+, Vref-, or a
voltage reference determined by the state of the
output comparator.
12. FSW1
A 1-bit field to select if FCap is connected. If set to
zero, FCap is not connected, and the block functions
as a comparator. If set to one, the FCap is in the
feedback path, and the circuit functions as a gain
stage or integrator.
13. FSW0
A 1-bit field to select if FCap is discharged during Φ1.
If set to one, the FCap is discharged and the circuit
functions as a gain stage. If set to zero, the capacitor
is not discharged and the circuit functions as an
integrator.
14. BMux(SCA)
A 2-bit field to set the inputs to the BCap.
Appendix E shows the connection options.
15. Power
A 2-bit field to set the power for the block. The options
are: off, low, medium, and high.
Type D Switched Capacitor Blocks
PSoC 1 also contains Type D switched capacitor blocks,
which allow for the construction of more complex analog
circuits. Figure 22 shows the type D switched capacitor
block. A map of the Control resistors for Type D SC-block
is given in Appendix BAppendix B. The canonical version
of Figure 22 may be found in the PSoC 1 Technical
Reference Manual under Analog System > Switched
Capacitor PSoC Block.
Document No. 001-40440 Rev. *F
9
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 22. Type D Switched Capacitor Block Architecture
f1*AutoZero
FCap
16,32
C
CCap
0,1,…,30,31 C
f2+!AutoZero)
* FSW1
BQTAP
f1* FSW0
A Mux (1)
A Inputs
RefHi
RefLo
AGND
ARefMux
ASign
f1
ACap
0,1,…,30,31 C
f2+AutoZero
f1 *
!AutoZero
f2
OUT
AnalogBus
f2 B
*
BCap
0,1,…,30,31 C
f2+!BSW (2)
B Inputs
ABUS
f2 +!BSW+AutoZero
Power
(Comparator)
CBUS
f1*BSW (2)
f1 *BSW*!AutoZero
BMuxSD (3)
f2
Figure 22 is similar to the Type C SC block shown in
Figure 21 with the following differences:


There is no multiplexed input to CCap but a
connection to the output of the block. The other side
of CCap connects to the summing node of the type C
SC block next to it. It is used to build biquad filters.
The control field BSW allows BCap to function as a
switched capacitor or as just a capacitor.
Type D Switched Cap Block Parameters
f1
CBUS
Driver

AMux
A 3-bit field to set the inputs to the ACap. Appendix C
shows the connection options.

BSW
A 1-bit field. When set, BCap functions as a switched
capacitor input. If not set, then BCap functions as a
series capacitor.

BMux(SD)
A 1-bit field to set the inputs to the BCap.
Appendix E shows the connection options.
There are 16 different parameters for a Type D switched
cap block. Thirteen are common with the Type C SC block
and have already been discussed. The remaining three
parameters with descriptions of their operations follow:
www.cypress.com
Document No. 001-40440 Rev. *F
10
Understanding PSoC® 1 Switched Capacitor Analog Blocks
SC Blocks and PSoC 1 Architecture
Figure 23 shows the array of analog blocks for the CY8C27x43 family of parts.
Figure 23. PSoC 1 Analog Block Array
There are four columns of analog blocks, with each
column having its own analog bus, comparator bus, and
clock to generate the Φ1 and Φ2 clocks.
Each column contains one type “C” SC block and one type
“D” SC block for a total of eight SCBlocks. The order of the
C and D blocks is reversed in each column, so that each
type C block is surrounded by type D blocks, and vice
versa.
PSoC 1 SCBlock User Module
The SCBlock User Module is found under the “generic”
category of User Modules in PSoC Designer IDE.
Figure 24 SCBlock User Module in Catalog
Different User Modules use different numbers of blocks.
For example:



The DAC6 User Module uses one SC block.


The LPF2 User Module uses two SC blocks.
The DAC8 User Module uses two SC blocks.
The DELSIG8, DELSIG11, and ADCINC12 ADC user
modules each use only one SC block.
The PWM8 is a digital only User Module and uses no
SC blocks.
The PSoC 1 switched capacitor blocks are
that one of the best ways to utilize them is to
settings of the block manually. To assist the
parameterized SC block User Module
developed.
www.cypress.com
so versatile
configure all
user, a fully
has been
This block may be placed in any of the eight available SC
blocks.
Document No. 001-40440 Rev. *F
11
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Additional Applications
Switched cap blocks can be used in many applications
besides those described previously. Some additional
examples are described in the following sections. The
project containing all three examples shown is distributed
along with this application note. Besides these examples,
Appendix G: SC-Block Applications Cook Book gives
settings for variety of applications using SC Block.
PSoC Designer Tool is used to create the projects for
PSoC 1. If you are new to PSoC 1 Designer, it is
recommended to go through online training material.
The two input buffers are programmable gain amplifier
(PGA) User Modules with matched gains. The three
switched cap blocks are populated with generic SC Block
user modules.
The difference output is defined by Equation 17.
Vdifference  PosInput  NegInput
Equation 17
The amplifier is an A-B amplifier with a gain of one. Its
parameters are shown in Figure 27.
Figure 27. Parameters for DiffBlock SCBLOCK
Example 1: Differential Amplifier with Common Mode
Output
A common mode output signal is useful to many signal
processing applications. It is also highly useful where the
common mode feedback is used to drive a shield or signal
guard. Figure 25 shows the architecture for a differential
amplifier with a common mode output. The PSoC
implementation is shown in Figure 26:
Figure 25. Differential Amplifier with Common Mode
Output
PosInput
P0.0
DiffBlock
Buf
1
NegInput
P0.1
ComBlock
1
2
P0.3
Differential
Signal
Buf
1
GainInvert
P0.5
Common
Mode
Signal
Figure 26. PSoC Block Placement of Differential Amplifier
with Common Mode Output
For a difference amplifier with a gain of one, the values of
FCap, ACap, and BCap must be the same. CCap is not
used so its value is set to zero. The continuous time
blocks source both input signals, and thus ClockPhase
can remain set to “Norm.” The ACMux is set to connect its
input to “ACB01.” ARefMux is set to “AGND” so both input
references have the same potential. BMux is set to
connect its input into “ACB00.” ASign is set to “Pos”. To
be an amplifier, FSW1, FSW0, and AutoZero must be set
“On.” The comparator is not used so CompBus is set to
“Disable.” AnalogBus is set to “AnalogOutBus0” so that
the output can be brought to the analog buffer on P0[3].
Power is set “High.”
The common mode output is defined by the Equation 18.
Vcommon 
PosInput  NegInput
2
Equation 18
A stage that can implement an A+B amplifier is required.
Unfortunately, the architecture limits the B input to
negative gains. The solution is to build a -A-B amplifier
and follow it with a gain stage of -1.
The parameters for a -A-B amplifier with a gain of one half
are shown in Figure 28:
www.cypress.com
Document No. 001-40440 Rev. *F
12
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 28. Parameters for the ComBlock SCBLOCK
to connect its input to “ASD11.” ARefMux is set to
“AGND.” BMux is not needed so it is not set. Again FSW1,
FSW0, and AutoZero must be set to “On.” The
comparator is not used so CompBus is set to “Disable.”
AnalogBus is set to “AnalogOutBus1” so that the output
can be brought to the analog buffer on P0[5]. Power for
this example is set to “High.” The actual setting for other
applications is determined by signal bandwidth.
These five blocks implement the circuit shown in
Figure 25. The column clocks are set to 1 MHz. This sets
the sample rate to 250 Ksps. It is recommended that when
used as amplifiers, the SC Blocks should not be sampled
faster than 350 Ksps.
Example Code: Example 1 only requires the PGA user
modules to be started. The code in C language follows.
For a gain of one half on both inputs, FCap is set to ‘32’
and both ACap and BCap are set to ‘16’. CCap is not
used so its value is set to zero. The continuous time
blocks source both input signals, and thus ClockPhase
can remain set to “Norm.” The AMux is set to connect its
input to “ACB01.” ARefMux is set to “AGND” so both
inputs references have the same potential. BMux is set to
connect its input into “ACB00.” BCap is required to be a
switched capacitor so BSW is set “On.” ASign is set to
“Neg.” To be an amplifier, FSW1, FSW0, and AutoZero
must be set “On.” The comparator is not used so
CompBus is set to “Disable.” AnalogBus is also not used
so it is set to “Disable.” Power is set to “High.”
This block is to be followed by a gain inversion stage. The
parameters for a -1 gain stage are shown in Figure 29.
Figure 29. Parameters for the GainInvert SCBLOCK
//-----------------------------------------// C main line
//----------------------------------------#include <m8c.h>
// part specific
constants and macros
#include "PSoCAPI.h"
// PSoC API
definitions for all User Modules
void main(void)
{
NegInput_Start(NegInput_HIGHPOWER);
PosInput_Start(PosInput_HIGHPOWER);
//No code necessary to start SC Blocks
while(1);
}
Example 2: A 2-Bit ADC
In Figure 19, a four state ADC was shown using a
SCBlock as a comparator and using the reference mux to
test different ranges. Figure 30 shows the block level
representation.
Figure 30. Two Bit ADC Example
PSoC
SCBlock
Comparator
Ain
MCU
P2.2
P1.1
P1.0
For a gain of -1, the values of Fcap and ACap must be the
same. BCap and CCap are not used so their values are
set to zero. ASign is set to “Neg." Its input is sampled on
the same phase as a valid Com Block output signal so
ClockPhase can remain set to “Norm.” The ACMux is set
www.cypress.com
D1out
D0out
The PSoC 1 implementation is shown in Figure 31. Note
that the PSoC 1 SC block is capable of implementing a 6bit SAR ADC using single SC block. It is available in the
form of a user module in PSoC Designer.
Document No. 001-40440 Rev. *F
13
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Figure 31. PSoC 1 SC Block Placement of TwoBit ADC
The input is brought in from P2[2] to an SCBlock (Instance
name: “TwoBit”). It is configured as a comparator.
Software manipulates the ARefMux field in Control
register TwoBit_cr3 to select the reference as Agnd, Vref+,
or Vref-.
Bit 7 of the Analog Comparator Control Register
(CMP_CR) allows the software to determine the state of
the column 3 comparator. This allows the software to
determine if the input is:




Greater than Vref+
Less than Vref+ but greater than analog ground
Less than analog ground but greater than VrefLess than Vref-
The parameters for a comparator with a configurable
reference are shown in Figure 32:
Figure 32. Parameters for the TwoBit SCBLOCK
For a comparator, the FCap is not connected so its value
is not important. ACap must be a non-zero value. BCap
and CCap are not used so their values are set to zero.
The input is from a continuous input signal so there is no
phase sampling problem and ClockPhase can remain set
to “Norm.” The AMux is set to connect its input to
“Port_2_2.” ARefMux must be controlled by software but
is set to a default value of “AGND.” BMux is not needed
so it is not set. ASign is set to “Pos." To be a comparator,
FSW1 and FSW0 must be set to “Off,” but AutoZero must
be set “On.” This disconnects the feedback capacitor.
Setting CompBus to “ComparatorBus_3” allows the CPU
access to the state of the comparator. AnalogBus is set
to “Disable.” BSW is not used and is set to “Off.” Power is
set “High.” The column clock is set to 8 MHz. This sets
the sample rate to 2 Msps. It is recommended that when
used as a comparator, the SC Blocks should not be
sampled faster than 2 Msps.
Example Code: In Example 2, the ARefMux reference is
controlled using software. This requires substantial code in
the main loop, shown in Appendix F.
Example 3: Isolated Analog Driver
It is sometimes necessary to get an analog signal across
an isolated barrier. For a higher frequency signal with no
DC component, this is easily done with capacitor or
transformer coupling. For lower frequencies, the
transformers and capacitors become increasing larger.
The expense and size of these components for lower
frequency and DC coupled signals makes this solution
prohibitively expensive.
A cheaper solution requires using a SC Block as an
analog-to-digital (AD) modulator. Figure 20 shows the
architecture for an AD modulator that converts an input
signal to a series of pulses where:



A one represents Vref+
A zero represents VrefThe average is equal to the input signal
Figure 33 shows how it is assembled to pass the signal
across an isolation barrier.
Figure 33. PSoC 1 Isolated Analog Driver
PSoC
Ain
Buffer
P0.7
Digital
Buffer
P1.7
AD
Modulator
Dout
Opto 475K
Isolator
Aout
220pF
The input signal (Ain) is buffered and passed to the AD
modulator where the signal is converted to a series of
digital pulses. These pulses are brought out of the chip
through the digital buffer. The pulses (Dout) pass through
www.cypress.com
Document No. 001-40440 Rev. *F
14
Understanding PSoC® 1 Switched Capacitor Analog Blocks
an opto-isolator. Now isolated, these pulses are averaged
to reconstruct an analog signal (Aout).
Figure 35. Parameters for ADModulator SCBLOCK
The low-pass filter is set to 1.5 kHz to knock out the
harmonics generated by the pulses.
The PSoC 1 implementation is shown in Figure 34.
Example Code: Example 3 does not require any main
code, but does require a start call to start the PGA. The
switched capacitor blocks do not require any calls to start.
The C code follows.
void main(void)
{
//Start user modules
DigBuf_Start();
PGA_Start(PGA_HIGHPOWER);
//SC block starts itself
while(1);//Execution
requires
further firmware interaction
no
}
Figure 34. PSoC 1 Analog Isolator Driver Block Placement
In theory, the ratio of ACap/FCap is unimportant. Practical
considerations of loop gain and comparator offset dictate
that FCap must be set to ‘32’ while ACap is set to ‘16’.
BCap and CCap are not used so their values are set to
zero. The continuous time blocks source the input signal,
and thus ClockPhase can remain set to “Norm.” The
ACMux is set to connect its input to “ACB00.” ARefMux is
set to “ComparatorBus_0”, allowing the output comparator
to control the reference selection. BMux is not required so
it need not be set. ASign must be set to “Pos." To be an
integrator, FSW1 and AutoZero must be set “On” while
FSW0 must be set “Off.” The comparator needs to
connect to the digital blocks so CompBus is set to
“ComparatorBus_0”. AnalogBus is set to “Disable.”
Power is set “High.”
The DigitalBuffer is a User Module that allows the
comparator bus to be output on P1[7]. This output is
connected to an external opto-isolator followed by an RC
filter.
Summary
The input buffer is a PGA User Module. Its parameter
selection is left as an exercise for the reader.
Switched capacitor circuitry allows building of integrated
circuitry with capacitors instead of expensive resistors.
Changing a circuit’s function can be as easy as changing
the sequence in which its switches are closed. With eight
SC Blocks offers good integration options. This makes
PSoC 1 a true programmable system on a chip.
The ADModulator is an integrator with a comparator
controlled input reference. Its parameters are shown in
Figure 35.
www.cypress.com
Document No. 001-40440 Rev. *F
15
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Related Application Notes

This application note explains how to use a switched
capacitor block in integrator mode as a simple
Opamp.


®
AN64475: PSoC 1 Optimizing Cascaded Switched
Capacitor filters
®
AN64475 demonstrates how PSoC 1 switched
capacitor band pass filters (BPF2, BPF4) and elliptical
www.cypress.com
®
AN2219: PSoC 1 Selecting Analog Ground and
Reference
This application note explains PSoC®1 internal
analog ground and reference voltage structure.
®
AN2168: PSoC 1 Understanding Switched Capacitor
Filters
This application note presents the theory behind
switched capactor filters – Low pass, High pass,
Bandpass and notch filters and provides guidelines
and examples for implementing these filters in
PSoC®1 devices.

low pass filters (ELPF2 and ELPF4) can be combined
to provide excellent near out-of-band rejection for
communications applications.
®
AN2223: PSoC 1 Approximating an Opamp with a
Switched Capacitor Integrator

®
AN32200: PSoC Clocks and Global Resources
This application note describes the clock resources of
®
PSoC 1.

®
AN2108: PSoC 1 Implementing Hysteresis
Comparator
This application note explains multiple
implementations of a hysteresis comparator.
Document No. 001-40440 Rev. *F
16
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Appendix A: Control Registers for a Type C Switched Capacitor Block
7
CR0
CR1
CR2
CR3
6
5
4
FCap
ClockPhase ASign
ACap
16, 32
Norm, Swap
[0..31]
Pos, Neg
ACMux
3
2
1
0
BCap
C: North => A: North, E1W2, REFHI, South;
C: Diag => A: Diag, Diag, Diag, Diag
[0..31]
AnalogBus
CompBus
AutoZero
CCap
Disable, Enable
Disable, Enable
Off, On
[0..31]
ARefMux
FSW1
FSW0
BMuxSCC
Power
AGND, REFHI, REFLO, CMP
Off, On
Off, On
North, E1W2, E2W1, South
Off, Low, Med, High
Appendix B: Control Registers for a Type D Switched Capacitor Block
7
CR0
CR1
CR2
CR3
6
5
4
FCap
ClockPhase ASign
ACap
16. 32
Norm, Swap
[0..31]
Pos, Neg
3
2
1
AMux
BCap
North, E1W2, E2W1, South, REFHI, Diag, NC, Hold
[0..31]
AnalogBus
CompBus
AutoZero
CCap
Disable, Enable
Disable, Enable
Off, On
[0..31]
ARefMux
FSW1
FSW0
BSW
BMuxSCD
Power
AGND, REFHI, REFLO, CMP
Off, On
Off, On
Off, On
Diag, North
Off, Low, Med, High
0
Appendix C: A Input Multiplexer Connections
ACC
ACC
ACC
ACC
00
01
02
03
(1)
VTemp
(0)
7)
(4
-
(3)
(3)
(2)
ABUS(2)
Document No. 001-40440 Rev. *F
RefHi
(2
)
(5
)
(1)
ASD
(0)
(3)
(0)
(3)
(2
)
(1)
22
(3)
(3)
(0)
(5
)
(0)
(3)
(2
)
21
P2.2
13
)
(4
ASC
(1)
ASD
(2)
)
-7
(4
(2)
RefHi
)
(4
20
ABUS(0)
www.cypress.com
(1)
ASD
(1)
12
)
(4
)
(4
(1)
P2.1
)
-7
(4
RefHi
ASC
11
ASC
23
(3)
ASD
(2)
(2
)
(1)
10
(0)
(0)
(4
-7
)
(0)
)
(5
)
(5
ASC
ABUS(3)
17
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Appendix D: C Input Multiplexer Connections
ACC
ACC
01
02
03
(4
-7
)
(4
-7
)
(0-3)
ACC
00
(0-3)
ACC
ASC
ASD
11
12
13
)
-7
(4
)
-7
(4
(03)
ASD
10
(0-3)
ASC
ASD
ASC
ASD
ASC
20
21
22
23
Appendix E: B Input Multiplexer Connections
ACC
ACC
01
02
03
ASC
(0)
(0)
ASC
21
(2)
ASD
(1)
22
TRefGND
www.cypress.com
Document No. 001-40440 Rev. *F
ASC
23
(2)
P2.0
(3)
(1)
ASD
13
(3)
20
(1
)
(0)
ASD
(1)
12
(3)
(2)
(3)
11
(0)
ASD
(1
)
(1)
10
(0)
(0)
ASC
)
(1
)
(1
(2)
P2.3
(0)
ACC
00
(0)
ACC
ABUS(3)
18
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Appendix F: C Code: 2-Bit ADC Example Project
//---------------------------------------------------------------------------// C main line – This code runs in a loop where the input
// input is continuously sampled and compared with the
// selectable references to determine one of four different
// levels. Dout1 and Dout0 are set accordingly.
// Inline assembly “nop” no-ops are used to stabilize the
// comparator readings.
//---------------------------------------------------------------------------#include <m8c.h>
#include "PSoCAPI.h"
// part specific constants and macros
// PSoC API definitions for all User Modules
void main()
{
//TwoBit_SCBLOCKcr3 register bits 6 and 7 are the reference bits
//00b Analog ground is selected.
//01b RefHi input selected. (This is usually the high reference.)
//10b RefLo input selected. (This is usually the low reference.)
while(1){
TwoBit_cr3 &= 0x3F;
//Initialize to analog ground reference
//TEST Comparator Bus
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
if(CMP_CR0 && 0x80){
//If it is greater then select RefHi reference
//Reference set to RefHi
TwoBit_cr3 &= 0x7F;
TwoBit_cr3 |= 0x40;
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
if(CMP_CR0 && 0x80){ //Value is above RefHi D = 11
PRT1DR |= 0x03;
}
else{
//Value is between AGND and RefHI D = 10
PRT1DR &= 0xFE;
PRT1DR |= 0x02;
}
}
else{
//Else select RefLo reference
//Reference set to RefLo
TwoBit_cr3 &= 0xBF;
TwoBit_cr3 |= 0x80;
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
asm("nop");
www.cypress.com
Document No. 001-40440 Rev. *F
19
Understanding PSoC® 1 Switched Capacitor Analog Blocks
if(CMP_CR0
PRT1DR
PRT1DR
}
else{
PRT1DR
}
&& 0x80){
&= 0xFD;
|= 0x01;
//Value is between AGND and RefLo D = 01
//Value is below RefLo D = 00
&= 0xFC;
}
}
}
www.cypress.com
Document No. 001-40440 Rev. *F
20
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Appendix G: SC-Block Applications Cook Book
Integrator
f1
CF
f2
CA
Gain 
f1
Vin
f2
Vout
Vout C A
1
1 C 

  f s A 
1
Vin CF (1  z ) s  CF 
Sign
Both Type C and Type D SC block can be used to build an integrator.
SCBlock
Parameter
Type C / D
Value
Comments
FCap
Both
16 / 32
Select FCap based on integrator time constant requirement
ClockPhase
Both
Norm
Options – Norm, Swap
ASign
Both
Pos
Options:
Pos – Non-inverting configuration
Neg – Inverting configuration
ACap
Both
1 – 31
Select ACap (CA) value based on required Integrator time constant
ACMux
Type C only
source
Select the source for integrator input signal (input Vin)
BCap
Both
0
Disconnect ‘B’ input
AnalogBus
Both
AnalogOutB
us_0
SC block output is routed to Analog output bus (which is then routed to
pin)
CompBus
Both
Disable
Not used
Autozero
Both
On
Autozero (input offset voltage correction) enabled
CCap
Type C only
0
Not used
ARefMux
Both
AGND
SC block reference is analog ground. The integrator output ramps up or
down depending on whether input voltage is greater than or less than
AGND.
FSW1
Both
On
FSW1 is enabled
FSW0
Both
Off
FSW0 is disabled
BMux
Both
x
Not used
Power
Both
High
SC block is operated in high power mode
AMux
Type D only
Source
Select the source for integrator input signal (input Vin)
BSW (SD)
Type D only
x
Not used
www.cypress.com
Document No. 001-40440 Rev. *F
21
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Integrator: Dual input
This is slight variant of the application given above. This architecture uses two inputs Vin1 and Vin2. In this implementation,
outputs ramps high or low depending on the difference between two input voltages. This can be implemented in both Type C
and D blocks.
f1
CF
f2
CA
f1
Vin1
f2
Sign
Vin2
Vout
CB
f2
f1
SCBlock
Parameter
Type C / D
Value
Comments
FCap
Both
16 / 32
Select FCap based on integrator time constant requirement
ClockPhase
Both
Norm
Options – Norm, Swap
ASign
Both
Pos
Options:
Pos – Non-inverting configuration
Neg – Inverting configuration
ACap
Both
1 – 31
Select ACap (CA) value based on required Integrator time constant
ACMux
Type C only
Source 1
Select the source for integrator input signal (Vin1)
BCap
Both
1 – 31
Select BCap (CB) value based on required Integrator time constant
AnalogBus
Both
AnalogOutB
us_0
SC block output is routed to Analog output bus (which is then routed to pin)
CompBus
Both
Disable
Not used
Autozero
Both
On
Autozero (input offset voltage correction) enabled
CCap
Type C only
0
Not used
ARefMux
Both
AGND
SC block reference is analog ground. The integrator output ramps up or
down depending on whether input voltage is greater than or less than AGND
respectively.
FSW1
Both
On
FSW1 is enabled
FSW0
Both
Off
FSW0 is disabled
BMux
Both
Source 2
Select the source for integrator input signal (Vin2)
Power
Both
High
SC block is operated in high power mode
AMux
Type D only
Source 1
Select the source for integrator input signal (Vin1)
BSW (SD)
Type D only
ON
Switching enabled for B input
www.cypress.com
Document No. 001-40440 Rev. *F
22
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Differentiator
f1
CF
CB
f2
f1
Gain 
Vin
Vout
 1 CB
Vout
C
  1  z 1 B   s
Vin
CF
 f s CF





Note Differentiator can be implemented only in Type-D SC block because of presence of BSW switch.
SCBlock
Parameter
Value
Comments
FCap
16/32
Select FCap based on differentiator gain requirement
ClockPhase
Norm
Options: Norm, Swap
ASign
Pos
Options:
Pos – Non-inverting configuration
Neg – Inverting Configuration
ACap
0
Disconnect ‘A’ input
AMux
x
Not used
BCap
1 - 31
Select BCap (CB) value based on differentiator gain requirement
AnalogBus
AnalogOutBus_1
Output routed to analog output bus
CompBus
Disable
Not used
Autozero
On
Autozero enabled
CCap
0
Not used
ARefMux
AGND
Reference of SC-Block set to AGND
FSW1
On
FSW1 is enabled
FSW0
On
FSW0 is enabled
BSW
Off
BSW switch is disabled
BMux
source
Select Vin
Power
High
High power mode
www.cypress.com
Document No. 001-40440 Rev. *F
23
Understanding PSoC® 1 Switched Capacitor Analog Blocks
N o n - I n v e r t i n g a n d I n ve r t i n g A m p l i f i e r
Figure 36. Non-Inverting Amplifier
f1
CF
f1
Vin
f2
f1
CA
Vout
f2
Figure 37. Inverting Amplifier
f1
CF
CA
Vin
f2
f1
f2
Vout
f1
SCBlock
Parameter
Type C / D
Value
Comments
FCap
Both
16 / 32
Select FCap (CF) based on amplifier gain requirement
ClockPhase
Both
Norm
Options – Norm, Swap
ASign
Both
Pos / Neg
Pos - Non-Inverting amplifier configuration
Neg – Inverting amplifier configuration
ACap
Both
1 – 31
Select ACap (CA) value based on amplifier gain requirement
ACMux
Type C only
Source 1
Select the source for amplifier input signal (Vin)
BCap
Both
0
Disconnects B input
AnalogBus
Both
AnalogOutB
us_0
SC block output is routed to Analog output bus (which is then routed to pin)
CompBus
Both
Disable
Not used
Autozero
Both
On
Autozero (input offset voltage correction) enabled
CCap
Type C only
0
Not used
www.cypress.com
Document No. 001-40440 Rev. *F
24
Understanding PSoC® 1 Switched Capacitor Analog Blocks
SCBlock
Parameter
Type C / D
Value
Comments
ARefMux
Both
AGND
SC block reference is analog ground.
FSW1
Both
On
FSW1 is enabled
FSW0
Both
On
FSW0 is enabled
BMux
Both
X
Not used
Power
Both
High
High power mode
AMux
Type D only
Source 1
Select the source for amplifier input signal (Vin)
BSW (SD)
Type D only
X
Not used
D i f f e r e n t i a l Am p l i f i e r
f1
CF
Vin1
f1
CA
f1
f2
Vout
f2
Vin2
f2
f1
CB
SCBlock
Parameter
Type C / D
Value
Comments
FCap
Both
16 / 32
Select FCap (CF) based on amplifier gain requirement
ClockPhase
Both
Norm
Options – Norm, Swap
ASign
Both
Pos
Non-Inverting configuration for input Vin1
ACap
Both
1 – 31
Select ACap (CA) value based on amplifier gain requirement
ACMux
Type C only
Source 1
Select the source for amplifier input signal (Vin1)
BCap
Both
1 – 31
Select BCap (CB) value based on amplifier gain requirement
AnalogBus
Both
AnalogOutB
us_0
SC block output is routed to Analog output bus (which is then routed to pin)
CompBus
Both
Disable
Not used
Autozero
Both
On
Autozero (input offset voltage correction) enabled
CCap
Type C only
0
Not used
ARefMux
Both
AGND
SC block reference is analog ground
FSW1
Both
On
FSW1 is enabled
www.cypress.com
Document No. 001-40440 Rev. *F
25
Understanding PSoC® 1 Switched Capacitor Analog Blocks
SCBlock
Parameter
Type C / D
Value
Comments
FSW0
Both
On
FSW0 is enabled
BMux
Both
Source 2
Select the source for amplifier input signal (Vin2)
Power
Both
High
High power mode
AMux
Type D only
Source 1
Select the source for amplifier input signal (Vin1)
BSW (SD)
Type D only
On
Enable switching for input B
Comparator
f1
CA
f1
Vin
f2
Vout
Sign
SCBlock
Parameter
Type C / D
Value
Comments
FCap
Both
X
Not used
ClockPhase
Both
Norm
Φ1 – charge acquisition
Φ2 – charge transfer
ASign
Both
Pos
Non-Inverting configuration
ACap
Both
>0
Select value greater than 0
ACMux
Type C only
source
Select the source for integrator input signal (input Vin)
BCap
Both
0
Disconnects ‘B’ input
AnalogBus
Both
Disable
Not used
CompBus
Both
Enable
Routes the comparator output to bus
Autozero
Both
On
Autozero enabled, but no effect on the offset correction
CCap
Type C only
0
Not used
ARefMux
Both
AGND
SC block reference is analog ground.
FSW1
Both
Off
FSW1 is disabled
FSW0
Both
Off
FSW0 is disabled
BMux
Both
x
Not used
Power
Both
High
High power mode
AMux
Type D only
Source
Select the source for comparator input signal (input Vin)
BSW (SD)
Type D only
x
Not used
www.cypress.com
Document No. 001-40440 Rev. *F
26
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Document History
®
Document Title: Understanding PSoC 1 Switched Capacitor Analog Blocks - AN2041
Document Number: 001-40440
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
1532004
DWV
10/02/2007
New application note
*A
1793485
DWV
12/03/2007
Added Appendix E: Input Multiplexer Connections
*B
2344389
CFW
04/11/2008
Appendix A and Appendix B - figures transposed
Corrected a couple of typos
*C
3210347
MAXK
03/30/2011
Updated projects to PD 5.1 SP1
Added Isolated Analog Driver project (was missing from previous versions)
General formatting updates
Added document history table
Updated figures
Updated Title and Abstract
*D
3244236
MAXK
04/29/2011
Corrected symbol fonts in various figures.
*E
3671850
RJVB
07/10/2012
Updated template.
Added detailed explanation for inverting amplifier, non-inverting amplifier,
comparator, differentiator and integrator.
Updated figures.
Added Appendix G: SC-Block Applications Cook Book.
*F
4393365
www.cypress.com
RJVB
05/29/2014
Sunset Review.
Document No. 001-40440 Rev. *F
27
Understanding PSoC® 1 Switched Capacitor Analog Blocks
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical Navigation Sensors
cypress.com/go/ons
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer and enCoRe are trademarks of
Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2007-2014. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-40440 Rev. *F
28
Similar pages