CYRF6986:WirelessUSB™ LPstar 2.4 GHz Radio SoC

CYRF6986
WirelessUSB™ LPstar 2.4 GHz
Radio SoC
WirelessUSB™ LPstar 2.4 GHz Radio SoC
Features
Simple Development
■
2.4 GHz direct sequence spread spectrum (DSSS) radio transceiver
■
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz)
■
Auto transaction sequencer (ATS): Enables MCU to sleep
longer
■
Framing, length, CRC16, and auto ACK
■
Separate 16-byte transmit and receive FIFOs
■
On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP
■
Receive signal strength indication (RSSI)
■
Pin-to-pin compatible with WirelessUSB LP except the Pin30
and Pin37
■
Serial peripheral interface (SPI) control while in sleep mode
■
4 MHz SPI microcontroller interface
Low Power
BOM Savings
■
Operating current: 21 mA (transmit at –5 dBm)
■
Low external component count
■
Sleep current less than 1 A
■
Battery voltage monitoring circuitry
■
Operating voltage: 2.7 V to 3.6 V
■
Small footprint 40-pin QFN (6 mm × 6 mm)
■
Fast startup and fast channel changes
Applications
■
Supports coin-cell operated applications
■
Wireless keyboards and mice
Reliable and Robust
■
Presentation tools
■
Receive Sensitivity typical –90 dBm
■
Wireless gamepads
■
AutoRate™ – dynamic data rate reception
❐ Enables data reception for any of the supported bit rates
automatically.
❐ DSSS (250 Kbps), GFSK (1 Mbps)
■
Remote controls
■
Toys
■
Fitness
■
Operating Temperature: 0 °C to 70 °C
■
Closed-loop frequency synthesis for minimal frequency drift
Applications Support
See www.cypress.com for development tools, reference
designs, and application notes.
Logic Block Diagram
IRQ
SS
SCK
MISO
MOSI
GFSK
Modulator
Data
Interface
and
Sequencer
DSSS
Baseband
& Framer
RFP
RFN
RFBIAS
Frequency
Synthesizer
SPI
GFSK
Demodulator
RSSI
Power Management
RST
VBAT
Cypress Semiconductor Corporation
Document Number: 001-66073 Rev. *D
•
VDD
VCC
198 Champion Court
GND
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 6, 2014
CYRF6986
Contents
Functional Description ..................................................... 3
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Data Transmission Modes ........................................... 4
Link Layer Modes ........................................................ 4
Packet Buffers ............................................................. 5
Auto Transaction Sequencer (ATS) ............................ 5
Functional Block Overview .............................................. 5
2.4 GHz Radio ............................................................. 5
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and
Radio Configuration Registers ............................................ 6
SPI Interface ................................................................ 6
Interrupts ..................................................................... 8
Clocks .......................................................................... 8
Power Management .................................................... 8
Low Noise Amplifier and
Received Signal Strength Indication ................................... 8
Application Example ........................................................ 9
Registers ......................................................................... 11
Document Number: 001-66073 Rev. *D
Absolute Maximum Ratings .......................................... 12
Operating Conditions ..................................................... 12
DC Characteristics ......................................................... 12
AC Characteristics ......................................................... 13
SPI Interface .............................................................. 13
RF Characteristics .......................................................... 14
Typical Operating Characteristics ................................ 16
AC Test Loads and Waveforms for Digital Pins .......... 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 2 of 23
CYRF6986
Functional Description
The CYRF6986 WirelessUSB LPstar radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC)
family. The CYRF6986 IC adds a range of enhanced features, including reduced supply current in all operating modes, reduced crystal
start up, synthesizer settling, and link turnaround times.
Pinouts
Figure 1. 40-pin QFN pinout
NC 31
33
NC 32
VIO
35
RST 34
VDD
NC 36
GND 37
38
NC 39
VBAT0
VCC 40
XTAL
1
30 NC
NC
2
29 XOUT / GPIO
VCC
3
28 MISO / GPIO
NC
4
NC
5
VBAT1
6
VCC
7
24 SS
VBAT2
8
23 NC
NC
9
27 MOSI / SDAT
CYRF6986
WirelessUSB LPstar
40-Pin QFN
26 IRQ / GPIO
25 SCK
22 NC
* E-PAD Bottom Side
21 NC
RFBIAS 10
20 NC
19 RESV
18 NC
17 NC
16 VCC
15 NC
14 NC
13 RFN
12 GND
11 RFP
Pin Definitions
Pin Number
Name
Type
Default
Description
1
XTAL
I
I
2, 4, 5, 9, 14,
15, 17, 18, 20,
21, 22, 23, 31,
32, 36, 39
NC
NC
Connect to GND.
3, 7, 16, 40
VCC
Pwr
VCC = 2.7 V to 3.6 V.
6, 8, 38
VBAT(0-2)
Pwr
10
RFBIAS
O
O
RF IO 1.8 V reference voltage.
11
RFP
I/O
I
Differential RF signal to and from antenna.
12
GND
GND
13
RFN
IO
19
RESV
I
24
SS
I
I
SPI enable, active LOW assertion. Enables and frames transfers.
25
SCK
I
I
SPI clock.
12 MHz crystal.
VBAT = 2.7 V to 3.6 V. Main supply.
Ground.
I
Differential RF signal to and from antenna.
Must be connected to GND.
26
IRQ
I/O
O
Interrupt output (configurable active HIGH or LOW), or GPIO.
27
MOSI
I/O
I
SPI data input pin (Master Out Slave In), or SDAT.
Document Number: 001-66073 Rev. *D
Page 3 of 23
CYRF6986
Pin Definitions (continued)
Pin Number
Name
Type
Default
28
MISO
I/O
Z
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS is deasserted.
29
XOUT
I/O
O
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
30
NC
NC
Must be floating.
33
VIO
Pwr
I/O interface voltage, 2.7–3.6 V.
34
RST
I
35
VDD
Pwr
Decoupling pin for 1.8 V logic regulator, connect through a 0.47 F capacitor
to GND.
37
GND
GND
Must be connected to ground.
E-PAD
GND
GND
Must be soldered to ground.
I
Description
Device reset. Internal 10 k pull down resistor. Active HIGH, connect through
a 0.47 F capacitor to VBAT. Must have RST = 1 event the first time power is
applied to the radio. Otherwise the state of the radio control registers is
unknown.
Functional Overview
The CYRF6986 IC provides a complete WirelessUSB SPI to
antenna wireless MODEMs. The SoC is designed to implement
wireless device links operating in the worldwide 2.4 GHz ISM
frequency band. It is intended for systems compliant with
worldwide regulations covered by ETSI EN 301 489-1 V1.41,
ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA
and Industry Canada), and TELEC ARIB_T66_March, 2003
(Japan).
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
Received Signal Strength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
Data Transmission Modes
The SoC supports two different data transmission modes:
■
■
32-chip pseudo noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any given
environment.
Link Layer Modes
The CYRF6986 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SoP marker. If framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the “body” of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
Length
Length field is the first eight bits after the SOP symbol, and is
transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16.
CRC16
The device may be configured to append a 16 bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the CRC16
calculation is configurable, and the CRC16 transmitted may be
calculated using either the loaded seed value or a zero seed; the
received data CRC16 is checked against both the configured
and zero CRC16 seeds.
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
CRC16 detects the following errors:
■
Any one bit in error.
In DSSS mode eight bits (8DR, 32-chip) are encoded in each
derived code symbol transmitted, resulting in effective 250 kbps
data rate.
■
Any two bits in error (irrespective of how far apart, which
column, and so on).
Document Number: 001-66073 Rev. *D
Page 4 of 23
CYRF6986
■
Any odd number of bits in error (irrespective of the location).
■
An error burst as wide as the checksum itself.
Figure 2 shows an example packet with SOP, CRC16, and
lengths fields enabled, and Figure 3 shows a standard ACK
packet.
Figure 2. Example Packet Format
2nd Framing Symbol*
Preamble N*16us
Preamble
SOP1
SOP2
1st Framing Symbol*
Length
<== P a y l o a d ==>
CRC 16
Packet length 1 Byte Period
*Note: 32 us
Figure 3. Example ACK Packet Format
Pream ble N *16us
Pream ble
2nd Fram ing Sym bol*
SOP1
SO P2
CRC 16
C R C Field From Received Packet.
1st Fram ing Sym bol*
2 Byte Periods
*Note: 32 us
Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
The CYRF6986 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF6986 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
■
Starts the crystal and synthesizer
■
Enters transmit mode
■
Transmits the packet in the transmit buffer
■
Transitions to receive mode and waits for an ACK packet
■
Transitions to the transaction end state when an ACK packet
is received or a timeout period expires
Document Number: 001-66073 Rev. *D
Similarly, when receiving in transaction mode, the device
automatically:
■
Waits in receive mode for a valid packet to be received
■
Transitions to transmit mode, transmits an ACK packet
■
Transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF6986 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
■
1000 kbps (GFSK)
■
250 kbps (32 chip 8DR)
Functional Block Overview
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power, range, and robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to 0 dBm transmit power, with an output power
Page 5 of 23
CYRF6986
control range of 35 dB in six steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
6
5
4
3
2
1
0
Typical Output Power (dBm)
0
–5
–13
–18
–24
–30
–35
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 s.
The ‘fast channels’ (less than 100 s settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
✟
Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically increments
at the end of each data byte in a burst access. Otherwise the
same address is accessed.
✟
Six bits of address
✟
Eight bits of data
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS) pin must be asserted to initiate an
SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in Table 2
through Figure 6 on page 7.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 4 on page 7 and Figure 5 on
page 7, respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 6 on page 7 and Figure 7 on
page 7, respectively.
Packet Buffers and Radio Configuration Registers
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet.
Configuration registers allow configuration of DSSS PN codes,
data rate, operating mode, interrupt masks, interrupt status, and
so on.
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
SPI Interface
The CYRF6986 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF6986). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
SPI communication may be described as the following:
✟
Command Direction (bit 7) = ‘1’ enables SPI write transaction.
A ‘0’ enables SPI read transactions.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS pin is LOW. When using this configuration,
user firmware must ensure that the MOSI pin on the MCU is in a
high impedance state whenever the SS pin is HIGH.
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO). This enables the device to interface
directly to MCUs operating at voltages below the CYRF6986 IC
supply voltage.
Table 2. SPI Transaction Format
Parameter
Bit #
Bit Name
Byte 1
7
DIR
6
INC
Document Number: 001-66073 Rev. *D
[5:0]
Address
Byte 1+N
[7:0]
Data
Page 6 of 23
CYRF6986
Figure 4. SPI Single Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. SPI Incrementing Burst Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu1
MISO
D7
D6
D5
D4
D3
data to mcu1+N
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Figure 6. SPI Single Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
Figure 7. SPI Incrementing Burst Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu1
A1
A0
D7
D6
D5
D4
D3
D2
data from mcu1+N
D1
D0
D7
D6
D5
D4
D3
D2
MISO
Document Number: 001-66073 Rev. *D
Page 7 of 23
CYRF6986
Interrupts
Power Management
The device provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of various different
events. The IRQ pin may be programmed to be either active
HIGH or active LOW, and be either a CMOS or open drain output.
The available interrupts are described in the section Registers
on page 11.
The operating voltage of the device is 2.7 V to 3.6 V DC, which
is applied to the VBAT pin. The device can be shut down to a fully
static sleep mode by writing to the FRC END = 1 and
END STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.
The CYRF6986 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that would otherwise
cause an interrupt can be determined by reading the appropriate
status register. It is therefore possible to use the devices without
the IRQ pin, by polling the status registers to wait for an event,
rather than using the IRQ pin.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
The requirements to directly connect the crystal to the XTAL pin
and GND are:
■
Nominal Frequency: 12 MHz
■
Operating Mode: Fundamental Mode
■
Resonance Mode: Parallel Resonant
■
Frequency Stability: ±30 ppm
■
Series Resistance: <60 ohms
■
Load Capacitance: 10 pF
■
Drive Level: 100 µW
Document Number: 001-66073 Rev. *D
Low Noise Amplifier and Received Signal Strength
Indication
The gain of the receiver can be controlled directly by clearing the
AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of
the RX_CFG_ADR register. Clearing the LNA bit reduces the
receiver gain approximately 20 dB, allowing accurate reception
of very strong received signals (for example, when operating a
receiver very close to the transmitter). Approximately 30 dB of
receiver attenuation can be added by setting the Attenuation
(ATT) bit. This limits data reception to devices at very short
ranges. Disabling AGC and enabling LNA is recommended,
unless receiving from a device using external PA.When the
device is in receive mode the RSSI_ADR register returns the
relative signal strength of the on-channel signal power.
When receiving, the device automatically measures and stores
the relative strength of the signal being received as a five bit
value. An RSSI reading is taken automatically when the SoP is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI_ADR register, allowing
the background RF energy level on any given channel to be
easily measured when RSSI is read while no signal is being
received. A new reading can occur as fast as once every 12 µs.
received.
Page 8 of 23
1
2
3
4
5
6
USB A RA PLUG SMD
VBUS
DM
DP
GND
S1
S2
Vcc_3.3V
R1
ZERO
VBUS
DM
DP
1
5V
R2
620 ohm
0402
J1
2
22 ohm
22 ohm
nSS
SCK
MOSI
MISO
11
2
9
4
3
7
6
S1
SW RA PUSH
1A
1B
D1
KR
KG
LED Green Red
RD
GR
2A
2B
"BIND"
2
1
3
4
8
VCC
P0[1]
P0[3]
P0[4]
P0[7]
XRES
SW1
nLED2
nLED1
CY7C64315
P2[3]
P2[5]
P1[7]/SPI_SS
P1[0]/SPI_SCLK/ISSP_SDA
P1[1]/MOSI/ISSP_SCLK
P1[5]/MISO
P1[4]
DM
DP
"CONNECT/ACTIVITY"
R6
R5
U2
VSS
5
IRQ
SW1
RST
1
16
nLED2
nLED1
10
15
14
12
13
0603
1500pFd
2
5V
0805
C13
4.7 uFd
IRQ
nSS
SCK
MOSI
MISO
RST
0805
C14
2.2 uFd
Vcc_3.3V
Power Supply
0805
Vbat
C16
10 uFd
Note2:Pin30 must be floating.
0402
C15
0.47uFd
Vcc_3.3V
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
GND
NC17
IRQ
SS
SCK
MOSI
MISO
RST
0402
C6
0.047 uFd
Vcc_3.3V
2
4
5
9
14
15
17
18
37
30
26
24
25
27
28
34
U1
CYRF6986
Vbat
Vcc_3.3V
0402
C7
0.047 uFd
0402
1
C5
0402
19
20
21
22
23
31
32
36
39
29
1
13
11
10
TV1
0.47 uFd
2
IND0402
IND0603
TV-20R
L2
1
1
L1
1.8 nH
2
2
22 nH
C3
0402
15 pFd
12 MHz Crystal
Y1
2.0 pFd
C1
0402
0402
1.5 pFd
C4
C8
0.047 uFd
0402
C9
0.047 uFd
0402
C10
0.047 uFd
0402
C11
0.047 uFd
Note1:E-PAD must be soldered to ground
RESV
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
XOUT
XTAL
RFn
RFp
RFbias
33
8
6
38
1
C12
1
1
2
1
2
40
VIO
VBAT2
VBAT1
VBAT0
GND1
12
VCC4
1
3
7
16
E-PAD
VCC1
VCC2
VCC3
2
1
2
1
2
1
2
41
35
VDD
2
1
2
1
2
0402
0402
Document Number: 001-66073 Rev. *D
ANT1
WIGGLE 32
1
2
Vcc_3.3V
CYRF6986
Application Example
Page 9 of 23
0402
CYRF6986
Table 3. Recommended BoM
Item Qty CY Part Number
Reference
1
1
NA
ANT1
2.5 GHz H-STUB WIGGLE ANTENNA
FOR 32 MIL PCB
Description
NA
Manufacturer
NA
2
1
730-10012
C1
CAP 15 pF 50 V CERAMIC NPO 0402
Panasonic
ECJ-0EC1H150J
3
1
730-11955
C3
CAP 2.0 pF 50 V CERAMIC NPO 0402
Kemet
C0402C209C5GACTU
4
1
730-11398
C4
CAP 1.5 pF 50 V CERAMIC NPO 0402
SMD
PANASONIC
ECJ-0EC1H1R5C
5
1
730-13322
C5, C15
CAP 0.47 uF 6.3 V CERAMIC X5R 0402 Murata
6
6
730-13404
C6,C7,C8,C CAP 0.047 uF 16 V CERAMIC X5R 0402 AVX
9,C10,C11
7
1
730-11953
C12
CAP 1500 pF 50 V CERAMIC X7R 0402 Kemet
C0402C152K5RACTU
8
1
730-13040
C13
CAP CERAMIC 4.7 uF 6.3 V XR5 0805
Kemet
C0805C475K9PACTU
9
1
730-12003
C14
CAP CER 2.2 uF 10 V 10% X7R 0805
GRM21BR71A225KA01L
Murata
Electronics North
America
10
1
NA
C16
CAP CERAMIC 10 uF 6.3 V XR5 0805
NA
11
1
800-13333
D1
LED GREEN/RED BICOLOR 1210 SMD LITEON
LTST-C155KGJRKT
12
1
420-13046
J1
CONN USB PLUG TYPE A PCB SMT
UAR72-4N5J10
ACON
Mfr Part Number
GRM155R60J474KE19D
0402YD473KAT2A
NA
13
1
800-13401
L1
INDUCTOR 22NH 2% FIXED 0603 SMD Panasonic - ECG ELJ-RE22NGF2
14
1
800-11651
L2
INDUCTOR 1.8NH +-.3NH FIXED 0402
SMD
Panasonic - ECG ELJ-RF1N8DF
15
1
610-10343
R1
RES ZERO ohm 1/16W 0402 SMD
Panasonic - ECG ERJ-2GE0R00X
16
1
610-13472
R2
RES CHIP 620 ohm 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ621X
17
1
200-13471
S1
SWITCH LT 3.5 mm x 2.9mm 160GF SMD Panasonic - ECG EVQ-P7J01K
18
1
CYRF698640LFC
U1
IC, LPstar 2.4 GHz RADIO SoC QFN-40 Cypress
Semiconductor
CYRF6986
19
1
CY7C64315
U2
IC enCoRe V FULL-SPEED USB
CONTROLLER
Cypress
Semiconductor
CY7C64315
20
1
800-13259
Y1
CRYSTAL 12.00 MHz HC49 SMD
eCERA
GF-1200008
21
1
xxx-xxxx-x
PCB
PRINTED CIRCUIT BOARD
Cypress
Semiconductor
xxx-xxxx-x
Document Number: 001-66073 Rev. *D
Page 10 of 23
CYRF6986
Registers
All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups.[1, 2]
Table 4. Register Map Summary
Address
Mnemonic
b7
b6
0x00
0x01
CHANNEL_ADR
TX_LENGTH_ADR
0x02
TX_CTRL_ADR
TX GO
TX CLR
0x03
TX_CFG_ADR
Not Used
OS
IRQ
Not Used
RSVD
b5
Not Used
0x04
TX_IRQ_STATUS_ADR
0x05
0x06
RX_CTRL_ADR
RX GO
RSVD
TXB15
IRQEN
DATA CODE
LENGTH
TXB15
IRQ
RXB16
IRQEN
RX_CFG_ADR
AGC EN
RXOW
IRQ
RX ACK
LNA
SOPDET
IRQ
PKT ERR
ATT
RXB16
IRQ
EOP ERR
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
XTAL_CTRL_ADR
IO_CFG_ADR
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
EOP_CTRL_ADR[3]
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
0x1E
0x1F
0x26
0x27
0x28
0x29
0x32
0x35
0x39
Register Files
0x20
0x21
0x22
0x23
0x24
0x25
b4
b3
Channel
TX Length
TXB8
TXB0
IRQEN
IRQEN
RSVD
Data mode
TXB8
IRQ
RXB8
IRQEN
TXB0
IRQ
RXB1
IRQEN
FAST
HILO
TURN EN
RXB8
RXB1
IRQ
IRQ
CRC0
Bad CRC
RX Count
RX Length
b2
b1
b0
TXBERR
IRQEN
TXC
IRQEN
TXE
IRQEN
TXBERR
IRQ
RXBERR
IRQEN
PA SETTING
TXC
IRQ
RXC
IRQEN
TXE
IRQ
RXE
IRQEN
Not Used
RXBERR
IRQ
RX Code
RXOW EN
VLD EN
RXC
RXE
IRQ
IRQ
RX Data Mode
The firmware should set “00010000” to this register while initiating
XOUT FN
IRQ OD
IRQ POL
XOUT OP
MISO OP
ACK EN
Not Used
SOP EN
SOP LEN
Not Used
Not Used
Not Used
Not Used
SOP
Not Used
HEN
Not Used
RSVD
Not Used
RSVD
RX_OVERRIDE_ADR
ACK RX
RXTX DLY
TX_OVERRIDE_ADR
XTAL_CFG_ADR
CLK_OVERRIDE_ADR
CLK_EN_ADR
RX_ABORT_ADR
AUTO_CAL_TIME_ADR
AUTO_CAL_OFFSET_ADR
ANALOG_CTRL_ADR
ACK TX
RSVD
RSVD
RSVD
RSVD
FRC PRE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
TX_BUFFER_ADR
RX_BUFFER_ADR
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
XSIRQ EN
MISO OD
RSVD
FRC END
LEN EN
Not Used
Not Used
LNA
HINT
Not Used
XOUT OD
IRQ OP
Not Used
RSVD
XOUT IP
END STATE
Not Used
RSVD
MISO IP
FREQ
SPI 3PIN
IRQ GPIO
RSVD
IRQ IP
ACK TO
SOP TH
TH32
TH64
RSSI
EOP
CRC SEED LSB
CRC SEED MSB
CRC LSB
CRC MSB
CRC LSB
CRC MSB
STRIM LSB
Not Used
Not Used
STRIM MSB
FRC SEN
FRC AWAKE
Not Used
Not Used
FRC
MAN RXACK
RXDR
DIS CRC0 DIS RXCRC
ACE
MAN
RSVD
TXACK
OVRD ACK DIS TXCRC
RSVD
RSVD
RSVD
START DLY
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
RSVD
RSVD
RSVD
RXF
ABORT EN
RSVD
RSVD
RSVD
RSVD
AUTO_CAL_TIME
AUTO_CAL_OFFSET
RSVD
RSVD
RSVD
RSVD
RX INV
TX Buffer File
RX Buffer File
SOP Code File
Data Code File
Preamble File
MFG ID File
RST
Default[1] Access[1]
-1001000
00000000
00000011
-bbbbbbb
bbbbbbbb
bbbbbbbb
--000101
--bbbbbb
--------
rrrrrrrr
00000111
bbbbbbbb
10010-10
bbbbb-bb
--------
brrrrrrr
-------00000000
00000000
rrrrrrrr
rrrrrrrr
rrrrrrrr
10100000
bbbbbbbb
000--100
00000000
0000---1-000000
10100101
----0100
---01010
0-100000
10100100
bbb--bbb
bbbbbbbb
bbbbrrrr
b-bbbbbb
bbbbbbbb
----bbbb
---bbbbb
r-rrrrrr
bbbbbbbb
00000000
00000000
--------------11111111
11111111
00000000
----0000
00000--0
0000000-
bbbbbbbb
bbbbbbbb
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbbbbbbb
----bbbb
wwwww--w
bbbbbbb-
Not Used
TX INV
RSVD
RSVD
RSVD
RSVD
ALL SLOW
00000000
bbbbbbbb
00000000
00000000
00000000
00000000
00000011
00000000
00000000
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
--------------Note 4
Note 5
Note 6
NA
wwwwwwww
rrrrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
Notes
1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.
2. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The GPIOs, and RSSI registers can be accessed in Active Tx and Rx mode.
3. EOP_CTRL_ADR[6:4] must never have the value of “000”, that is, EOP Hint Symbol count must never be “0”
4. SOP_CODE_ADR default = 0x17FF9E213690C782.
5. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
6. PREAMBLE_ADR default = 0x333302.
Document Number: 001-66073 Rev. *D
Page 11 of 23
CYRF6986
Static discharge voltage (Digital) [9] ......................... >2000 V
Static discharge voltage (RF) [9] ................................ 1100 V
Latch-up current .....................................+200 mA, –200 mA
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on any power supply pin
relative to VSS ..............................................–0.3 V to +3.9 V
DC voltage to logic inputs [8] ................. –0.3 V to VIO +0.3 V
DC voltage applied to outputs
in High-Z State ...................................... –0.3 V to VIO +0.3 V
Operating Conditions
VCC ................................................................. 2.7 V to 3.6 V
VIO ...................................................................2.7 V to 3.6 V
VBAT .................................................................2.7 V to 3.6 V
TA (Ambient Temperature Under Bias) .......... 0 °C to +70 °C
Ground Voltage ................................................................ 0 V
FOSC (Crystal Frequency) .......................... 12 MHz ±30 ppm
DC Characteristics
(T = 25 C, VBAT = 2.7 V, fOSC = 12.000000 MHz)
Parameter
Description
Conditions
0–70 C
Min
Typ
Max
Unit
2.7
–
3.6
V
2.7
–
3.6
V
2.7
–
3.6
V
VIO – 0.2
VIO
–
V
VIO – 0.4
VIO
–
V
–
0
0.45
V
VBAT
Battery Voltage
VIO[10]
VIO Voltage
VCC
VCC Voltage
VOH1
VOH2
Output High Voltage Condition 1 At IOH = –100.0 µA
Output High Voltage Condition 2 At IOH = –2.0 mA
VOL
Output Low Voltage
VIH
Input High Voltage
0.7 × VIO
VIO
V
VIL
Input Low Voltage
0
0.3 × VIO
V
IIL
Input Leakage Current
0 < VIN < VIO
–1
0.26
+1
µA
CIN
Pin Input Capacitance
except XTAL, RFN, RFP, RFBIAS
–
3.5
10
pF
Average TX ICC, 1 Mbps, slow
channel
PA = 5, 2 way, 4 bytes/10 ms
–
0.87
–
mA
ICC (32-8DR)[11]
Average TX ICC, 250 kbps, fast
channel
PA = 5, 2 way, 4 bytes/10 ms
–
1.2
–
mA
ISB[12]
Sleep Mode ICC
–
0.8
10
µA
IDLE ICC
Radio off, XTAL Active
–
1.0
–
mA
ICC
(GFSK)[11]
0–70 C
At IOL = 2.0 mA
XOUT disabled
Isynth
ICC during Synth Start
–
8.4
–
mA
TX ICC
ICC during Transmit
PA = 5 (–5 dBm)
–
20.8
–
mA
TX ICC
ICC during Transmit
PA = 6 (0 dBm)
–
26.2
–
mA
RX ICC
ICC during Receive
LNA off, ATT on
–
18.4
–
mA
RX ICC
ICC during Receive
LNA on, ATT off
–
21.2
–
mA
Notes
8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
9. Human Body Model (HBM).
10. In sleep mode, the IO interface voltage reference is VBAT.
11. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK
handshake. Device is in sleep except during this transaction.
12. ISB is not guaranteed if any IO pin is connected to voltages higher than VIO.
Document Number: 001-66073 Rev. *D
Page 12 of 23
CYRF6986
AC Characteristics
SPI Interface
Parameter [13, 14]
Description
Min
Typ
Max
Unit
238.1
–
–
ns
tSCK_CYC
SPI Clock Period
tSCK_HI
SPI Clock High Time
100
–
–
ns
tSCK_LO
SPI Clock Low Time
100
–
–
ns
tDAT_SU
SPI Input Data Setup Time
25
–
–
ns
tDAT_HLD
SPI Input Data Hold Time
10
–
–
ns
tDAT_VAL
SPI Output Data Valid Time
0
–
50
ns
tDAT_VAL_TRI
SPI Output Data Tri-state (MOSI from Slave Select Deassert)
–
–
20
ns
tSS_SU
SPI Slave Select Setup Time before first positive edge of SCK[15]
10
–
–
ns
tSS_HLD
SPI Slave Select Hold Time after last negative edge of SCK
10
–
–
ns
tSS_PW
SPI Slave Select Minimum Pulse Width
20
–
–
ns
tSCK_SU
SPI Slave Select Setup Time
10
–
–
ns
tSCK_HLD
SPI SCK Hold Time
10
–
–
ns
tRESET
Minimum RST Pin Pulse Width
10
–
–
ns
Figure 8. SPI Timing
tSCK_CYC
tSCK_HI
SCK
tSCK_LO
tSCK_HLD
tSCK_SU
nSS
tSS_SU
tDAT_SU
tSS_HLD
tDAT_HLD
MOSI input
tDAT_VAL
tDAT_VAL_TRI
MISO
MOSI output
Notes
13. AC values are not guaranteed if voltage on any pin exceeding VIO.
14. CLOAD = 30 pF
15. SCK must start low at the time SS goes LOW, otherwise the success of SPI transactions are not guaranteed.
Document Number: 001-66073 Rev. *D
Page 13 of 23
CYRF6986
RF Characteristics
Table 5. Radio Parameters
Parameter Description
RF Frequency Range
Conditions
Note 19
Min
Typ
Max
Unit
2.400
–
2.497
GHz
Receiver (T = 25 °C, VCC = VBAT = 3.0 V, fOSC = 12.000000 MHz, BER < 1E-3)
Sensitivity 250 kbps 32-8DR
BER 1E-3
–
–90
–
dBm
Sensitivity GFSK
BER 1E-3, ALL SLOW = 1
–
–84
–
dBm
LNA Gain
–
22.8
–
dB
ATT Gain
–
–31.7
–
dB
–15
–6
–
dBm
RSSI Value for PWRin –60 dBm LNA On
–
21
–
Count
RSSI Slope
–
1.9
–
dB/Count
Maximum Received Signal
LNA On
Interference Performance (CER 1E-3)
Co-channel Interference
rejection
Carrier-to-Interference (C/I)
C = –60 dBm
–
9
–
dB
Adjacent (±1 MHz) channel
selectivity C/I 1 MHz
C = –60 dBm
–
3
–
dB
Adjacent (±2 MHz) channel
selectivity C/I 2 MHz
C = –60 dBm
–
–30
–
dB
Adjacent (> 3 MHz) channel
selectivity C/I > 3 MHz
C = –67 dBm
–
–38
–
dB
Out-of-Band Blocking
30 MHz–12.75 MHz[20]
C = –67 dBm
–
–30
–
dBm
Inter modulation
C = –64 dBm, f = 5,10 MHz
–
–36
–
dBm
800 MHz
100 kHz ResBW
–
–79
–
dBm
1.6 GHz
100 kHz ResBW
–
–71
–
dBm
3.2 GHz
100 kHz ResBW
–
–65
–
dBm
Maximum RF Transmit Power
PA = 6
–2
0
+2
dBm
Maximum RF Transmit Power
PA = 5
–7
–5
–3
dBm
Maximum RF Transmit Power
PA = 0
–
–35
–
35
dB
RF Power Range Control Step
Size
Six steps, monotonic
–
5.6
dB
Frequency Deviation Min
PN Code Pattern 10101010
–
270
kHz
Frequency Deviation Max
PN Code Pattern 11110000
–
323
kHz
Error Vector Magnitude
(FSK error)
>0 dBm
–
10
–
%rms
Occupied Bandwidth
–6 dBc, 100 kHz ResBW
500
876
–
kHz
Receive Spurious Emission
Transmitter (T = 25 °C, VCC = 3.0 V)
RF Power Control Range
dBm
Notes
19. Subject to regulation.
20. Exceptions F/3 & 5C/3.
Document Number: 001-66073 Rev. *D
Page 14 of 23
CYRF6986
Table 5. Radio Parameters (continued)
Parameter Description
Conditions
Min
Typ
Max
Unit
In-band Spurious Second
Channel Power (±2 MHz)
–
–38
–
dBm
In-band Spurious Third Channel
Power (>3 MHz)
–
–44
–
dBm
Non-Harmonically Related Spurs
(800 MHz)
–
–38
–
dBm
Non-Harmonically Related Spurs
(1.6 GHz)
–
–34
–
dBm
Non-Harmonically Related Spurs
(3.2 GHz)
–
–47
–
dBm
Harmonic Spurs
(Second Harmonic)
–
–43
–
dBm
Harmonic Spurs
(Third Harmonic)
–
–48
–
dBm
Fourth and Greater Harmonics
–
–59
–
dBm
–
0.7
1.3
ms
Transmit Spurious Emission (PA = 6)
Power Management (Crystal PN# eCERA GF-1200008)
Crystal Start to 10 ppm
Crystal Start to IRQ
XSIRQ EN = 1
–
0.6
–
ms
Synth Settle
Slow channels
–
–
270
µs
Synth Settle
Medium channels
–
–
180
µs
Synth Settle
Fast channels
–
–
100
µs
Link Turnaround Time
GFSK
–
–
30
µs
Link Turnaround Time
250 kbps
–
–
62
µs
Max Packet Length
<60 ppm crystal-to-crystal
–
–
40
bytes
Document Number: 001-66073 Rev. *D
Page 15 of 23
CYRF6986
Typical Operating Characteristics
Figure 9. Typical Operating Characteristics [21]
Transmit Power vs. Vcc
Transmit Power vs. Temperature
(Vcc = 2.7 V)
1
Transmit Power vs. Channel
1
PA6
PA5
-7
-9
-11
PA4
-3
-5
PA5
-7
-9
-11
PA4
-13
0
20
40
2.9
3.1
Temp (deg C)
3.3
3.5
PA4
0
20
40
60
80
Channel
Average RSSI vs. Vcc
(Rx signal = -70 dBm)
20
19
19
LNAOFF
18
ATTON
18
17
RSSI Count
17
16
RSSI Count
24
16
15
16
15
14
13
14
8
12
13
0
11
10
12
-120
-100
-80
-60
-40
-20
0
20
Input Power (dBm)
RSSI vs. Channel
(Rx signal = -70 dBm)
40
Temp (deg C)
2.7
60
Rx Sensitivity vs. Vcc
(1 Mbps CER)
-74
-76
-76
14
-78
-78
10
8
6
4
-80
-82
-86
-90
-92
40
Channel
60
8DR32
-88
0
20
GFSK
-84
2
0
RX Sensitivity (dBm)
-74
16
12
80
-84
-86
-92
2.9
3.1
Vcc
3.3
3.5
0
Receiver Sensitivity vs. Channel
(3.0 V, Room Temp)
10
-78
8DR32
-88
GFSK
-84
-90
-92
-92
50
Crystal Offset (ppm)
150
-20
-30
-86
8DR32
-40
-88
-50
60
-10
-82
-90
-150
40
Temp (deg C)
0
-80
C/I (dB)
RX Sensitivity (dBm)
-76
-78
-86
20
Carrier to Interferer
(Narrow band, LP modulation)
-76
GFSK
8DR32
-88
20
-84
3.5
-82
-74
-82
3.3
GFSK
-80
-74
-80
3.1
Vcc
-90
2.7
Receiver Sensitivity vs. Frequency
Offset
2.9
Rx Sensitivity vs. Temperature
(1 Mbps CER)
18
RX Sensitivity (dBm)
RSSI Count
-9
-11
Average RSSI vs. Temperature
(Rx signal = -70 dBm)
32
RX Sensitivity (dBm)
PA5
-7
Vcc
Typical RSSI Count vs. Input Power
LNAON
-5
-15
2.7
60
-3
-13
-15
-15
PA6
-1
Output Power (dBm)
-5
Output Power (dBm)
Output Power (dBm)
-3
-13
RSSI Count
1
PA6
-1
-1
-50
-60
0
20
40
Channel
60
80
-10
-5
0
5
Channel Offset (MHz)
10
Note
21. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document Number: 001-66073 Rev. *D
Page 16 of 23
CYRF6986
Typical Operating Characteristics (continued)
ICC RX
(LNA ON)
3.3V
3.0V
2.7V
19
18.5
18
17.5
17
25
24.5
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
16
15.5
15
14.5
16
15.5
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
16.5
3.3V
3.0V
2.7V
16.5
16
15.5
15
14.5
14
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX at PA4
20.5
19
3.3V
3.0V
2.7V
17
ICC TX at PA3
20
18.5
18
17.5
3.3V
3.0V
2.7V
17
16.5
16
ICC TX at PA5
3.3V
3.0V
2.7V
19
18.5
18
17.5
16.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
19.5
17
15.5
15
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX at PA6
30
23
3.3V
3.0V
2.7V
21.5
21
20.5
20
19.5
OPERATING CURRENT (mA)
23.5
OPERATING CURRENT (mA)
3.3V
3.0V
2.7V
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
18
22
17.5
16.5
ICC TX at PA2
22.5
ICC TX at PA1
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
ICC TX at PA0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
17
TEMPERATURE (C)
14
17.5
3.3V
3.0V
2.7V
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
17
3.3V
3.0V
2.7V
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
3.3V
3.0V
2.7V
OPERATING CURRENT (mA)
20
19.5
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
21
20.5
ICC RX SYNTH
OPERATING CURRENT (mA)
ICC RX
(LNA OFF)
29.5
29
28.5
28
3.3V
3.0V
2.7V
27.5
27
26.5
26
25.5
25
24.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Document Number: 001-66073 Rev. *D
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Page 17 of 23
CYRF6986
AC Test Loads and Waveforms for Digital Pins
Figure 10. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
INCLUDING
JIG AND
SCOPE
R1
VCC
5 pF
30 pF
OUTPUT
INCLUDING
JIG AND
Typical
SCOPE
Max
R2
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
Unit



V
V
1071
937
500
1.4
3.00
VCC
90%
GND
Fall time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
VTH
OUTPUT
Equivalent to:
GFSK vs. BER
(SOP Threshold = 5, C38 slow)
100
0through6
10
1
1
%BER
0.1
%BER
10%
Rise time: 1 V/ns
BER vs. Data Threshold (32-8DR)
(SOP Threshold = 5, C38 slow)
10
90%
10%
0.01
0.001
0.1
0.01
0.001
0.0001
GFSK
0.0001
0.00001
0.00001
-100
Document Number: 001-66073 Rev. *D
-90
-80
Input Power (dBm)
-70
-100
-50
Input Power (dBm)
0
Page 18 of 23
CYRF6986
Ordering Information
Table 6. Key Feature and Package Information
Part Number
Radio
CYRF6986-40LTXC
Package
Name
Package Type
Transceiver 001-44328 40-pin QFN (Sawn type)
Operating
Range
Commercial
Ordering Code Definitions
CY RF
6986 - 40
LT
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
LT = 40-pin QFN (Sawn Type)
No of pins in package / KGD Level:
40 = 40 pins
Part Number
Marketing Code: RF = Wireless (radio frequency) product line
Company ID: CY = Cypress
Document Number: 001-66073 Rev. *D
Page 19 of 23
CYRF6986
Package Diagram
The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm × 3.5 mm (width × length).
Figure 11. 40-pin QFN (6 × 6 × 0.90 mm) 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-44328
001-44328 *F
Document Number: 001-66073 Rev. *D
Page 20 of 23
CYRF6986
Acronyms
Document Conventions
Table 7. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 8. Units of Measure
ACK
Acknowledge (packet received, no errors)
BER
Bit Error Rate
°C
degree Celsius
BOM
Bill Of Materials
dB
decibel
CMOS
Complementary Metal Oxide Semiconductor
dBc
decibel relative to carrier
CRC
Cyclic Redundancy Check
dBm
decibel-milliwatt
FEC
Forward Error Correction
Hz
hertz
FER
Frame Error Rate
KB
1024 bytes
GFSK
Gaussian Frequency-Shift Keying
Kbit
1024 bits
HBM
Human Body Model
kHz
kilohertz
ISM
Industrial, Scientific, and Medical
k
kilohm
IRQ
Interrupt Request
MHz
megahertz
MCU
Microcontroller Unit
M
megaohm
NRZ
Non Return to Zero
A
microampere
PLL
Phase Locked Loop
s
microsecond
QFN
Quad Flat No-leads
V
microvolt
RSSI
Received Signal Strength Indication
Vrms
microvolts root-mean-square
RF
Radio Frequency
W
microwatt
Rx
Receive
mA
milliampere
Tx
Transmit
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt

ohm
pp
peak-to-peak
ppm
parts per million
ps
picosecond
sps
samples per second
V
volt
Document Number: 001-66073 Rev. *D
Symbol
Unit of Measure
Page 21 of 23
CYRF6986
Document History Page
Description Title: CYRF6986, WirelessUSB™ LPstar 2.4 GHz Radio SoC
Document Number: 001-66073
Revision
ECN
Orig. of
Change
Submission
Date
**
3139241
KKCN
01/14/2011
New data sheet.
*A
3170692
KKCN
02/11/2011
Updated in new template.
Description of Change
*B
3196461
KKCN
03/15/2011
Updated the text with LPstar.
*C
3333406
KPMD
08/01/2011
Changed status from Preliminary to Final.
*D
4237039
LIP
01/06/2014
Updated Package Diagram:
spec 001-44328 – Changed revision from *D to *F.
Updated in new template.
Completing Sunset Review.
Document Number: 001-66073 Rev. *D
Page 22 of 23
CYRF6986
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/psoc
Technical Support
cypress.com/go/support
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-66073 Rev. *D
Revised January 6, 2014
Page 23 of 23
WirelessUSB™ is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.