DC840A - Schematic

3
2
1
REVISION HISTORY
ECO
LDO
REV
DESCRIPTION
DATE
2
PROTO, CHANGE IC TO DD8 3X3, ADD LDO
02/03/05
OFF
6
D
JP4
5
3
AUTO
1
ON
E7
U1
2.5V-5.5V CIN1 *
47uF
10V
C
4 VIN
VIN
+
CIN
4.7uF
6.3V
ON
3
JP1
2
OFF
VOUT
1
ENABLE
GND
E4
JP2
2.25MHz
RSD
1.5MHz
4.7M
FREQ
SYNC
E2
2
RFS
1
4.7M
SW 5
2.2uH
7 SYNC
SYNC
SYNC
JP3 3
FREE-RUNNING
2
B
SYNC
COUT
10uF
4V
VOUT 2
E5
CFFW 22pF
FB 1
E3
VOUT
COUT1 600mA MAX
0.1uF
6.3V
VOUT
SUMIDA
CDRH2D18-HP2R2NC
6 FREQ
LDO
CONTROL
L1
C
GND
RFB2
RFB1
1.2V
499K
1%
9
SETTING
8 RUN
3
GND
E1
LDOCNTRL 3
LTC3448EDD
VIN
APPROVED
CONTROL
4
D
4
2
5
This circuit is proprietary to Linear Technology and supplied
for use with Linear Technology parts.
Customer Notice: Linear Technology has made a best effort to
design a circuit that meets customer-supplied specifications;
however, it remains the customers responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly
affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
RPD
1.5V
JP5
E6
JP6
4.7M
1.8V
1
499K 1%
JP7
RFB3
GND
249K 1%
RFB4
B
249K 1%
USER
SELECT RFB5 **
0
*CAPACITOR CIN1 IS AN OPTIONAL PART. IT WAS INSERTED ON THE DC840A
CONTRACT NO.
TO DAMPEN THE (POSSIBLE) RINGING VOLTAGE DUE TO THE USE OF LONG
APPROVALS
INPUT LEADS. ON A NORMAL, TYPICAL PCB, WITH SHORT TRACES,
A
DRAWN
THE CAPACITOR IS NOT NEEDED.
DATE
09/24/04
CHECKED
**SPACE PROVIDED FOR AN OPTIONAL RESISTOR TO
PROGRAM A CUSTOM OUTPUT VOLTAGE. RFB5 IS
INSERTED TO PREVENT THE OUTPUT VOLTAGE FROM
RISING TO VIN IN CASE THE JUMPER SHUNT IS
ACCIDENTALLY LEFT OFF.
5
MEI
4
TECHNOLOGY
TITLE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
SCH, LTC3448EDD, BUCK/LDO REGULATOR
A
APPROVED
ENGINEER
DESIGNER
Thursday, February 03, 2005
3
SIZE CAGE CODE
DWG NO
FILENAME: 840A-2.DSN
SCALE:
2
REV
DC840A
2
SHEET
1
1
OF
1
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