DC992A - Schematic

5
4
3
2
1
D
D
*
+CIN1
JP1
VOUT ENABLE
ON
OFF
C
JP2
MODE
PULSE-SKIP
BURST
CIN
4.7UF
6.3V
0603
22UF
10V
5
4
VIN
SW
RUN
MODE
GND
1
GND
VIN
2
GND
E2
U1
LTC3549EDCB
7
VIN E1
1.6V-5.5V
FB
L1
3.3UH
3
TDK
VLF3010AT-3R3MR87
6
VOUT
COUT
4.7UF
6.3V
0603
RFB1
102K
COUT1
0.1UF
0603
JP3
USER SELECT
RSD
1.0M
GND
GND
CFFW
47PF
RFB2
97.6K
1%
1.2V
JP5
C
RFB3
49.9K
1%
1.5V
RFB4
49.9K
1%
JP6
1.8V
E4
E5
RFB6
OPT
JP4
RBM
1.0M
E3 VOUT
250mA MAX.
RFB5
0
B
B
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0402.
ALL CAPACITORS ARE 0402.
2. INSTALL SHUNT ON JP1-JP2 & JP5 PIN 1 AND 2.
A
*
CIN1 IS AN OPTIONAL CAPACITOR. IT IS INSERTED
ON THE DC992A TO DAMPEN THE (POSSIBLE)
RINGING VOLTAGE DUE TO THE LONG INPUT LEADS.
ON A NORMAL, TYPICAL PCB, WITH SHORT TRACES,
THE CAPACITOR IS NOT NEEDED.
5
4
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
CONTRACT NO.
APPROVALS
DRAWN:
TECHNOLOGY
KIM T.
CHECKED:
TITLE: SCHEMATIC
MONOLITHIC SYNCHRONOUS BUCK REGULATOR
APPROVED:
ENGINEER: TOM G.
DESIGNER:
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
SIZE
A
DATE:
2
DWG NO.
DC992A-1 * LTC3549EDCB
Wednesday, August 23, 2006
SHEET
1
REV
A-1
1 OF 1
A
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