DAC8560

DAC8560
DA
C8
560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
16-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter
with 2.5V, 2ppm/°C Internal Reference
Check for Samples: DAC8560
FEATURES
DESCRIPTION
•
•
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•
The DAC8560 is a low-power, voltage output, 16-bit
digital-to-analog converter (DAC). The DAC8560
includes a 2.5V, 2ppm/°C internal reference (enabled
by default), giving a full-scale output voltage range of
2.5V. The internal reference has an initial accuracy of
0.02% and can source up to 20mA at the VREF pin.
The device is monotonic, provides very good linearity,
and minimizes undesired code-to-code transient
voltages (glitch). The DAC8560 uses a versatile
3-wire serial interface that operates at clock rates up
to 30MHz. It is compatible with standard SPI™,
QSPI™, Microwire™, and digital signal processor
(DSP) interfaces.
1
234
•
•
•
•
•
•
•
•
•
•
Relative Accuracy: 4LSB
Glitch Energy: 0.15nV-s
MicroPower Operation: 510μA at 2.7V
Internal Reference:
– 2.5V Reference Voltage (enabled by default)
– 0.02% Initial Accuracy
– 2ppm/°C Temperature Drift (typ)
– 5ppm/°C Temperature Drift (max)
– 20mA Sink/Source Capability
Power-On Reset to Zero
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature Range
Settling Time: 10μs to ±0.003% FSR
Low-Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Power-Down Capability
Drop-In Compatible With DAC8531 /01 and
DAC8550 /51
Temperature Range: –40°C to +105°C
Available in a Tiny MSOP-8 Package
The DAC8560 incorporates a power-on-reset circuit
that ensures the DAC output powers up at zero-scale
and remains there until a valid code is written to the
device. The DAC8560 contains a power-down
feature, accessed over the serial interface, that
reduces the current consumption of the device to
1.2μA at 5V.
The low-power consumption, internal reference, and
small footprint make this device ideal for portable,
battery-operated equipment. The power consumption
is 2.6mW at 5V, reducing to 6μW in power-down
mode.
The DAC8560 is available in an MSOP-8 package.
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
•
•
•
•
•
Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
VDD
VFB
VREF
VOUT
Ref (+)
16-Bit DAC
2.5V
Reference
16
DAC Register
16
SYNC
SCLK
Shift Register
PWD
Control
Resistor
Network
DIN
GND
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2011, Texas Instruments Incorporated
DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
MAXIMUM
REFERENCE
DRIFT
(ppm/°C)
DAC8560A
±12
±1
25
DAC8560B
±8
±1
25
DAC8560C
±12
±1
5
DAC8560D
±8
±1
5
(1)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
MSOP-8
DGK
–40°C TO +105°C
D860
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
–0.3V to 6V
VDD to GND
Digital input voltage to GND
–0.3V to +VDD + 0.3V
VOUT to GND
–0.3V to +VDD + 0.3V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature range (TJ max)
+150°C
Power dissipation (DGK)
(TJ max – TA)/θJA
Thermal impedance, θJA
206°C/W
Thermal impedance, θJC
44°C/W
ESD rating
(1)
2
Human body model (HBM)
4000V
Charged device model (CDM)
1500V
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±4
±12
LSB
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by line passing
through codes 485 and 64714
Differential nonlinearity
16-bit Monotonic
DAC8560A, DAC8560C
DAC8560B, DAC8560D
Zero-code error
Full-scale error
Measured by line passing through codes 485 and 64714.
Gain error
PSRR
Power supply rejection ratio
±4
±8
LSB
±0.5
±1
LSB
±5
±12
mV
±0.2
±0.5
% of FSR
±0.05
±0.2
% of FSR
±4
Zero-code error drift
Gain temperature coefficient
Bits
VDD = 5V
±1
VDD = 2.7V
±3
Output unloaded
μV/°C
ppm of FSR/°C
1
mV/V
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
RL = 2kΩ, CL = 500pF
Slew rate
Capacitive load stability
RL = ∞
VREF
8
V
10
μs
12
1.8
V/μs
470
pF
RL = 2kΩ
1000
Code change glitch impulse
1LSB change around major carry
0.15
nV-s
Digital feedthrough
SCLK toggling, SYNC high
0.15
nV-s
DC output impedance
At mid-code input
Short-circuit current
Power-up time
1
VDD = 5V
50
VDD = 3V
20
Coming out of power-down mode VDD = 5V
2.5
Coming out of power-down mode VDD = 3V
5
Ω
mA
μs
AC PERFORMANCE (2)
SNR
88
dB
THD
TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
–77
dB
79
dB
77
dB
DAC output noise density
TA = +25°C, at mid-code input, fOUT = 1kHz
170
nV/√Hz
DAC output noise
TA = +25°C, at mid-code input, 0.1Hz to 10Hz
50
μVPP
SFDR
SINAD
(1)
(2)
Linearity calculated using a reduced code range of 485 to 64714; output unloaded.
Ensured by design and characterization, not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, –40°C to +105°C range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE OUTPUT
Output voltage
TA = +25°C
2.4975
2.5
2.5025
V
Initial accuracy
TA = +25°C
–0.1
±0.004
0.1
%
DAC8560A, DAC8560B (3)
5
25
DAC8560C, DAC8560D (4)
2
5
Output voltage temperature drift
Output voltage noise
f = 0.1Hz to 10Hz
Output voltage noise density
(high-frequency noise)
Load regulation, sourcing (5)
Load regulation, sinking
(5)
125
TA = +25°C, f = 1MHz, CL = 1μF
20
TA = +25°C, f = 1MHz, CL = 4μF
2
TA = +25°C
TA = +25°C
Output current load capability (6)
Line regulation
TA = +25°C
Long-term stability/drift (aging) (5)
TA = +25°C, time = 0 to 1900 hours
Thermal hysteresis (5)
μVPP
16
TA = +25°C, f = 1MHz, CL = 0μF
First cycle
nV/√Hz
30
μV/mA
15
μV/mA
±20
mA
10
μV/V
50
ppm
100
Additional cycles
ppm/°C
ppm
25
REFERENCE
Internal reference current consumption
External reference current
VDD = 5.5V
360
VDD = 3.6V
348
External VREF = 2.5V, if internal reference is disabled
Reference input range
μA
20
0
Reference input impedance
LOGIC INPUTS
μA
VDD
125
V
kΩ
(6)
±1
Input current
VINL
Logic input LOW voltage
VINH
Logic input HIGH voltage
μA
VDD = 5V
0.8
VDD = 3V
0.6
VDD = 5V
2.4
VDD = 3V
2.1
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
Normal mode
IDD
(7)
All power-down modes
Power
dissipation
Normal mode
(7)
All power-down modes
VDD = 3.6V to 5.5V, VIH = VDD and VIL = GND
0.530
0.850
VDD = 2.7V to 3.6V, VIH = VDD and VIL = GND
0.510
0.840
VDD = 3.6V to 5.5V, VIH = VDD and VIL = GND
1.2
2.5
VDD = 2.7V to 3.6V, VIH = VDD and VIL = GND
0.7
2.2
VDD = 3.6V to 5.5V
2.6
4.7
VDD = 2.7V to 3.6V
1.5
3.0
VDD = 3.6V to 5.5V
6
14
VDD = 2.7V to 3.6V
2
8
mA
μA
mW
μW
TEMPERATURE RANGE
–40
Specified performance
(3)
(4)
(5)
(6)
(7)
4
+105
°C
Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C.
Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C.
Explained in more detail in the Application Information section of this data sheet.
Ensured by design and characterization, not production tested.
Input code = 32768, reference current included, no load.
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DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
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PIN CONFIGURATION
MSOP-8
(Top View)
VDD
1
VREF
2
8
GND
7
DIN
DAC8560
VFB
3
6
SCLK
VOUT
4
5
SYNC
PIN DESCRIPTIONS
PIN
NAME
1
VDD
Power supply input, 2.7V to 5.5V.
DESCRIPTION
2
VREF
Reference voltage input/output.
3
VFB
Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally.
4
VOUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register, and data is sampled on subsequent falling clock edges. The DAC output updates
following the 24th clock. If SYNC is taken HIGH before the 24th clock edge, the rising edge of SYNC acts as an interrupt,
and the write sequence is ignored by the DAC8560. Schmitt-Trigger logic Input.
6
SCLK
Serial clock input. Schmitt-Trigger logic input.
7
DIN
8
GND
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic Input.
Ground reference point for all circuitry on the part.
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DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
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SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t3
t4
t2
t7
SYNC
t6
t10
t5
DIN
DB23
TIMING REQUIREMENTS (1)
DB0
DB23
(2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted)
PARAMETER
t1
(3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
t10
SYNC rising edge to 24th SCLK falling edge
(for successful SYNC interrupt)
(1)
(2)
(3)
6
TEST CONDITIONS
MIN
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 3.6V
13
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
22.5
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
5
VDD = 3.6V to 5.5V
5
VDD = 2.7V to 3.6V
4.5
VDD = 3.6V to 5.5V
4.5
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 3.6V
100
VDD = 3.6V to 5.5V
100
VDD = 2.7V to 3.6V
15
VDD = 3.6V to 5.5V
15
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
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TYPICAL CHARACTERISTICS: Internal Reference
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades A and B)
2.503
2.503
2.502
2.502
2.501
2.501
VREF (V)
VREF (V)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE (Grades C and D)
2.500
2.499
2.500
2.499
2.498
2.498
10 Units Shown
2.497
-40
-20
0
20
40
60
100
13 Units Shown
2.497
-40
120
-20
0
20
Temperature (°C)
40
60
80
100
120
Temperature (°C)
Figure 1.
Figure 2.
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°C, Grades C and D)
REFERENCE OUTPUT TEMPERATURE DRIFT
(–40°C to +120°, Grades A and B)
40
30
Typ: 5ppm/°C
Max: 25ppm/°C
Typ: 2ppm/°C
Max: 5ppm/°C
Population (%)
Population (%)
30
20
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1
5.0
3
Temperature Drift (ppm/°C)
7
9
11
13
15
17
19
Temperature Drift (ppm/°C)
Figure 3.
Figure 4.
REFERENCE OUTPUT TEMPERATURE DRIFT
(0°C to +120°C, Grades C and D)
LONG-TERM
STABILITY/DRIFT (1)
200
40
Typ: 1.2ppm/°C
Max: 3ppm/°C
See the Applications Information
section for more information
150
100
Drift (ppm)
30
Population (%)
5
20
50
0
-50
Average
-100
10
-150
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
Figure 5.
(1)
300
600
900
1200
1500
1800
Time (Hours)
Temperature Drift (ppm/°C)
1900
20 Units Shown
-200
0
Figure 6.
Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: Internal Reference (continued)
At TA = +25°C, unless otherwise noted.
INTERNAL REFERENCE NOISE DENSITY
vs FREQUENCY (2)
400
INTERNAL REFERENCE NOISE
0.1Hz TO 10Hz (2)
See the Applications Information
section for more information
See the Applications Information
section for more information
16mVPP
VNOISE (4mV/div)
Vn (nV/ÖHz)
300
VDD = 5V
Reference Unbuffered
CREF = 0mF
200
100
CREF = 4mF
0
10
100
1k
10k
100k
Time (2s/div)
1M
Frequency (Hz)
Figure 7.
Figure 8.
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs LOAD CURRENT (Grades A and B)
2.504
2.504
2.503
2.503
2.502
15mV/mA (sinking)
2.501
15mV/mA (sinking)
-40°C
+25°C
2.500
2.499
VREF (V)
VREF (V)
2.502
-40°C
+120°C
2.498
2.501
+25°C
2.500
2.499
30mV/mA (sourcing)
2.498
30mV/mA (sourcing)
2.497
2.497
2.496
-25
2.496
-25
-20
-15
-10
-5
0
5
10
15
20
25
+120°C
-20
-15
-10
-5
ILOAD (mA)
15
20
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades C and D)
INTERNAL REFERENCE VOLTAGE
vs SUPPLY VOLTAGE (Grades A and B)
2.504
2.504
2.503
2.503
25
-40°C
2.502
-40°C
< 10mV/V
2.501
+25°C
2.500
VREF (V)
VREF (V)
10
Figure 10.
2.499
2.501
< 10mV/V
+25°C
2.500
2.499
+120°C
2.498
2.498
2.497
+120°C
2.497
2.0
8
5
Figure 9.
2.502
(2)
0
ILOAD (mA)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
VDD (V)
VDD (V)
Figure 11.
Figure 12.
4.5
5.0
5.5
6.0
Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: DAC at VDD = 5V
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
LE (LSB)
1.0
1.0
0.5
0.5
0
-0.5
-1.0
0
-0.5
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 13.
Figure 14.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
10
VDD = 5V, External VREF = 4.99V
57344 65536
VDD = 5.0V
Internal VREF = 2.5V
5
Error (mV)
LE (LSB)
VDD = 5V, External VREF = 4.99V
-1.0
0
1.0
DLE (LSB)
6
4
2
0
-2
-4
-6
VDD = 5V, External VREF = 4.99V
DLE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
0
0.5
0
-0.5
-5
-40
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
40
80
120
Temperature (°C)
Digital Input Code
Figure 15.
Figure 16.
FULL-SCALE ERROR
vs TEMPERATURE
SOURCE AND SINK
CURRENT CAPABILITY
10
3.0
VDD = 5.0V
Internal VREF = 2.5V
2.5
5
VDD = 5V
Internal Reference Enabled
DAC Loaded with FFFFh
VOUT (V)
Error (mV)
2.0
0
1.5
1.0
0.5
DAC Loaded with 0000h
-5
-40
0
0
40
80
120
0
Temperature (°C)
5
10
15
20
ISOURCE/SINK (mA)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
SOURCE AND SINK
CURRENT CAPABILITY
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
650
6
VDD = 5.5V
Internal VREF = 2.5V
5
VDD = 5V
Internal Reference Disabled
External VREF = 4.99V
DAC Loaded with FFFFh
600
IDD (mA)
VOUT (V)
4
3
550
2
500
1
DAC Loaded with 0000h
450
0
0
700
650
5
10
15
0
20
8192 16384 24576 32768 40960 49152 57344 65536
ISOURCE/SINK (mA)
Digital Input Code
Figure 19.
Figure 20.
POWER-SUPPLY CURRENT
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
510
VDD = 5.5V
Internal VREF = 2.5V
VDD = 2.7V to 5.5V
Internal VREF Included
505
IDD (mA)
IDD (mA)
600
550
500
495
500
490
450
400
-40
485
0
40
80
120
2.7
3.1
3.5
3.9
Temperature (°C)
4.7
Figure 21.
Figure 22.
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
2500
1.4
5.1
5.5
VDD = 5.5V, Internal VREF Included,
Sweep from 0V to 5V
SCLK Input
(all other digital inputs = GND)
Sweep from 5V to 0V
VDD = 2.7V to 5.5V
1.2
2000
1.0
IDD (mA)
Power-Down Current (mA)
4.3
VDD (V)
0.8
0.6
1500
1000
0.4
500
0.2
0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
VDD (V)
2
3
4
5
VLOGIC (V)
Figure 23.
10
1
Figure 24.
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TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
POWER-SUPPLY CURRENT
HISTOGRAM
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
80
70
-40
VDD = 5.5V
Internal VREF = 2.5V
VDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
-50
-60
50
THD (dB)
Occurrences
60
40
30
THD
-70
2nd Harmonic
-80
20
10
-90
0
-100
3rd Harmonic
450
475
500
525
550
575
600
0
IDD (mA)
1
2
3
4
Figure 25.
Figure 26.
FULL-SCALE SETTLING TIME:
5V RISING EDGE
FULL-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: 0000h
To Code: FFFFh
Rising Edge
1V/div
5
fOUT (kHz)
Zoomed Rising Edge
1mV/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: FFFFh
To Code: 0000h
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 27.
Figure 28.
HALF-SCALE SETTLING TIME:
5V RISING EDGE
HALF-SCALE SETTLING TIME:
5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
Ext VREF = 4.096V
From Code: CFFFh
To Code: 4000h
Rising
Edge
1V/div
VDD = 5V
Ext VREF = 4.096V
From Code: 4000h
To Code: CFFFh
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
VDD = 5V
Ext VREF = 4.096V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
GLITCH ENERGY:
5V, 1LSB STEP, FALLING EDGE
VOUT (500mV/div)
VOUT (500mV/div)
GLITCH ENERGY:
5V, 1LSB STEP, RISING EDGE
Time (400ns/div)
Time (400ns/div)
Figure 32.
GLITCH ENERGY:
5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 16LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
Time (400ns/div)
Figure 33.
Figure 34.
GLITCH ENERGY:
5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
5V, 256LSB STEP, FALLING EDGE
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
VDD = 5V
Ext VREF = 4.096V
From Code: 8010h
To Code: 8000h
Glitch: 0.08nV-s
VOUT (500mV/div)
VOUT (500mV/div)
Figure 31.
Time (400ns/div)
VDD = 5V
Ext VREF = 4.096V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 35.
12
VDD = 5V
Ext VREF = 4.096V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Figure 36.
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TYPICAL CHARACTERISTICS: DAC at VDD = 5V (continued)
At TA = +25°C, external reference used, and DAC output not loaded, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
98
POWER SPECTRAL DENSITY
VDD = 5V, External VREF = 4.9V
-1dB FSR Digital Input, fS = 225kSPS
Measurement Bandwidth = 20kHz
96
Gain (dB)
SNR (dB)
94
92
90
88
86
84
0
1
2
3
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
VDD = 5V, External VREF = 4.9V
fOUT = 1kHz, fS = 225kSPS
Measurement Bandwidth = 20kHz
0
5
5
15
Figure 37.
Figure 38.
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (1)
DAC OUTPUT NOISE DENSITY
vs FREQUENCY (1)
1800
1000
Internal Reference Enabled
No Load at VREF Pin
See the Applications Information
section for more information
1600
1400
1200
Full-Scale
1000
Midscale
800
Zero-Scale
600
20
Internal Reference Enabled
4mF vs No Load at VREF Pin
See the Applications Information
section for more information
800
Vn (nV/ÖHz)
Vn (nV/ÖHz)
10
Frequency (kHz)
fOUT (kHz)
400
600
400
CREF = 0mF
200
CREF = 4mF
200
0
0
10
100
1k
10k
100k
1M
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
Figure 39.
Figure 40.
100k
1M
DAC OUTPUT NOISE
0.1Hz TO 10Hz
VNOISE (10mV/div)
DAC = Midscale
Internal Reference Enabled
50mVPP
Time (2s/div)
Figure 41.
(1)
Explained in more detail in the Application Information section of this data sheet.
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TYPICAL CHARACTERISTICS: DAC at VDD = 3.6V
At TA = +25°C, internal reference used, and DAC output not loaded, unless otherwise noted
POWER-SUPPLY CURRENT
vs TEMPERATURE
700
650
POWER-SUPPLY CURRENT
HISTOGRAM
90
VDD = 3.6V
Internal VREF = 2.5V
VDD = 3.6V
Internal VREF = 2.5V
80
70
Occurrences
IDD (mA)
600
550
500
60
50
40
30
20
450
10
400
-40
0
0
40
80
120
450
Temperature (°C)
500
525
550
575
600
IDD (mA)
Figure 42.
14
475
Figure 43.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V
At TA = +25°C, internal reference used, and DAC output not loaded, unless otherwise noted
6
4
2
0
-2
-4
-6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+25°C)
6
4
2
0
-2
-4
-6
VDD = 2.7V, Internal VREF = 2.5V
LE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (–40°C)
1.0
DLE (LSB)
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
0
-0.5
6
4
2
0
-2
-4
-6
8192
16384 24576 32768 40960 49152
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Digital Input Code
Figure 44.
Figure 45.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE (+105°C)
ZERO-SCALE ERROR
vs TEMPERATURE
57344 65536
10
VDD = 2.7V, Internal VREF = 2.5V
VDD = 2.7V
Internal VREF = 2.5V
5
Error (mV)
LE (LSB)
0.5
-1.0
0
1.0
DLE (LSB)
VDD = 2.7V, Internal VREF = 2.5V
0
0.5
0
-0.5
-5
-40
-1.0
0
8192
16384 24576 32768 40960 49152
57344 65536
0
40
80
120
Temperature (°C)
Digital Input Code
Figure 46.
Figure 47.
FULL-SCALE ERROR
vs TEMPERATURE
SOURCE AND SINK
CURRENT CAPABILITY
10
3.0
VDD = 2.7V
Internal VREF = 2.5V
2.5
5
VDD = 2.7V
Internal Reference Enabled
DAC Loaded with FFFFh
VOUT (V)
Error (mV)
2.0
0
1.5
1.0
0.5
DAC Loaded with 0000h
-5
-40
0
0
40
80
120
0
Temperature (°C)
5
10
15
20
ISOURCE/SINK (mA)
Figure 48.
Figure 49.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, unless otherwise noted
SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
650
1000
VDD = 2.7V
Internal VREF = 2.5V
VDD = 2.7V, Internal VREF Included,
SCLK Input
(all other digital inputs = GND)
Sweep from 0V to 2.7V
900
600
IDD (mA)
IDD (mA)
800
550
700
Sweep from 2.7V to 0V
600
500
500
450
400
0
8192 16384 24576 32768 40960 49152 57344 65536
0
0.3
Digital Input Code
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
VLOGIC (V)
Figure 50.
Figure 51.
FULL-SCALE SETTLING TIME:
2.7V RISING EDGE
FULL-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: FFFFh
To Code: 0000h
Rising
Edge
0.5V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: 0000h
To Code: FFFFh
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 52.
Figure 53.
HALF-SCALE SETTLING TIME:
2.7V RISING EDGE
HALF-SCALE SETTLING TIME:
2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
Int VREF = 2.5V
From Code: CFFFh
To Code: 4000h
VDD = 2.7V
Int VREF = 2.5V
From Code: 4000h
To Code: CFFFh
Rising
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Time (2ms/div)
Figure 54.
16
Zoomed Falling Edge
1mV/div
Figure 55.
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TYPICAL CHARACTERISTICS: DAC at VDD = 2.7V (continued)
At TA = +25°C, internal reference used, and DAC output not loaded, unless otherwise noted
VDD = 2.7V
Int VREF = 2.5V
From Code: 7FFFh
To Code: 8000h
Glitch: 0.08nV-s
GLITCH ENERGY:
2.7V, 1LSB STEP, FALLING EDGE
VOUT (200mV/div)
VOUT (200mV/div)
GLITCH ENERGY:
2.7V, 1LSB STEP, RISING EDGE
Time (400ns/div)
Time (400ns/div)
Figure 57.
GLITCH ENERGY:
2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 16LSB STEP, FALLING EDGE
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 8010h
Glitch: 0.04nV-s
VDD = 2.7V
Int VREF = 2.5V
From Code: 8010h
To Code: 8000h
Glitch: 0.12nV-s
VOUT (200mV/div)
VOUT (200mV/div)
Figure 56.
Time (400ns/div)
Time (400ns/div)
Figure 58.
Figure 59.
GLITCH ENERGY:
2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY:
2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 80FFh
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
VDD = 2.7V
Int VREF = 2.5V
From Code: 8000h
To Code: 7FFFh
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
VDD = 2.7V
Int VREF = 2.5V
From Code: 80FFh
To Code: 8000h
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Figure 60.
Figure 61.
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
VREF
The DAC8560 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 62
shows a block diagram of the DAC architecture.
VREF
50kW
RDIVIDER
VREF
2
50kW
VFB
R
62kW
DAC
Register
REF (+)
Register String
REF (-)
VOUT
R
To Output Amplifier
(2x Gain)
GND
Figure 62. DAC8560 Architecture
The input coding to the DAC8560 is straight binary,
so the ideal output voltage is given by:
DIN
V OUT +
V REF
65536
(1)
R
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535.
R
RESISTOR STRING
The resistor string section is shown in Figure 63. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to VDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 1.8V/μs
with a full-scale settling time of 8μs with the output
unloaded.
18
Figure 63. Resistor String
The inverting input of the output amplifier is available
at the VFB pin. This feature allows better accuracy in
critical applications by tying the VFB point and the
amplifier output together directly at the load. Other
signal conditioning circuitry may also be connected
between these points for specific applications.
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INTERNAL REFERENCE
VREF
The DAC8560 includes a 2.5V internal reference that
is enabled by default. The internal reference is
externally available at the VREF pin. A minimum
100nF capacitor is recommended between the
reference output and GND for noise filtering.
Reference
Disable
The internal reference of the DAC8560 is a bipolar
transistor-based,
precision
bandgap
voltage
reference. The basic bandgap topology is shown in
Figure 64. Transistors Q1 and Q2 are biased such
that the current density of Q1 is greater than that of
Q2. The difference of the two base-emitter voltages
(VBE1 - VBE2) has a positive temperature coefficient
and is forced across resistor R1. This voltage is
gained up and added to the base-emitter voltage of
Q2, which has a negative temperature coefficient. The
resulting output voltage is virtually independent of
temperature. The short-circuit current is limited by
design to approximately 100mA.
Enable/Disable Internal Reference
The DAC8560 internal reference is enabled by
default; however, the reference can be disabled for
debugging or evaluation purposes. A serial command
requiring at least two additional SCLK cycles at the
end of the 24-bit write sequence (see Serial Interface
section) must be used to disable the internal
reference. For proper operation, a total of at least 26
SCLK cycles are required for each enable/disable
internal reference update sequence, during which
SYNC must be held low. To disable the internal
reference, execute the write sequence illustrated in
Table 1 followed by at least two additional SCLK
falling edges while SYNC is low.
Q1
1
N
Q2
R1
R2
Figure 64. Simplified Schematic of the Bandgap
Reference
To then enable the reference, either perform a
power-cycle to reset the device, or sequentially
execute the two write sequences in Table 2 and
Table 3. Each of these write sequences must be
followed by at least two additional SCLK falling edges
while SYNC remains low.
During the time that the internal reference is disabled,
the DAC will function normally using an external
reference. At this point, the internal reference is
disconnected from the VREF pin (tri-state). Do not
attempt to drive the VREF pin externally and internally
at the same time indefinitely.
Table 1. Write Sequence for Disabling the DAC8560 Internal Reference
DB23
0
DB0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
Table 2. Enabling the DAC8560 Internal Reference (Write Sequence 1 of 2)
DB23
0
DB0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Table 3. Enabling the DAC8560 Internal Reference (Write Sequence 2 of 2)
DB23
0
DB0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
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SERIAL INTERFACE
The DAC8560 has a 3-wire serial interface ( SYNC,
SCLK, and DIN) that is compatible with SPI, QSPI,
and Microwire interface standards, as well as most
DSPs. See the Serial Write Operation timing diagram
for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line
LOW. Data from the DIN line is clocked into the 24-bit
shift register on each falling edge of SCLK. The serial
clock frequency can be as high as 30MHz, making
the DAC8560 compatible with high-speed DSPs. On
the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed.
At this point, the SYNC line may be kept LOW or
brought HIGH. In either case, it must be brought
HIGH for a minimum of 33ns before the next write
sequence so that a falling edge of SYNC can initiate
the next write sequence. As previously mentioned, it
must be brought HIGH again before the next write
sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Table 4. The first six bits must be '000000'. The next
two bits (PD1 and PD0) are control bits that set the
desired mode of operation (normal mode or any one
of three power-down modes) as indicated in Table 5.
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A more complete description of the various modes is
located in the Power-Down Modes section. The next
16 bits are the data bits, which are transferred to the
DAC register on the 24th falling edge of SCLK under
normal operation (see Table 5).
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register
contents, nor a change in the operating mode occurs,
as shown in Figure 65.
POWER-ON RESET
The DAC8560 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, all registers are filled with zeros and the
output voltage is zero-scale; it remains there until a
valid write sequence is made to the DAC. This
feature is useful in applications where it is important
to know the state of the output of the DAC while it is
in the process of powering up.
Table 4. DAC8560 Data Input Register Format
DB23
0
DB0
0
0
0
0
0
PD
1
PD
0
D15 D14 D13 D12 D11 D10
D9
D8
24th Falling Edge
D7
D6
D5
D4
D3
D2
D1
D0
24th Falling Edge
CLK
SYNC
DIN
DB23
DB0
DB23
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
DB0
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 65. SYNC Interrupt Facility
20
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POWER-DOWN MODES
The DAC8560 supports four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 5 shows how to control the operating mode
with data bits PD1 (DB17) and PD0 (DB16).
The advantage of this switching is that the output
impedance of the device is known while it is in
power-down mode. As shown in Table 5, there are
three different power-down options. VOUT can be
connected internally to GND through a 1kΩ resistor, a
100kΩ resistor, or open circuited (High-Z). The output
stage is illustrated in Figure 66.
Table 5. Operating Modes
PD1
(DB17)
PD0
(DB16)
0
0
Normal operation
0
1
Power-down 1 kΩ to GND
1
0
Power-down 100 kΩ to GND
1
1
Power-down High-Z
VFB
OPERATING MODE
Resistor
String
DAC
When both bits are set to '0', the device works
normally with its typical current consumption of
530μA at 5.5V. However, for the three power-down
modes, the supply current falls to 1.2μA at 5.5V
(0.7μA at 3.6V). Not only does the supply current fall,
but the output stage is also internally switched from
the output of the amplifier to a resistor network of
known values.
Amplifier
Power-Down
Circuitry
VOUT
Resistor
Network
Figure 66. Output Stage During Power Down
All analog circuitry is shut down when the
power-down mode is activated. However, the
contents of the DAC register are unaffected when in
power down. The time to exit power-down is typically
2.5μs for VDD = 5V, and 5μs for VDD = 3V. See the
Typical Characteristics for more information.
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DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
APPLICATION INFORMATION
INTERNAL REFERENCE
The DAC8560 internal reference does not require an
external load capacitor for stability because it is
stable with any capacitive load. However, for
improved noise performance, an external load
capacitor of 150nF or larger connected to the VREF
output is recommended. Figure 67 shows the typical
connections required for operation of the DAC8560
internal reference. A supply bypass capacitor at the
VDD input is also recommended.
DAC8560
VDD
GND
8
DIN
7
VFB
SCLK
6
VOUT
SYNC
5
1
VDD
2
VREF
3
4
1mF
VREF
150nF
Figure 67. Typical Connections for Operating the
DAC8560 Internal Reference
The DAC8560 internal reference (grades C and D)
features an exceptional typical drift coefficient of
2ppm/°C from –40°C to +120°C. Characterizing a
large number of units, a maximum drift coefficient of
5ppm/°C (grades C and D) is observed. Temperature
drift results are summarized in the Typical
Characteristics.
Noise Performance
Typical 0.1Hz to 10Hz voltage noise can be seen in
Figure 8, Internal Reference Noise. Additional filtering
can be used to improve output noise levels, although
care should be taken to ensure the output impedance
does not degrade the AC performance. The output
noise spectrum at VREF without any external
components is depicted in Figure 7, Internal
Reference Noise Density vs Frequency. Another
noise density spectrum is also shown in Figure 7,
which was obtained using a 4μF load capacitor at
VREF for noise filtering. Internal reference noise
impacts the DAC output noise; see the DAC Noise
Performance section for more details.
Load Regulation
Supply Voltage
The DAC8560 internal reference features an
extremely low dropout voltage. It can be operated
with a supply of only 5mV above the reference output
voltage in an unloaded condition. For loaded
conditions, refer to the Load Regulation section. The
stability of the DAC8560 internal reference with
variations in supply voltage (line regulation, DC
PSRR) is also exceptional. Within the specified
supply voltage range of 2.7V to 5.5V, the variation at
VREF is smaller than 10μV/V; see the Typical
Characteristics.
Load regulation is defined as the change in reference
output voltage as a result of changes in load current.
The load regulation of the DAC8560 internal
reference is measured using force and sense
contacts as pictured in Figure 68. The force and
sense lines reduce the impact of contact and trace
resistance, resulting in accurate measurement of the
load regulation contributed solely by the DAC8560
internal reference. Measurement results are
summarized in the Typical Characteristics. Force and
sense lines should be used for applications requiring
improved load regulation.
Temperature Drift
The DAC8560 internal reference is designed to
exhibit minimal drift error, defined as the change in
reference output voltage over varying temperature.
The drift is calculated using the box method, which is
described by Equation 2:
Drift Error +
ǒ
Ǔ
V REF_MAX * V REF_MIN
V REF T RANGE
10 6 (ppmń°C)
Output Pin
VOUT
Force Line
IL
Sense Line
(2)
Where:
VREF_MAX = maximum reference voltage observed
within temperature range TRANGE.
VREF_MIN = minimum reference voltage observed
within temperature range TRANGE.
VREF = 2.5V, target value for reference output
voltage.
22
Contact and
Trace Resistance
Meter
Load
Figure 68. Accurate Load Regulation of the
DAC8560 Internal Reference
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DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
Long-Term Stability
Long-term stability/aging refers to the change of the
output voltage of a reference over a period of months
or years. This effect lessens as time progresses, as
shown in Figure 6, the typical long-term stability
curve. The typical drift value for the DAC8560 internal
reference is 50ppm from 0 hours to 1900 hours. This
parameter is characterized by powering-up and
measuring 20 units at regular intervals for a period of
1900 hours.
DD
REF
+6V
R1
10kW
OPA703
VDD
VREF
10mF
±5V
VFB
VOUT
DAC8560
0.1mF
-6V
GND
Three-Wire
Serial Interface
Thermal Hysteresis
Thermal hysteresis for a reference is defined as the
change in output voltage after operating the device at
+25°C, cycling the device through the specified
temperature range, and returning to +25°C. It is
expressed in Equation 3:
Ť VREF_PRE * V REF_POST Ť
10 6 (ppm)
V HYST +
VREF_NOM
ǒ
R2
10kW
V
V
Ǔ
Figure 69. Bipolar Output Range Using External
Reference at 5V
R2
10kW
V
DD
(3)
Where:
VHYST = thermal hysteresis.
VREF_PRE = output voltage measured at +25°C
pre-temperature cycling.
VREF_POST = output voltage measured after the
device has been cycled through the temperature
range of –40°C to +120°C, and returned to
+25°C.
+6V
R1
10kW
±2.5V
OPA703
VDD
VFB
VREF
DAC8560
150nF
VOUT
-6V
GND
Three-Wire
Serial Interface
DAC NOISE PERFORMANCE
Typical noise performance for the DAC8560 with the
internal reference enabled is shown in Figure 39 to
Figure 41. Output noise spectral density at pin VOUT
versus frequency is depicted in Figure 39 for
full-scale, midscale, and zero scale input codes. The
typical noise density for midscale code is 170nV/√Hz
at 1kHz and 100nV/√Hz at 1MHz. High-frequency
noise can be improved by filtering the reference noise
as shown in Figure 40, where a 4μF load capacitor is
connected to the VREF pin and compared to the
no-load condition. Integrated output noise between
0.1Hz and 10Hz is close to 50μVPP (midscale), as
shown in Figure 41.
BIPOLAR OPERATION USING THE DAC8560
The DAC8560 has been designed for single-supply
operation, but a bipolar output range is also possible
using the circuit in either Figure 69 or Figure 70. The
circuit shown gives an output voltage range of ±VREF.
Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
Figure 70. Bipolar Output Range Using Internal
Reference
The output voltage for any input code can be
calculated as using Equation 4:
ƪ
V O + VREF
D Ǔ
ǒ65536
ǒR R) R Ǔ * V
1
ǒRR Ǔƫ
2
2
REF
1
1
(4)
where D represents the input code in decimal
(0–65535).
With VREF = 5V, R1 = R2 = 10kΩ.
ǒ
Ǔ
V O + 10 D * 5V
65536
(5)
This result has an output voltage range of ±5V with
0000h corresponding to a –5V output and FFFFh
corresponding to a 5V output, as shown in Figure 69.
Similarly, using the internal reference, a ±2.5V output
voltage range can be achieved, as shown in
Figure 70.
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Product Folder Link(s): DAC8560
23
DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
MICROPROCESSOR INTERFACING
www.ti.com
MicrowireTM
DAC8560 (1)
DAC8560 TO 8051 Interface
CS
SYNC
See Figure 71 for a serial interface between the
DAC8560 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8560, while RXD drives
the serial data line of the device. The SYNC signal is
derived from a bit-programmable pin on the port of
the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8560, P3.3 is
taken LOW. The 8051 transmits data in 8-bit bytes;
thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left
LOW after the first eight bits are transmitted, then a
second write cycle is initiated to transmit the second
byte of data. P3.3 is taken HIGH following the
completion of the third write cycle. The 8051 outputs
the serial data in a format which has the LSB first.
The DAC8560 requires its data with the MSB as the
first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 72. DAC8560 to Microwire Interface
DAC8560 to 68HC11 Interface
Figure 73 shows a serial interface between the
DAC8560 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8560, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
DAC8560 (1)
68HC11(1)
PC7
SYNC
SCK
SCLK
MOSI
80C51/80L51(1)
DAC8560 (1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 71. DAC8560 to 80C51/80L51 Interface
DAC8560 to Microwire Interface
Figure 72 shows an interface between the DAC8560
and any Microwire compatible device. Serial data is
shifted out on the falling edge of the serial clock and
is clocked into the DAC8560 on the rising edge of the
SK signal.
24
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 73. DAC8560 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data is being
transmitted to the DAC, the SYNC line is held LOW
(PC7). Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted
MSB first.) In order to load data to the DAC8560,
PC7 is left LOW after the first eight bits are
transferred, then a second and third serial write
operation is performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
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Product Folder Link(s): DAC8560
DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8560 offers single-supply operation, and it
often is used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it is to keep digital noise from appearing at
the output.
As a result of the single ground pin of the DAC8560,
all return currents, including digital and analog return
currents for the DAC, must flow through a single
point. Ideally, GND would be connected directly to an
analog ground plane. This plane would be separate
from the ground connection for the digital
components until they were connected at the
power-entry point of the system.
The power applied to VDD should be well regulated
and low noise. Switching power supplies and DC/DC
converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes
as their internal logic switches states. This noise can
easily couple into the DAC output voltage through
various paths between the power connections and
analog output.
As with the GND connection, VDD should be
connected to a power-supply plane or trace that is
separate from the connection for digital logic until
they are connected at the power-entry point. In
addition, a 1μF to 10μF capacitor and 0.1μF bypass
capacitor are strongly recommended. In some
situations, additional bypassing may be required,
such as a 100μF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors – all
designed to essentially low-pass filter the supply,
removing the high-frequency noise.
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Product Folder Link(s): DAC8560
25
DAC8560
SLAS464B – DECEMBER 2006 – REVISED NOVEMBER 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2006) to Revision A
Page
•
Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively ........... 4
•
Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ........................... 4
Changes from Revision A (May 2011) to Revision B
Page
•
Changed Revision date from A, May 2011 to B, November 2011 ....................................................................................... 1
•
Changed "Zero-code error drift" in the ELEC CHARA table, TYP from ±20 to ±4 ............................................................... 3
26
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Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): DAC8560
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC8560IADGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IADGKRG4
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IADGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IADGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IBDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560ICDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
D860
DAC8560IDDGKTG4
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
D860
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
DAC8560IADGKR
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IADGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IBDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IBDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560ICDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560ICDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IDDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC8560IDDGKT
VSSOP
DGK
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8560IADGKR
VSSOP
DGK
8
2500
367.0
367.0
38.0
DAC8560IADGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560IBDGKR
VSSOP
DGK
8
2500
367.0
367.0
38.0
DAC8560IBDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560ICDGKR
VSSOP
DGK
8
2500
367.0
367.0
38.0
DAC8560ICDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
DAC8560IDDGKR
VSSOP
DGK
8
2500
367.0
367.0
38.0
DAC8560IDDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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